Commit | Line | Data |
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56d237d2 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
3cb9ae4f | 29 | #include <drm/drm_plane_helper.h> |
4874322e | 30 | #include <drm/drm_dp_helper.h> |
26f6d88b | 31 | |
fdb751ef BS |
32 | #include <nvif/class.h> |
33 | ||
77145f1c BS |
34 | #include "nouveau_drm.h" |
35 | #include "nouveau_dma.h" | |
36 | #include "nouveau_gem.h" | |
26f6d88b BS |
37 | #include "nouveau_connector.h" |
38 | #include "nouveau_encoder.h" | |
39 | #include "nouveau_crtc.h" | |
f589be88 | 40 | #include "nouveau_fence.h" |
3a89cd02 | 41 | #include "nv50_display.h" |
26f6d88b | 42 | |
8a46438a BS |
43 | #define EVO_DMA_NR 9 |
44 | ||
bdb8c212 | 45 | #define EVO_MASTER (0x00) |
a63a97eb | 46 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
47 | #define EVO_OVLY(c) (0x05 + (c)) |
48 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
49 | #define EVO_CURS(c) (0x0d + (c)) |
50 | ||
816af2f2 BS |
51 | /* offsets in shared sync bo of various structures */ |
52 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
53 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
54 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
55 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
816af2f2 | 56 | |
b5a794b0 BS |
57 | /****************************************************************************** |
58 | * EVO channel | |
59 | *****************************************************************************/ | |
60 | ||
e225f446 | 61 | struct nv50_chan { |
0ad72863 | 62 | struct nvif_object user; |
b5a794b0 BS |
63 | }; |
64 | ||
65 | static int | |
410f3ec6 | 66 | nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head, |
e225f446 | 67 | void *data, u32 size, struct nv50_chan *chan) |
b5a794b0 | 68 | { |
6af5289e BS |
69 | const u32 handle = (oclass[0] << 16) | head; |
70 | u32 sclass[8]; | |
71 | int ret, i; | |
72 | ||
73 | ret = nvif_object_sclass(disp, sclass, ARRAY_SIZE(sclass)); | |
74 | WARN_ON(ret > ARRAY_SIZE(sclass)); | |
75 | if (ret < 0) | |
76 | return ret; | |
77 | ||
410f3ec6 | 78 | while (oclass[0]) { |
6af5289e BS |
79 | for (i = 0; i < ARRAY_SIZE(sclass); i++) { |
80 | if (sclass[i] == oclass[0]) { | |
81 | ret = nvif_object_init(disp, NULL, handle, | |
82 | oclass[0], data, size, | |
83 | &chan->user); | |
84 | if (ret == 0) | |
85 | nvif_object_map(&chan->user); | |
86 | return ret; | |
87 | } | |
b76f1529 | 88 | } |
6af5289e | 89 | oclass++; |
410f3ec6 | 90 | } |
6af5289e | 91 | |
410f3ec6 | 92 | return -ENOSYS; |
b5a794b0 BS |
93 | } |
94 | ||
95 | static void | |
0ad72863 | 96 | nv50_chan_destroy(struct nv50_chan *chan) |
b5a794b0 | 97 | { |
0ad72863 | 98 | nvif_object_fini(&chan->user); |
b5a794b0 BS |
99 | } |
100 | ||
101 | /****************************************************************************** | |
102 | * PIO EVO channel | |
103 | *****************************************************************************/ | |
104 | ||
e225f446 BS |
105 | struct nv50_pioc { |
106 | struct nv50_chan base; | |
b5a794b0 BS |
107 | }; |
108 | ||
109 | static void | |
0ad72863 | 110 | nv50_pioc_destroy(struct nv50_pioc *pioc) |
b5a794b0 | 111 | { |
0ad72863 | 112 | nv50_chan_destroy(&pioc->base); |
b5a794b0 BS |
113 | } |
114 | ||
115 | static int | |
410f3ec6 | 116 | nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head, |
e225f446 | 117 | void *data, u32 size, struct nv50_pioc *pioc) |
b5a794b0 | 118 | { |
410f3ec6 BS |
119 | return nv50_chan_create(disp, oclass, head, data, size, &pioc->base); |
120 | } | |
121 | ||
122 | /****************************************************************************** | |
123 | * Cursor Immediate | |
124 | *****************************************************************************/ | |
125 | ||
126 | struct nv50_curs { | |
127 | struct nv50_pioc base; | |
128 | }; | |
129 | ||
130 | static int | |
131 | nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs) | |
132 | { | |
648d4dfd | 133 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
134 | .head = head, |
135 | }; | |
136 | static const u32 oclass[] = { | |
648d4dfd BS |
137 | GK104_DISP_CURSOR, |
138 | GF110_DISP_CURSOR, | |
139 | GT214_DISP_CURSOR, | |
140 | G82_DISP_CURSOR, | |
141 | NV50_DISP_CURSOR, | |
410f3ec6 BS |
142 | 0 |
143 | }; | |
144 | ||
145 | return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), | |
146 | &curs->base); | |
147 | } | |
148 | ||
149 | /****************************************************************************** | |
150 | * Overlay Immediate | |
151 | *****************************************************************************/ | |
152 | ||
153 | struct nv50_oimm { | |
154 | struct nv50_pioc base; | |
155 | }; | |
156 | ||
157 | static int | |
158 | nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm) | |
159 | { | |
648d4dfd | 160 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
161 | .head = head, |
162 | }; | |
163 | static const u32 oclass[] = { | |
648d4dfd BS |
164 | GK104_DISP_OVERLAY, |
165 | GF110_DISP_OVERLAY, | |
166 | GT214_DISP_OVERLAY, | |
167 | G82_DISP_OVERLAY, | |
168 | NV50_DISP_OVERLAY, | |
410f3ec6 BS |
169 | 0 |
170 | }; | |
171 | ||
172 | return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), | |
173 | &oimm->base); | |
b5a794b0 BS |
174 | } |
175 | ||
176 | /****************************************************************************** | |
177 | * DMA EVO channel | |
178 | *****************************************************************************/ | |
179 | ||
e225f446 BS |
180 | struct nv50_dmac { |
181 | struct nv50_chan base; | |
3376ee37 BS |
182 | dma_addr_t handle; |
183 | u32 *ptr; | |
59ad1465 | 184 | |
0ad72863 BS |
185 | struct nvif_object sync; |
186 | struct nvif_object vram; | |
187 | ||
59ad1465 DV |
188 | /* Protects against concurrent pushbuf access to this channel, lock is |
189 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
190 | * dropped again by evo_kick. */ | |
191 | struct mutex lock; | |
b5a794b0 BS |
192 | }; |
193 | ||
194 | static void | |
0ad72863 | 195 | nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) |
b5a794b0 | 196 | { |
0ad72863 BS |
197 | nvif_object_fini(&dmac->vram); |
198 | nvif_object_fini(&dmac->sync); | |
199 | ||
200 | nv50_chan_destroy(&dmac->base); | |
201 | ||
b5a794b0 | 202 | if (dmac->ptr) { |
0ad72863 | 203 | struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev; |
b5a794b0 BS |
204 | pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); |
205 | } | |
b5a794b0 BS |
206 | } |
207 | ||
47057302 | 208 | static int |
410f3ec6 | 209 | nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head, |
47057302 | 210 | void *data, u32 size, u64 syncbuf, |
e225f446 | 211 | struct nv50_dmac *dmac) |
47057302 | 212 | { |
f392ec4b | 213 | struct nvif_device *device = nvif_device(disp); |
648d4dfd | 214 | struct nv50_disp_core_channel_dma_v0 *args = data; |
0ad72863 | 215 | struct nvif_object pushbuf; |
47057302 BS |
216 | int ret; |
217 | ||
59ad1465 DV |
218 | mutex_init(&dmac->lock); |
219 | ||
f392ec4b | 220 | dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev, |
0ad72863 | 221 | PAGE_SIZE, &dmac->handle); |
47057302 BS |
222 | if (!dmac->ptr) |
223 | return -ENOMEM; | |
224 | ||
f392ec4b | 225 | ret = nvif_object_init(nvif_object(device), NULL, |
648d4dfd | 226 | args->pushbuf, NV_DMA_FROM_MEMORY, |
4acfd707 BS |
227 | &(struct nv_dma_v0) { |
228 | .target = NV_DMA_V0_TARGET_PCI_US, | |
229 | .access = NV_DMA_V0_ACCESS_RD, | |
47057302 BS |
230 | .start = dmac->handle + 0x0000, |
231 | .limit = dmac->handle + 0x0fff, | |
4acfd707 | 232 | }, sizeof(struct nv_dma_v0), &pushbuf); |
b5a794b0 | 233 | if (ret) |
47057302 | 234 | return ret; |
b5a794b0 | 235 | |
410f3ec6 | 236 | ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base); |
0ad72863 | 237 | nvif_object_fini(&pushbuf); |
47057302 BS |
238 | if (ret) |
239 | return ret; | |
240 | ||
f45f55c4 | 241 | ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000, |
4acfd707 BS |
242 | NV_DMA_IN_MEMORY, |
243 | &(struct nv_dma_v0) { | |
244 | .target = NV_DMA_V0_TARGET_VRAM, | |
245 | .access = NV_DMA_V0_ACCESS_RDWR, | |
47057302 BS |
246 | .start = syncbuf + 0x0000, |
247 | .limit = syncbuf + 0x0fff, | |
4acfd707 | 248 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 249 | &dmac->sync); |
47057302 BS |
250 | if (ret) |
251 | return ret; | |
252 | ||
f45f55c4 | 253 | ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001, |
4acfd707 BS |
254 | NV_DMA_IN_MEMORY, |
255 | &(struct nv_dma_v0) { | |
256 | .target = NV_DMA_V0_TARGET_VRAM, | |
257 | .access = NV_DMA_V0_ACCESS_RDWR, | |
b5a794b0 | 258 | .start = 0, |
f392ec4b | 259 | .limit = device->info.ram_user - 1, |
4acfd707 | 260 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 261 | &dmac->vram); |
b5a794b0 | 262 | if (ret) |
47057302 BS |
263 | return ret; |
264 | ||
b5a794b0 BS |
265 | return ret; |
266 | } | |
267 | ||
410f3ec6 BS |
268 | /****************************************************************************** |
269 | * Core | |
270 | *****************************************************************************/ | |
271 | ||
e225f446 BS |
272 | struct nv50_mast { |
273 | struct nv50_dmac base; | |
b5a794b0 BS |
274 | }; |
275 | ||
410f3ec6 BS |
276 | static int |
277 | nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core) | |
278 | { | |
648d4dfd BS |
279 | struct nv50_disp_core_channel_dma_v0 args = { |
280 | .pushbuf = 0xb0007d00, | |
410f3ec6 BS |
281 | }; |
282 | static const u32 oclass[] = { | |
dbbd6bcf | 283 | GM204_DISP_CORE_CHANNEL_DMA, |
648d4dfd BS |
284 | GM107_DISP_CORE_CHANNEL_DMA, |
285 | GK110_DISP_CORE_CHANNEL_DMA, | |
286 | GK104_DISP_CORE_CHANNEL_DMA, | |
287 | GF110_DISP_CORE_CHANNEL_DMA, | |
288 | GT214_DISP_CORE_CHANNEL_DMA, | |
289 | GT206_DISP_CORE_CHANNEL_DMA, | |
290 | GT200_DISP_CORE_CHANNEL_DMA, | |
291 | G82_DISP_CORE_CHANNEL_DMA, | |
292 | NV50_DISP_CORE_CHANNEL_DMA, | |
410f3ec6 BS |
293 | 0 |
294 | }; | |
295 | ||
296 | return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf, | |
297 | &core->base); | |
298 | } | |
299 | ||
300 | /****************************************************************************** | |
301 | * Base | |
302 | *****************************************************************************/ | |
b5a794b0 | 303 | |
e225f446 BS |
304 | struct nv50_sync { |
305 | struct nv50_dmac base; | |
9f9bdaaf BS |
306 | u32 addr; |
307 | u32 data; | |
3376ee37 BS |
308 | }; |
309 | ||
410f3ec6 BS |
310 | static int |
311 | nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf, | |
312 | struct nv50_sync *base) | |
313 | { | |
648d4dfd BS |
314 | struct nv50_disp_base_channel_dma_v0 args = { |
315 | .pushbuf = 0xb0007c00 | head, | |
410f3ec6 BS |
316 | .head = head, |
317 | }; | |
318 | static const u32 oclass[] = { | |
648d4dfd BS |
319 | GK110_DISP_BASE_CHANNEL_DMA, |
320 | GK104_DISP_BASE_CHANNEL_DMA, | |
321 | GF110_DISP_BASE_CHANNEL_DMA, | |
322 | GT214_DISP_BASE_CHANNEL_DMA, | |
323 | GT200_DISP_BASE_CHANNEL_DMA, | |
324 | G82_DISP_BASE_CHANNEL_DMA, | |
325 | NV50_DISP_BASE_CHANNEL_DMA, | |
410f3ec6 BS |
326 | 0 |
327 | }; | |
328 | ||
329 | return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), | |
330 | syncbuf, &base->base); | |
331 | } | |
332 | ||
333 | /****************************************************************************** | |
334 | * Overlay | |
335 | *****************************************************************************/ | |
336 | ||
e225f446 BS |
337 | struct nv50_ovly { |
338 | struct nv50_dmac base; | |
b5a794b0 | 339 | }; |
f20ce962 | 340 | |
410f3ec6 BS |
341 | static int |
342 | nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf, | |
343 | struct nv50_ovly *ovly) | |
344 | { | |
648d4dfd BS |
345 | struct nv50_disp_overlay_channel_dma_v0 args = { |
346 | .pushbuf = 0xb0007e00 | head, | |
410f3ec6 BS |
347 | .head = head, |
348 | }; | |
349 | static const u32 oclass[] = { | |
648d4dfd BS |
350 | GK104_DISP_OVERLAY_CONTROL_DMA, |
351 | GF110_DISP_OVERLAY_CONTROL_DMA, | |
352 | GT214_DISP_OVERLAY_CHANNEL_DMA, | |
353 | GT200_DISP_OVERLAY_CHANNEL_DMA, | |
354 | G82_DISP_OVERLAY_CHANNEL_DMA, | |
355 | NV50_DISP_OVERLAY_CHANNEL_DMA, | |
410f3ec6 BS |
356 | 0 |
357 | }; | |
358 | ||
359 | return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), | |
360 | syncbuf, &ovly->base); | |
361 | } | |
26f6d88b | 362 | |
e225f446 | 363 | struct nv50_head { |
dd0e3d53 | 364 | struct nouveau_crtc base; |
8dda53fc | 365 | struct nouveau_bo *image; |
e225f446 BS |
366 | struct nv50_curs curs; |
367 | struct nv50_sync sync; | |
368 | struct nv50_ovly ovly; | |
369 | struct nv50_oimm oimm; | |
b5a794b0 BS |
370 | }; |
371 | ||
e225f446 BS |
372 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
373 | #define nv50_curs(c) (&nv50_head(c)->curs) | |
374 | #define nv50_sync(c) (&nv50_head(c)->sync) | |
375 | #define nv50_ovly(c) (&nv50_head(c)->ovly) | |
376 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
377 | #define nv50_chan(c) (&(c)->base.base) | |
0ad72863 BS |
378 | #define nv50_vers(c) nv50_chan(c)->user.oclass |
379 | ||
380 | struct nv50_fbdma { | |
381 | struct list_head head; | |
382 | struct nvif_object core; | |
383 | struct nvif_object base[4]; | |
384 | }; | |
b5a794b0 | 385 | |
e225f446 | 386 | struct nv50_disp { |
0ad72863 | 387 | struct nvif_object *disp; |
e225f446 | 388 | struct nv50_mast mast; |
b5a794b0 | 389 | |
8a423647 | 390 | struct list_head fbdma; |
b5a794b0 BS |
391 | |
392 | struct nouveau_bo *sync; | |
dd0e3d53 BS |
393 | }; |
394 | ||
e225f446 BS |
395 | static struct nv50_disp * |
396 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 397 | { |
77145f1c | 398 | return nouveau_display(dev)->priv; |
26f6d88b BS |
399 | } |
400 | ||
e225f446 | 401 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 402 | |
bdb8c212 | 403 | static struct drm_crtc * |
e225f446 | 404 | nv50_display_crtc_get(struct drm_encoder *encoder) |
bdb8c212 BS |
405 | { |
406 | return nouveau_encoder(encoder)->crtc; | |
407 | } | |
408 | ||
409 | /****************************************************************************** | |
410 | * EVO channel helpers | |
411 | *****************************************************************************/ | |
51beb428 | 412 | static u32 * |
b5a794b0 | 413 | evo_wait(void *evoc, int nr) |
51beb428 | 414 | { |
e225f446 | 415 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 416 | u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; |
51beb428 | 417 | |
59ad1465 | 418 | mutex_lock(&dmac->lock); |
de8268c5 | 419 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 420 | dmac->ptr[put] = 0x20000000; |
51beb428 | 421 | |
0ad72863 BS |
422 | nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); |
423 | if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) { | |
59ad1465 | 424 | mutex_unlock(&dmac->lock); |
0ad72863 | 425 | nv_error(nvkm_object(&dmac->base.user), "channel stalled\n"); |
51beb428 BS |
426 | return NULL; |
427 | } | |
428 | ||
429 | put = 0; | |
430 | } | |
431 | ||
b5a794b0 | 432 | return dmac->ptr + put; |
51beb428 BS |
433 | } |
434 | ||
435 | static void | |
b5a794b0 | 436 | evo_kick(u32 *push, void *evoc) |
51beb428 | 437 | { |
e225f446 | 438 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 439 | nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 440 | mutex_unlock(&dmac->lock); |
51beb428 BS |
441 | } |
442 | ||
2b1930c3 | 443 | #if 1 |
51beb428 BS |
444 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) |
445 | #define evo_data(p,d) *((p)++) = (d) | |
2b1930c3 BS |
446 | #else |
447 | #define evo_mthd(p,m,s) do { \ | |
448 | const u32 _m = (m), _s = (s); \ | |
449 | printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \ | |
450 | *((p)++) = ((_s << 18) | _m); \ | |
451 | } while(0) | |
452 | #define evo_data(p,d) do { \ | |
453 | const u32 _d = (d); \ | |
454 | printk(KERN_ERR "\t%08x\n", _d); \ | |
455 | *((p)++) = _d; \ | |
456 | } while(0) | |
457 | #endif | |
51beb428 | 458 | |
3376ee37 BS |
459 | static bool |
460 | evo_sync_wait(void *data) | |
461 | { | |
5cc027f6 BS |
462 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
463 | return true; | |
464 | usleep_range(1, 2); | |
465 | return false; | |
3376ee37 BS |
466 | } |
467 | ||
468 | static int | |
b5a794b0 | 469 | evo_sync(struct drm_device *dev) |
3376ee37 | 470 | { |
967e7bde | 471 | struct nvif_device *device = &nouveau_drm(dev)->device; |
e225f446 BS |
472 | struct nv50_disp *disp = nv50_disp(dev); |
473 | struct nv50_mast *mast = nv50_mast(dev); | |
b5a794b0 | 474 | u32 *push = evo_wait(mast, 8); |
3376ee37 | 475 | if (push) { |
816af2f2 | 476 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
3376ee37 | 477 | evo_mthd(push, 0x0084, 1); |
816af2f2 | 478 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
3376ee37 BS |
479 | evo_mthd(push, 0x0080, 2); |
480 | evo_data(push, 0x00000000); | |
481 | evo_data(push, 0x00000000); | |
b5a794b0 | 482 | evo_kick(push, mast); |
967e7bde | 483 | if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync)) |
3376ee37 BS |
484 | return 0; |
485 | } | |
486 | ||
487 | return -EBUSY; | |
488 | } | |
489 | ||
490 | /****************************************************************************** | |
a63a97eb | 491 | * Page flipping channel |
3376ee37 BS |
492 | *****************************************************************************/ |
493 | struct nouveau_bo * | |
e225f446 | 494 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
3376ee37 | 495 | { |
e225f446 | 496 | return nv50_disp(dev)->sync; |
3376ee37 BS |
497 | } |
498 | ||
9f9bdaaf BS |
499 | struct nv50_display_flip { |
500 | struct nv50_disp *disp; | |
501 | struct nv50_sync *chan; | |
502 | }; | |
503 | ||
504 | static bool | |
505 | nv50_display_flip_wait(void *data) | |
506 | { | |
507 | struct nv50_display_flip *flip = data; | |
508 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == | |
b1ea3e6e | 509 | flip->chan->data) |
9f9bdaaf BS |
510 | return true; |
511 | usleep_range(1, 2); | |
512 | return false; | |
513 | } | |
514 | ||
3376ee37 | 515 | void |
e225f446 | 516 | nv50_display_flip_stop(struct drm_crtc *crtc) |
3376ee37 | 517 | { |
967e7bde | 518 | struct nvif_device *device = &nouveau_drm(crtc->dev)->device; |
9f9bdaaf BS |
519 | struct nv50_display_flip flip = { |
520 | .disp = nv50_disp(crtc->dev), | |
521 | .chan = nv50_sync(crtc), | |
522 | }; | |
3376ee37 BS |
523 | u32 *push; |
524 | ||
9f9bdaaf | 525 | push = evo_wait(flip.chan, 8); |
3376ee37 BS |
526 | if (push) { |
527 | evo_mthd(push, 0x0084, 1); | |
528 | evo_data(push, 0x00000000); | |
529 | evo_mthd(push, 0x0094, 1); | |
530 | evo_data(push, 0x00000000); | |
531 | evo_mthd(push, 0x00c0, 1); | |
532 | evo_data(push, 0x00000000); | |
533 | evo_mthd(push, 0x0080, 1); | |
534 | evo_data(push, 0x00000000); | |
9f9bdaaf | 535 | evo_kick(push, flip.chan); |
3376ee37 | 536 | } |
9f9bdaaf | 537 | |
967e7bde | 538 | nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip); |
3376ee37 BS |
539 | } |
540 | ||
541 | int | |
e225f446 | 542 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3376ee37 BS |
543 | struct nouveau_channel *chan, u32 swap_interval) |
544 | { | |
545 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
3376ee37 | 546 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
8dda53fc | 547 | struct nv50_head *head = nv50_head(crtc); |
e225f446 | 548 | struct nv50_sync *sync = nv50_sync(crtc); |
3376ee37 | 549 | u32 *push; |
8dda53fc | 550 | int ret; |
3376ee37 BS |
551 | |
552 | swap_interval <<= 4; | |
553 | if (swap_interval == 0) | |
554 | swap_interval |= 0x100; | |
f60b6e7a BS |
555 | if (chan == NULL) |
556 | evo_sync(crtc->dev); | |
3376ee37 | 557 | |
b5a794b0 | 558 | push = evo_wait(sync, 128); |
3376ee37 BS |
559 | if (unlikely(push == NULL)) |
560 | return -EBUSY; | |
561 | ||
bbf8906b | 562 | if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) { |
9f9bdaaf BS |
563 | ret = RING_SPACE(chan, 8); |
564 | if (ret) | |
565 | return ret; | |
566 | ||
567 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); | |
8dda53fc | 568 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
9f9bdaaf BS |
569 | OUT_RING (chan, sync->addr ^ 0x10); |
570 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); | |
571 | OUT_RING (chan, sync->data + 1); | |
572 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); | |
573 | OUT_RING (chan, sync->addr); | |
574 | OUT_RING (chan, sync->data); | |
575 | } else | |
bbf8906b | 576 | if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) { |
8dda53fc | 577 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
578 | ret = RING_SPACE(chan, 12); |
579 | if (ret) | |
580 | return ret; | |
581 | ||
582 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
0ad72863 | 583 | OUT_RING (chan, chan->vram.handle); |
9f9bdaaf BS |
584 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
585 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
586 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
587 | OUT_RING (chan, sync->data + 1); | |
588 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
589 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
590 | OUT_RING (chan, upper_32_bits(addr)); | |
591 | OUT_RING (chan, lower_32_bits(addr)); | |
592 | OUT_RING (chan, sync->data); | |
593 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); | |
594 | } else | |
595 | if (chan) { | |
8dda53fc | 596 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
597 | ret = RING_SPACE(chan, 10); |
598 | if (ret) | |
599 | return ret; | |
600 | ||
601 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
602 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
603 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
604 | OUT_RING (chan, sync->data + 1); | |
605 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | | |
606 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
607 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
608 | OUT_RING (chan, upper_32_bits(addr)); | |
609 | OUT_RING (chan, lower_32_bits(addr)); | |
610 | OUT_RING (chan, sync->data); | |
611 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | | |
612 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
613 | } | |
35bcf5d5 | 614 | |
9f9bdaaf BS |
615 | if (chan) { |
616 | sync->addr ^= 0x10; | |
617 | sync->data++; | |
3376ee37 | 618 | FIRE_RING (chan); |
3376ee37 BS |
619 | } |
620 | ||
621 | /* queue the flip */ | |
622 | evo_mthd(push, 0x0100, 1); | |
623 | evo_data(push, 0xfffe0000); | |
624 | evo_mthd(push, 0x0084, 1); | |
625 | evo_data(push, swap_interval); | |
626 | if (!(swap_interval & 0x00000100)) { | |
627 | evo_mthd(push, 0x00e0, 1); | |
628 | evo_data(push, 0x40000000); | |
629 | } | |
630 | evo_mthd(push, 0x0088, 4); | |
9f9bdaaf BS |
631 | evo_data(push, sync->addr); |
632 | evo_data(push, sync->data++); | |
633 | evo_data(push, sync->data); | |
f45f55c4 | 634 | evo_data(push, sync->base.sync.handle); |
3376ee37 BS |
635 | evo_mthd(push, 0x00a0, 2); |
636 | evo_data(push, 0x00000000); | |
637 | evo_data(push, 0x00000000); | |
638 | evo_mthd(push, 0x00c0, 1); | |
8a423647 | 639 | evo_data(push, nv_fb->r_handle); |
3376ee37 BS |
640 | evo_mthd(push, 0x0110, 2); |
641 | evo_data(push, 0x00000000); | |
642 | evo_data(push, 0x00000000); | |
648d4dfd | 643 | if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) { |
ed5085a5 BS |
644 | evo_mthd(push, 0x0800, 5); |
645 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
646 | evo_data(push, 0); | |
647 | evo_data(push, (fb->height << 16) | fb->width); | |
648 | evo_data(push, nv_fb->r_pitch); | |
649 | evo_data(push, nv_fb->r_format); | |
650 | } else { | |
651 | evo_mthd(push, 0x0400, 5); | |
652 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
653 | evo_data(push, 0); | |
654 | evo_data(push, (fb->height << 16) | fb->width); | |
655 | evo_data(push, nv_fb->r_pitch); | |
656 | evo_data(push, nv_fb->r_format); | |
657 | } | |
3376ee37 BS |
658 | evo_mthd(push, 0x0080, 1); |
659 | evo_data(push, 0x00000000); | |
b5a794b0 | 660 | evo_kick(push, sync); |
8dda53fc BS |
661 | |
662 | nouveau_bo_ref(nv_fb->nvbo, &head->image); | |
3376ee37 BS |
663 | return 0; |
664 | } | |
665 | ||
438d99e3 BS |
666 | /****************************************************************************** |
667 | * CRTC | |
668 | *****************************************************************************/ | |
669 | static int | |
e225f446 | 670 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 671 | { |
e225f446 | 672 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de691855 BS |
673 | struct nouveau_connector *nv_connector; |
674 | struct drm_connector *connector; | |
675 | u32 *push, mode = 0x00; | |
438d99e3 | 676 | |
488ff207 | 677 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
de691855 BS |
678 | connector = &nv_connector->base; |
679 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
f4510a27 | 680 | if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) |
de691855 BS |
681 | mode = DITHERING_MODE_DYNAMIC2X2; |
682 | } else { | |
683 | mode = nv_connector->dithering_mode; | |
684 | } | |
685 | ||
686 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { | |
687 | if (connector->display_info.bpc >= 8) | |
688 | mode |= DITHERING_DEPTH_8BPC; | |
689 | } else { | |
690 | mode |= nv_connector->dithering_depth; | |
438d99e3 BS |
691 | } |
692 | ||
de8268c5 | 693 | push = evo_wait(mast, 4); |
438d99e3 | 694 | if (push) { |
648d4dfd | 695 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
696 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
697 | evo_data(push, mode); | |
698 | } else | |
648d4dfd | 699 | if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
700 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
701 | evo_data(push, mode); | |
702 | } else { | |
703 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); | |
704 | evo_data(push, mode); | |
705 | } | |
706 | ||
438d99e3 BS |
707 | if (update) { |
708 | evo_mthd(push, 0x0080, 1); | |
709 | evo_data(push, 0x00000000); | |
710 | } | |
de8268c5 | 711 | evo_kick(push, mast); |
438d99e3 BS |
712 | } |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | static int | |
e225f446 | 718 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 719 | { |
e225f446 | 720 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
92854622 | 721 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
3376ee37 | 722 | struct drm_crtc *crtc = &nv_crtc->base; |
f3fdc52d | 723 | struct nouveau_connector *nv_connector; |
92854622 BS |
724 | int mode = DRM_MODE_SCALE_NONE; |
725 | u32 oX, oY, *push; | |
f3fdc52d | 726 | |
92854622 BS |
727 | /* start off at the resolution we programmed the crtc for, this |
728 | * effectively handles NONE/FULL scaling | |
729 | */ | |
f3fdc52d | 730 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
92854622 BS |
731 | if (nv_connector && nv_connector->native_mode) |
732 | mode = nv_connector->scaling_mode; | |
733 | ||
734 | if (mode != DRM_MODE_SCALE_NONE) | |
735 | omode = nv_connector->native_mode; | |
736 | else | |
737 | omode = umode; | |
738 | ||
739 | oX = omode->hdisplay; | |
740 | oY = omode->vdisplay; | |
741 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
742 | oY *= 2; | |
743 | ||
744 | /* add overscan compensation if necessary, will keep the aspect | |
745 | * ratio the same as the backend mode unless overridden by the | |
746 | * user setting both hborder and vborder properties. | |
747 | */ | |
748 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
749 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
750 | nv_connector->edid && | |
751 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
752 | u32 bX = nv_connector->underscan_hborder; | |
753 | u32 bY = nv_connector->underscan_vborder; | |
754 | u32 aspect = (oY << 19) / oX; | |
755 | ||
756 | if (bX) { | |
757 | oX -= (bX * 2); | |
758 | if (bY) oY -= (bY * 2); | |
759 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
760 | } else { | |
761 | oX -= (oX >> 4) + 32; | |
762 | if (bY) oY -= (bY * 2); | |
763 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
764 | } | |
765 | } | |
766 | ||
767 | /* handle CENTER/ASPECT scaling, taking into account the areas | |
768 | * removed already for overscan compensation | |
769 | */ | |
770 | switch (mode) { | |
771 | case DRM_MODE_SCALE_CENTER: | |
772 | oX = min((u32)umode->hdisplay, oX); | |
773 | oY = min((u32)umode->vdisplay, oY); | |
774 | /* fall-through */ | |
775 | case DRM_MODE_SCALE_ASPECT: | |
776 | if (oY < oX) { | |
777 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; | |
778 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
779 | } else { | |
780 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; | |
781 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
f3fdc52d | 782 | } |
92854622 BS |
783 | break; |
784 | default: | |
785 | break; | |
f3fdc52d | 786 | } |
438d99e3 | 787 | |
de8268c5 | 788 | push = evo_wait(mast, 8); |
438d99e3 | 789 | if (push) { |
648d4dfd | 790 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
791 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
792 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); | |
793 | evo_data(push, (oY << 16) | oX); | |
794 | evo_data(push, (oY << 16) | oX); | |
795 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); | |
796 | evo_data(push, 0x00000000); | |
797 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); | |
798 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
799 | } else { | |
800 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); | |
801 | evo_data(push, (oY << 16) | oX); | |
802 | evo_data(push, (oY << 16) | oX); | |
803 | evo_data(push, (oY << 16) | oX); | |
804 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); | |
805 | evo_data(push, 0x00000000); | |
806 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); | |
807 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
808 | } | |
809 | ||
810 | evo_kick(push, mast); | |
811 | ||
438d99e3 | 812 | if (update) { |
e225f446 | 813 | nv50_display_flip_stop(crtc); |
f4510a27 MR |
814 | nv50_display_flip_next(crtc, crtc->primary->fb, |
815 | NULL, 1); | |
438d99e3 | 816 | } |
438d99e3 BS |
817 | } |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
f9887d09 | 822 | static int |
e225f446 | 823 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
f9887d09 | 824 | { |
e225f446 | 825 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
f9887d09 BS |
826 | u32 *push, hue, vib; |
827 | int adj; | |
828 | ||
829 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; | |
830 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; | |
831 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; | |
832 | ||
833 | push = evo_wait(mast, 16); | |
834 | if (push) { | |
648d4dfd | 835 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
f9887d09 BS |
836 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
837 | evo_data(push, (hue << 20) | (vib << 8)); | |
838 | } else { | |
839 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); | |
840 | evo_data(push, (hue << 20) | (vib << 8)); | |
841 | } | |
842 | ||
843 | if (update) { | |
844 | evo_mthd(push, 0x0080, 1); | |
845 | evo_data(push, 0x00000000); | |
846 | } | |
847 | evo_kick(push, mast); | |
848 | } | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
438d99e3 | 853 | static int |
e225f446 | 854 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
438d99e3 BS |
855 | int x, int y, bool update) |
856 | { | |
857 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); | |
e225f446 | 858 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
438d99e3 BS |
859 | u32 *push; |
860 | ||
de8268c5 | 861 | push = evo_wait(mast, 16); |
438d99e3 | 862 | if (push) { |
648d4dfd | 863 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
864 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
865 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
866 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); | |
867 | evo_data(push, (fb->height << 16) | fb->width); | |
868 | evo_data(push, nvfb->r_pitch); | |
869 | evo_data(push, nvfb->r_format); | |
870 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); | |
871 | evo_data(push, (y << 16) | x); | |
648d4dfd | 872 | if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 873 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 874 | evo_data(push, nvfb->r_handle); |
de8268c5 BS |
875 | } |
876 | } else { | |
877 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); | |
878 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
879 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); | |
880 | evo_data(push, (fb->height << 16) | fb->width); | |
881 | evo_data(push, nvfb->r_pitch); | |
882 | evo_data(push, nvfb->r_format); | |
8a423647 | 883 | evo_data(push, nvfb->r_handle); |
de8268c5 BS |
884 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); |
885 | evo_data(push, (y << 16) | x); | |
886 | } | |
887 | ||
a46232ee BS |
888 | if (update) { |
889 | evo_mthd(push, 0x0080, 1); | |
890 | evo_data(push, 0x00000000); | |
891 | } | |
de8268c5 | 892 | evo_kick(push, mast); |
438d99e3 BS |
893 | } |
894 | ||
8a423647 | 895 | nv_crtc->fb.handle = nvfb->r_handle; |
438d99e3 BS |
896 | return 0; |
897 | } | |
898 | ||
899 | static void | |
e225f446 | 900 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
438d99e3 | 901 | { |
e225f446 | 902 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 903 | u32 *push = evo_wait(mast, 16); |
438d99e3 | 904 | if (push) { |
648d4dfd | 905 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
906 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
907 | evo_data(push, 0x85000000); | |
908 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
909 | } else | |
648d4dfd | 910 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
911 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
912 | evo_data(push, 0x85000000); | |
913 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
914 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
f45f55c4 | 915 | evo_data(push, mast->base.vram.handle); |
de8268c5 | 916 | } else { |
438d99e3 BS |
917 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
918 | evo_data(push, 0x85000000); | |
919 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
920 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
f45f55c4 | 921 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
922 | } |
923 | evo_kick(push, mast); | |
924 | } | |
925 | } | |
926 | ||
927 | static void | |
e225f446 | 928 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
de8268c5 | 929 | { |
e225f446 | 930 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
931 | u32 *push = evo_wait(mast, 16); |
932 | if (push) { | |
648d4dfd | 933 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
934 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
935 | evo_data(push, 0x05000000); | |
936 | } else | |
648d4dfd | 937 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
938 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
939 | evo_data(push, 0x05000000); | |
940 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
941 | evo_data(push, 0x00000000); | |
438d99e3 BS |
942 | } else { |
943 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); | |
944 | evo_data(push, 0x05000000); | |
945 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
946 | evo_data(push, 0x00000000); | |
947 | } | |
de8268c5 BS |
948 | evo_kick(push, mast); |
949 | } | |
950 | } | |
438d99e3 | 951 | |
de8268c5 | 952 | static void |
e225f446 | 953 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
de8268c5 | 954 | { |
e225f446 | 955 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
956 | |
957 | if (show) | |
e225f446 | 958 | nv50_crtc_cursor_show(nv_crtc); |
de8268c5 | 959 | else |
e225f446 | 960 | nv50_crtc_cursor_hide(nv_crtc); |
de8268c5 BS |
961 | |
962 | if (update) { | |
963 | u32 *push = evo_wait(mast, 2); | |
964 | if (push) { | |
438d99e3 BS |
965 | evo_mthd(push, 0x0080, 1); |
966 | evo_data(push, 0x00000000); | |
de8268c5 | 967 | evo_kick(push, mast); |
438d99e3 | 968 | } |
438d99e3 BS |
969 | } |
970 | } | |
971 | ||
972 | static void | |
e225f446 | 973 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
438d99e3 BS |
974 | { |
975 | } | |
976 | ||
977 | static void | |
e225f446 | 978 | nv50_crtc_prepare(struct drm_crtc *crtc) |
438d99e3 BS |
979 | { |
980 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 981 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
982 | u32 *push; |
983 | ||
e225f446 | 984 | nv50_display_flip_stop(crtc); |
3376ee37 | 985 | |
56d237d2 | 986 | push = evo_wait(mast, 6); |
438d99e3 | 987 | if (push) { |
648d4dfd | 988 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
989 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
990 | evo_data(push, 0x00000000); | |
991 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
992 | evo_data(push, 0x40000000); | |
993 | } else | |
648d4dfd | 994 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
995 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
996 | evo_data(push, 0x00000000); | |
997 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
998 | evo_data(push, 0x40000000); | |
999 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
1000 | evo_data(push, 0x00000000); | |
1001 | } else { | |
1002 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
1003 | evo_data(push, 0x00000000); | |
1004 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); | |
1005 | evo_data(push, 0x03000000); | |
1006 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
1007 | evo_data(push, 0x00000000); | |
1008 | } | |
1009 | ||
1010 | evo_kick(push, mast); | |
438d99e3 BS |
1011 | } |
1012 | ||
e225f446 | 1013 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
438d99e3 BS |
1014 | } |
1015 | ||
1016 | static void | |
e225f446 | 1017 | nv50_crtc_commit(struct drm_crtc *crtc) |
438d99e3 BS |
1018 | { |
1019 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 1020 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1021 | u32 *push; |
1022 | ||
de8268c5 | 1023 | push = evo_wait(mast, 32); |
438d99e3 | 1024 | if (push) { |
648d4dfd | 1025 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 1026 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 1027 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1028 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1029 | evo_data(push, 0xc0000000); | |
1030 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1031 | } else | |
648d4dfd | 1032 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 1033 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 1034 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1035 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1036 | evo_data(push, 0xc0000000); | |
1037 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1038 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
f45f55c4 | 1039 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
1040 | } else { |
1041 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
8a423647 | 1042 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1043 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); |
1044 | evo_data(push, 0x83000000); | |
1045 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1046 | evo_data(push, 0x00000000); | |
1047 | evo_data(push, 0x00000000); | |
1048 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
f45f55c4 | 1049 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
1050 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
1051 | evo_data(push, 0xffffff00); | |
1052 | } | |
1053 | ||
1054 | evo_kick(push, mast); | |
438d99e3 BS |
1055 | } |
1056 | ||
e225f446 | 1057 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); |
f4510a27 | 1058 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
438d99e3 BS |
1059 | } |
1060 | ||
1061 | static bool | |
e225f446 | 1062 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
438d99e3 BS |
1063 | struct drm_display_mode *adjusted_mode) |
1064 | { | |
eb2e9686 | 1065 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
438d99e3 BS |
1066 | return true; |
1067 | } | |
1068 | ||
1069 | static int | |
e225f446 | 1070 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
438d99e3 | 1071 | { |
f4510a27 | 1072 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
8dda53fc | 1073 | struct nv50_head *head = nv50_head(crtc); |
438d99e3 BS |
1074 | int ret; |
1075 | ||
1076 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); | |
8dda53fc BS |
1077 | if (ret == 0) { |
1078 | if (head->image) | |
1079 | nouveau_bo_unpin(head->image); | |
1080 | nouveau_bo_ref(nvfb->nvbo, &head->image); | |
438d99e3 BS |
1081 | } |
1082 | ||
8dda53fc | 1083 | return ret; |
438d99e3 BS |
1084 | } |
1085 | ||
1086 | static int | |
e225f446 | 1087 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
438d99e3 BS |
1088 | struct drm_display_mode *mode, int x, int y, |
1089 | struct drm_framebuffer *old_fb) | |
1090 | { | |
e225f446 | 1091 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1092 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1093 | struct nouveau_connector *nv_connector; | |
2d1d898b BS |
1094 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
1095 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
1096 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
1097 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
1dce6264 | 1098 | u32 vblan2e = 0, vblan2s = 1, vblankus = 0; |
3488c57b | 1099 | u32 *push; |
438d99e3 BS |
1100 | int ret; |
1101 | ||
2d1d898b BS |
1102 | hactive = mode->htotal; |
1103 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
1104 | hbackp = mode->htotal - mode->hsync_end; | |
1105 | hblanke = hsynce + hbackp; | |
1106 | hfrontp = mode->hsync_start - mode->hdisplay; | |
1107 | hblanks = mode->htotal - hfrontp - 1; | |
1108 | ||
1109 | vactive = mode->vtotal * vscan / ilace; | |
1110 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
1111 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
1112 | vblanke = vsynce + vbackp; | |
1113 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
1114 | vblanks = vactive - vfrontp - 1; | |
1dce6264 RS |
1115 | /* XXX: Safe underestimate, even "0" works */ |
1116 | vblankus = (vactive - mode->vdisplay - 2) * hactive; | |
1117 | vblankus *= 1000; | |
1118 | vblankus /= mode->clock; | |
1119 | ||
2d1d898b BS |
1120 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
1121 | vblan2e = vactive + vsynce + vbackp; | |
1122 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
1123 | vactive = (vactive * 2) + 1; | |
2d1d898b BS |
1124 | } |
1125 | ||
e225f446 | 1126 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1127 | if (ret) |
1128 | return ret; | |
1129 | ||
de8268c5 | 1130 | push = evo_wait(mast, 64); |
438d99e3 | 1131 | if (push) { |
648d4dfd | 1132 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1133 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
1134 | evo_data(push, 0x00800000 | mode->clock); | |
1135 | evo_data(push, (ilace == 2) ? 2 : 0); | |
1dce6264 | 1136 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 8); |
de8268c5 BS |
1137 | evo_data(push, 0x00000000); |
1138 | evo_data(push, (vactive << 16) | hactive); | |
1139 | evo_data(push, ( vsynce << 16) | hsynce); | |
1140 | evo_data(push, (vblanke << 16) | hblanke); | |
1141 | evo_data(push, (vblanks << 16) | hblanks); | |
1142 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1dce6264 | 1143 | evo_data(push, vblankus); |
de8268c5 BS |
1144 | evo_data(push, 0x00000000); |
1145 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); | |
1146 | evo_data(push, 0x00000311); | |
1147 | evo_data(push, 0x00000100); | |
1148 | } else { | |
1149 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); | |
1150 | evo_data(push, 0x00000000); | |
1151 | evo_data(push, (vactive << 16) | hactive); | |
1152 | evo_data(push, ( vsynce << 16) | hsynce); | |
1153 | evo_data(push, (vblanke << 16) | hblanke); | |
1154 | evo_data(push, (vblanks << 16) | hblanks); | |
1155 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1156 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); | |
1157 | evo_data(push, 0x00000000); /* ??? */ | |
1158 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); | |
1159 | evo_data(push, mode->clock * 1000); | |
1160 | evo_data(push, 0x00200000); /* ??? */ | |
1161 | evo_data(push, mode->clock * 1000); | |
1162 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); | |
1163 | evo_data(push, 0x00000311); | |
1164 | evo_data(push, 0x00000100); | |
1165 | } | |
1166 | ||
1167 | evo_kick(push, mast); | |
438d99e3 BS |
1168 | } |
1169 | ||
1170 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
e225f446 BS |
1171 | nv50_crtc_set_dither(nv_crtc, false); |
1172 | nv50_crtc_set_scale(nv_crtc, false); | |
1173 | nv50_crtc_set_color_vibrance(nv_crtc, false); | |
f4510a27 | 1174 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); |
438d99e3 BS |
1175 | return 0; |
1176 | } | |
1177 | ||
1178 | static int | |
e225f446 | 1179 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
438d99e3 BS |
1180 | struct drm_framebuffer *old_fb) |
1181 | { | |
77145f1c | 1182 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
438d99e3 BS |
1183 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1184 | int ret; | |
1185 | ||
f4510a27 | 1186 | if (!crtc->primary->fb) { |
77145f1c | 1187 | NV_DEBUG(drm, "No FB bound\n"); |
84e2ad8b BS |
1188 | return 0; |
1189 | } | |
1190 | ||
e225f446 | 1191 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1192 | if (ret) |
1193 | return ret; | |
1194 | ||
e225f446 | 1195 | nv50_display_flip_stop(crtc); |
f4510a27 MR |
1196 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); |
1197 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); | |
438d99e3 BS |
1198 | return 0; |
1199 | } | |
1200 | ||
1201 | static int | |
e225f446 | 1202 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
438d99e3 BS |
1203 | struct drm_framebuffer *fb, int x, int y, |
1204 | enum mode_set_atomic state) | |
1205 | { | |
1206 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1207 | nv50_display_flip_stop(crtc); |
1208 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); | |
438d99e3 BS |
1209 | return 0; |
1210 | } | |
1211 | ||
1212 | static void | |
e225f446 | 1213 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
438d99e3 | 1214 | { |
e225f446 | 1215 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
1216 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1217 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
1218 | int i; | |
1219 | ||
1220 | for (i = 0; i < 256; i++) { | |
de8268c5 BS |
1221 | u16 r = nv_crtc->lut.r[i] >> 2; |
1222 | u16 g = nv_crtc->lut.g[i] >> 2; | |
1223 | u16 b = nv_crtc->lut.b[i] >> 2; | |
1224 | ||
648d4dfd | 1225 | if (disp->disp->oclass < GF110_DISP) { |
de8268c5 BS |
1226 | writew(r + 0x0000, lut + (i * 0x08) + 0); |
1227 | writew(g + 0x0000, lut + (i * 0x08) + 2); | |
1228 | writew(b + 0x0000, lut + (i * 0x08) + 4); | |
1229 | } else { | |
1230 | writew(r + 0x6000, lut + (i * 0x20) + 0); | |
1231 | writew(g + 0x6000, lut + (i * 0x20) + 2); | |
1232 | writew(b + 0x6000, lut + (i * 0x20) + 4); | |
1233 | } | |
438d99e3 BS |
1234 | } |
1235 | } | |
1236 | ||
8dda53fc BS |
1237 | static void |
1238 | nv50_crtc_disable(struct drm_crtc *crtc) | |
1239 | { | |
1240 | struct nv50_head *head = nv50_head(crtc); | |
efa366fd | 1241 | evo_sync(crtc->dev); |
8dda53fc BS |
1242 | if (head->image) |
1243 | nouveau_bo_unpin(head->image); | |
1244 | nouveau_bo_ref(NULL, &head->image); | |
1245 | } | |
1246 | ||
438d99e3 | 1247 | static int |
e225f446 | 1248 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
438d99e3 BS |
1249 | uint32_t handle, uint32_t width, uint32_t height) |
1250 | { | |
1251 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
1252 | struct drm_device *dev = crtc->dev; | |
1253 | struct drm_gem_object *gem; | |
1254 | struct nouveau_bo *nvbo; | |
1255 | bool visible = (handle != 0); | |
1256 | int i, ret = 0; | |
1257 | ||
1258 | if (visible) { | |
1259 | if (width != 64 || height != 64) | |
1260 | return -EINVAL; | |
1261 | ||
1262 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
1263 | if (unlikely(!gem)) | |
1264 | return -ENOENT; | |
1265 | nvbo = nouveau_gem_object(gem); | |
1266 | ||
1267 | ret = nouveau_bo_map(nvbo); | |
1268 | if (ret == 0) { | |
1269 | for (i = 0; i < 64 * 64; i++) { | |
1270 | u32 v = nouveau_bo_rd32(nvbo, i); | |
1271 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); | |
1272 | } | |
1273 | nouveau_bo_unmap(nvbo); | |
1274 | } | |
1275 | ||
1276 | drm_gem_object_unreference_unlocked(gem); | |
1277 | } | |
1278 | ||
1279 | if (visible != nv_crtc->cursor.visible) { | |
e225f446 | 1280 | nv50_crtc_cursor_show_hide(nv_crtc, visible, true); |
438d99e3 BS |
1281 | nv_crtc->cursor.visible = visible; |
1282 | } | |
1283 | ||
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | static int | |
e225f446 | 1288 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
438d99e3 | 1289 | { |
e225f446 BS |
1290 | struct nv50_curs *curs = nv50_curs(crtc); |
1291 | struct nv50_chan *chan = nv50_chan(curs); | |
0ad72863 BS |
1292 | nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
1293 | nvif_wr32(&chan->user, 0x0080, 0x00000000); | |
438d99e3 BS |
1294 | return 0; |
1295 | } | |
1296 | ||
1297 | static void | |
e225f446 | 1298 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
438d99e3 BS |
1299 | uint32_t start, uint32_t size) |
1300 | { | |
1301 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
bdefc8cb | 1302 | u32 end = min_t(u32, start + size, 256); |
438d99e3 BS |
1303 | u32 i; |
1304 | ||
1305 | for (i = start; i < end; i++) { | |
1306 | nv_crtc->lut.r[i] = r[i]; | |
1307 | nv_crtc->lut.g[i] = g[i]; | |
1308 | nv_crtc->lut.b[i] = b[i]; | |
1309 | } | |
1310 | ||
e225f446 | 1311 | nv50_crtc_lut_load(crtc); |
438d99e3 BS |
1312 | } |
1313 | ||
1314 | static void | |
e225f446 | 1315 | nv50_crtc_destroy(struct drm_crtc *crtc) |
438d99e3 BS |
1316 | { |
1317 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1318 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1319 | struct nv50_head *head = nv50_head(crtc); | |
0ad72863 | 1320 | struct nv50_fbdma *fbdma; |
8dda53fc | 1321 | |
0ad72863 BS |
1322 | list_for_each_entry(fbdma, &disp->fbdma, head) { |
1323 | nvif_object_fini(&fbdma->base[nv_crtc->index]); | |
1324 | } | |
1325 | ||
1326 | nv50_dmac_destroy(&head->ovly.base, disp->disp); | |
1327 | nv50_pioc_destroy(&head->oimm.base); | |
1328 | nv50_dmac_destroy(&head->sync.base, disp->disp); | |
1329 | nv50_pioc_destroy(&head->curs.base); | |
8dda53fc BS |
1330 | |
1331 | /*XXX: this shouldn't be necessary, but the core doesn't call | |
1332 | * disconnect() during the cleanup paths | |
1333 | */ | |
1334 | if (head->image) | |
1335 | nouveau_bo_unpin(head->image); | |
1336 | nouveau_bo_ref(NULL, &head->image); | |
1337 | ||
438d99e3 | 1338 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
04c8c210 MS |
1339 | if (nv_crtc->cursor.nvbo) |
1340 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
438d99e3 | 1341 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
8dda53fc | 1342 | |
438d99e3 | 1343 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
04c8c210 MS |
1344 | if (nv_crtc->lut.nvbo) |
1345 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
438d99e3 | 1346 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
8dda53fc | 1347 | |
438d99e3 BS |
1348 | drm_crtc_cleanup(crtc); |
1349 | kfree(crtc); | |
1350 | } | |
1351 | ||
e225f446 BS |
1352 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
1353 | .dpms = nv50_crtc_dpms, | |
1354 | .prepare = nv50_crtc_prepare, | |
1355 | .commit = nv50_crtc_commit, | |
1356 | .mode_fixup = nv50_crtc_mode_fixup, | |
1357 | .mode_set = nv50_crtc_mode_set, | |
1358 | .mode_set_base = nv50_crtc_mode_set_base, | |
1359 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, | |
1360 | .load_lut = nv50_crtc_lut_load, | |
8dda53fc | 1361 | .disable = nv50_crtc_disable, |
438d99e3 BS |
1362 | }; |
1363 | ||
e225f446 BS |
1364 | static const struct drm_crtc_funcs nv50_crtc_func = { |
1365 | .cursor_set = nv50_crtc_cursor_set, | |
1366 | .cursor_move = nv50_crtc_cursor_move, | |
1367 | .gamma_set = nv50_crtc_gamma_set, | |
5addcf0a | 1368 | .set_config = nouveau_crtc_set_config, |
e225f446 | 1369 | .destroy = nv50_crtc_destroy, |
3376ee37 | 1370 | .page_flip = nouveau_crtc_page_flip, |
438d99e3 BS |
1371 | }; |
1372 | ||
1373 | static int | |
0ad72863 | 1374 | nv50_crtc_create(struct drm_device *dev, int index) |
438d99e3 | 1375 | { |
e225f446 BS |
1376 | struct nv50_disp *disp = nv50_disp(dev); |
1377 | struct nv50_head *head; | |
438d99e3 BS |
1378 | struct drm_crtc *crtc; |
1379 | int ret, i; | |
1380 | ||
dd0e3d53 BS |
1381 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
1382 | if (!head) | |
438d99e3 BS |
1383 | return -ENOMEM; |
1384 | ||
dd0e3d53 | 1385 | head->base.index = index; |
e225f446 BS |
1386 | head->base.set_dither = nv50_crtc_set_dither; |
1387 | head->base.set_scale = nv50_crtc_set_scale; | |
1388 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; | |
f9887d09 BS |
1389 | head->base.color_vibrance = 50; |
1390 | head->base.vibrant_hue = 0; | |
438d99e3 | 1391 | for (i = 0; i < 256; i++) { |
dd0e3d53 BS |
1392 | head->base.lut.r[i] = i << 8; |
1393 | head->base.lut.g[i] = i << 8; | |
1394 | head->base.lut.b[i] = i << 8; | |
438d99e3 BS |
1395 | } |
1396 | ||
dd0e3d53 | 1397 | crtc = &head->base.base; |
e225f446 BS |
1398 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
1399 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); | |
438d99e3 BS |
1400 | drm_mode_crtc_set_gamma_size(crtc, 256); |
1401 | ||
b5a794b0 | 1402 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
bb6178b0 | 1403 | 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); |
b5a794b0 BS |
1404 | if (!ret) { |
1405 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM); | |
04c8c210 | 1406 | if (!ret) { |
b5a794b0 | 1407 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
1408 | if (ret) |
1409 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1410 | } | |
b5a794b0 BS |
1411 | if (ret) |
1412 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
1413 | } | |
1414 | ||
1415 | if (ret) | |
1416 | goto out; | |
1417 | ||
e225f446 | 1418 | nv50_crtc_lut_load(crtc); |
b5a794b0 BS |
1419 | |
1420 | /* allocate cursor resources */ | |
410f3ec6 | 1421 | ret = nv50_curs_create(disp->disp, index, &head->curs); |
b5a794b0 BS |
1422 | if (ret) |
1423 | goto out; | |
1424 | ||
438d99e3 | 1425 | ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, |
bb6178b0 | 1426 | 0, 0x0000, NULL, NULL, &head->base.cursor.nvbo); |
438d99e3 | 1427 | if (!ret) { |
dd0e3d53 | 1428 | ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM); |
04c8c210 | 1429 | if (!ret) { |
dd0e3d53 | 1430 | ret = nouveau_bo_map(head->base.cursor.nvbo); |
04c8c210 MS |
1431 | if (ret) |
1432 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1433 | } | |
438d99e3 | 1434 | if (ret) |
dd0e3d53 | 1435 | nouveau_bo_ref(NULL, &head->base.cursor.nvbo); |
438d99e3 BS |
1436 | } |
1437 | ||
1438 | if (ret) | |
1439 | goto out; | |
1440 | ||
b5a794b0 | 1441 | /* allocate page flip / sync resources */ |
410f3ec6 BS |
1442 | ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset, |
1443 | &head->sync); | |
b5a794b0 BS |
1444 | if (ret) |
1445 | goto out; | |
1446 | ||
9f9bdaaf BS |
1447 | head->sync.addr = EVO_FLIP_SEM0(index); |
1448 | head->sync.data = 0x00000000; | |
438d99e3 | 1449 | |
b5a794b0 | 1450 | /* allocate overlay resources */ |
410f3ec6 | 1451 | ret = nv50_oimm_create(disp->disp, index, &head->oimm); |
438d99e3 BS |
1452 | if (ret) |
1453 | goto out; | |
1454 | ||
410f3ec6 BS |
1455 | ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset, |
1456 | &head->ovly); | |
b5a794b0 BS |
1457 | if (ret) |
1458 | goto out; | |
438d99e3 BS |
1459 | |
1460 | out: | |
1461 | if (ret) | |
e225f446 | 1462 | nv50_crtc_destroy(crtc); |
438d99e3 BS |
1463 | return ret; |
1464 | } | |
1465 | ||
26f6d88b BS |
1466 | /****************************************************************************** |
1467 | * DAC | |
1468 | *****************************************************************************/ | |
8eaa9669 | 1469 | static void |
e225f446 | 1470 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
8eaa9669 BS |
1471 | { |
1472 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1473 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
bf0eb898 BS |
1474 | struct { |
1475 | struct nv50_disp_mthd_v1 base; | |
1476 | struct nv50_disp_dac_pwr_v0 pwr; | |
1477 | } args = { | |
1478 | .base.version = 1, | |
1479 | .base.method = NV50_DISP_MTHD_V1_DAC_PWR, | |
1480 | .base.hasht = nv_encoder->dcb->hasht, | |
1481 | .base.hashm = nv_encoder->dcb->hashm, | |
1482 | .pwr.state = 1, | |
1483 | .pwr.data = 1, | |
1484 | .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND && | |
1485 | mode != DRM_MODE_DPMS_OFF), | |
1486 | .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY && | |
1487 | mode != DRM_MODE_DPMS_OFF), | |
1488 | }; | |
8eaa9669 | 1489 | |
bf0eb898 | 1490 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
8eaa9669 BS |
1491 | } |
1492 | ||
1493 | static bool | |
e225f446 | 1494 | nv50_dac_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 1495 | const struct drm_display_mode *mode, |
8eaa9669 BS |
1496 | struct drm_display_mode *adjusted_mode) |
1497 | { | |
1498 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1499 | struct nouveau_connector *nv_connector; | |
1500 | ||
1501 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1502 | if (nv_connector && nv_connector->native_mode) { | |
1503 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1504 | int id = adjusted_mode->base.id; | |
1505 | *adjusted_mode = *nv_connector->native_mode; | |
1506 | adjusted_mode->base.id = id; | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | return true; | |
1511 | } | |
1512 | ||
8eaa9669 | 1513 | static void |
e225f446 | 1514 | nv50_dac_commit(struct drm_encoder *encoder) |
8eaa9669 BS |
1515 | { |
1516 | } | |
1517 | ||
1518 | static void | |
e225f446 | 1519 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
8eaa9669 BS |
1520 | struct drm_display_mode *adjusted_mode) |
1521 | { | |
e225f446 | 1522 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
1523 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1524 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
97b19b5c | 1525 | u32 *push; |
8eaa9669 | 1526 | |
e225f446 | 1527 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
8eaa9669 | 1528 | |
97b19b5c | 1529 | push = evo_wait(mast, 8); |
8eaa9669 | 1530 | if (push) { |
648d4dfd | 1531 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
1532 | u32 syncs = 0x00000000; |
1533 | ||
1534 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1535 | syncs |= 0x00000001; | |
1536 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1537 | syncs |= 0x00000002; | |
1538 | ||
1539 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
1540 | evo_data(push, 1 << nv_crtc->index); | |
1541 | evo_data(push, syncs); | |
1542 | } else { | |
1543 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1544 | u32 syncs = 0x00000001; | |
1545 | ||
1546 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1547 | syncs |= 0x00000008; | |
1548 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1549 | syncs |= 0x00000010; | |
1550 | ||
1551 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1552 | magic |= 0x00000001; | |
1553 | ||
1554 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1555 | evo_data(push, syncs); | |
1556 | evo_data(push, magic); | |
1557 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
1558 | evo_data(push, 1 << nv_crtc->index); | |
1559 | } | |
1560 | ||
1561 | evo_kick(push, mast); | |
8eaa9669 BS |
1562 | } |
1563 | ||
1564 | nv_encoder->crtc = encoder->crtc; | |
1565 | } | |
1566 | ||
1567 | static void | |
e225f446 | 1568 | nv50_dac_disconnect(struct drm_encoder *encoder) |
8eaa9669 BS |
1569 | { |
1570 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1571 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
97b19b5c | 1572 | const int or = nv_encoder->or; |
8eaa9669 BS |
1573 | u32 *push; |
1574 | ||
1575 | if (nv_encoder->crtc) { | |
e225f446 | 1576 | nv50_crtc_prepare(nv_encoder->crtc); |
8eaa9669 | 1577 | |
97b19b5c | 1578 | push = evo_wait(mast, 4); |
8eaa9669 | 1579 | if (push) { |
648d4dfd | 1580 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
1581 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
1582 | evo_data(push, 0x00000000); | |
1583 | } else { | |
1584 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
1585 | evo_data(push, 0x00000000); | |
1586 | } | |
97b19b5c | 1587 | evo_kick(push, mast); |
8eaa9669 | 1588 | } |
8eaa9669 | 1589 | } |
97b19b5c BS |
1590 | |
1591 | nv_encoder->crtc = NULL; | |
8eaa9669 BS |
1592 | } |
1593 | ||
b6d8e7ec | 1594 | static enum drm_connector_status |
e225f446 | 1595 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 1596 | { |
c4abd317 | 1597 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 1598 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
c4abd317 BS |
1599 | struct { |
1600 | struct nv50_disp_mthd_v1 base; | |
1601 | struct nv50_disp_dac_load_v0 load; | |
1602 | } args = { | |
1603 | .base.version = 1, | |
1604 | .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, | |
1605 | .base.hasht = nv_encoder->dcb->hasht, | |
1606 | .base.hashm = nv_encoder->dcb->hashm, | |
1607 | }; | |
1608 | int ret; | |
1609 | ||
1610 | args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; | |
1611 | if (args.load.data == 0) | |
1612 | args.load.data = 340; | |
b681993f | 1613 | |
c4abd317 BS |
1614 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
1615 | if (ret || !args.load.load) | |
35b21d39 | 1616 | return connector_status_disconnected; |
b681993f | 1617 | |
35b21d39 | 1618 | return connector_status_connected; |
b6d8e7ec BS |
1619 | } |
1620 | ||
8eaa9669 | 1621 | static void |
e225f446 | 1622 | nv50_dac_destroy(struct drm_encoder *encoder) |
8eaa9669 BS |
1623 | { |
1624 | drm_encoder_cleanup(encoder); | |
1625 | kfree(encoder); | |
1626 | } | |
1627 | ||
e225f446 BS |
1628 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
1629 | .dpms = nv50_dac_dpms, | |
1630 | .mode_fixup = nv50_dac_mode_fixup, | |
1631 | .prepare = nv50_dac_disconnect, | |
1632 | .commit = nv50_dac_commit, | |
1633 | .mode_set = nv50_dac_mode_set, | |
1634 | .disable = nv50_dac_disconnect, | |
1635 | .get_crtc = nv50_display_crtc_get, | |
1636 | .detect = nv50_dac_detect | |
8eaa9669 BS |
1637 | }; |
1638 | ||
e225f446 BS |
1639 | static const struct drm_encoder_funcs nv50_dac_func = { |
1640 | .destroy = nv50_dac_destroy, | |
8eaa9669 BS |
1641 | }; |
1642 | ||
1643 | static int | |
e225f446 | 1644 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 1645 | { |
5ed50209 | 1646 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
967e7bde | 1647 | struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); |
8eaa9669 BS |
1648 | struct nouveau_encoder *nv_encoder; |
1649 | struct drm_encoder *encoder; | |
5ed50209 | 1650 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
1651 | |
1652 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1653 | if (!nv_encoder) | |
1654 | return -ENOMEM; | |
1655 | nv_encoder->dcb = dcbe; | |
1656 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 1657 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
8eaa9669 BS |
1658 | |
1659 | encoder = to_drm_encoder(nv_encoder); | |
1660 | encoder->possible_crtcs = dcbe->heads; | |
1661 | encoder->possible_clones = 0; | |
5ed50209 | 1662 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); |
e225f446 | 1663 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
8eaa9669 BS |
1664 | |
1665 | drm_mode_connector_attach_encoder(connector, encoder); | |
1666 | return 0; | |
1667 | } | |
26f6d88b | 1668 | |
78951d22 BS |
1669 | /****************************************************************************** |
1670 | * Audio | |
1671 | *****************************************************************************/ | |
1672 | static void | |
e225f446 | 1673 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 BS |
1674 | { |
1675 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
cc2a9071 | 1676 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
78951d22 | 1677 | struct nouveau_connector *nv_connector; |
e225f446 | 1678 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
d889c524 BS |
1679 | struct __packed { |
1680 | struct { | |
1681 | struct nv50_disp_mthd_v1 mthd; | |
1682 | struct nv50_disp_sor_hda_eld_v0 eld; | |
1683 | } base; | |
120b0c39 BS |
1684 | u8 data[sizeof(nv_connector->base.eld)]; |
1685 | } args = { | |
d889c524 BS |
1686 | .base.mthd.version = 1, |
1687 | .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
1688 | .base.mthd.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
1689 | .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
1690 | (0x0100 << nv_crtc->index), | |
120b0c39 | 1691 | }; |
78951d22 BS |
1692 | |
1693 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1694 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
1695 | return; | |
1696 | ||
78951d22 | 1697 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
120b0c39 | 1698 | memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); |
78951d22 | 1699 | |
d889c524 | 1700 | nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4); |
78951d22 BS |
1701 | } |
1702 | ||
1703 | static void | |
cc2a9071 | 1704 | nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 BS |
1705 | { |
1706 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1707 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
120b0c39 BS |
1708 | struct { |
1709 | struct nv50_disp_mthd_v1 base; | |
1710 | struct nv50_disp_sor_hda_eld_v0 eld; | |
1711 | } args = { | |
1712 | .base.version = 1, | |
1713 | .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
1714 | .base.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
1715 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
1716 | (0x0100 << nv_crtc->index), | |
120b0c39 | 1717 | }; |
78951d22 | 1718 | |
120b0c39 | 1719 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
1720 | } |
1721 | ||
1722 | /****************************************************************************** | |
1723 | * HDMI | |
1724 | *****************************************************************************/ | |
1725 | static void | |
e225f446 | 1726 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 1727 | { |
64d9cc04 BS |
1728 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1729 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
e225f446 | 1730 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
1731 | struct { |
1732 | struct nv50_disp_mthd_v1 base; | |
1733 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
1734 | } args = { | |
1735 | .base.version = 1, | |
1736 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
1737 | .base.hasht = nv_encoder->dcb->hasht, | |
1738 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
1739 | (0x0100 << nv_crtc->index), | |
1740 | .pwr.state = 1, | |
1741 | .pwr.rekey = 56, /* binary driver, and tegra, constant */ | |
1742 | }; | |
1743 | struct nouveau_connector *nv_connector; | |
64d9cc04 BS |
1744 | u32 max_ac_packet; |
1745 | ||
1746 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1747 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
1748 | return; | |
1749 | ||
1750 | max_ac_packet = mode->htotal - mode->hdisplay; | |
e00f2235 | 1751 | max_ac_packet -= args.pwr.rekey; |
64d9cc04 | 1752 | max_ac_packet -= 18; /* constant from tegra */ |
e00f2235 | 1753 | args.pwr.max_ac_packet = max_ac_packet / 32; |
091e40cd | 1754 | |
e00f2235 | 1755 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
e225f446 | 1756 | nv50_audio_mode_set(encoder, mode); |
78951d22 BS |
1757 | } |
1758 | ||
1759 | static void | |
e84a35a8 | 1760 | nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 | 1761 | { |
64d9cc04 | 1762 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 1763 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
1764 | struct { |
1765 | struct nv50_disp_mthd_v1 base; | |
1766 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
1767 | } args = { | |
1768 | .base.version = 1, | |
1769 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
1770 | .base.hasht = nv_encoder->dcb->hasht, | |
1771 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
1772 | (0x0100 << nv_crtc->index), | |
1773 | }; | |
64d9cc04 | 1774 | |
e00f2235 | 1775 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
1776 | } |
1777 | ||
26f6d88b BS |
1778 | /****************************************************************************** |
1779 | * SOR | |
1780 | *****************************************************************************/ | |
83fc083c | 1781 | static void |
e225f446 | 1782 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
83fc083c BS |
1783 | { |
1784 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
d55b4af9 BS |
1785 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1786 | struct { | |
1787 | struct nv50_disp_mthd_v1 base; | |
1788 | struct nv50_disp_sor_pwr_v0 pwr; | |
1789 | } args = { | |
1790 | .base.version = 1, | |
1791 | .base.method = NV50_DISP_MTHD_V1_SOR_PWR, | |
1792 | .base.hasht = nv_encoder->dcb->hasht, | |
1793 | .base.hashm = nv_encoder->dcb->hashm, | |
1794 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
1795 | }; | |
c02ed2bf BS |
1796 | struct { |
1797 | struct nv50_disp_mthd_v1 base; | |
1798 | struct nv50_disp_sor_dp_pwr_v0 pwr; | |
1799 | } link = { | |
1800 | .base.version = 1, | |
1801 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR, | |
1802 | .base.hasht = nv_encoder->dcb->hasht, | |
1803 | .base.hashm = nv_encoder->dcb->hashm, | |
1804 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
1805 | }; | |
83fc083c BS |
1806 | struct drm_device *dev = encoder->dev; |
1807 | struct drm_encoder *partner; | |
83fc083c BS |
1808 | |
1809 | nv_encoder->last_dpms = mode; | |
1810 | ||
1811 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { | |
1812 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); | |
1813 | ||
1814 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) | |
1815 | continue; | |
1816 | ||
1817 | if (nv_partner != nv_encoder && | |
26cfa813 | 1818 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
83fc083c BS |
1819 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1820 | return; | |
1821 | break; | |
1822 | } | |
1823 | } | |
1824 | ||
4874322e | 1825 | if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { |
d55b4af9 BS |
1826 | args.pwr.state = 1; |
1827 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
c02ed2bf | 1828 | nvif_mthd(disp->disp, 0, &link, sizeof(link)); |
4874322e | 1829 | } else { |
d55b4af9 | 1830 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
4874322e | 1831 | } |
83fc083c BS |
1832 | } |
1833 | ||
1834 | static bool | |
e225f446 | 1835 | nv50_sor_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 1836 | const struct drm_display_mode *mode, |
83fc083c BS |
1837 | struct drm_display_mode *adjusted_mode) |
1838 | { | |
1839 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1840 | struct nouveau_connector *nv_connector; | |
1841 | ||
1842 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1843 | if (nv_connector && nv_connector->native_mode) { | |
1844 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1845 | int id = adjusted_mode->base.id; | |
1846 | *adjusted_mode = *nv_connector->native_mode; | |
1847 | adjusted_mode->base.id = id; | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | return true; | |
1852 | } | |
1853 | ||
4cbb0f8d | 1854 | static void |
e84a35a8 | 1855 | nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data) |
4cbb0f8d | 1856 | { |
e84a35a8 BS |
1857 | struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); |
1858 | u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push; | |
1859 | if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) { | |
648d4dfd | 1860 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
e84a35a8 BS |
1861 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); |
1862 | evo_data(push, (nv_encoder->ctrl = temp)); | |
1863 | } else { | |
1864 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); | |
1865 | evo_data(push, (nv_encoder->ctrl = temp)); | |
4cbb0f8d | 1866 | } |
e84a35a8 | 1867 | evo_kick(push, mast); |
4cbb0f8d | 1868 | } |
e84a35a8 BS |
1869 | } |
1870 | ||
1871 | static void | |
1872 | nv50_sor_disconnect(struct drm_encoder *encoder) | |
1873 | { | |
1874 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1875 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
419e8dc0 BS |
1876 | |
1877 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1878 | nv_encoder->crtc = NULL; | |
e84a35a8 BS |
1879 | |
1880 | if (nv_crtc) { | |
1881 | nv50_crtc_prepare(&nv_crtc->base); | |
1882 | nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0); | |
cc2a9071 | 1883 | nv50_audio_disconnect(encoder, nv_crtc); |
e84a35a8 BS |
1884 | nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc); |
1885 | } | |
4cbb0f8d BS |
1886 | } |
1887 | ||
83fc083c | 1888 | static void |
e225f446 | 1889 | nv50_sor_commit(struct drm_encoder *encoder) |
83fc083c BS |
1890 | { |
1891 | } | |
1892 | ||
1893 | static void | |
e225f446 | 1894 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
3b6d83d1 | 1895 | struct drm_display_mode *mode) |
83fc083c | 1896 | { |
a3761fa2 BS |
1897 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1898 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1899 | struct { | |
1900 | struct nv50_disp_mthd_v1 base; | |
1901 | struct nv50_disp_sor_lvds_script_v0 lvds; | |
1902 | } lvds = { | |
1903 | .base.version = 1, | |
1904 | .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, | |
1905 | .base.hasht = nv_encoder->dcb->hasht, | |
1906 | .base.hashm = nv_encoder->dcb->hashm, | |
1907 | }; | |
e225f446 BS |
1908 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1909 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
78951d22 | 1910 | struct drm_device *dev = encoder->dev; |
77145f1c | 1911 | struct nouveau_drm *drm = nouveau_drm(dev); |
3b6d83d1 | 1912 | struct nouveau_connector *nv_connector; |
77145f1c | 1913 | struct nvbios *bios = &drm->vbios; |
a3761fa2 | 1914 | u32 mask, ctrl; |
419e8dc0 BS |
1915 | u8 owner = 1 << nv_crtc->index; |
1916 | u8 proto = 0xf; | |
1917 | u8 depth = 0x0; | |
83fc083c | 1918 | |
3b6d83d1 | 1919 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
e84a35a8 BS |
1920 | nv_encoder->crtc = encoder->crtc; |
1921 | ||
3b6d83d1 | 1922 | switch (nv_encoder->dcb->type) { |
cb75d97e | 1923 | case DCB_OUTPUT_TMDS: |
3b6d83d1 BS |
1924 | if (nv_encoder->dcb->sorconf.link & 1) { |
1925 | if (mode->clock < 165000) | |
419e8dc0 | 1926 | proto = 0x1; |
3b6d83d1 | 1927 | else |
419e8dc0 | 1928 | proto = 0x5; |
3b6d83d1 | 1929 | } else { |
419e8dc0 | 1930 | proto = 0x2; |
3b6d83d1 BS |
1931 | } |
1932 | ||
e84a35a8 | 1933 | nv50_hdmi_mode_set(&nv_encoder->base.base, mode); |
3b6d83d1 | 1934 | break; |
cb75d97e | 1935 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
1936 | proto = 0x0; |
1937 | ||
3b6d83d1 BS |
1938 | if (bios->fp_no_ddc) { |
1939 | if (bios->fp.dual_link) | |
a3761fa2 | 1940 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 1941 | if (bios->fp.if_is_24bit) |
a3761fa2 | 1942 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 1943 | } else { |
befb51e9 | 1944 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 1945 | if (((u8 *)nv_connector->edid)[121] == 2) |
a3761fa2 | 1946 | lvds.lvds.script |= 0x0100; |
3b6d83d1 BS |
1947 | } else |
1948 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
a3761fa2 | 1949 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 1950 | } |
83fc083c | 1951 | |
a3761fa2 | 1952 | if (lvds.lvds.script & 0x0100) { |
3b6d83d1 | 1953 | if (bios->fp.strapless_is_24bit & 2) |
a3761fa2 | 1954 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
1955 | } else { |
1956 | if (bios->fp.strapless_is_24bit & 1) | |
a3761fa2 | 1957 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
1958 | } |
1959 | ||
1960 | if (nv_connector->base.display_info.bpc == 8) | |
a3761fa2 | 1961 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 1962 | } |
4a230fa6 | 1963 | |
a3761fa2 | 1964 | nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); |
3b6d83d1 | 1965 | break; |
cb75d97e | 1966 | case DCB_OUTPUT_DP: |
3488c57b | 1967 | if (nv_connector->base.display_info.bpc == 6) { |
6e83fda2 | 1968 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
419e8dc0 | 1969 | depth = 0x2; |
bf2c886a BS |
1970 | } else |
1971 | if (nv_connector->base.display_info.bpc == 8) { | |
6e83fda2 | 1972 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
419e8dc0 | 1973 | depth = 0x5; |
bf2c886a BS |
1974 | } else { |
1975 | nv_encoder->dp.datarate = mode->clock * 30 / 8; | |
1976 | depth = 0x6; | |
3488c57b | 1977 | } |
6e83fda2 BS |
1978 | |
1979 | if (nv_encoder->dcb->sorconf.link & 1) | |
419e8dc0 | 1980 | proto = 0x8; |
6e83fda2 | 1981 | else |
419e8dc0 | 1982 | proto = 0x9; |
3eee8646 | 1983 | nv50_audio_mode_set(encoder, mode); |
6e83fda2 | 1984 | break; |
3b6d83d1 BS |
1985 | default: |
1986 | BUG_ON(1); | |
1987 | break; | |
1988 | } | |
ff8ff503 | 1989 | |
e84a35a8 | 1990 | nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON); |
83fc083c | 1991 | |
648d4dfd | 1992 | if (nv50_vers(mast) >= GF110_DISP) { |
e84a35a8 BS |
1993 | u32 *push = evo_wait(mast, 3); |
1994 | if (push) { | |
419e8dc0 BS |
1995 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
1996 | u32 syncs = 0x00000001; | |
1997 | ||
1998 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1999 | syncs |= 0x00000008; | |
2000 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2001 | syncs |= 0x00000010; | |
2002 | ||
2003 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2004 | magic |= 0x00000001; | |
2005 | ||
2006 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
2007 | evo_data(push, syncs | (depth << 6)); | |
2008 | evo_data(push, magic); | |
e84a35a8 | 2009 | evo_kick(push, mast); |
419e8dc0 BS |
2010 | } |
2011 | ||
e84a35a8 BS |
2012 | ctrl = proto << 8; |
2013 | mask = 0x00000f00; | |
2014 | } else { | |
2015 | ctrl = (depth << 16) | (proto << 8); | |
2016 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2017 | ctrl |= 0x00001000; | |
2018 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2019 | ctrl |= 0x00002000; | |
2020 | mask = 0x000f3f00; | |
83fc083c BS |
2021 | } |
2022 | ||
e84a35a8 | 2023 | nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner); |
83fc083c BS |
2024 | } |
2025 | ||
83fc083c | 2026 | static void |
e225f446 | 2027 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c BS |
2028 | { |
2029 | drm_encoder_cleanup(encoder); | |
2030 | kfree(encoder); | |
2031 | } | |
2032 | ||
e225f446 BS |
2033 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
2034 | .dpms = nv50_sor_dpms, | |
2035 | .mode_fixup = nv50_sor_mode_fixup, | |
5a885f0b | 2036 | .prepare = nv50_sor_disconnect, |
e225f446 BS |
2037 | .commit = nv50_sor_commit, |
2038 | .mode_set = nv50_sor_mode_set, | |
2039 | .disable = nv50_sor_disconnect, | |
2040 | .get_crtc = nv50_display_crtc_get, | |
83fc083c BS |
2041 | }; |
2042 | ||
e225f446 BS |
2043 | static const struct drm_encoder_funcs nv50_sor_func = { |
2044 | .destroy = nv50_sor_destroy, | |
83fc083c BS |
2045 | }; |
2046 | ||
2047 | static int | |
e225f446 | 2048 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 2049 | { |
5ed50209 | 2050 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
967e7bde | 2051 | struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); |
83fc083c BS |
2052 | struct nouveau_encoder *nv_encoder; |
2053 | struct drm_encoder *encoder; | |
5ed50209 BS |
2054 | int type; |
2055 | ||
2056 | switch (dcbe->type) { | |
2057 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
2058 | case DCB_OUTPUT_TMDS: | |
2059 | case DCB_OUTPUT_DP: | |
2060 | default: | |
2061 | type = DRM_MODE_ENCODER_TMDS; | |
2062 | break; | |
2063 | } | |
83fc083c BS |
2064 | |
2065 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2066 | if (!nv_encoder) | |
2067 | return -ENOMEM; | |
2068 | nv_encoder->dcb = dcbe; | |
2069 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 2070 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
83fc083c BS |
2071 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
2072 | ||
2073 | encoder = to_drm_encoder(nv_encoder); | |
2074 | encoder->possible_crtcs = dcbe->heads; | |
2075 | encoder->possible_clones = 0; | |
5ed50209 | 2076 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); |
e225f446 | 2077 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
83fc083c BS |
2078 | |
2079 | drm_mode_connector_attach_encoder(connector, encoder); | |
2080 | return 0; | |
2081 | } | |
26f6d88b | 2082 | |
eb6313ad BS |
2083 | /****************************************************************************** |
2084 | * PIOR | |
2085 | *****************************************************************************/ | |
2086 | ||
2087 | static void | |
2088 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) | |
2089 | { | |
2090 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2091 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
67cb49c4 BS |
2092 | struct { |
2093 | struct nv50_disp_mthd_v1 base; | |
2094 | struct nv50_disp_pior_pwr_v0 pwr; | |
2095 | } args = { | |
2096 | .base.version = 1, | |
2097 | .base.method = NV50_DISP_MTHD_V1_PIOR_PWR, | |
2098 | .base.hasht = nv_encoder->dcb->hasht, | |
2099 | .base.hashm = nv_encoder->dcb->hashm, | |
2100 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
2101 | .pwr.type = nv_encoder->dcb->type, | |
2102 | }; | |
2103 | ||
2104 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
eb6313ad BS |
2105 | } |
2106 | ||
2107 | static bool | |
2108 | nv50_pior_mode_fixup(struct drm_encoder *encoder, | |
2109 | const struct drm_display_mode *mode, | |
2110 | struct drm_display_mode *adjusted_mode) | |
2111 | { | |
2112 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2113 | struct nouveau_connector *nv_connector; | |
2114 | ||
2115 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2116 | if (nv_connector && nv_connector->native_mode) { | |
2117 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
2118 | int id = adjusted_mode->base.id; | |
2119 | *adjusted_mode = *nv_connector->native_mode; | |
2120 | adjusted_mode->base.id = id; | |
2121 | } | |
2122 | } | |
2123 | ||
2124 | adjusted_mode->clock *= 2; | |
2125 | return true; | |
2126 | } | |
2127 | ||
2128 | static void | |
2129 | nv50_pior_commit(struct drm_encoder *encoder) | |
2130 | { | |
2131 | } | |
2132 | ||
2133 | static void | |
2134 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
2135 | struct drm_display_mode *adjusted_mode) | |
2136 | { | |
2137 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2138 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2139 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
2140 | struct nouveau_connector *nv_connector; | |
2141 | u8 owner = 1 << nv_crtc->index; | |
2142 | u8 proto, depth; | |
2143 | u32 *push; | |
2144 | ||
2145 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2146 | switch (nv_connector->base.display_info.bpc) { | |
2147 | case 10: depth = 0x6; break; | |
2148 | case 8: depth = 0x5; break; | |
2149 | case 6: depth = 0x2; break; | |
2150 | default: depth = 0x0; break; | |
2151 | } | |
2152 | ||
2153 | switch (nv_encoder->dcb->type) { | |
2154 | case DCB_OUTPUT_TMDS: | |
2155 | case DCB_OUTPUT_DP: | |
2156 | proto = 0x0; | |
2157 | break; | |
2158 | default: | |
2159 | BUG_ON(1); | |
2160 | break; | |
2161 | } | |
2162 | ||
2163 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); | |
2164 | ||
2165 | push = evo_wait(mast, 8); | |
2166 | if (push) { | |
648d4dfd | 2167 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
2168 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
2169 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2170 | ctrl |= 0x00001000; | |
2171 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2172 | ctrl |= 0x00002000; | |
2173 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
2174 | evo_data(push, ctrl); | |
2175 | } | |
2176 | ||
2177 | evo_kick(push, mast); | |
2178 | } | |
2179 | ||
2180 | nv_encoder->crtc = encoder->crtc; | |
2181 | } | |
2182 | ||
2183 | static void | |
2184 | nv50_pior_disconnect(struct drm_encoder *encoder) | |
2185 | { | |
2186 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2187 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2188 | const int or = nv_encoder->or; | |
2189 | u32 *push; | |
2190 | ||
2191 | if (nv_encoder->crtc) { | |
2192 | nv50_crtc_prepare(nv_encoder->crtc); | |
2193 | ||
2194 | push = evo_wait(mast, 4); | |
2195 | if (push) { | |
648d4dfd | 2196 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
2197 | evo_mthd(push, 0x0700 + (or * 0x040), 1); |
2198 | evo_data(push, 0x00000000); | |
2199 | } | |
eb6313ad BS |
2200 | evo_kick(push, mast); |
2201 | } | |
2202 | } | |
2203 | ||
2204 | nv_encoder->crtc = NULL; | |
2205 | } | |
2206 | ||
2207 | static void | |
2208 | nv50_pior_destroy(struct drm_encoder *encoder) | |
2209 | { | |
2210 | drm_encoder_cleanup(encoder); | |
2211 | kfree(encoder); | |
2212 | } | |
2213 | ||
2214 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { | |
2215 | .dpms = nv50_pior_dpms, | |
2216 | .mode_fixup = nv50_pior_mode_fixup, | |
2217 | .prepare = nv50_pior_disconnect, | |
2218 | .commit = nv50_pior_commit, | |
2219 | .mode_set = nv50_pior_mode_set, | |
2220 | .disable = nv50_pior_disconnect, | |
2221 | .get_crtc = nv50_display_crtc_get, | |
2222 | }; | |
2223 | ||
2224 | static const struct drm_encoder_funcs nv50_pior_func = { | |
2225 | .destroy = nv50_pior_destroy, | |
2226 | }; | |
2227 | ||
2228 | static int | |
2229 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
2230 | { | |
2231 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
967e7bde | 2232 | struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); |
eb6313ad BS |
2233 | struct nouveau_i2c_port *ddc = NULL; |
2234 | struct nouveau_encoder *nv_encoder; | |
2235 | struct drm_encoder *encoder; | |
2236 | int type; | |
2237 | ||
2238 | switch (dcbe->type) { | |
2239 | case DCB_OUTPUT_TMDS: | |
2240 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); | |
2241 | type = DRM_MODE_ENCODER_TMDS; | |
2242 | break; | |
2243 | case DCB_OUTPUT_DP: | |
2244 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); | |
2245 | type = DRM_MODE_ENCODER_TMDS; | |
2246 | break; | |
2247 | default: | |
2248 | return -ENODEV; | |
2249 | } | |
2250 | ||
2251 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2252 | if (!nv_encoder) | |
2253 | return -ENOMEM; | |
2254 | nv_encoder->dcb = dcbe; | |
2255 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2256 | nv_encoder->i2c = ddc; | |
2257 | ||
2258 | encoder = to_drm_encoder(nv_encoder); | |
2259 | encoder->possible_crtcs = dcbe->heads; | |
2260 | encoder->possible_clones = 0; | |
2261 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); | |
2262 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); | |
2263 | ||
2264 | drm_mode_connector_attach_encoder(connector, encoder); | |
2265 | return 0; | |
2266 | } | |
2267 | ||
ab0af559 BS |
2268 | /****************************************************************************** |
2269 | * Framebuffer | |
2270 | *****************************************************************************/ | |
2271 | ||
8a423647 | 2272 | static void |
0ad72863 | 2273 | nv50_fbdma_fini(struct nv50_fbdma *fbdma) |
8a423647 | 2274 | { |
0ad72863 BS |
2275 | int i; |
2276 | for (i = 0; i < ARRAY_SIZE(fbdma->base); i++) | |
2277 | nvif_object_fini(&fbdma->base[i]); | |
2278 | nvif_object_fini(&fbdma->core); | |
8a423647 BS |
2279 | list_del(&fbdma->head); |
2280 | kfree(fbdma); | |
2281 | } | |
2282 | ||
2283 | static int | |
2284 | nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind) | |
2285 | { | |
2286 | struct nouveau_drm *drm = nouveau_drm(dev); | |
2287 | struct nv50_disp *disp = nv50_disp(dev); | |
2288 | struct nv50_mast *mast = nv50_mast(dev); | |
4acfd707 BS |
2289 | struct __attribute__ ((packed)) { |
2290 | struct nv_dma_v0 base; | |
2291 | union { | |
2292 | struct nv50_dma_v0 nv50; | |
2293 | struct gf100_dma_v0 gf100; | |
2294 | struct gf110_dma_v0 gf110; | |
2295 | }; | |
2296 | } args = {}; | |
8a423647 BS |
2297 | struct nv50_fbdma *fbdma; |
2298 | struct drm_crtc *crtc; | |
4acfd707 | 2299 | u32 size = sizeof(args.base); |
8a423647 BS |
2300 | int ret; |
2301 | ||
2302 | list_for_each_entry(fbdma, &disp->fbdma, head) { | |
0ad72863 | 2303 | if (fbdma->core.handle == name) |
8a423647 BS |
2304 | return 0; |
2305 | } | |
2306 | ||
2307 | fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL); | |
2308 | if (!fbdma) | |
2309 | return -ENOMEM; | |
2310 | list_add(&fbdma->head, &disp->fbdma); | |
8a423647 | 2311 | |
4acfd707 BS |
2312 | args.base.target = NV_DMA_V0_TARGET_VRAM; |
2313 | args.base.access = NV_DMA_V0_ACCESS_RDWR; | |
2314 | args.base.start = offset; | |
2315 | args.base.limit = offset + length - 1; | |
8a423647 | 2316 | |
967e7bde | 2317 | if (drm->device.info.chipset < 0x80) { |
4acfd707 BS |
2318 | args.nv50.part = NV50_DMA_V0_PART_256; |
2319 | size += sizeof(args.nv50); | |
8a423647 | 2320 | } else |
967e7bde | 2321 | if (drm->device.info.chipset < 0xc0) { |
4acfd707 BS |
2322 | args.nv50.part = NV50_DMA_V0_PART_256; |
2323 | args.nv50.kind = kind; | |
2324 | size += sizeof(args.nv50); | |
8a423647 | 2325 | } else |
967e7bde | 2326 | if (drm->device.info.chipset < 0xd0) { |
4acfd707 BS |
2327 | args.gf100.kind = kind; |
2328 | size += sizeof(args.gf100); | |
8a423647 | 2329 | } else { |
4acfd707 BS |
2330 | args.gf110.page = GF110_DMA_V0_PAGE_LP; |
2331 | args.gf110.kind = kind; | |
2332 | size += sizeof(args.gf110); | |
8a423647 BS |
2333 | } |
2334 | ||
2335 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
0ad72863 BS |
2336 | struct nv50_head *head = nv50_head(crtc); |
2337 | int ret = nvif_object_init(&head->sync.base.base.user, NULL, | |
4acfd707 | 2338 | name, NV_DMA_IN_MEMORY, &args, size, |
0ad72863 | 2339 | &fbdma->base[head->base.index]); |
8a423647 | 2340 | if (ret) { |
0ad72863 | 2341 | nv50_fbdma_fini(fbdma); |
8a423647 BS |
2342 | return ret; |
2343 | } | |
2344 | } | |
2345 | ||
0ad72863 | 2346 | ret = nvif_object_init(&mast->base.base.user, NULL, name, |
4acfd707 | 2347 | NV_DMA_IN_MEMORY, &args, size, |
0ad72863 | 2348 | &fbdma->core); |
8a423647 | 2349 | if (ret) { |
0ad72863 | 2350 | nv50_fbdma_fini(fbdma); |
8a423647 BS |
2351 | return ret; |
2352 | } | |
2353 | ||
2354 | return 0; | |
2355 | } | |
2356 | ||
ab0af559 BS |
2357 | static void |
2358 | nv50_fb_dtor(struct drm_framebuffer *fb) | |
2359 | { | |
2360 | } | |
2361 | ||
2362 | static int | |
2363 | nv50_fb_ctor(struct drm_framebuffer *fb) | |
2364 | { | |
2365 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
2366 | struct nouveau_drm *drm = nouveau_drm(fb->dev); | |
2367 | struct nouveau_bo *nvbo = nv_fb->nvbo; | |
8a423647 | 2368 | struct nv50_disp *disp = nv50_disp(fb->dev); |
8a423647 BS |
2369 | u8 kind = nouveau_bo_tile_layout(nvbo) >> 8; |
2370 | u8 tile = nvbo->tile_mode; | |
ab0af559 BS |
2371 | |
2372 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { | |
2373 | NV_ERROR(drm, "framebuffer requires contiguous bo\n"); | |
2374 | return -EINVAL; | |
2375 | } | |
2376 | ||
967e7bde | 2377 | if (drm->device.info.chipset >= 0xc0) |
8a423647 BS |
2378 | tile >>= 4; /* yep.. */ |
2379 | ||
ab0af559 BS |
2380 | switch (fb->depth) { |
2381 | case 8: nv_fb->r_format = 0x1e00; break; | |
2382 | case 15: nv_fb->r_format = 0xe900; break; | |
2383 | case 16: nv_fb->r_format = 0xe800; break; | |
2384 | case 24: | |
2385 | case 32: nv_fb->r_format = 0xcf00; break; | |
2386 | case 30: nv_fb->r_format = 0xd100; break; | |
2387 | default: | |
2388 | NV_ERROR(drm, "unknown depth %d\n", fb->depth); | |
2389 | return -EINVAL; | |
2390 | } | |
2391 | ||
648d4dfd | 2392 | if (disp->disp->oclass < G82_DISP) { |
8a423647 BS |
2393 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2394 | (fb->pitches[0] | 0x00100000); | |
2395 | nv_fb->r_format |= kind << 16; | |
2396 | } else | |
648d4dfd | 2397 | if (disp->disp->oclass < GF110_DISP) { |
8a423647 BS |
2398 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2399 | (fb->pitches[0] | 0x00100000); | |
ab0af559 | 2400 | } else { |
8a423647 BS |
2401 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2402 | (fb->pitches[0] | 0x01000000); | |
ab0af559 | 2403 | } |
8a423647 | 2404 | nv_fb->r_handle = 0xffff0000 | kind; |
ab0af559 | 2405 | |
f392ec4b BS |
2406 | return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0, |
2407 | drm->device.info.ram_user, kind); | |
ab0af559 BS |
2408 | } |
2409 | ||
26f6d88b BS |
2410 | /****************************************************************************** |
2411 | * Init | |
2412 | *****************************************************************************/ | |
ab0af559 | 2413 | |
2a44e499 | 2414 | void |
e225f446 | 2415 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 2416 | { |
26f6d88b BS |
2417 | } |
2418 | ||
2419 | int | |
e225f446 | 2420 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 2421 | { |
9f9bdaaf BS |
2422 | struct nv50_disp *disp = nv50_disp(dev); |
2423 | struct drm_crtc *crtc; | |
2424 | u32 *push; | |
2425 | ||
2426 | push = evo_wait(nv50_mast(dev), 32); | |
2427 | if (!push) | |
2428 | return -EBUSY; | |
2429 | ||
2430 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2431 | struct nv50_sync *sync = nv50_sync(crtc); | |
2432 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); | |
bdb8c212 | 2433 | } |
efd272a7 | 2434 | |
9f9bdaaf | 2435 | evo_mthd(push, 0x0088, 1); |
f45f55c4 | 2436 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
9f9bdaaf BS |
2437 | evo_kick(push, nv50_mast(dev)); |
2438 | return 0; | |
26f6d88b BS |
2439 | } |
2440 | ||
2441 | void | |
e225f446 | 2442 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 2443 | { |
e225f446 | 2444 | struct nv50_disp *disp = nv50_disp(dev); |
8a423647 BS |
2445 | struct nv50_fbdma *fbdma, *fbtmp; |
2446 | ||
2447 | list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) { | |
0ad72863 | 2448 | nv50_fbdma_fini(fbdma); |
8a423647 | 2449 | } |
bdb8c212 | 2450 | |
0ad72863 | 2451 | nv50_dmac_destroy(&disp->mast.base, disp->disp); |
26f6d88b | 2452 | |
816af2f2 | 2453 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
2454 | if (disp->sync) |
2455 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 2456 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 2457 | |
77145f1c | 2458 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
2459 | kfree(disp); |
2460 | } | |
2461 | ||
2462 | int | |
e225f446 | 2463 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 2464 | { |
967e7bde | 2465 | struct nvif_device *device = &nouveau_drm(dev)->device; |
77145f1c | 2466 | struct nouveau_drm *drm = nouveau_drm(dev); |
77145f1c | 2467 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 2468 | struct drm_connector *connector, *tmp; |
e225f446 | 2469 | struct nv50_disp *disp; |
cb75d97e | 2470 | struct dcb_output *dcbe; |
7c5f6a87 | 2471 | int crtcs, ret, i; |
26f6d88b BS |
2472 | |
2473 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
2474 | if (!disp) | |
2475 | return -ENOMEM; | |
8a423647 | 2476 | INIT_LIST_HEAD(&disp->fbdma); |
77145f1c BS |
2477 | |
2478 | nouveau_display(dev)->priv = disp; | |
e225f446 BS |
2479 | nouveau_display(dev)->dtor = nv50_display_destroy; |
2480 | nouveau_display(dev)->init = nv50_display_init; | |
2481 | nouveau_display(dev)->fini = nv50_display_fini; | |
ab0af559 BS |
2482 | nouveau_display(dev)->fb_ctor = nv50_fb_ctor; |
2483 | nouveau_display(dev)->fb_dtor = nv50_fb_dtor; | |
0ad72863 | 2484 | disp->disp = &nouveau_display(dev)->disp; |
26f6d88b | 2485 | |
b5a794b0 BS |
2486 | /* small shared memory area we use for notifiers and semaphores */ |
2487 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
bb6178b0 | 2488 | 0, 0x0000, NULL, NULL, &disp->sync); |
b5a794b0 BS |
2489 | if (!ret) { |
2490 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); | |
04c8c210 | 2491 | if (!ret) { |
b5a794b0 | 2492 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
2493 | if (ret) |
2494 | nouveau_bo_unpin(disp->sync); | |
2495 | } | |
b5a794b0 BS |
2496 | if (ret) |
2497 | nouveau_bo_ref(NULL, &disp->sync); | |
2498 | } | |
2499 | ||
b5a794b0 BS |
2500 | if (ret) |
2501 | goto out; | |
2502 | ||
2503 | /* allocate master evo channel */ | |
410f3ec6 BS |
2504 | ret = nv50_core_create(disp->disp, disp->sync->bo.offset, |
2505 | &disp->mast); | |
b5a794b0 BS |
2506 | if (ret) |
2507 | goto out; | |
2508 | ||
438d99e3 | 2509 | /* create crtc objects to represent the hw heads */ |
648d4dfd | 2510 | if (disp->disp->oclass >= GF110_DISP) |
db2bec18 | 2511 | crtcs = nvif_rd32(device, 0x022448); |
63718a07 BS |
2512 | else |
2513 | crtcs = 2; | |
2514 | ||
7c5f6a87 | 2515 | for (i = 0; i < crtcs; i++) { |
0ad72863 | 2516 | ret = nv50_crtc_create(dev, i); |
438d99e3 BS |
2517 | if (ret) |
2518 | goto out; | |
2519 | } | |
2520 | ||
83fc083c BS |
2521 | /* create encoder/connector objects based on VBIOS DCB table */ |
2522 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
2523 | connector = nouveau_connector_create(dev, dcbe->connector); | |
2524 | if (IS_ERR(connector)) | |
2525 | continue; | |
2526 | ||
eb6313ad BS |
2527 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
2528 | switch (dcbe->type) { | |
2529 | case DCB_OUTPUT_TMDS: | |
2530 | case DCB_OUTPUT_LVDS: | |
2531 | case DCB_OUTPUT_DP: | |
2532 | ret = nv50_sor_create(connector, dcbe); | |
2533 | break; | |
2534 | case DCB_OUTPUT_ANALOG: | |
2535 | ret = nv50_dac_create(connector, dcbe); | |
2536 | break; | |
2537 | default: | |
2538 | ret = -ENODEV; | |
2539 | break; | |
2540 | } | |
2541 | } else { | |
2542 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
2543 | } |
2544 | ||
eb6313ad BS |
2545 | if (ret) { |
2546 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
2547 | dcbe->location, dcbe->type, | |
2548 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 2549 | ret = 0; |
83fc083c BS |
2550 | } |
2551 | } | |
2552 | ||
2553 | /* cull any connectors we created that don't have an encoder */ | |
2554 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
2555 | if (connector->encoder_ids[0]) | |
2556 | continue; | |
2557 | ||
77145f1c | 2558 | NV_WARN(drm, "%s has no encoders, removing\n", |
8c6c361a | 2559 | connector->name); |
83fc083c BS |
2560 | connector->funcs->destroy(connector); |
2561 | } | |
2562 | ||
26f6d88b BS |
2563 | out: |
2564 | if (ret) | |
e225f446 | 2565 | nv50_display_destroy(dev); |
26f6d88b BS |
2566 | return ret; |
2567 | } |