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drm/nv50: remove some unnecessary PDISPLAY init
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "nv50_display.h"
28#include "nouveau_crtc.h"
29#include "nouveau_encoder.h"
30#include "nouveau_connector.h"
31#include "nouveau_fb.h"
4abe3520 32#include "nouveau_fbcon.h"
a8eaebc6 33#include "nouveau_ramht.h"
6ee73861
BS		 34#include "drm_crtc_helper.h"
35
8597a1ba
BS		 36static inline int
37nv50_sor_nr(struct drm_device *dev)
38{
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40
41 if (dev_priv->chipset < 0x90 ||
42 dev_priv->chipset == 0x92 ||
43 dev_priv->chipset == 0xa0)
44 return 2;
45
46 return 4;
47}
48
6ee73861
BS		 49static void
50nv50_evo_channel_del(struct nouveau_channel **pchan)
51{
52 struct nouveau_channel *chan = *pchan;
53
54 if (!chan)
55 return;
56 *pchan = NULL;
57
58 nouveau_gpuobj_channel_takedown(chan);
9d59e8a1 59 nouveau_bo_unmap(chan->pushbuf_bo);
6ee73861
BS		 60 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
61
62 if (chan->user)
63 iounmap(chan->user);
64
65 kfree(chan);
66}
67
68static int
69nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
70 uint32_t tile_flags, uint32_t magic_flags,
71 uint32_t offset, uint32_t limit)
72{
73 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
74 struct drm_device *dev = evo->dev;
75 struct nouveau_gpuobj *obj = NULL;
76 int ret;
77
78 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
79 if (ret)
80 return ret;
81 obj->engine = NVOBJ_ENGINE_DISPLAY;
82
b3beb167
BS		 83 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
84 nv_wo32(obj, 4, limit);
85 nv_wo32(obj, 8, offset);
86 nv_wo32(obj, 12, 0x00000000);
87 nv_wo32(obj, 16, 0x00000000);
0165d15d 88 if (dev_priv->card_type < NV_C0)
b3beb167 89 nv_wo32(obj, 20, 0x00010000);
0165d15d 90 else
b3beb167 91 nv_wo32(obj, 20, 0x00020000);
f56cb86f 92 dev_priv->engine.instmem.flush(dev);
6ee73861 93
a8eaebc6
BS		 94 ret = nouveau_ramht_insert(evo, name, obj);
95 nouveau_gpuobj_ref(NULL, &obj);
96 if (ret) {
97 return ret;
98 }
99
6ee73861
BS		 100 return 0;
101}
102
103static int
104nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
105{
106 struct drm_nouveau_private *dev_priv = dev->dev_private;
a8eaebc6 107 struct nouveau_gpuobj *ramht = NULL;
6ee73861
BS		 108 struct nouveau_channel *chan;
109 int ret;
110
111 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
112 if (!chan)
113 return -ENOMEM;
114 *pchan = chan;
115
116 chan->id = -1;
117 chan->dev = dev;
118 chan->user_get = 4;
119 chan->user_put = 0;
120
a8eaebc6
BS		 121 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
122 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
6ee73861
BS		 123 if (ret) {
124 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
125 nv50_evo_channel_del(pchan);
126 return ret;
127 }
128
de3a6c0a 129 ret = drm_mm_init(&chan->ramin_heap, 0, 32768);
6ee73861
BS		 130 if (ret) {
131 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
132 nv50_evo_channel_del(pchan);
133 return ret;
134 }
135
a8eaebc6 136 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
6ee73861
BS		 137 if (ret) {
138 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
139 nv50_evo_channel_del(pchan);
140 return ret;
141 }
142
a8eaebc6
BS		 143 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
144 nouveau_gpuobj_ref(NULL, &ramht);
145 if (ret) {
146 nv50_evo_channel_del(pchan);
147 return ret;
148 }
149
6ee73861
BS		 150 if (dev_priv->chipset != 0x50) {
151 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
152 0, 0xffffffff);
153 if (ret) {
154 nv50_evo_channel_del(pchan);
155 return ret;
156 }
157
158
159 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
160 0, 0xffffffff);
161 if (ret) {
162 nv50_evo_channel_del(pchan);
163 return ret;
164 }
165 }
166
167 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
a76fb4e8 168 0, dev_priv->vram_size);
6ee73861
BS		 169 if (ret) {
170 nv50_evo_channel_del(pchan);
171 return ret;
172 }
173
174 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
175 false, true, &chan->pushbuf_bo);
176 if (ret == 0)
177 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
178 if (ret) {
179 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
180 nv50_evo_channel_del(pchan);
181 return ret;
182 }
183
184 ret = nouveau_bo_map(chan->pushbuf_bo);
185 if (ret) {
186 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
187 nv50_evo_channel_del(pchan);
188 return ret;
189 }
190
191 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
192 NV50_PDISPLAY_USER(0), PAGE_SIZE);
193 if (!chan->user) {
194 NV_ERROR(dev, "Error mapping EVO control regs.\n");
195 nv50_evo_channel_del(pchan);
196 return -ENOMEM;
197 }
198
199 return 0;
200}
201
c88c2e06
FJ		 202int
203nv50_display_early_init(struct drm_device *dev)
204{
205 return 0;
206}
207
208void
209nv50_display_late_takedown(struct drm_device *dev)
210{
211}
212
6ee73861
BS		 213int
214nv50_display_init(struct drm_device *dev)
215{
216 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
ee2e0131 218 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861
BS		 219 struct nouveau_channel *evo = dev_priv->evo;
220 struct drm_connector *connector;
6ee73861 221 int ret, i;
cbb4b608
BS		 222 u64 start;
223 u32 val;
6ee73861 224
ef2bb506 225 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 226
227 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
228 /*
229 * I think the 0x006101XX range is some kind of main control area
230 * that enables things.
231 */
232 /* CRTC? */
233 for (i = 0; i < 2; i++) {
234 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
235 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
236 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
237 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
238 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
239 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
240 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
241 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
242 }
243 /* DAC */
244 for (i = 0; i < 3; i++) {
245 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
246 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
247 }
248 /* SOR */
8597a1ba 249 for (i = 0; i < nv50_sor_nr(dev); i++) {
6ee73861
BS		 250 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
251 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
252 }
8597a1ba 253 /* EXT */
6ee73861
BS		 254 for (i = 0; i < 3; i++) {
255 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
256 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
257 }
258
259 for (i = 0; i < 3; i++) {
260 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
261 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
262 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
263 }
264
6ee73861
BS		 265 /* The precise purpose is unknown, i suspect it has something to do
266 * with text mode.
267 */
268 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
269 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
270 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
4b5c152a 271 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
6ee73861
BS		 272 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
273 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
274 nv_rd32(dev, 0x6194e8));
275 return -EBUSY;
276 }
277 }
278
279 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
280 * stuck in some unspecified state
281 */
282 start = ptimer->read(dev);
283 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
284 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
285 if ((val & 0x9f0000) == 0x20000)
286 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
287 val | 0x800000);
288
289 if ((val & 0x3f0000) == 0x30000)
290 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
291 val | 0x200000);
292
293 if (ptimer->read(dev) - start > 1000000000ULL) {
294 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
295 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
296 return -EBUSY;
297 }
298 }
299
300 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
301 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
4b5c152a
FJ		 302 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
303 0x40000000, 0x40000000)) {
6ee73861
BS		 304 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
305 NV_ERROR(dev, "0x610200 = 0x%08x\n",
306 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
307 return -EBUSY;
308 }
309
310 for (i = 0; i < 2; i++) {
311 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
4b5c152a 312 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
6ee73861
BS		 313 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
314 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
315 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
316 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
317 return -EBUSY;
318 }
319
320 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
321 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
4b5c152a 322 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
6ee73861
BS		 323 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
324 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
325 NV_ERROR(dev, "timeout: "
326 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
327 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
328 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
329 return -EBUSY;
330 }
331 }
332
a8eaebc6 333 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
6ee73861
BS		 334
335 /* initialise fifo */
336 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
d961db75 337 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
6ee73861
BS		 338 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
339 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
340 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
341 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
4b5c152a 342 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
6ee73861
BS		 343 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
344 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
345 return -EBUSY;
346 }
347 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
348 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
349 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
350 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
351 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
352 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
353 nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
354
355 evo->dma.max = (4096/4) - 2;
356 evo->dma.put = 0;
357 evo->dma.cur = evo->dma.put;
358 evo->dma.free = evo->dma.max - evo->dma.cur;
359
360 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
361 if (ret)
362 return ret;
363
364 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
365 OUT_RING(evo, 0);
366
367 ret = RING_SPACE(evo, 11);
368 if (ret)
369 return ret;
370 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
371 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
372 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
373 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
374 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
375 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
376 OUT_RING(evo, 0);
377 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
378 OUT_RING(evo, 0);
379 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
380 OUT_RING(evo, 0);
381 FIRE_RING(evo);
4b5c152a 382 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
6ee73861
BS		 383 NV_ERROR(dev, "evo pushbuf stalled\n");
384
385 /* enable clock change interrupts. */
386 nv_wr32(dev, 0x610028, 0x00010001);
387 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
388 NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
389 NV50_PDISPLAY_INTR_EN_CLK_UNK40));
390
391 /* enable hotplug interrupts */
6ee73861
BS		 392 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
393 struct nouveau_connector *conn = nouveau_connector(connector);
6ee73861 394
0ccb3a75
BS		 395 if (conn->dcb->gpio_tag == 0xff)
396 continue;
397
ee2e0131 398 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
6ee73861
BS		 399 }
400
401 return 0;
402}
403
404static int nv50_display_disable(struct drm_device *dev)
405{
406 struct drm_nouveau_private *dev_priv = dev->dev_private;
407 struct drm_crtc *drm_crtc;
408 int ret, i;
409
ef2bb506 410 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 411
412 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
413 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
414
415 nv50_crtc_blank(crtc, true);
416 }
417
418 ret = RING_SPACE(dev_priv->evo, 2);
419 if (ret == 0) {
420 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
421 OUT_RING(dev_priv->evo, 0);
422 }
423 FIRE_RING(dev_priv->evo);
424
425 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
426 * cleaning up?
427 */
428 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
429 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
430 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
431
432 if (!crtc->base.enabled)
433 continue;
434
435 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
4b5c152a 436 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
6ee73861
BS		 437 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
438 "0x%08x\n", mask, mask);
439 NV_ERROR(dev, "0x610024 = 0x%08x\n",
440 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
441 }
442 }
443
444 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
445 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
4b5c152a 446 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
6ee73861
BS		 447 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
448 NV_ERROR(dev, "0x610200 = 0x%08x\n",
449 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
450 }
451
452 for (i = 0; i < 3; i++) {
4b5c152a 453 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
6ee73861
BS		 454 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
455 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
456 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
457 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
458 }
459 }
460
461 /* disable interrupts. */
462 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
463
464 /* disable hotplug interrupts */
465 nv_wr32(dev, 0xe054, 0xffffffff);
466 nv_wr32(dev, 0xe050, 0x00000000);
467 if (dev_priv->chipset >= 0x90) {
468 nv_wr32(dev, 0xe074, 0xffffffff);
469 nv_wr32(dev, 0xe070, 0x00000000);
470 }
471 return 0;
472}
473
474int nv50_display_create(struct drm_device *dev)
475{
476 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 477 struct dcb_table *dcb = &dev_priv->vbios.dcb;
8f1a6086 478 struct drm_connector *connector, *ct;
6ee73861
BS		 479 int ret, i;
480
ef2bb506 481 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 482
483 /* init basic kernel modesetting */
484 drm_mode_config_init(dev);
485
486 /* Initialise some optional connector properties. */
487 drm_mode_create_scaling_mode_property(dev);
488 drm_mode_create_dithering_property(dev);
489
490 dev->mode_config.min_width = 0;
491 dev->mode_config.min_height = 0;
492
493 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
494
495 dev->mode_config.max_width = 8192;
496 dev->mode_config.max_height = 8192;
497
498 dev->mode_config.fb_base = dev_priv->fb_phys;
499
500 /* Create EVO channel */
501 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
502 if (ret) {
503 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
504 return ret;
505 }
506
507 /* Create CRTC objects */
508 for (i = 0; i < 2; i++)
509 nv50_crtc_create(dev, i);
510
511 /* We setup the encoders from the BIOS table */
512 for (i = 0 ; i < dcb->entries; i++) {
513 struct dcb_entry *entry = &dcb->entry[i];
514
515 if (entry->location != DCB_LOC_ON_CHIP) {
516 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
517 entry->type, ffs(entry->or) - 1);
518 continue;
519 }
520
8f1a6086
BS		 521 connector = nouveau_connector_create(dev, entry->connector);
522 if (IS_ERR(connector))
523 continue;
524
6ee73861
BS		 525 switch (entry->type) {
526 case OUTPUT_TMDS:
527 case OUTPUT_LVDS:
528 case OUTPUT_DP:
8f1a6086 529 nv50_sor_create(connector, entry);
6ee73861
BS		 530 break;
531 case OUTPUT_ANALOG:
8f1a6086 532 nv50_dac_create(connector, entry);
6ee73861
BS		 533 break;
534 default:
535 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
536 continue;
537 }
6ee73861
BS		 538 }
539
8f1a6086
BS		 540 list_for_each_entry_safe(connector, ct,
541 &dev->mode_config.connector_list, head) {
542 if (!connector->encoder_ids[0]) {
543 NV_WARN(dev, "%s has no encoders, removing\n",
544 drm_get_connector_name(connector));
545 connector->funcs->destroy(connector);
546 }
6ee73861
BS		 547 }
548
549 ret = nv50_display_init(dev);
a1663ed3
BS		 550 if (ret) {
551 nv50_display_destroy(dev);
6ee73861 552 return ret;
a1663ed3 553 }
6ee73861
BS		 554
555 return 0;
556}
557
c88c2e06
FJ		 558void
559nv50_display_destroy(struct drm_device *dev)
6ee73861
BS		 560{
561 struct drm_nouveau_private *dev_priv = dev->dev_private;
562
ef2bb506 563 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 564
565 drm_mode_config_cleanup(dev);
566
567 nv50_display_disable(dev);
568 nv50_evo_channel_del(&dev_priv->evo);
6ee73861
BS		 569}
570
87c0e0e5
BS		 571static u16
572nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
573 u32 mc, int pxclk)
6ee73861
BS		 574{
575 struct drm_nouveau_private *dev_priv = dev->dev_private;
75c722d7
BS		 576 struct nouveau_connector *nv_connector = NULL;
577 struct drm_encoder *encoder;
04a39c57 578 struct nvbios *bios = &dev_priv->vbios;
87c0e0e5 579 u32 script = 0, or;
6ee73861 580
75c722d7
BS		 581 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
582 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
583
87c0e0e5 584 if (nv_encoder->dcb != dcb)
75c722d7
BS		 585 continue;
586
587 nv_connector = nouveau_encoder_connector_get(nv_encoder);
588 break;
589 }
590
87c0e0e5
BS		 591 or = ffs(dcb->or) - 1;
592 switch (dcb->type) {
6ee73861
BS		 593 case OUTPUT_LVDS:
594 script = (mc >> 8) & 0xf;
04a39c57 595 if (bios->fp_no_ddc) {
6ee73861
BS		 596 if (bios->fp.dual_link)
597 script |= 0x0100;
598 if (bios->fp.if_is_24bit)
599 script |= 0x0200;
600 } else {
601 if (pxclk >= bios->fp.duallink_transition_clk) {
602 script |= 0x0100;
603 if (bios->fp.strapless_is_24bit & 2)
604 script |= 0x0200;
605 } else
606 if (bios->fp.strapless_is_24bit & 1)
607 script |= 0x0200;
75c722d7
BS		 608
609 if (nv_connector && nv_connector->edid &&
610 (nv_connector->edid->revision >= 4) &&
611 (nv_connector->edid->input & 0x70) >= 0x20)
612 script |= 0x0200;
6ee73861
BS		 613 }
614
615 if (nouveau_uscript_lvds >= 0) {
616 NV_INFO(dev, "override script 0x%04x with 0x%04x "
617 "for output LVDS-%d\n", script,
618 nouveau_uscript_lvds, or);
619 script = nouveau_uscript_lvds;
620 }
621 break;
622 case OUTPUT_TMDS:
623 script = (mc >> 8) & 0xf;
624 if (pxclk >= 165000)
625 script |= 0x0100;
626
627 if (nouveau_uscript_tmds >= 0) {
628 NV_INFO(dev, "override script 0x%04x with 0x%04x "
629 "for output TMDS-%d\n", script,
630 nouveau_uscript_tmds, or);
631 script = nouveau_uscript_tmds;
632 }
633 break;
634 case OUTPUT_DP:
635 script = (mc >> 8) & 0xf;
636 break;
637 case OUTPUT_ANALOG:
638 script = 0xff;
639 break;
640 default:
641 NV_ERROR(dev, "modeset on unsupported output type!\n");
642 break;
643 }
644
645 return script;
646}
647
648static void
649nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
650{
651 struct drm_nouveau_private *dev_priv = dev->dev_private;
652 struct nouveau_channel *chan;
653 struct list_head *entry, *tmp;
654
655 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
656 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
657
658 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
659 chan->nvsw.vblsem_rval);
660 list_del(&chan->nvsw.vbl_wait);
661 }
662}
663
664static void
665nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
666{
667 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
668
669 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
670 nv50_display_vblank_crtc_handler(dev, 0);
671
672 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
673 nv50_display_vblank_crtc_handler(dev, 1);
674
675 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
676 NV50_PDISPLAY_INTR_EN) & ~intr);
677 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
678}
679
680static void
681nv50_display_unk10_handler(struct drm_device *dev)
682{
87c0e0e5
BS		 683 struct drm_nouveau_private *dev_priv = dev->dev_private;
684 u32 unk30 = nv_rd32(dev, 0x610030), mc;
685 int i, crtc, or, type = OUTPUT_ANY;
6ee73861 686
87c0e0e5
BS		 687 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
688 dev_priv->evo_irq.dcb = NULL;
6ee73861
BS		 689
690 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
691
87c0e0e5
BS		 692 /* Determine which CRTC we're dealing with, only 1 ever will be
693 * signalled at the same time with the current nouveau code.
694 */
695 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
696 if (crtc < 0)
697 goto ack;
698
699 /* Nothing needs to be done for the encoder */
700 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
701 if (crtc < 0)
702 goto ack;
6ee73861 703
87c0e0e5
BS		 704 /* Find which encoder was connected to the CRTC */
705 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
706 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
707 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
708 if (!(mc & (1 << crtc)))
709 continue;
710
711 switch ((mc & 0x00000f00) >> 8) {
712 case 0: type = OUTPUT_ANALOG; break;
713 case 1: type = OUTPUT_TV; break;
714 default:
715 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
716 goto ack;
717 }
718
719 or = i;
720 }
721
8597a1ba 722 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
87c0e0e5
BS		 723 if (dev_priv->chipset < 0x90 ||
724 dev_priv->chipset == 0x92 ||
725 dev_priv->chipset == 0xa0)
726 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
727 else
728 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
729
730 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
731 if (!(mc & (1 << crtc)))
732 continue;
733
734 switch ((mc & 0x00000f00) >> 8) {
735 case 0: type = OUTPUT_LVDS; break;
736 case 1: type = OUTPUT_TMDS; break;
737 case 2: type = OUTPUT_TMDS; break;
738 case 5: type = OUTPUT_TMDS; break;
739 case 8: type = OUTPUT_DP; break;
740 case 9: type = OUTPUT_DP; break;
741 default:
742 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
743 goto ack;
744 }
745
746 or = i;
747 }
748
749 /* There was no encoder to disable */
750 if (type == OUTPUT_ANY)
751 goto ack;
752
753 /* Disable the encoder */
754 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
755 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
756
757 if (dcb->type == type && (dcb->or & (1 << or))) {
758 nouveau_bios_run_display_table(dev, dcb, 0, -1);
759 dev_priv->evo_irq.dcb = dcb;
760 goto ack;
761 }
762 }
763
764 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
6ee73861
BS		 765ack:
766 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
767 nv_wr32(dev, 0x610030, 0x80000000);
768}
769
afa3b4c3
BS		 770static void
771nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
772{
773 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
774 struct drm_encoder *encoder;
775 uint32_t tmp, unk0 = 0, unk1 = 0;
776
777 if (dcb->type != OUTPUT_DP)
778 return;
779
780 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
781 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
782
783 if (nv_encoder->dcb == dcb) {
784 unk0 = nv_encoder->dp.unk0;
785 unk1 = nv_encoder->dp.unk1;
786 break;
787 }
788 }
789
790 if (unk0 || unk1) {
791 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
792 tmp &= 0xfffffe03;
793 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
794
795 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
796 tmp &= 0xfef080c0;
797 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
798 }
799}
800
6ee73861
BS		 801static void
802nv50_display_unk20_handler(struct drm_device *dev)
803{
87c0e0e5
BS		 804 struct drm_nouveau_private *dev_priv = dev->dev_private;
805 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
806 struct dcb_entry *dcb;
807 int i, crtc, or, type = OUTPUT_ANY;
6ee73861 808
87c0e0e5
BS		 809 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
810 dcb = dev_priv->evo_irq.dcb;
811 if (dcb) {
812 nouveau_bios_run_display_table(dev, dcb, 0, -2);
813 dev_priv->evo_irq.dcb = NULL;
814 }
815
816 /* CRTC clock change requested? */
817 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
818 if (crtc >= 0) {
819 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
820 pclk &= 0x003fffff;
821
822 nv50_crtc_set_clock(dev, crtc, pclk);
823
824 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
825 tmp &= ~0x000000f;
826 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
827 }
828
829 /* Nothing needs to be done for the encoder */
830 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
831 if (crtc < 0)
6ee73861 832 goto ack;
87c0e0e5 833 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
6ee73861 834
87c0e0e5
BS		 835 /* Find which encoder is connected to the CRTC */
836 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
837 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
838 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
839 if (!(mc & (1 << crtc)))
840 continue;
6ee73861 841
87c0e0e5
BS		 842 switch ((mc & 0x00000f00) >> 8) {
843 case 0: type = OUTPUT_ANALOG; break;
844 case 1: type = OUTPUT_TV; break;
845 default:
846 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
847 goto ack;
848 }
849
850 or = i;
851 }
852
8597a1ba 853 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
87c0e0e5
BS		 854 if (dev_priv->chipset < 0x90 ||
855 dev_priv->chipset == 0x92 ||
856 dev_priv->chipset == 0xa0)
857 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
858 else
859 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
860
861 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
862 if (!(mc & (1 << crtc)))
863 continue;
864
865 switch ((mc & 0x00000f00) >> 8) {
866 case 0: type = OUTPUT_LVDS; break;
867 case 1: type = OUTPUT_TMDS; break;
868 case 2: type = OUTPUT_TMDS; break;
869 case 5: type = OUTPUT_TMDS; break;
870 case 8: type = OUTPUT_DP; break;
871 case 9: type = OUTPUT_DP; break;
872 default:
873 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
874 goto ack;
875 }
6ee73861 876
87c0e0e5
BS		 877 or = i;
878 }
6ee73861 879
87c0e0e5
BS		 880 if (type == OUTPUT_ANY)
881 goto ack;
6ee73861 882
87c0e0e5
BS		 883 /* Enable the encoder */
884 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
885 dcb = &dev_priv->vbios.dcb.entry[i];
886 if (dcb->type == type && (dcb->or & (1 << or)))
887 break;
888 }
afa3b4c3 889
87c0e0e5
BS		 890 if (i == dev_priv->vbios.dcb.entries) {
891 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
892 goto ack;
893 }
894
895 script = nv50_display_script_select(dev, dcb, mc, pclk);
896 nouveau_bios_run_display_table(dev, dcb, script, pclk);
6ee73861 897
87c0e0e5 898 nv50_display_unk20_dp_hack(dev, dcb);
87c0e0e5
BS		 899
900 if (dcb->type != OUTPUT_ANALOG) {
6ee73861
BS		 901 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
902 tmp &= ~0x00000f0f;
903 if (script & 0x0100)
904 tmp |= 0x00000101;
905 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
906 } else {
907 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
908 }
909
87c0e0e5
BS		 910 dev_priv->evo_irq.dcb = dcb;
911 dev_priv->evo_irq.pclk = pclk;
912 dev_priv->evo_irq.script = script;
913
6ee73861
BS		 914ack:
915 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
916 nv_wr32(dev, 0x610030, 0x80000000);
917}
918
271f29e7
BS		 919/* If programming a TMDS output on a SOR that can also be configured for
920 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
921 *
922 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
923 * the VBIOS scripts on at least one board I have only switch it off on
924 * link 0, causing a blank display if the output has previously been
925 * programmed for DisplayPort.
926 */
927static void
928nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
929{
930 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
931 struct drm_encoder *encoder;
932 u32 tmp;
933
934 if (dcb->type != OUTPUT_TMDS)
935 return;
936
937 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
938 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
939
940 if (nv_encoder->dcb->type == OUTPUT_DP &&
941 nv_encoder->dcb->or & (1 << or)) {
942 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
943 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
944 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
945 break;
946 }
947 }
948}
949
6ee73861
BS		 950static void
951nv50_display_unk40_handler(struct drm_device *dev)
952{
87c0e0e5
BS		 953 struct drm_nouveau_private *dev_priv = dev->dev_private;
954 struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
955 u16 script = dev_priv->evo_irq.script;
956 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
6ee73861 957
87c0e0e5
BS		 958 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
959 dev_priv->evo_irq.dcb = NULL;
960 if (!dcb)
6ee73861 961 goto ack;
6ee73861 962
87c0e0e5 963 nouveau_bios_run_display_table(dev, dcb, script, -pclk);
271f29e7
BS		 964 nv50_display_unk40_dp_set_tmds(dev, dcb);
965
6ee73861
BS		 966ack:
967 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
968 nv_wr32(dev, 0x610030, 0x80000000);
969 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
970}
971
972void
973nv50_display_irq_handler_bh(struct work_struct *work)
974{
975 struct drm_nouveau_private *dev_priv =
976 container_of(work, struct drm_nouveau_private, irq_work);
977 struct drm_device *dev = dev_priv->dev;
978
979 for (;;) {
980 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
981 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
982
ef2bb506 983 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 984
985 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
986 nv50_display_unk10_handler(dev);
987 else
988 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
989 nv50_display_unk20_handler(dev);
990 else
991 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
992 nv50_display_unk40_handler(dev);
993 else
994 break;
995 }
996
997 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
998}
999
1000static void
1001nv50_display_error_handler(struct drm_device *dev)
1002{
1003 uint32_t addr, data;
1004
1005 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
1006 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
1007 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
1008
1009 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
1010 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
1011
1012 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1013}
1014
a5acac66
BS		 1015void
1016nv50_display_irq_hotplug_bh(struct work_struct *work)
6ee73861 1017{
a5acac66
BS		 1018 struct drm_nouveau_private *dev_priv =
1019 container_of(work, struct drm_nouveau_private, hpd_work);
1020 struct drm_device *dev = dev_priv->dev;
6ee73861
BS		 1021 struct drm_connector *connector;
1022 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1023 uint32_t unplug_mask, plug_mask, change_mask;
ab838338 1024 uint32_t hpd0, hpd1;
6ee73861 1025
ab838338
AL		 1026 spin_lock_irq(&dev_priv->hpd_state.lock);
1027 hpd0 = dev_priv->hpd_state.hpd0_bits;
1028 dev_priv->hpd_state.hpd0_bits = 0;
1029 hpd1 = dev_priv->hpd_state.hpd1_bits;
1030 dev_priv->hpd_state.hpd1_bits = 0;
1031 spin_unlock_irq(&dev_priv->hpd_state.lock);
1032
1033 hpd0 &= nv_rd32(dev, 0xe050);
6ee73861 1034 if (dev_priv->chipset >= 0x90)
ab838338 1035 hpd1 &= nv_rd32(dev, 0xe070);
6ee73861
BS		 1036
1037 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1038 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1039 change_mask = plug_mask | unplug_mask;
1040
1041 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1042 struct drm_encoder_helper_funcs *helper;
1043 struct nouveau_connector *nv_connector =
1044 nouveau_connector(connector);
1045 struct nouveau_encoder *nv_encoder;
1046 struct dcb_gpio_entry *gpio;
1047 uint32_t reg;
1048 bool plugged;
1049
1050 if (!nv_connector->dcb)
1051 continue;
1052
1053 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1054 if (!gpio || !(change_mask & (1 << gpio->line)))
1055 continue;
1056
1057 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1058 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1059 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1060 drm_get_connector_name(connector)) ;
1061
1062 if (!connector->encoder || !connector->encoder->crtc ||
1063 !connector->encoder->crtc->enabled)
1064 continue;
1065 nv_encoder = nouveau_encoder(connector->encoder);
1066 helper = connector->encoder->helper_private;
1067
1068 if (nv_encoder->dcb->type != OUTPUT_DP)
1069 continue;
1070
1071 if (plugged)
1072 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1073 else
1074 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1075 }
1076
eb1f8e4f 1077 drm_helper_hpd_irq_event(dev);
6ee73861
BS		 1078}
1079
1080void
1081nv50_display_irq_handler(struct drm_device *dev)
1082{
1083 struct drm_nouveau_private *dev_priv = dev->dev_private;
1084 uint32_t delayed = 0;
1085
a5acac66 1086 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
ab838338
AL		 1087 uint32_t hpd0_bits, hpd1_bits = 0;
1088
1089 hpd0_bits = nv_rd32(dev, 0xe054);
1090 nv_wr32(dev, 0xe054, hpd0_bits);
1091
1092 if (dev_priv->chipset >= 0x90) {
1093 hpd1_bits = nv_rd32(dev, 0xe074);
1094 nv_wr32(dev, 0xe074, hpd1_bits);
1095 }
1096
1097 spin_lock(&dev_priv->hpd_state.lock);
1098 dev_priv->hpd_state.hpd0_bits |= hpd0_bits;
1099 dev_priv->hpd_state.hpd1_bits |= hpd1_bits;
1100 spin_unlock(&dev_priv->hpd_state.lock);
1101
1102 queue_work(dev_priv->wq, &dev_priv->hpd_work);
a5acac66 1103 }
6ee73861
BS		 1104
1105 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1106 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1107 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1108 uint32_t clock;
1109
ef2bb506 1110 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 1111
1112 if (!intr0 && !(intr1 & ~delayed))
1113 break;
1114
1115 if (intr0 & 0x00010000) {
1116 nv50_display_error_handler(dev);
1117 intr0 &= ~0x00010000;
1118 }
1119
1120 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1121 nv50_display_vblank_handler(dev, intr1);
1122 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1123 }
1124
1125 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1126 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1127 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1128 if (clock) {
1129 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1130 if (!work_pending(&dev_priv->irq_work))
1131 queue_work(dev_priv->wq, &dev_priv->irq_work);
1132 delayed |= clock;
1133 intr1 &= ~clock;
1134 }
1135
1136 if (intr0) {
1137 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1138 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1139 }
1140
1141 if (intr1) {
1142 NV_ERROR(dev,
1143 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1144 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1145 }
1146 }
1147}
1148
Linux kernel - Deliverables
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