[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_gpio.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"

#include "nv50_display.h"

static void nv50_gpio_isr(struct drm_device *dev);

static int
nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
{
	const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };

	if (gpio->line >= 32)
		return -EINVAL;

	*reg = nv50_gpio_reg[gpio->line >> 3];
	*shift = (gpio->line & 7) << 2;
	return 0;
}

int
nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
{
	struct dcb_gpio_entry *gpio;
	uint32_t r, s, v;

	gpio = nouveau_bios_gpio_entry(dev, tag);
	if (!gpio)
		return -ENOENT;

	if (nv50_gpio_location(gpio, &r, &s))
		return -EINVAL;

	v = nv_rd32(dev, r) >> (s + 2);
	return ((v & 1) == (gpio->state[1] & 1));
}

int
nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
{
	struct dcb_gpio_entry *gpio;
	uint32_t r, s, v;

	gpio = nouveau_bios_gpio_entry(dev, tag);
	if (!gpio)
		return -ENOENT;

	if (nv50_gpio_location(gpio, &r, &s))
		return -EINVAL;

	v  = nv_rd32(dev, r) & ~(0x3 << s);
	v |= (gpio->state[state] ^ 2) << s;
	nv_wr32(dev, r, v);
	return 0;
}

void
nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
{
	struct dcb_gpio_entry *gpio;
	u32 reg, mask;

	gpio = nouveau_bios_gpio_entry(dev, tag);
	if (!gpio) {
		NV_ERROR(dev, "gpio tag 0x%02x not found\n", tag);
		return;
	}

	reg  = gpio->line < 16 ? 0xe050 : 0xe070;
	mask = 0x00010001 << (gpio->line & 0xf);

	nv_wr32(dev, reg + 4, mask);
	nv_mask(dev, reg + 0, mask, on ? mask : 0);
}

int
nv50_gpio_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* disable, and ack any pending gpio interrupts */
	nv_wr32(dev, 0xe050, 0x00000000);
	nv_wr32(dev, 0xe054, 0xffffffff);
	if (dev_priv->chipset >= 0x90) {
		nv_wr32(dev, 0xe070, 0x00000000);
		nv_wr32(dev, 0xe074, 0xffffffff);
	}

	INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
	spin_lock_init(&dev_priv->hpd_state.lock);
	nouveau_irq_register(dev, 21, nv50_gpio_isr);
	return 0;
}

void
nv50_gpio_fini(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nv_wr32(dev, 0xe050, 0x00000000);
	if (dev_priv->chipset >= 0x90)
		nv_wr32(dev, 0xe070, 0x00000000);
	nouveau_irq_unregister(dev, 21);
}

static void
nv50_gpio_isr(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t hpd0_bits, hpd1_bits = 0;

	hpd0_bits = nv_rd32(dev, 0xe054);
	nv_wr32(dev, 0xe054, hpd0_bits);

	if (dev_priv->chipset >= 0x90) {
		hpd1_bits = nv_rd32(dev, 0xe074);
		nv_wr32(dev, 0xe074, hpd1_bits);
	}

	spin_lock(&dev_priv->hpd_state.lock);
	dev_priv->hpd_state.hpd0_bits |= hpd0_bits;
	dev_priv->hpd_state.hpd1_bits |= hpd1_bits;
	spin_unlock(&dev_priv->hpd_state.lock);

	queue_work(dev_priv->wq, &dev_priv->hpd_work);
}
Commit	Line	Data
45284162 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
	27	#include "nouveau_hw.h"
	28
19b7fc7b BS	29	#include "nv50_display.h"
19b7fc7b BS	30
2cbd4c81 BS	31	static void nv50_gpio_isr(struct drm_device *dev);
2cbd4c81 BS	32
45284162 BS	33	static int
	34	nv50_gpio_location(struct dcb_gpio_entry gpio, uint32_t reg, uint32_t *shift)
	35	{
	36	const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
	37
55a4c5c5	38	if (gpio->line >= 32)
45284162 BS	39	return -EINVAL;
	40
	41	*reg = nv50_gpio_reg[gpio->line >> 3];
	42	*shift = (gpio->line & 7) << 2;
	43	return 0;
	44	}
	45
	46	int
	47	nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
	48	{
	49	struct dcb_gpio_entry *gpio;
	50	uint32_t r, s, v;
	51
	52	gpio = nouveau_bios_gpio_entry(dev, tag);
	53	if (!gpio)
	54	return -ENOENT;
	55
	56	if (nv50_gpio_location(gpio, &r, &s))
	57	return -EINVAL;
	58
	59	v = nv_rd32(dev, r) >> (s + 2);
	60	return ((v & 1) == (gpio->state[1] & 1));
	61	}
	62
	63	int
	64	nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
	65	{
	66	struct dcb_gpio_entry *gpio;
	67	uint32_t r, s, v;
	68
	69	gpio = nouveau_bios_gpio_entry(dev, tag);
	70	if (!gpio)
	71	return -ENOENT;
	72
	73	if (nv50_gpio_location(gpio, &r, &s))
	74	return -EINVAL;
	75
	76	v = nv_rd32(dev, r) & ~(0x3 << s);
	77	v \|= (gpio->state[state] ^ 2) << s;
	78	nv_wr32(dev, r, v);
	79	return 0;
	80	}
d0875edd BS	81
	82	void
	83	nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
	84	{
	85	struct dcb_gpio_entry *gpio;
	86	u32 reg, mask;
	87
	88	gpio = nouveau_bios_gpio_entry(dev, tag);
	89	if (!gpio) {
	90	NV_ERROR(dev, "gpio tag 0x%02x not found\n", tag);
	91	return;
	92	}
	93
	94	reg = gpio->line < 16 ? 0xe050 : 0xe070;
	95	mask = 0x00010001 << (gpio->line & 0xf);
	96
	97	nv_wr32(dev, reg + 4, mask);
	98	nv_mask(dev, reg + 0, mask, on ? mask : 0);
	99	}
ee2e0131 BS	100
	101	int
	102	nv50_gpio_init(struct drm_device *dev)
	103	{
	104	struct drm_nouveau_private *dev_priv = dev->dev_private;
	105
	106	/* disable, and ack any pending gpio interrupts */
	107	nv_wr32(dev, 0xe050, 0x00000000);
	108	nv_wr32(dev, 0xe054, 0xffffffff);
	109	if (dev_priv->chipset >= 0x90) {
	110	nv_wr32(dev, 0xe070, 0x00000000);
	111	nv_wr32(dev, 0xe074, 0xffffffff);
	112	}
	113
19b7fc7b BS	114	INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
19b7fc7b BS	115	spin_lock_init(&dev_priv->hpd_state.lock);
2cbd4c81	116	nouveau_irq_register(dev, 21, nv50_gpio_isr);
ee2e0131 BS	117	return 0;
ee2e0131 BS	118	}
2cbd4c81 BS	119
	120	void
	121	nv50_gpio_fini(struct drm_device *dev)
	122	{
	123	struct drm_nouveau_private *dev_priv = dev->dev_private;
	124
	125	nv_wr32(dev, 0xe050, 0x00000000);
	126	if (dev_priv->chipset >= 0x90)
	127	nv_wr32(dev, 0xe070, 0x00000000);
	128	nouveau_irq_unregister(dev, 21);
	129	}
	130
	131	static void
	132	nv50_gpio_isr(struct drm_device *dev)
	133	{
	134	struct drm_nouveau_private *dev_priv = dev->dev_private;
	135	uint32_t hpd0_bits, hpd1_bits = 0;
	136
	137	hpd0_bits = nv_rd32(dev, 0xe054);
	138	nv_wr32(dev, 0xe054, hpd0_bits);
	139
	140	if (dev_priv->chipset >= 0x90) {
	141	hpd1_bits = nv_rd32(dev, 0xe074);
	142	nv_wr32(dev, 0xe074, hpd1_bits);
	143	}
	144
	145	spin_lock(&dev_priv->hpd_state.lock);
	146	dev_priv->hpd_state.hpd0_bits \|= hpd0_bits;
	147	dev_priv->hpd_state.hpd1_bits \|= hpd1_bits;
	148	spin_unlock(&dev_priv->hpd_state.lock);
	149
	150	queue_work(dev_priv->wq, &dev_priv->hpd_work);
	151	}