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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
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25 | #include <core/object.h> |
26 | #include <core/class.h> | |
27 | ||
02a841d4 | 28 | #include <engine/fifo.h> |
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29 | |
30 | #include "nouveau_drm.h" | |
31 | #include "nouveau_dma.h" | |
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32 | #include "nouveau_fence.h" |
33 | ||
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34 | #include "nv50_display.h" |
35 | ||
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36 | struct nv84_fence_chan { |
37 | struct nouveau_fence_chan base; | |
38 | }; | |
39 | ||
40 | struct nv84_fence_priv { | |
41 | struct nouveau_fence_priv base; | |
42 | struct nouveau_gpuobj *mem; | |
43 | }; | |
44 | ||
45 | static int | |
46 | nv84_fence_emit(struct nouveau_fence *fence) | |
47 | { | |
48 | struct nouveau_channel *chan = fence->channel; | |
ebb945a9 | 49 | struct nouveau_fifo_chan *fifo = (void *)chan->object; |
e18c080f | 50 | int ret = RING_SPACE(chan, 8); |
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51 | if (ret == 0) { |
52 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
53 | OUT_RING (chan, NvSema); | |
e18c080f | 54 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); |
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55 | OUT_RING (chan, upper_32_bits(fifo->chid * 16)); |
56 | OUT_RING (chan, lower_32_bits(fifo->chid * 16)); | |
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57 | OUT_RING (chan, fence->sequence); |
58 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
e18c080f | 59 | OUT_RING (chan, 0x00000000); |
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60 | FIRE_RING (chan); |
61 | } | |
62 | return ret; | |
63 | } | |
64 | ||
906c033e | 65 | |
5e120f6e | 66 | static int |
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67 | nv84_fence_sync(struct nouveau_fence *fence, |
68 | struct nouveau_channel *prev, struct nouveau_channel *chan) | |
5e120f6e | 69 | { |
ebb945a9 | 70 | struct nouveau_fifo_chan *fifo = (void *)prev->object; |
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71 | int ret = RING_SPACE(chan, 7); |
72 | if (ret == 0) { | |
73 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
74 | OUT_RING (chan, NvSema); | |
75 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
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76 | OUT_RING (chan, upper_32_bits(fifo->chid * 16)); |
77 | OUT_RING (chan, lower_32_bits(fifo->chid * 16)); | |
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78 | OUT_RING (chan, fence->sequence); |
79 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); | |
80 | FIRE_RING (chan); | |
81 | } | |
82 | return ret; | |
83 | } | |
84 | ||
85 | static u32 | |
86 | nv84_fence_read(struct nouveau_channel *chan) | |
87 | { | |
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88 | struct nouveau_fifo_chan *fifo = (void *)chan->object; |
89 | struct nv84_fence_priv *priv = chan->drm->fence; | |
90 | return nv_ro32(priv->mem, fifo->chid * 16); | |
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91 | } |
92 | ||
93 | static void | |
e193b1d4 | 94 | nv84_fence_context_del(struct nouveau_channel *chan) |
5e120f6e | 95 | { |
e193b1d4 | 96 | struct nv84_fence_chan *fctx = chan->fence; |
5e120f6e | 97 | nouveau_fence_context_del(&fctx->base); |
e193b1d4 | 98 | chan->fence = NULL; |
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99 | kfree(fctx); |
100 | } | |
101 | ||
102 | static int | |
e193b1d4 | 103 | nv84_fence_context_new(struct nouveau_channel *chan) |
5e120f6e | 104 | { |
77145f1c | 105 | struct drm_device *dev = chan->drm->dev; |
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106 | struct nouveau_fifo_chan *fifo = (void *)chan->object; |
107 | struct nv84_fence_priv *priv = chan->drm->fence; | |
5e120f6e | 108 | struct nv84_fence_chan *fctx; |
ebb945a9 | 109 | struct nouveau_object *object; |
f589be88 | 110 | int ret, i; |
5e120f6e | 111 | |
e193b1d4 | 112 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); |
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113 | if (!fctx) |
114 | return -ENOMEM; | |
115 | ||
116 | nouveau_fence_context_new(&fctx->base); | |
117 | ||
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118 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, |
119 | NvSema, 0x0002, | |
120 | &(struct nv_dma_class) { | |
121 | .flags = NV_DMA_TARGET_VRAM | | |
122 | NV_DMA_ACCESS_RDWR, | |
123 | .start = priv->mem->addr, | |
124 | .limit = priv->mem->addr + | |
125 | priv->mem->size - 1, | |
126 | }, sizeof(struct nv_dma_class), | |
127 | &object); | |
5e120f6e | 128 | |
f589be88 | 129 | /* dma objects for display sync channel semaphore blocks */ |
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130 | for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { |
131 | struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); | |
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132 | |
133 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, | |
134 | NvEvoSema0 + i, 0x003d, | |
135 | &(struct nv_dma_class) { | |
136 | .flags = NV_DMA_TARGET_VRAM | | |
137 | NV_DMA_ACCESS_RDWR, | |
138 | .start = bo->bo.offset, | |
139 | .limit = bo->bo.offset + 0xfff, | |
140 | }, sizeof(struct nv_dma_class), | |
141 | &object); | |
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142 | } |
143 | ||
5e120f6e | 144 | if (ret) |
e193b1d4 | 145 | nv84_fence_context_del(chan); |
ebb945a9 | 146 | nv_wo32(priv->mem, fifo->chid * 16, 0x00000000); |
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147 | return ret; |
148 | } | |
149 | ||
5e120f6e | 150 | static void |
ebb945a9 | 151 | nv84_fence_destroy(struct nouveau_drm *drm) |
5e120f6e | 152 | { |
ebb945a9 | 153 | struct nv84_fence_priv *priv = drm->fence; |
5e120f6e | 154 | nouveau_gpuobj_ref(NULL, &priv->mem); |
ebb945a9 | 155 | drm->fence = NULL; |
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156 | kfree(priv); |
157 | } | |
158 | ||
159 | int | |
ebb945a9 | 160 | nv84_fence_create(struct nouveau_drm *drm) |
5e120f6e | 161 | { |
ebb945a9 | 162 | struct nouveau_fifo *pfifo = nouveau_fifo(drm->device); |
5e120f6e | 163 | struct nv84_fence_priv *priv; |
ebb945a9 | 164 | u32 chan = pfifo->max + 1; |
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165 | int ret; |
166 | ||
ebb945a9 | 167 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
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168 | if (!priv) |
169 | return -ENOMEM; | |
170 | ||
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171 | priv->base.dtor = nv84_fence_destroy; |
172 | priv->base.context_new = nv84_fence_context_new; | |
173 | priv->base.context_del = nv84_fence_context_del; | |
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174 | priv->base.emit = nv84_fence_emit; |
175 | priv->base.sync = nv84_fence_sync; | |
176 | priv->base.read = nv84_fence_read; | |
5e120f6e | 177 | |
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178 | init_waitqueue_head(&priv->base.waiting); |
179 | priv->base.uevent = true; | |
180 | ||
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181 | ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0, |
182 | &priv->mem); | |
5e120f6e | 183 | if (ret) |
ebb945a9 | 184 | nv84_fence_destroy(drm); |
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185 | return ret; |
186 | } |