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drm/nvc0: fix suspend/resume of PGRAPH/PCOPYn
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvc0_graph.c
CommitLineData
4b223eef
BS		 1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
966a5b7d
BS		 25#include <linux/firmware.h>
26
4b223eef
BS		 27#include "drmP.h"
28
29#include "nouveau_drv.h"
966a5b7d
BS		 30#include "nouveau_mm.h"
31#include "nvc0_graph.h"
32
7a45cd19
BS		 33static int
34nvc0_graph_load_context(struct nouveau_channel *chan)
35{
36 struct drm_device *dev = chan->dev;
37
38 nv_wr32(dev, 0x409840, 0x00000030);
39 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
40 nv_wr32(dev, 0x409504, 0x00000003);
41 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
42 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
43
44 return 0;
45}
46
47static int
48nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
49{
50 nv_wr32(dev, 0x409840, 0x00000003);
51 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
52 nv_wr32(dev, 0x409504, 0x00000009);
53 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
54 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
55 return -EBUSY;
56 }
57
58 return 0;
59}
60
966a5b7d
BS		 61static int
62nvc0_graph_construct_context(struct nouveau_channel *chan)
63{
64 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
7a45cd19
BS		 65 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
66 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
966a5b7d
BS		 67 struct drm_device *dev = chan->dev;
68 int ret, i;
69 u32 *ctx;
70
71 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
72 if (!ctx)
73 return -ENOMEM;
74
75 nvc0_graph_load_context(chan);
76
77 nv_wo32(grch->grctx, 0x1c, 1);
78 nv_wo32(grch->grctx, 0x20, 0);
79 nv_wo32(grch->grctx, 0x28, 0);
80 nv_wo32(grch->grctx, 0x2c, 0);
81 dev_priv->engine.instmem.flush(dev);
82
83 ret = nvc0_grctx_generate(chan);
84 if (ret) {
85 kfree(ctx);
86 return ret;
87 }
88
89 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
90 if (ret) {
91 kfree(ctx);
92 return ret;
93 }
94
95 for (i = 0; i < priv->grctx_size; i += 4)
96 ctx[i / 4] = nv_ro32(grch->grctx, i);
97
98 priv->grctx_vals = ctx;
99 return 0;
100}
101
102static int
103nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
104{
7a45cd19
BS		 105 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
106 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
966a5b7d
BS		 107 struct drm_device *dev = chan->dev;
108 int i = 0, gpc, tp, ret;
109 u32 magic;
110
111 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
112 &grch->unk408004);
113 if (ret)
114 return ret;
115
116 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
117 &grch->unk40800c);
118 if (ret)
119 return ret;
120
c906ca0f
BS		 121 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096,
122 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
966a5b7d
BS		 123 &grch->unk418810);
124 if (ret)
125 return ret;
126
127 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
128 &grch->mmio);
129 if (ret)
130 return ret;
131
132
133 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
f8522fc8 134 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
966a5b7d
BS		 135 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
136 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
137
138 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
f8522fc8 139 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
966a5b7d
BS		 140 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
141 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
142
143 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
f8522fc8 144 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
966a5b7d 145 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
f8522fc8 146 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
966a5b7d
BS		 147
148 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
f8522fc8 149 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
966a5b7d
BS		 150 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
151 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
152
153 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
f8522fc8 154 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
966a5b7d
BS		 155 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
156 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
157
158 magic = 0x02180000;
159 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
160 nv_wo32(grch->mmio, i++ * 4, magic);
161 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
e1b89b1c 162 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) {
966a5b7d
BS		 163 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
164 nv_wo32(grch->mmio, i++ * 4, reg);
165 nv_wo32(grch->mmio, i++ * 4, magic);
166 }
167 }
168
169 grch->mmio_nr = i / 2;
170 return 0;
171}
172
7a45cd19
BS		 173static int
174nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
4b223eef 175{
7a45cd19
BS		 176 struct drm_device *dev = chan->dev;
177 struct drm_nouveau_private *dev_priv = dev->dev_private;
966a5b7d 178 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
7a45cd19 179 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
966a5b7d 180 struct nvc0_graph_chan *grch;
966a5b7d
BS		 181 struct nouveau_gpuobj *grctx;
182 int ret, i;
183
7a45cd19
BS		 184 grch = kzalloc(sizeof(*grch), GFP_KERNEL);
185 if (!grch)
966a5b7d 186 return -ENOMEM;
7a45cd19 187 chan->engctx[NVOBJ_ENGINE_GR] = grch;
966a5b7d
BS		 188
189 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
190 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
191 &grch->grctx);
192 if (ret)
193 goto error;
966a5b7d
BS		 194 grctx = grch->grctx;
195
196 ret = nvc0_graph_create_context_mmio_list(chan);
197 if (ret)
198 goto error;
199
f8522fc8
BS		 200 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
201 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
966a5b7d
BS		 202 pinstmem->flush(dev);
203
204 if (!priv->grctx_vals) {
205 ret = nvc0_graph_construct_context(chan);
206 if (ret)
207 goto error;
208 }
209
210 for (i = 0; i < priv->grctx_size; i += 4)
211 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
212
71298e2f
EV		 213 nv_wo32(grctx, 0xf4, 0);
214 nv_wo32(grctx, 0xf8, 0);
215 nv_wo32(grctx, 0x10, grch->mmio_nr);
f8522fc8
BS		 216 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
217 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
71298e2f
EV		 218 nv_wo32(grctx, 0x1c, 1);
219 nv_wo32(grctx, 0x20, 0);
220 nv_wo32(grctx, 0x28, 0);
221 nv_wo32(grctx, 0x2c, 0);
966a5b7d 222 pinstmem->flush(dev);
4b223eef 223 return 0;
966a5b7d
BS		 224
225error:
7a45cd19 226 priv->base.context_del(chan, engine);
966a5b7d 227 return ret;
4b223eef
BS		 228}
229
7a45cd19
BS		 230static void
231nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
4b223eef 232{
7a45cd19 233 struct nvc0_graph_chan *grch = chan->engctx[engine];
966a5b7d
BS		 234
235 nouveau_gpuobj_ref(NULL, &grch->mmio);
236 nouveau_gpuobj_ref(NULL, &grch->unk418810);
237 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
238 nouveau_gpuobj_ref(NULL, &grch->unk408004);
239 nouveau_gpuobj_ref(NULL, &grch->grctx);
7a45cd19 240 chan->engctx[engine] = NULL;
4b223eef
BS		 241}
242
7a45cd19
BS		 243static int
244nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
245 u32 handle, u16 class)
4b223eef 246{
966a5b7d
BS		 247 return 0;
248}
249
250static int
7a45cd19 251nvc0_graph_fini(struct drm_device *dev, int engine)
966a5b7d 252{
4b223eef
BS		 253 return 0;
254}
255
bd2f2037
BS		 256static int
257nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
258 u32 class, u32 mthd, u32 data)
259{
260 nouveau_finish_page_flip(chan, NULL);
261 return 0;
262}
263
966a5b7d
BS		 264static void
265nvc0_graph_init_obj418880(struct drm_device *dev)
266{
7a45cd19 267 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 268 int i;
269
270 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
271 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
272 for (i = 0; i < 4; i++)
273 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
274 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
275 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
276}
277
278static void
279nvc0_graph_init_regs(struct drm_device *dev)
280{
281 nv_wr32(dev, 0x400080, 0x003083c2);
282 nv_wr32(dev, 0x400088, 0x00006fe7);
283 nv_wr32(dev, 0x40008c, 0x00000000);
284 nv_wr32(dev, 0x400090, 0x00000030);
285 nv_wr32(dev, 0x40013c, 0x013901f7);
286 nv_wr32(dev, 0x400140, 0x00000100);
287 nv_wr32(dev, 0x400144, 0x00000000);
288 nv_wr32(dev, 0x400148, 0x00000110);
289 nv_wr32(dev, 0x400138, 0x00000000);
290 nv_wr32(dev, 0x400130, 0x00000000);
291 nv_wr32(dev, 0x400134, 0x00000000);
292 nv_wr32(dev, 0x400124, 0x00000002);
293}
294
295static void
296nvc0_graph_init_gpc_0(struct drm_device *dev)
297{
7a45cd19 298 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
aa58c405
BS		 299 u32 data[TP_MAX / 8];
300 u8 tpnr[GPC_MAX];
301 int i, gpc, tpc;
f212949c
EV		 302
303 /*
304 * TP ROP UNKVAL(magic_not_rop_nr)
305 * 450: 4/0/0/0 2 3
306 * 460: 3/4/0/0 4 1
307 * 465: 3/4/4/0 4 7
308 * 470: 3/3/4/4 5 5
309 * 480: 3/4/4/4 6 6
aa58c405 310 *
f212949c
EV		 311 * magicgpc918
312 * 450: 00200000 00000000001000000000000000000000
313 * 460: 00124925 00000000000100100100100100100101
314 * 465: 000ba2e9 00000000000010111010001011101001
315 * 470: 00092493 00000000000010010010010010010011
316 * 480: 00088889 00000000000010001000100010001001
f212949c
EV		 317 */
318
aa58c405
BS		 319 memset(data, 0x00, sizeof(data));
320 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
321 for (i = 0, gpc = -1; i < priv->tp_total; i++) {
322 do {
323 gpc = (gpc + 1) % priv->gpc_nr;
324 } while (!tpnr[gpc]);
325 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
326
327 data[i / 8] |= tpc << ((i % 8) * 4);
328 }
329
330 nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
331 nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
332 nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
333 nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
966a5b7d
BS		 334
335 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
336 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
337 priv->tp_nr[gpc]);
338 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
339 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
340 }
341
342 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
343 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
344}
345
346static void
347nvc0_graph_init_units(struct drm_device *dev)
348{
349 nv_wr32(dev, 0x409c24, 0x000f0000);
350 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
351 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
352 nv_wr32(dev, 0x408030, 0xc0000000);
353 nv_wr32(dev, 0x40601c, 0xc0000000);
354 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
355 nv_wr32(dev, 0x406018, 0xc0000000);
356 nv_wr32(dev, 0x405840, 0xc0000000);
357 nv_wr32(dev, 0x405844, 0x00ffffff);
358 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
359 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
360}
361
362static void
363nvc0_graph_init_gpc_1(struct drm_device *dev)
364{
7a45cd19 365 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 366 int gpc, tp;
367
368 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
369 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
370 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
371 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
372 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
373 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
374 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
375 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
376 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
377 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
378 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
0f1cb203
BS		 379 nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
380 nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
966a5b7d
BS		 381 }
382 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
383 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
384 }
385}
386
387static void
388nvc0_graph_init_rop(struct drm_device *dev)
389{
7a45cd19 390 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 391 int rop;
392
393 for (rop = 0; rop < priv->rop_nr; rop++) {
394 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
395 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
396 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
397 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
398 }
399}
400
fe799114
BS		 401static void
402nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
403 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
966a5b7d 404{
fe799114 405 int i;
966a5b7d
BS		 406
407 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
fe799114
BS		 408 for (i = 0; i < data->size / 4; i++)
409 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
966a5b7d
BS		 410
411 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
fe799114 412 for (i = 0; i < code->size / 4; i++) {
966a5b7d
BS		 413 if ((i & 0x3f) == 0)
414 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
fe799114 415 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
966a5b7d 416 }
966a5b7d
BS		 417}
418
419static int
420nvc0_graph_init_ctxctl(struct drm_device *dev)
421{
7a45cd19 422 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d 423 u32 r000260;
966a5b7d
BS		 424
425 /* load fuc microcode */
426 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
fe799114
BS		 427 nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
428 nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
966a5b7d
BS		 429 nv_wr32(dev, 0x000260, r000260);
430
966a5b7d
BS		 431 /* start both of them running */
432 nv_wr32(dev, 0x409840, 0xffffffff);
433 nv_wr32(dev, 0x41a10c, 0x00000000);
434 nv_wr32(dev, 0x40910c, 0x00000000);
435 nv_wr32(dev, 0x41a100, 0x00000002);
436 nv_wr32(dev, 0x409100, 0x00000002);
437 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
438 NV_INFO(dev, "0x409800 wait failed\n");
439
440 nv_wr32(dev, 0x409840, 0xffffffff);
441 nv_wr32(dev, 0x409500, 0x7fffffff);
442 nv_wr32(dev, 0x409504, 0x00000021);
443
444 nv_wr32(dev, 0x409840, 0xffffffff);
445 nv_wr32(dev, 0x409500, 0x00000000);
446 nv_wr32(dev, 0x409504, 0x00000010);
447 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
448 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
449 return -EBUSY;
450 }
451 priv->grctx_size = nv_rd32(dev, 0x409800);
452
453 nv_wr32(dev, 0x409840, 0xffffffff);
454 nv_wr32(dev, 0x409500, 0x00000000);
455 nv_wr32(dev, 0x409504, 0x00000016);
456 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
457 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
458 return -EBUSY;
459 }
460
461 nv_wr32(dev, 0x409840, 0xffffffff);
462 nv_wr32(dev, 0x409500, 0x00000000);
463 nv_wr32(dev, 0x409504, 0x00000025);
464 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
465 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
466 return -EBUSY;
467 }
468
469 return 0;
4b223eef
BS		 470}
471
7a45cd19
BS		 472static int
473nvc0_graph_init(struct drm_device *dev, int engine)
4b223eef 474{
966a5b7d
BS		 475 int ret;
476
966a5b7d
BS		 477 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
478 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
479
966a5b7d
BS		 480 nvc0_graph_init_obj418880(dev);
481 nvc0_graph_init_regs(dev);
f212949c 482 /*nvc0_graph_init_unitplemented_magics(dev);*/
966a5b7d 483 nvc0_graph_init_gpc_0(dev);
f212949c 484 /*nvc0_graph_init_unitplemented_c242(dev);*/
966a5b7d
BS		 485
486 nv_wr32(dev, 0x400500, 0x00010001);
487 nv_wr32(dev, 0x400100, 0xffffffff);
488 nv_wr32(dev, 0x40013c, 0xffffffff);
489
490 nvc0_graph_init_units(dev);
491 nvc0_graph_init_gpc_1(dev);
492 nvc0_graph_init_rop(dev);
493
494 nv_wr32(dev, 0x400108, 0xffffffff);
495 nv_wr32(dev, 0x400138, 0xffffffff);
496 nv_wr32(dev, 0x400118, 0xffffffff);
497 nv_wr32(dev, 0x400130, 0xffffffff);
498 nv_wr32(dev, 0x40011c, 0xffffffff);
499 nv_wr32(dev, 0x400134, 0xffffffff);
500 nv_wr32(dev, 0x400054, 0x34ce3464);
501
502 ret = nvc0_graph_init_ctxctl(dev);
a82dd49f
BS		 503 if (ret)
504 return ret;
505
4b223eef
BS		 506 return 0;
507}
508
d5a27370 509int
966a5b7d
BS		 510nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
511{
512 struct drm_nouveau_private *dev_priv = dev->dev_private;
513 struct nouveau_channel *chan;
514 unsigned long flags;
515 int i;
516
517 spin_lock_irqsave(&dev_priv->channels.lock, flags);
518 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
519 chan = dev_priv->channels.ptr[i];
520 if (!chan || !chan->ramin)
521 continue;
522
523 if (inst == chan->ramin->vinst)
524 break;
525 }
526 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
527 return i;
528}
529
530static void
531nvc0_graph_isr(struct drm_device *dev)
532{
533 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
534 u32 chid = nvc0_graph_isr_chid(dev, inst);
535 u32 stat = nv_rd32(dev, 0x400100);
536 u32 addr = nv_rd32(dev, 0x400704);
537 u32 mthd = (addr & 0x00003ffc);
538 u32 subc = (addr & 0x00070000) >> 16;
539 u32 data = nv_rd32(dev, 0x400708);
540 u32 code = nv_rd32(dev, 0x400110);
541 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
542
543 if (stat & 0x00000010) {
bd2f2037
BS		 544 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
545 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
546 "subc %d class 0x%04x mthd 0x%04x "
547 "data 0x%08x\n",
548 chid, inst, subc, class, mthd, data);
549 }
966a5b7d
BS		 550 nv_wr32(dev, 0x400100, 0x00000010);
551 stat &= ~0x00000010;
552 }
553
eae5e7f3
BS		 554 if (stat & 0x00000020) {
555 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
556 "class 0x%04x mthd 0x%04x data 0x%08x\n",
557 chid, inst, subc, class, mthd, data);
558 nv_wr32(dev, 0x400100, 0x00000020);
559 stat &= ~0x00000020;
560 }
561
966a5b7d
BS		 562 if (stat & 0x00100000) {
563 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
6effe393 564 nouveau_enum_print(nv50_data_error_names, code);
966a5b7d
BS		 565 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
566 "mthd 0x%04x data 0x%08x\n",
567 chid, inst, subc, class, mthd, data);
568 nv_wr32(dev, 0x400100, 0x00100000);
569 stat &= ~0x00100000;
570 }
571
eae5e7f3
BS		 572 if (stat & 0x00200000) {
573 u32 trap = nv_rd32(dev, 0x400108);
574 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
575 nv_wr32(dev, 0x400108, trap);
576 nv_wr32(dev, 0x400100, 0x00200000);
577 stat &= ~0x00200000;
578 }
579
966a5b7d
BS		 580 if (stat & 0x00080000) {
581 u32 ustat = nv_rd32(dev, 0x409c18);
582
583 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
584
585 nv_wr32(dev, 0x409c20, ustat);
586 nv_wr32(dev, 0x400100, 0x00080000);
587 stat &= ~0x00080000;
588 }
589
590 if (stat) {
591 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
592 nv_wr32(dev, 0x400100, stat);
593 }
594
595 nv_wr32(dev, 0x400500, 0x00010001);
596}
51f73d64
BS		 597
598static void
599nvc0_runk140_isr(struct drm_device *dev)
600{
601 u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
602
603 while (units) {
604 u32 unit = ffs(units) - 1;
605 u32 reg = 0x140000 + unit * 0x2000;
606 u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
607 u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
608
609 NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
610 units &= ~(1 << unit);
611 }
612}
7a45cd19 613
fe799114
BS		 614static int
615nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
616 struct nvc0_graph_fuc *fuc)
617{
618 struct drm_nouveau_private *dev_priv = dev->dev_private;
619 const struct firmware *fw;
620 char f[32];
621 int ret;
622
623 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
624 ret = request_firmware(&fw, f, &dev->pdev->dev);
625 if (ret) {
626 snprintf(f, sizeof(f), "nouveau/%s", fwname);
627 ret = request_firmware(&fw, f, &dev->pdev->dev);
628 if (ret) {
629 NV_ERROR(dev, "failed to load %s\n", fwname);
630 return ret;
631 }
632 }
633
634 fuc->size = fw->size;
635 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
636 release_firmware(fw);
637 return (fuc->data != NULL) ? 0 : -ENOMEM;
638}
639
640static void
641nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
642{
643 if (fuc->data) {
644 kfree(fuc->data);
645 fuc->data = NULL;
646 }
647}
648
7a45cd19
BS		 649static void
650nvc0_graph_destroy(struct drm_device *dev, int engine)
651{
652 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
653
fe799114
BS		 654 nvc0_graph_destroy_fw(&priv->fuc409c);
655 nvc0_graph_destroy_fw(&priv->fuc409d);
656 nvc0_graph_destroy_fw(&priv->fuc41ac);
657 nvc0_graph_destroy_fw(&priv->fuc41ad);
658
7a45cd19
BS		 659 nouveau_irq_unregister(dev, 12);
660 nouveau_irq_unregister(dev, 25);
661
662 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
663 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
664
665 if (priv->grctx_vals)
666 kfree(priv->grctx_vals);
667
668 NVOBJ_ENGINE_DEL(dev, GR);
669 kfree(priv);
670}
671
672int
673nvc0_graph_create(struct drm_device *dev)
674{
675 struct drm_nouveau_private *dev_priv = dev->dev_private;
676 struct nvc0_graph_priv *priv;
677 int ret, gpc, i;
847adea2 678 u32 fermi;
7a45cd19 679
847adea2
BS		 680 fermi = nvc0_graph_class(dev);
681 if (!fermi) {
a82dd49f
BS		 682 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
683 return 0;
684 }
685
7a45cd19
BS		 686 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
687 if (!priv)
688 return -ENOMEM;
689
690 priv->base.destroy = nvc0_graph_destroy;
691 priv->base.init = nvc0_graph_init;
692 priv->base.fini = nvc0_graph_fini;
693 priv->base.context_new = nvc0_graph_context_new;
694 priv->base.context_del = nvc0_graph_context_del;
695 priv->base.object_new = nvc0_graph_object_new;
696
697 NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
698 nouveau_irq_register(dev, 12, nvc0_graph_isr);
699 nouveau_irq_register(dev, 25, nvc0_runk140_isr);
700
fe799114
BS		 701 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
702 nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
703 nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
704 nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
705 ret = 0;
706 goto error;
707 }
708
709
7a45cd19
BS		 710 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
711 if (ret)
712 goto error;
713
714 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
715 if (ret)
716 goto error;
717
718 for (i = 0; i < 0x1000; i += 4) {
719 nv_wo32(priv->unk4188b4, i, 0x00000010);
720 nv_wo32(priv->unk4188b8, i, 0x00000010);
721 }
722
723 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
724 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
725 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
726 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
727 priv->tp_total += priv->tp_nr[gpc];
728 }
729
730 /*XXX: these need figuring out... */
731 switch (dev_priv->chipset) {
732 case 0xc0:
733 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
734 priv->magic_not_rop_nr = 0x07;
735 /* filled values up to tp_total, the rest 0 */
7a45cd19
BS		 736 priv->magicgpc918 = 0x000ba2e9;
737 } else
738 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
739 priv->magic_not_rop_nr = 0x05;
7a45cd19
BS		 740 priv->magicgpc918 = 0x00092493;
741 } else
742 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
743 priv->magic_not_rop_nr = 0x06;
7a45cd19
BS		 744 priv->magicgpc918 = 0x00088889;
745 }
746 break;
747 case 0xc3: /* 450, 4/0/0/0, 2 */
748 priv->magic_not_rop_nr = 0x03;
7a45cd19
BS		 749 priv->magicgpc918 = 0x00200000;
750 break;
751 case 0xc4: /* 460, 3/4/0/0, 4 */
752 priv->magic_not_rop_nr = 0x01;
7a45cd19
BS		 753 priv->magicgpc918 = 0x00124925;
754 break;
755 }
756
757 if (!priv->magic_not_rop_nr) {
758 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
759 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
760 priv->tp_nr[3], priv->rop_nr);
761 /* use 0xc3's values... */
762 priv->magic_not_rop_nr = 0x03;
7a45cd19
BS		 763 priv->magicgpc918 = 0x00200000;
764 }
765
766 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
767 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
768 NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
769 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
847adea2
BS		 770 if (fermi >= 0x9197)
771 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
772 if (fermi >= 0x9297)
773 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
7a45cd19
BS		 774 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
775 return 0;
776
777error:
778 nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
779 return ret;
780}
fe799114
BS		 781
782MODULE_FIRMWARE("nouveau/nvc0_fuc409c");
783MODULE_FIRMWARE("nouveau/nvc0_fuc409d");
784MODULE_FIRMWARE("nouveau/nvc0_fuc41ac");
785MODULE_FIRMWARE("nouveau/nvc0_fuc41ad");
786MODULE_FIRMWARE("nouveau/nvc3_fuc409c");
787MODULE_FIRMWARE("nouveau/nvc3_fuc409d");
788MODULE_FIRMWARE("nouveau/nvc3_fuc41ac");
789MODULE_FIRMWARE("nouveau/nvc3_fuc41ad");
790MODULE_FIRMWARE("nouveau/nvc4_fuc409c");
791MODULE_FIRMWARE("nouveau/nvc4_fuc409d");
792MODULE_FIRMWARE("nouveau/nvc4_fuc41ac");
793MODULE_FIRMWARE("nouveau/nvc4_fuc41ad");
794MODULE_FIRMWARE("nouveau/fuc409c");
795MODULE_FIRMWARE("nouveau/fuc409d");
796MODULE_FIRMWARE("nouveau/fuc41ac");
797MODULE_FIRMWARE("nouveau/fuc41ad");
Linux kernel - Deliverables
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