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drm/nv50-/disp: audit and version SOR_HDMI_PWR method
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvif / class.h
CommitLineData
d01c3092
BS		 1#ifndef __NVIF_CLASS_H__
2#define __NVIF_CLASS_H__
3
4/*******************************************************************************
5 * class identifiers
6 ******************************************************************************/
7
8/* the below match nvidia-assigned (either in hw, or sw) class numbers */
9#define NV_DEVICE 0x00000080
10
4acfd707
BS		 11#define NV_DMA_FROM_MEMORY 0x00000002
12#define NV_DMA_TO_MEMORY 0x00000003
13#define NV_DMA_IN_MEMORY 0x0000003d
14
bbf8906b
BS		 15#define NV03_CHANNEL_DMA 0x0000006b
16#define NV10_CHANNEL_DMA 0x0000006e
17#define NV17_CHANNEL_DMA 0x0000176e
18#define NV40_CHANNEL_DMA 0x0000406e
19#define NV50_CHANNEL_DMA 0x0000506e
20#define G82_CHANNEL_DMA 0x0000826e
21
22#define NV50_CHANNEL_GPFIFO 0x0000506f
23#define G82_CHANNEL_GPFIFO 0x0000826f
24#define FERMI_CHANNEL_GPFIFO 0x0000906f
25#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
26
d01c3092 27
803c1787
BS		 28/*******************************************************************************
29 * client
30 ******************************************************************************/
31
32#define NV_CLIENT_DEVLIST 0x00
33
34struct nv_client_devlist_v0 {
35 __u8 version;
36 __u8 count;
37 __u8 pad02[6];
38 __u64 device[];
39};
40
41
d01c3092
BS		 42/*******************************************************************************
43 * device
44 ******************************************************************************/
45
586491e6
BS		 46struct nv_device_v0 {
47 __u8 version;
48 __u8 pad01[7];
49 __u64 device; /* device identifier, ~0 for client default */
50#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
51#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
52#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
53#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
54#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
55#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
56#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL
57#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
58#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
59#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
60#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL
61#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
62#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
63#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL
64#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL
65#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
66#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
67 __u64 disable; /* disable particular subsystems */
68 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
69};
70
d01c3092
BS		 71#define NV_DEVICE_V0_INFO 0x00
72
73struct nv_device_info_v0 {
74 __u8 version;
75#define NV_DEVICE_INFO_V0_IGP 0x00
76#define NV_DEVICE_INFO_V0_PCI 0x01
77#define NV_DEVICE_INFO_V0_AGP 0x02
78#define NV_DEVICE_INFO_V0_PCIE 0x03
79#define NV_DEVICE_INFO_V0_SOC 0x04
80 __u8 platform;
81 __u16 chipset; /* from NV_PMC_BOOT_0 */
82 __u8 revision; /* from NV_PMC_BOOT_0 */
83#define NV_DEVICE_INFO_V0_TNT 0x01
84#define NV_DEVICE_INFO_V0_CELSIUS 0x02
85#define NV_DEVICE_INFO_V0_KELVIN 0x03
86#define NV_DEVICE_INFO_V0_RANKINE 0x04
87#define NV_DEVICE_INFO_V0_CURIE 0x05
88#define NV_DEVICE_INFO_V0_TESLA 0x06
89#define NV_DEVICE_INFO_V0_FERMI 0x07
90#define NV_DEVICE_INFO_V0_KEPLER 0x08
91#define NV_DEVICE_INFO_V0_MAXWELL 0x09
92 __u8 family;
93 __u8 pad06[2];
94 __u64 ram_size;
95 __u64 ram_user;
96};
97
4acfd707
BS		 98
99/*******************************************************************************
100 * context dma
101 ******************************************************************************/
102
103struct nv_dma_v0 {
104 __u8 version;
105#define NV_DMA_V0_TARGET_VM 0x00
106#define NV_DMA_V0_TARGET_VRAM 0x01
107#define NV_DMA_V0_TARGET_PCI 0x02
108#define NV_DMA_V0_TARGET_PCI_US 0x03
109#define NV_DMA_V0_TARGET_AGP 0x04
110 __u8 target;
111#define NV_DMA_V0_ACCESS_VM 0x00
112#define NV_DMA_V0_ACCESS_RD 0x01
113#define NV_DMA_V0_ACCESS_WR 0x02
114#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
115 __u8 access;
116 __u8 pad03[5];
117 __u64 start;
118 __u64 limit;
119 /* ... chipset-specific class data */
120};
121
122struct nv50_dma_v0 {
123 __u8 version;
124#define NV50_DMA_V0_PRIV_VM 0x00
125#define NV50_DMA_V0_PRIV_US 0x01
126#define NV50_DMA_V0_PRIV__S 0x02
127 __u8 priv;
128#define NV50_DMA_V0_PART_VM 0x00
129#define NV50_DMA_V0_PART_256 0x01
130#define NV50_DMA_V0_PART_1KB 0x02
131 __u8 part;
132#define NV50_DMA_V0_COMP_NONE 0x00
133#define NV50_DMA_V0_COMP_1 0x01
134#define NV50_DMA_V0_COMP_2 0x02
135#define NV50_DMA_V0_COMP_VM 0x03
136 __u8 comp;
137#define NV50_DMA_V0_KIND_PITCH 0x00
138#define NV50_DMA_V0_KIND_VM 0x7f
139 __u8 kind;
140 __u8 pad05[3];
141};
142
143struct gf100_dma_v0 {
144 __u8 version;
145#define GF100_DMA_V0_PRIV_VM 0x00
146#define GF100_DMA_V0_PRIV_US 0x01
147#define GF100_DMA_V0_PRIV__S 0x02
148 __u8 priv;
149#define GF100_DMA_V0_KIND_PITCH 0x00
150#define GF100_DMA_V0_KIND_VM 0xff
151 __u8 kind;
152 __u8 pad03[5];
153};
154
155struct gf110_dma_v0 {
156 __u8 version;
157#define GF110_DMA_V0_PAGE_LP 0x00
158#define GF110_DMA_V0_PAGE_SP 0x01
159 __u8 page;
160#define GF110_DMA_V0_KIND_PITCH 0x00
161#define GF110_DMA_V0_KIND_VM 0xff
162 __u8 kind;
163 __u8 pad03[5];
164};
165
96af8222
BS		 166
167/*******************************************************************************
168 * perfmon
169 ******************************************************************************/
170
171struct nvif_perfctr_v0 {
172 __u8 version;
173 __u8 pad01[1];
174 __u16 logic_op;
175 __u8 pad04[4];
176 char name[4][64];
177};
178
179#define NVIF_PERFCTR_V0_QUERY 0x00
180#define NVIF_PERFCTR_V0_SAMPLE 0x01
181#define NVIF_PERFCTR_V0_READ 0x02
182
183struct nvif_perfctr_query_v0 {
184 __u8 version;
185 __u8 pad01[3];
186 __u32 iter;
187 char name[64];
188};
189
190struct nvif_perfctr_sample {
191};
192
193struct nvif_perfctr_read_v0 {
194 __u8 version;
195 __u8 pad01[7];
196 __u32 ctr;
197 __u32 clk;
198};
199
a532da97
BS		 200
201/*******************************************************************************
202 * device control
203 ******************************************************************************/
204
205#define NVIF_CONTROL_PSTATE_INFO 0x00
206#define NVIF_CONTROL_PSTATE_ATTR 0x01
207#define NVIF_CONTROL_PSTATE_USER 0x02
208
209struct nvif_control_pstate_info_v0 {
210 __u8 version;
211 __u8 count; /* out: number of power states */
212#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
213#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
214 __s8 ustate_ac; /* out: target pstate index */
215 __s8 ustate_dc; /* out: target pstate index */
216 __s8 pwrsrc; /* out: current power source */
217#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
218#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
219 __s8 pstate; /* out: current pstate index */
220 __u8 pad06[2];
221};
222
223struct nvif_control_pstate_attr_v0 {
224 __u8 version;
225#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
226 __s8 state; /* in: index of pstate to query
227 * out: pstate identifier
228 */
229 __u8 index; /* in: index of attribute to query
230 * out: index of next attribute, or 0 if no more
231 */
232 __u8 pad03[5];
233 __u32 min;
234 __u32 max;
235 char name[32];
236 char unit[16];
237};
238
239struct nvif_control_pstate_user_v0 {
240 __u8 version;
241#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
242#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
243 __s8 ustate; /* in: pstate identifier */
244 __s8 pwrsrc; /* in: target power source */
245 __u8 pad03[5];
246};
247
bbf8906b
BS		 248
249/*******************************************************************************
250 * DMA FIFO channels
251 ******************************************************************************/
252
253struct nv03_channel_dma_v0 {
254 __u8 version;
255 __u8 chid;
256 __u8 pad02[2];
257 __u32 pushbuf;
258 __u64 offset;
259};
260
867920f8 261#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
bbf8906b
BS		 262
263/*******************************************************************************
264 * GPFIFO channels
265 ******************************************************************************/
266
267struct nv50_channel_gpfifo_v0 {
268 __u8 version;
269 __u8 chid;
270 __u8 pad01[6];
271 __u32 pushbuf;
272 __u32 ilength;
273 __u64 ioffset;
274};
275
276struct kepler_channel_gpfifo_a_v0 {
277 __u8 version;
278#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
279#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
280#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
281#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08
282#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
283#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
284#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
285 __u8 engine;
286 __u16 chid;
287 __u8 pad04[4];
288 __u32 pushbuf;
289 __u32 ilength;
290 __u64 ioffset;
291};
292
bf0eb898
BS		 293/*******************************************************************************
294 * legacy display
295 ******************************************************************************/
296
297
298/*******************************************************************************
299 * display
300 ******************************************************************************/
301
302#define NV50_DISP_MTHD 0x00
303
304struct nv50_disp_mthd_v0 {
305 __u8 version;
306 __u8 method;
307 __u8 head;
308 __u8 pad03[5];
309};
310
311struct nv50_disp_mthd_v1 {
312 __u8 version;
313#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
314#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
315#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
316#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
317#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
318#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
319#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
320#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
321 __u8 method;
322 __u16 hasht;
323 __u16 hashm;
324 __u8 pad06[2];
325};
326
327struct nv50_disp_dac_pwr_v0 {
328 __u8 version;
329 __u8 state;
330 __u8 data;
331 __u8 vsync;
332 __u8 hsync;
333 __u8 pad05[3];
334};
335
c4abd317
BS		 336struct nv50_disp_dac_load_v0 {
337 __u8 version;
338 __u8 load;
339 __u16 data;
340 __u8 pad04[4];
341};
342
d55b4af9
BS		 343struct nv50_disp_sor_pwr_v0 {
344 __u8 version;
345 __u8 state;
346 __u8 pad02[6];
347};
348
120b0c39
BS		 349struct nv50_disp_sor_hda_eld_v0 {
350 __u8 version;
351 __u8 pad01[7];
352 __u8 data[];
353};
354
e00f2235
BS		 355struct nv50_disp_sor_hdmi_pwr_v0 {
356 __u8 version;
357 __u8 state;
358 __u8 max_ac_packet;
359 __u8 rekey;
360 __u8 pad04[4];
361};
362
d01c3092 363#endif
Linux kernel - Deliverables
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