[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / core / gpuobj.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include <core/gpuobj.h>
#include <core/engine.h>

#include <subdev/instmem.h>
#include <subdev/bar.h>
#include <subdev/mmu.h>

/* fast-path, where backend is able to provide direct pointer to memory */
static u32
nvkm_gpuobj_rd32_fast(struct nvkm_gpuobj *gpuobj, u32 offset)
{
	return ioread32_native(gpuobj->map + offset);
}

static void
nvkm_gpuobj_wr32_fast(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data)
{
	iowrite32_native(data, gpuobj->map + offset);
}

/* accessor functions for gpuobjs allocated directly from instmem */
static u32
nvkm_gpuobj_heap_rd32(struct nvkm_gpuobj *gpuobj, u32 offset)
{
	return nvkm_ro32(gpuobj->memory, offset);
}

static void
nvkm_gpuobj_heap_wr32(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data)
{
	nvkm_wo32(gpuobj->memory, offset, data);
}

static const struct nvkm_gpuobj_func nvkm_gpuobj_heap;
static void
nvkm_gpuobj_heap_release(struct nvkm_gpuobj *gpuobj)
{
	gpuobj->func = &nvkm_gpuobj_heap;
	nvkm_done(gpuobj->memory);
}

static const struct nvkm_gpuobj_func
nvkm_gpuobj_heap_fast = {
	.release = nvkm_gpuobj_heap_release,
	.rd32 = nvkm_gpuobj_rd32_fast,
	.wr32 = nvkm_gpuobj_wr32_fast,
};

static const struct nvkm_gpuobj_func
nvkm_gpuobj_heap_slow = {
	.release = nvkm_gpuobj_heap_release,
	.rd32 = nvkm_gpuobj_heap_rd32,
	.wr32 = nvkm_gpuobj_heap_wr32,
};

static void *
nvkm_gpuobj_heap_acquire(struct nvkm_gpuobj *gpuobj)
{
	gpuobj->map = nvkm_kmap(gpuobj->memory);
	if (likely(gpuobj->map))
		gpuobj->func = &nvkm_gpuobj_heap_fast;
	else
		gpuobj->func = &nvkm_gpuobj_heap_slow;
	return gpuobj->map;
}

static const struct nvkm_gpuobj_func
nvkm_gpuobj_heap = {
	.acquire = nvkm_gpuobj_heap_acquire,
};

/* accessor functions for gpuobjs sub-allocated from a parent gpuobj */
static u32
nvkm_gpuobj_rd32(struct nvkm_gpuobj *gpuobj, u32 offset)
{
	return nvkm_ro32(gpuobj->parent, gpuobj->node->offset + offset);
}

static void
nvkm_gpuobj_wr32(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data)
{
	nvkm_wo32(gpuobj->parent, gpuobj->node->offset + offset, data);
}

static const struct nvkm_gpuobj_func nvkm_gpuobj_func;
static void
nvkm_gpuobj_release(struct nvkm_gpuobj *gpuobj)
{
	gpuobj->func = &nvkm_gpuobj_func;
	nvkm_done(gpuobj->parent);
}

static const struct nvkm_gpuobj_func
nvkm_gpuobj_fast = {
	.release = nvkm_gpuobj_release,
	.rd32 = nvkm_gpuobj_rd32_fast,
	.wr32 = nvkm_gpuobj_wr32_fast,
};

static const struct nvkm_gpuobj_func
nvkm_gpuobj_slow = {
	.release = nvkm_gpuobj_release,
	.rd32 = nvkm_gpuobj_rd32,
	.wr32 = nvkm_gpuobj_wr32,
};

static void *
nvkm_gpuobj_acquire(struct nvkm_gpuobj *gpuobj)
{
	gpuobj->map = nvkm_kmap(gpuobj->parent);
	if (likely(gpuobj->map)) {
		gpuobj->map  = (u8 *)gpuobj->map + gpuobj->node->offset;
		gpuobj->func = &nvkm_gpuobj_fast;
	} else {
		gpuobj->func = &nvkm_gpuobj_slow;
	}
	return gpuobj->map;
}

static const struct nvkm_gpuobj_func
nvkm_gpuobj_func = {
	.acquire = nvkm_gpuobj_acquire,
};

static int
nvkm_gpuobj_ctor(struct nvkm_device *device, u32 size, int align, bool zero,
		 struct nvkm_gpuobj *parent, struct nvkm_gpuobj *gpuobj)
{
	u32 offset;
	int ret;

	if (parent) {
		if (align >= 0) {
			ret = nvkm_mm_head(&parent->heap, 0, 1, size, size,
					   max(align, 1), &gpuobj->node);
		} else {
			ret = nvkm_mm_tail(&parent->heap, 0, 1, size, size,
					   -align, &gpuobj->node);
		}
		if (ret)
			return ret;

		gpuobj->parent = parent;
		gpuobj->func = &nvkm_gpuobj_func;
		gpuobj->addr = parent->addr + gpuobj->node->offset;
		gpuobj->size = gpuobj->node->length;

		if (zero) {
			nvkm_kmap(gpuobj);
			for (offset = 0; offset < gpuobj->size; offset += 4)
				nvkm_wo32(gpuobj, offset, 0x00000000);
			nvkm_done(gpuobj);
		}
	} else {
		ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size,
				      abs(align), zero, &gpuobj->memory);
		if (ret)
			return ret;

		gpuobj->func = &nvkm_gpuobj_heap;
		gpuobj->addr = nvkm_memory_addr(gpuobj->memory);
		gpuobj->size = nvkm_memory_size(gpuobj->memory);
	}

	return nvkm_mm_init(&gpuobj->heap, 0, gpuobj->size, 1);
}

void
nvkm_gpuobj_del(struct nvkm_gpuobj **pgpuobj)
{
	struct nvkm_gpuobj *gpuobj = *pgpuobj;
	if (gpuobj) {
		if (gpuobj->parent)
			nvkm_mm_free(&gpuobj->parent->heap, &gpuobj->node);
		nvkm_mm_fini(&gpuobj->heap);
		nvkm_memory_del(&gpuobj->memory);
		kfree(*pgpuobj);
		*pgpuobj = NULL;
	}
}

int
nvkm_gpuobj_new(struct nvkm_device *device, u32 size, int align, bool zero,
		struct nvkm_gpuobj *parent, struct nvkm_gpuobj **pgpuobj)
{
	struct nvkm_gpuobj *gpuobj;
	int ret;

	if (!(gpuobj = *pgpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL)))
		return -ENOMEM;

	ret = nvkm_gpuobj_ctor(device, size, align, zero, parent, gpuobj);
	if (ret)
		nvkm_gpuobj_del(pgpuobj);
	return ret;
}

void
nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
{
	if (gpuobj->node)
		nvkm_mm_free(&gpuobj->parent->heap, &gpuobj->node);

	gpuobj->heap.block_size = 1;
	nvkm_mm_fini(&gpuobj->heap);

	nvkm_memory_del(&gpuobj->memory);
	nvkm_object_destroy(&gpuobj->object);
}

#include <engine/fifo/chan.h>

int
nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
		    struct nvkm_oclass *oclass, u32 pclass,
		    struct nvkm_object *objgpu, u32 size, u32 align, u32 flags,
		    int length, void **pobject)
{
	struct nvkm_device *device = nv_device(parent);
	struct nvkm_gpuobj *pargpu = NULL;
	struct nvkm_gpuobj *gpuobj;
	struct nvkm_object *object = objgpu;
	const bool zero = (flags & NVOBJ_FLAG_ZERO_ALLOC);
	int ret;

	*pobject = NULL;

	while (object && object->func != &nvkm_fifo_chan_func)
		object = object->parent;

	if (object) {
		struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
		pargpu = chan->inst;
	} else
	if (objgpu) {
		while ((objgpu = nv_pclass(objgpu, NV_GPUOBJ_CLASS))) {
			if (nv_gpuobj(objgpu)->heap.block_size)
				break;
			objgpu = objgpu->parent;
		}

		if (WARN_ON(objgpu == NULL))
			return -EINVAL;
		pargpu = nv_gpuobj(objgpu);
	}

	ret = nvkm_object_create_(parent, engine, oclass, pclass |
				  NV_GPUOBJ_CLASS, length, pobject);
	gpuobj = *pobject;
	if (ret)
		return ret;

	ret = nvkm_gpuobj_ctor(device, size, align, zero, pargpu, gpuobj);
	if (!(flags & NVOBJ_FLAG_HEAP))
		gpuobj->heap.block_size = 0;
	return ret;
}

void
_nvkm_gpuobj_dtor(struct nvkm_object *object)
{
	nvkm_gpuobj_destroy(nv_gpuobj(object));
}

int
_nvkm_gpuobj_init(struct nvkm_object *object)
{
	return nvkm_gpuobj_init(nv_gpuobj(object));
}

int
_nvkm_gpuobj_fini(struct nvkm_object *object, bool suspend)
{
	return nvkm_gpuobj_fini(nv_gpuobj(object), suspend);
}

u32
_nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr)
{
	struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
	return nvkm_ro32(gpuobj, addr);
}

void
_nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
	struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
	nvkm_wo32(gpuobj, addr, data);
}

int
nvkm_gpuobj_map(struct nvkm_gpuobj *gpuobj, struct nvkm_vm *vm,
		u32 access, struct nvkm_vma *vma)
{
	struct nvkm_memory *memory = gpuobj->memory;
	int ret = nvkm_vm_get(vm, gpuobj->size, 12, access, vma);
	if (ret == 0)
		nvkm_memory_map(memory, vma, 0);
	return ret;
}

void
nvkm_gpuobj_unmap(struct nvkm_vma *vma)
{
	if (vma->node) {
		nvkm_vm_unmap(vma);
		nvkm_vm_put(vma);
	}
}

/* the below is basically only here to support sharing the paged dma object
 * for PCI(E)GART on <=nv4x chipsets, and should *not* be expected to work
 * anywhere else.
 */

int
nvkm_gpuobj_wrap(struct nvkm_memory *memory, struct nvkm_gpuobj **pgpuobj)
{
	if (!(*pgpuobj = kzalloc(sizeof(**pgpuobj), GFP_KERNEL)))
		return -ENOMEM;

	(*pgpuobj)->addr = nvkm_memory_addr(memory);
	(*pgpuobj)->size = nvkm_memory_size(memory);
	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
9274f4a9	24	#include <core/gpuobj.h>
42594600	25	#include <core/engine.h>
9274f4a9 BS	26
	27	#include <subdev/instmem.h>
	28	#include <subdev/bar.h>
5ce3bf3c	29	#include <subdev/mmu.h>
9274f4a9	30
f027f491 BS	31	/* fast-path, where backend is able to provide direct pointer to memory */
	32	static u32
	33	nvkm_gpuobj_rd32_fast(struct nvkm_gpuobj *gpuobj, u32 offset)
d8e83994	34	{
f027f491	35	return ioread32_native(gpuobj->map + offset);
d8e83994 BS	36	}
	37
	38	static void
f027f491	39	nvkm_gpuobj_wr32_fast(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data)
d8e83994	40	{
f027f491	41	iowrite32_native(data, gpuobj->map + offset);
d8e83994 BS	42	}
d8e83994 BS	43
f027f491	44	/* accessor functions for gpuobjs allocated directly from instmem */
d8e83994	45	static u32
f027f491	46	nvkm_gpuobj_heap_rd32(struct nvkm_gpuobj *gpuobj, u32 offset)
d8e83994	47	{
d8e83994 BS	48	return nvkm_ro32(gpuobj->memory, offset);
	49	}
	50
	51	static void
f027f491	52	nvkm_gpuobj_heap_wr32(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data)
d8e83994	53	{
d8e83994 BS	54	nvkm_wo32(gpuobj->memory, offset, data);
	55	}
	56
f027f491 BS	57	static const struct nvkm_gpuobj_func nvkm_gpuobj_heap;
	58	static void
	59	nvkm_gpuobj_heap_release(struct nvkm_gpuobj *gpuobj)
9274f4a9	60	{
f027f491 BS	61	gpuobj->func = &nvkm_gpuobj_heap;
	62	nvkm_done(gpuobj->memory);
	63	}
9274f4a9	64
f027f491 BS	65	static const struct nvkm_gpuobj_func
	66	nvkm_gpuobj_heap_fast = {
	67	.release = nvkm_gpuobj_heap_release,
	68	.rd32 = nvkm_gpuobj_rd32_fast,
	69	.wr32 = nvkm_gpuobj_wr32_fast,
	70	};
9274f4a9	71
f027f491 BS	72	static const struct nvkm_gpuobj_func
	73	nvkm_gpuobj_heap_slow = {
	74	.release = nvkm_gpuobj_heap_release,
	75	.rd32 = nvkm_gpuobj_heap_rd32,
	76	.wr32 = nvkm_gpuobj_heap_wr32,
	77	};
92485cef	78
f027f491 BS	79	static void *
	80	nvkm_gpuobj_heap_acquire(struct nvkm_gpuobj *gpuobj)
	81	{
	82	gpuobj->map = nvkm_kmap(gpuobj->memory);
	83	if (likely(gpuobj->map))
	84	gpuobj->func = &nvkm_gpuobj_heap_fast;
	85	else
	86	gpuobj->func = &nvkm_gpuobj_heap_slow;
	87	return gpuobj->map;
	88	}
9274f4a9	89
f027f491 BS	90	static const struct nvkm_gpuobj_func
	91	nvkm_gpuobj_heap = {
	92	.acquire = nvkm_gpuobj_heap_acquire,
	93	};
	94
	95	/* accessor functions for gpuobjs sub-allocated from a parent gpuobj */
	96	static u32
	97	nvkm_gpuobj_rd32(struct nvkm_gpuobj *gpuobj, u32 offset)
	98	{
	99	return nvkm_ro32(gpuobj->parent, gpuobj->node->offset + offset);
	100	}
	101
	102	static void
	103	nvkm_gpuobj_wr32(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data)
	104	{
	105	nvkm_wo32(gpuobj->parent, gpuobj->node->offset + offset, data);
	106	}
	107
	108	static const struct nvkm_gpuobj_func nvkm_gpuobj_func;
	109	static void
	110	nvkm_gpuobj_release(struct nvkm_gpuobj *gpuobj)
	111	{
	112	gpuobj->func = &nvkm_gpuobj_func;
	113	nvkm_done(gpuobj->parent);
9274f4a9 BS	114	}
9274f4a9 BS	115
d8e83994	116	static const struct nvkm_gpuobj_func
f027f491 BS	117	nvkm_gpuobj_fast = {
	118	.release = nvkm_gpuobj_release,
	119	.rd32 = nvkm_gpuobj_rd32_fast,
	120	.wr32 = nvkm_gpuobj_wr32_fast,
	121	};
	122
	123	static const struct nvkm_gpuobj_func
	124	nvkm_gpuobj_slow = {
d8e83994 BS	125	.release = nvkm_gpuobj_release,
	126	.rd32 = nvkm_gpuobj_rd32,
	127	.wr32 = nvkm_gpuobj_wr32,
	128	};
	129
f027f491 BS	130	static void *
	131	nvkm_gpuobj_acquire(struct nvkm_gpuobj *gpuobj)
	132	{
	133	gpuobj->map = nvkm_kmap(gpuobj->parent);
	134	if (likely(gpuobj->map)) {
	135	gpuobj->map = (u8 *)gpuobj->map + gpuobj->node->offset;
	136	gpuobj->func = &nvkm_gpuobj_fast;
	137	} else {
	138	gpuobj->func = &nvkm_gpuobj_slow;
	139	}
	140	return gpuobj->map;
	141	}
	142
	143	static const struct nvkm_gpuobj_func
	144	nvkm_gpuobj_func = {
	145	.acquire = nvkm_gpuobj_acquire,
	146	};
	147
	148	static int
	149	nvkm_gpuobj_ctor(struct nvkm_device *device, u32 size, int align, bool zero,
	150	struct nvkm_gpuobj parent, struct nvkm_gpuobj gpuobj)
	151	{
	152	u32 offset;
	153	int ret;
	154
	155	if (parent) {
	156	if (align >= 0) {
	157	ret = nvkm_mm_head(&parent->heap, 0, 1, size, size,
	158	max(align, 1), &gpuobj->node);
	159	} else {
	160	ret = nvkm_mm_tail(&parent->heap, 0, 1, size, size,
	161	-align, &gpuobj->node);
	162	}
	163	if (ret)
	164	return ret;
	165
	166	gpuobj->parent = parent;
	167	gpuobj->func = &nvkm_gpuobj_func;
	168	gpuobj->addr = parent->addr + gpuobj->node->offset;
	169	gpuobj->size = gpuobj->node->length;
	170
	171	if (zero) {
	172	nvkm_kmap(gpuobj);
	173	for (offset = 0; offset < gpuobj->size; offset += 4)
	174	nvkm_wo32(gpuobj, offset, 0x00000000);
	175	nvkm_done(gpuobj);
	176	}
	177	} else {
	178	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size,
	179	abs(align), zero, &gpuobj->memory);
	180	if (ret)
	181	return ret;
	182
	183	gpuobj->func = &nvkm_gpuobj_heap;
	184	gpuobj->addr = nvkm_memory_addr(gpuobj->memory);
	185	gpuobj->size = nvkm_memory_size(gpuobj->memory);
	186	}
	187
	188	return nvkm_mm_init(&gpuobj->heap, 0, gpuobj->size, 1);
	189	}
	190
	191	void
	192	nvkm_gpuobj_del(struct nvkm_gpuobj **pgpuobj)
	193	{
194	struct nvkm_gpuobj gpuobj = pgpuobj;
195	if (gpuobj) {
196	if (gpuobj->parent)
197	nvkm_mm_free(&gpuobj->parent->heap, &gpuobj->node);
198	nvkm_mm_fini(&gpuobj->heap);
199	nvkm_memory_del(&gpuobj->memory);
200	kfree(*pgpuobj);
201	*pgpuobj = NULL;
202	}
203	}
204
205	int
206	nvkm_gpuobj_new(struct nvkm_device *device, u32 size, int align, bool zero,
207	struct nvkm_gpuobj parent, struct nvkm_gpuobj *pgpuobj)
208	{
209	struct nvkm_gpuobj *gpuobj;
210	int ret;
211
212	if (!(gpuobj = pgpuobj = kzalloc(sizeof(gpuobj), GFP_KERNEL)))
213	return -ENOMEM;
214
215	ret = nvkm_gpuobj_ctor(device, size, align, zero, parent, gpuobj);
216	if (ret)
217	nvkm_gpuobj_del(pgpuobj);
218	return ret;
219	}
220
221	void
222	nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
223	{
224	if (gpuobj->node)
225	nvkm_mm_free(&gpuobj->parent->heap, &gpuobj->node);
226
227	gpuobj->heap.block_size = 1;
228	nvkm_mm_fini(&gpuobj->heap);
229
230	nvkm_memory_del(&gpuobj->memory);
231	nvkm_object_destroy(&gpuobj->object);
232	}
233
13de7f46	234	#include <engine/fifo/chan.h>
8f0649b5	235
9274f4a9	236	int
5025407b BS	237	nvkm_gpuobj_create_(struct nvkm_object parent, struct nvkm_object engine,
5025407b BS	238	struct nvkm_oclass *oclass, u32 pclass,
d8e83994	239	struct nvkm_object *objgpu, u32 size, u32 align, u32 flags,
5025407b	240	int length, void **pobject)
9274f4a9	241	{
d8e83994	242	struct nvkm_device *device = nv_device(parent);
d8e83994	243	struct nvkm_gpuobj *pargpu = NULL;
5025407b	244	struct nvkm_gpuobj *gpuobj;
8f0649b5	245	struct nvkm_object *object = objgpu;
f027f491 BS	246	const bool zero = (flags & NVOBJ_FLAG_ZERO_ALLOC);
f027f491 BS	247	int ret;
9274f4a9 BS	248
	249	*pobject = NULL;
	250
8f0649b5 BS	251	while (object && object->func != &nvkm_fifo_chan_func)
	252	object = object->parent;
	253
	254	if (object) {
	255	struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
	256	pargpu = chan->inst;
	257	} else
d8e83994 BS	258	if (objgpu) {
	259	while ((objgpu = nv_pclass(objgpu, NV_GPUOBJ_CLASS))) {
	260	if (nv_gpuobj(objgpu)->heap.block_size)
9274f4a9	261	break;
d8e83994	262	objgpu = objgpu->parent;
9274f4a9 BS	263	}
9274f4a9 BS	264
d8e83994	265	if (WARN_ON(objgpu == NULL))
9274f4a9	266	return -EINVAL;
d8e83994	267	pargpu = nv_gpuobj(objgpu);
9274f4a9 BS	268	}
9274f4a9 BS	269
5025407b BS	270	ret = nvkm_object_create_(parent, engine, oclass, pclass \|
5025407b BS	271	NV_GPUOBJ_CLASS, length, pobject);
9274f4a9	272	gpuobj = *pobject;
9274f4a9 BS	273	if (ret)
	274	return ret;
	275
f027f491 BS	276	ret = nvkm_gpuobj_ctor(device, size, align, zero, pargpu, gpuobj);
	277	if (!(flags & NVOBJ_FLAG_HEAP))
	278	gpuobj->heap.block_size = 0;
	279	return ret;
9274f4a9 BS	280	}
	281
	282	void
5025407b	283	_nvkm_gpuobj_dtor(struct nvkm_object *object)
9274f4a9	284	{
5025407b	285	nvkm_gpuobj_destroy(nv_gpuobj(object));
9274f4a9 BS	286	}
	287
	288	int
5025407b	289	_nvkm_gpuobj_init(struct nvkm_object *object)
9274f4a9	290	{
5025407b	291	return nvkm_gpuobj_init(nv_gpuobj(object));
9274f4a9 BS	292	}
	293
	294	int
5025407b	295	_nvkm_gpuobj_fini(struct nvkm_object *object, bool suspend)
9274f4a9	296	{
5025407b	297	return nvkm_gpuobj_fini(nv_gpuobj(object), suspend);
9274f4a9 BS	298	}
	299
	300	u32
5025407b	301	_nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr)
9274f4a9	302	{
5025407b	303	struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
d8e83994	304	return nvkm_ro32(gpuobj, addr);
9274f4a9 BS	305	}
	306
	307	void
5025407b	308	_nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
9274f4a9	309	{
5025407b	310	struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
d8e83994	311	nvkm_wo32(gpuobj, addr, data);
9274f4a9 BS	312	}
9274f4a9 BS	313
9274f4a9	314	int
f027f491 BS	315	nvkm_gpuobj_map(struct nvkm_gpuobj gpuobj, struct nvkm_vm vm,
f027f491 BS	316	u32 access, struct nvkm_vma *vma)
9274f4a9	317	{
d8e83994 BS	318	struct nvkm_memory *memory = gpuobj->memory;
	319	int ret = nvkm_vm_get(vm, gpuobj->size, 12, access, vma);
	320	if (ret == 0)
	321	nvkm_memory_map(memory, vma, 0);
	322	return ret;
9274f4a9 BS	323	}
	324
	325	void
5025407b	326	nvkm_gpuobj_unmap(struct nvkm_vma *vma)
9274f4a9 BS	327	{
9274f4a9 BS	328	if (vma->node) {
5025407b BS	329	nvkm_vm_unmap(vma);
5025407b BS	330	nvkm_vm_put(vma);
9274f4a9 BS	331	}
	332	}
	333
	334	/* the below is basically only here to support sharing the paged dma object
	335	* for PCI(E)GART on <=nv4x chipsets, and should not be expected to work
	336	* anywhere else.
	337	*/
	338
9274f4a9	339	int
f027f491	340	nvkm_gpuobj_wrap(struct nvkm_memory memory, struct nvkm_gpuobj *pgpuobj)
9274f4a9	341	{
f027f491 BS	342	if (!(pgpuobj = kzalloc(sizeof(*pgpuobj), GFP_KERNEL)))
f027f491 BS	343	return -ENOMEM;
9274f4a9	344
f027f491 BS	345	(*pgpuobj)->addr = nvkm_memory_addr(memory);
f027f491 BS	346	(*pgpuobj)->size = nvkm_memory_size(memory);
9274f4a9 BS	347	return 0;
9274f4a9 BS	348	}