[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / gk104.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

int
gk104_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0xe4:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
		break;
	case 0xe7:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
		break;
	case 0xe6:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
		break;
	case 0xea:
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_gr_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &gk20a_volt_oclass;
		break;
	case 0xf0:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk110_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] = &gk110_pm_oclass;
		break;
	case 0xf1:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] = &gk110_pm_oclass;
		break;
	case 0x106:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		break;
	case 0x108:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
9719047b	24	#include "priv.h"
9274f4a9	25
9274f4a9	26	int
9719047b	27	gk104_identify(struct nvkm_device *device)
9274f4a9 BS	28	{
	29	switch (device->chipset) {
	30	case 0xe4:
c9c0ccae	31	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	32	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	33	device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
f84aff4e	34	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
e3c71eb2	35	device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
878da15a	36	device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
bd6c5cab BS	37	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	38	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	39	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	40	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	41	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	42	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
1914f673	43	device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
9274f4a9 BS	44	break;
9274f4a9 BS	45	case 0xe7:
c9c0ccae	46	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	47	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	48	device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
f84aff4e	49	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
e3c71eb2	50	device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
878da15a	51	device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
bd6c5cab BS	52	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	53	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	54	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	55	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	56	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	57	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
1914f673	58	device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
caba5570 BS	59	break;
caba5570 BS	60	case 0xe6:
c9c0ccae	61	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	62	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	63	device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
f84aff4e	64	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
e3c71eb2	65	device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
878da15a	66	device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
bd6c5cab BS	67	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	68	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	69	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	70	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	71	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	72	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
1914f673	73	device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
9274f4a9	74	break;
52e98f1a	75	case 0xea:
5b85057a	76	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
52e98f1a	77	device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
f84aff4e	78	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
b8bf04e1	79	device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
bd6c5cab	80	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
1914f673	81	device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
ef1df1bc	82	device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
52e98f1a	83	break;
7b4f638b	84	case 0xf0:
9abdbab0	85	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	86	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	87	device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
f84aff4e	88	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
e3c71eb2	89	device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
878da15a	90	device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
bd6c5cab BS	91	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	92	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	93	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	94	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	95	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	96	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
4d34686e	97	device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
9abdbab0 JR	98	break;
9abdbab0 JR	99	case 0xf1:
c9c0ccae	100	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	101	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	102	device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
f84aff4e	103	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
b8bf04e1	104	device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
878da15a	105	device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
bd6c5cab BS	106	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	107	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	108	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	109	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	110	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	111	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
4d34686e	112	device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
aabf19c2	113	break;
8d5e3af1	114	case 0x106:
8d5e3af1	115	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	116	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	117	device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
f84aff4e	118	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
e3c71eb2	119	device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
878da15a	120	device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
bd6c5cab BS	121	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	122	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	123	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	124	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	125	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	126	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
8d5e3af1	127	break;
aabf19c2	128	case 0x108:
c9c0ccae	129	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
5b85057a	130	device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d	131	device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
f84aff4e	132	device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
e3c71eb2	133	device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
878da15a	134	device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
bd6c5cab BS	135	device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
	136	device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
	137	device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
87c33f4e	138	device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20	139	device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657	140	device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
7b4f638b	141	break;
9274f4a9	142	default:
9274f4a9 BS	143	return -EINVAL;
	144	}
	145
	146	return 0;
	147	}