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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
9719047b | 24 | #include "priv.h" |
9274f4a9 | 25 | |
70c0f263 | 26 | #include <subdev/bios.h> |
a10220bb | 27 | #include <subdev/bus.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
f3867f43 | 29 | #include <subdev/clk.h> |
cb75d97e | 30 | #include <subdev/devinit.h> |
7d9115de | 31 | #include <subdev/mc.h> |
5a5c7432 | 32 | #include <subdev/timer.h> |
861d2107 | 33 | #include <subdev/fb.h> |
3863c9bc | 34 | #include <subdev/instmem.h> |
5ce3bf3c | 35 | #include <subdev/mmu.h> |
9274f4a9 | 36 | |
ebb945a9 BS |
37 | #include <engine/dmaobj.h> |
38 | #include <engine/fifo.h> | |
8700287b | 39 | #include <engine/sw.h> |
b8bf04e1 | 40 | #include <engine/gr.h> |
ebb945a9 BS |
41 | #include <engine/disp.h> |
42 | ||
9274f4a9 | 43 | int |
9719047b | 44 | nv04_identify(struct nvkm_device *device) |
9274f4a9 BS |
45 | { |
46 | switch (device->chipset) { | |
47 | case 0x04: | |
2094dd82 | 48 | device->cname = "NV04"; |
9719047b | 49 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
c26fe843 | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 51 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 52 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; |
08f6fbdb | 53 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 54 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
5a5c7432 | 55 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 56 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; |
24a4ae86 | 57 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 58 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 59 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 60 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; |
8700287b | 61 | device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; |
b8bf04e1 | 62 | device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; |
a8f8b489 | 63 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
64 | break; |
65 | case 0x05: | |
2094dd82 | 66 | device->cname = "NV05"; |
9719047b | 67 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
c26fe843 | 68 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 69 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 70 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; |
08f6fbdb | 71 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 72 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
5a5c7432 | 73 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 74 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; |
24a4ae86 | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 76 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 78 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; |
8700287b | 79 | device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; |
b8bf04e1 | 80 | device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; |
a8f8b489 | 81 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
82 | break; |
83 | default: | |
84 | nv_fatal(device, "unknown RIVA chipset\n"); | |
85 | return -EINVAL; | |
86 | } | |
87 | ||
88 | return 0; | |
89 | } |