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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
9719047b | 24 | #include "priv.h" |
9274f4a9 | 25 | |
70c0f263 | 26 | #include <subdev/bios.h> |
a10220bb | 27 | #include <subdev/bus.h> |
e0996aea | 28 | #include <subdev/gpio.h> |
4196faa8 | 29 | #include <subdev/i2c.h> |
f3867f43 | 30 | #include <subdev/clk.h> |
cb75d97e | 31 | #include <subdev/devinit.h> |
7d9115de | 32 | #include <subdev/mc.h> |
5a5c7432 | 33 | #include <subdev/timer.h> |
861d2107 | 34 | #include <subdev/fb.h> |
3863c9bc | 35 | #include <subdev/instmem.h> |
5ce3bf3c | 36 | #include <subdev/mmu.h> |
9274f4a9 | 37 | |
ebb945a9 BS |
38 | #include <engine/dmaobj.h> |
39 | #include <engine/fifo.h> | |
8700287b | 40 | #include <engine/sw.h> |
b8bf04e1 | 41 | #include <engine/gr.h> |
ebb945a9 BS |
42 | #include <engine/mpeg.h> |
43 | #include <engine/disp.h> | |
44 | ||
9274f4a9 | 45 | int |
9719047b | 46 | nv30_identify(struct nvkm_device *device) |
9274f4a9 BS |
47 | { |
48 | switch (device->chipset) { | |
49 | case 0x30: | |
2094dd82 | 50 | device->cname = "NV30"; |
9719047b | 51 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
d93174ec | 52 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
c26fe843 | 53 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 54 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 55 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
08f6fbdb | 56 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
5a5c7432 | 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
24a4ae86 | 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 61 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 64 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 65 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; |
a8f8b489 | 66 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
67 | break; |
68 | case 0x35: | |
2094dd82 | 69 | device->cname = "NV35"; |
9719047b | 70 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
d93174ec | 71 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
c26fe843 | 72 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 73 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 74 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
08f6fbdb | 75 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
5a5c7432 | 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; |
24a4ae86 | 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 80 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 83 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 84 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; |
a8f8b489 | 85 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
86 | break; |
87 | case 0x31: | |
2094dd82 | 88 | device->cname = "NV31"; |
9719047b | 89 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
d93174ec | 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
c26fe843 | 91 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 92 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
08f6fbdb | 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
5a5c7432 | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
24a4ae86 | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 99 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 102 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 103 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; |
ebb945a9 | 104 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
a8f8b489 | 105 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
106 | break; |
107 | case 0x36: | |
2094dd82 | 108 | device->cname = "NV36"; |
9719047b | 109 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
d93174ec | 110 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
c26fe843 | 111 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 112 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 113 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
08f6fbdb | 114 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 115 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
5a5c7432 | 116 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 117 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; |
24a4ae86 | 118 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 119 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 120 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 121 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 122 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 123 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; |
ebb945a9 | 124 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
a8f8b489 | 125 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
126 | break; |
127 | case 0x34: | |
2094dd82 | 128 | device->cname = "NV34"; |
9719047b | 129 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; |
d93174ec | 130 | device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; |
c26fe843 | 131 | device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; |
f3867f43 | 132 | device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; |
cf336014 | 133 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
08f6fbdb | 134 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
48ae0b35 | 135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
5a5c7432 | 136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
24a4ae86 | 138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
5ce3bf3c | 139 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
bc98540b | 140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
16c4f227 | 141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
8700287b | 142 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
b8bf04e1 | 143 | device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; |
ebb945a9 | 144 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
a8f8b489 | 145 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
9274f4a9 BS |
146 | break; |
147 | default: | |
148 | nv_fatal(device, "unknown Rankine chipset\n"); | |
149 | return -EINVAL; | |
150 | } | |
151 | ||
152 | return 0; | |
153 | } |