[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nv50.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

int
nv50_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0x50:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
		break;
	case 0x84:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x86:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x92:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x94:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x96:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x98:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xa0:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt200_pm_oclass;
		break;
	case 0xaa:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xac:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xa3:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xa5:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xa8:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xaf:
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
9719047b	24	#include "priv.h"
9274f4a9	25
9274f4a9	26	int
9719047b	27	nv50_identify(struct nvkm_device *device)
9274f4a9 BS	28	{
	29	switch (device->chipset) {
	30	case 0x50:
c9c0ccae	31	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	32	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227	33	device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
8700287b	34	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	35	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9	36	device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
a8f8b489	37	device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
d5752b9b	38	device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
9274f4a9 BS	39	break;
9274f4a9 BS	40	case 0x84:
c9c0ccae	41	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	42	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	43	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	44	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	45	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	46	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
a56866a9	47	device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
ccdfdf21	48	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
912a29c3	49	device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
878da15a	50	device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
4d34686e	51	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	52	break;
9274f4a9 BS	53	case 0x86:
c9c0ccae	54	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	55	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	56	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	57	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	58	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	59	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
a56866a9	60	device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
ccdfdf21	61	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
912a29c3	62	device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
878da15a	63	device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
4d34686e	64	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	65	break;
9274f4a9 BS	66	case 0x92:
c9c0ccae	67	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	68	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	69	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	70	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	71	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	72	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
a56866a9	73	device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
ccdfdf21	74	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
912a29c3	75	device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
878da15a	76	device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
4d34686e	77	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	78	break;
9274f4a9 BS	79	case 0x94:
c9c0ccae	80	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	81	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	82	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	83	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	84	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	85	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
a56866a9	86	device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
ccdfdf21	87	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
912a29c3	88	device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
878da15a	89	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	90	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	91	break;
9274f4a9 BS	92	case 0x96:
c9c0ccae	93	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	94	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	95	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	96	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	97	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	98	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
a56866a9	99	device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
ccdfdf21	100	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
912a29c3	101	device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
878da15a	102	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	103	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	104	break;
9274f4a9 BS	105	case 0x98:
c9c0ccae	106	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	107	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	108	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	109	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	110	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e3332c20	111	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
25a64025	112	device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
87c33f4e	113	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	114	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
878da15a	115	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	116	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	117	break;
9274f4a9 BS	118	case 0xa0:
c9c0ccae	119	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	120	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	121	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	122	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	123	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	124	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
a56866a9	125	device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
ccdfdf21	126	device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
912a29c3	127	device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
878da15a	128	device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
06b7972d	129	device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
9274f4a9 BS	130	break;
9274f4a9 BS	131	case 0xaa:
c9c0ccae	132	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	133	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	134	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	135	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	136	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e3332c20	137	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
25a64025	138	device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
87c33f4e	139	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	140	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
878da15a	141	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	142	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	143	break;
9274f4a9 BS	144	case 0xac:
c9c0ccae	145	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	146	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	147	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	148	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	149	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e3332c20	150	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
25a64025	151	device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
87c33f4e	152	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	153	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
878da15a	154	device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
4d34686e	155	device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
9274f4a9 BS	156	break;
9274f4a9 BS	157	case 0xa3:
c9c0ccae	158	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	159	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	160	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	161	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	162	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e7c29683	163	device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
e3332c20	164	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
87c33f4e	165	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	166	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
bd6c5cab	167	device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
878da15a	168	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	169	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	170	break;
9274f4a9 BS	171	case 0xa5:
c9c0ccae	172	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	173	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	174	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	175	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	176	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e3332c20	177	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
87c33f4e	178	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	179	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
bd6c5cab	180	device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
878da15a	181	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	182	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	183	break;
9274f4a9 BS	184	case 0xa8:
c9c0ccae	185	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	186	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	187	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	188	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	189	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e3332c20	190	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
87c33f4e	191	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	192	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
bd6c5cab	193	device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
878da15a	194	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	195	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	196	break;
9274f4a9 BS	197	case 0xaf:
c9c0ccae	198	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b	199	device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
05c7145d	200	device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
8700287b	201	device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1	202	device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
e3332c20	203	device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
87c33f4e	204	device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
87a87657	205	device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
bd6c5cab	206	device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
878da15a	207	device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
4d34686e	208	device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
9274f4a9 BS	209	break;
9274f4a9 BS	210	default:
9274f4a9 BS	211	return -EINVAL;
	212	}
	213
	214	return 0;
	215	}