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drm/nouveau/bsp: namespace + nvidia gpu names (no binary change)
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nv50.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
70c0f263 25#include <subdev/bios.h>
a10220bb 26#include <subdev/bus.h>
e0996aea 27#include <subdev/gpio.h>
4196faa8 28#include <subdev/i2c.h>
3ca6cd43 29#include <subdev/fuse.h>
f3867f43 30#include <subdev/clk.h>
aa1b9b48 31#include <subdev/therm.h>
d38ac521 32#include <subdev/mxm.h>
cb75d97e 33#include <subdev/devinit.h>
7d9115de 34#include <subdev/mc.h>
5a5c7432 35#include <subdev/timer.h>
861d2107 36#include <subdev/fb.h>
3863c9bc 37#include <subdev/instmem.h>
5ce3bf3c 38#include <subdev/mmu.h>
3863c9bc 39#include <subdev/bar.h>
ebb58dc2 40#include <subdev/pmu.h>
c9c0ccae 41#include <subdev/volt.h>
9274f4a9 42
dded35de 43#include <engine/device.h>
ebb945a9
BS		 44#include <engine/dmaobj.h>
45#include <engine/fifo.h>
8700287b 46#include <engine/sw.h>
b8bf04e1 47#include <engine/gr.h>
ebb945a9
BS		 48#include <engine/mpeg.h>
49#include <engine/vp.h>
93d90ad7
BS		 50#include <engine/cipher.h>
51#include <engine/sec.h>
ebb945a9 52#include <engine/bsp.h>
eccf7e8a 53#include <engine/msvld.h>
37a5d028 54#include <engine/mspdec.h>
fd8666f7 55#include <engine/msppp.h>
aedf24ff 56#include <engine/ce.h>
ebb945a9 57#include <engine/disp.h>
d5752b9b 58#include <engine/pm.h>
ebb945a9 59
9274f4a9
BS		 60int
61nv50_identify(struct nouveau_device *device)
62{
63 switch (device->chipset) {
64 case 0x50:
2094dd82 65 device->cname = "G80";
70c0f263 66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 67 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 68 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
630ec6c0 69 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
f3867f43 70 device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
aa1b9b48 71 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
d38ac521 72 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014 73 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
08f6fbdb 74 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 75 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 76 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 77 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
24a4ae86 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 79 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 80 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 82 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 83 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
8700287b 84 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 85 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9 86 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
a8f8b489 87 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
d5752b9b 88 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
9274f4a9
BS		 89 break;
90 case 0x84:
2094dd82 91 device->cname = "G84";
70c0f263 92 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 93 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 94 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
630ec6c0 95 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 96 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 97 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 98 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 99 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
08f6fbdb 100 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 101 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 102 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 103 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 104 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 105 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 106 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 107 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 108 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 109 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 110 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 111 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9
BS		 112 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
113 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
93d90ad7 114 device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
912a29c3 115 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
a8f8b489 116 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
d5752b9b 117 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 118 break;
119 case 0x86:
2094dd82 120 device->cname = "G86";
70c0f263 121 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 122 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 123 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
630ec6c0 124 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 125 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 126 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 127 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
08f6fbdb 129 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 132 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 135 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 138 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 139 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 140 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9
BS		 141 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
142 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
93d90ad7 143 device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
912a29c3 144 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
a8f8b489 145 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
d5752b9b 146 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 147 break;
148 case 0x92:
2094dd82 149 device->cname = "G92";
70c0f263 150 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 151 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 152 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
630ec6c0 153 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 154 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 155 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 156 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 157 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
08f6fbdb 158 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 159 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 160 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 161 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 162 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 163 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 165 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 166 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 167 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 168 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 169 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9
BS		 170 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
171 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
93d90ad7 172 device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
912a29c3 173 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
a8f8b489 174 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
d5752b9b 175 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 176 break;
177 case 0x94:
2094dd82 178 device->cname = "G94";
70c0f263 179 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 180 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 181 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 182 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 183 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 184 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 185 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 186 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
d7e5fcd2 187 device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
5f8824de 188 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 189 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 190 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 191 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 192 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 193 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 194 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 195 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 196 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 197 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 198 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9
BS		 199 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
200 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
93d90ad7 201 device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
912a29c3 202 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
a8f8b489 203 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
d5752b9b 204 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 205 break;
206 case 0x96:
2094dd82 207 device->cname = "G96";
70c0f263 208 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 209 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 210 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 211 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 212 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 213 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 214 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 215 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
d7e5fcd2 216 device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
5f8824de 217 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 218 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 219 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 220 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 221 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 222 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 223 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 224 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 225 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 226 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 227 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9
BS		 228 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
229 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
93d90ad7 230 device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
912a29c3 231 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
a8f8b489 232 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
d5752b9b 233 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 234 break;
235 case 0x98:
2094dd82 236 device->cname = "G98";
70c0f263 237 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 238 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 239 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 240 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 241 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 242 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 243 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
d7e5fcd2 245 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 246 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 248 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 249 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 250 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 252 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 253 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 254 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 255 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 256 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
37a5d028 257 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
93d90ad7 258 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
eccf7e8a 259 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 260 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
a8f8b489 261 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
d5752b9b 262 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 263 break;
264 case 0xa0:
2094dd82 265 device->cname = "G200";
70c0f263 266 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 267 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
c26fe843 268 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
630ec6c0 269 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 270 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
e1404611 271 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 272 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 273 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
d7e5fcd2 274 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 275 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 276 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 277 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
24a4ae86 278 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 279 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 280 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 281 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 282 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 283 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 284 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 285 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9
BS		 286 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
287 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
93d90ad7 288 device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
912a29c3 289 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
a8f8b489 290 device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
d5752b9b 291 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 292 break;
293 case 0xaa:
2094dd82 294 device->cname = "MCP77/MCP78";
70c0f263 295 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 296 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 297 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 298 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 299 device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
e1404611 300 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 301 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 302 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
d7e5fcd2 303 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 304 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 305 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 306 device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
24a4ae86 307 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 308 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 309 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 312 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 313 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 314 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
37a5d028 315 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
93d90ad7 316 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
eccf7e8a 317 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 318 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
a8f8b489 319 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
d5752b9b 320 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 321 break;
322 case 0xac:
2094dd82 323 device->cname = "MCP79/MCP7A";
70c0f263 324 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 325 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 326 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 327 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 328 device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
e1404611 329 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
d38ac521 330 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 331 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
d7e5fcd2 332 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 333 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 335 device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
24a4ae86 336 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 337 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 338 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 339 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 340 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 341 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 342 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 343 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
37a5d028 344 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
93d90ad7 345 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
eccf7e8a 346 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 347 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
a8f8b489 348 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
d5752b9b 349 device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
9274f4a9
BS		 350 break;
351 case 0xa3:
2094dd82 352 device->cname = "GT215";
70c0f263 353 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 354 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 355 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 356 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 357 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
e1404611 358 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
d38ac521 359 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 360 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
d7e5fcd2 361 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 362 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 363 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 364 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
24a4ae86 365 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 366 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 367 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
21b13791 368 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
c9c0ccae 369 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 370 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 371 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 372 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 373 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
ebb945a9 374 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
37a5d028 375 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
eccf7e8a 376 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 377 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
aedf24ff 378 device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
a8f8b489 379 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 380 device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
9274f4a9
BS		 381 break;
382 case 0xa5:
2094dd82 383 device->cname = "GT216";
70c0f263 384 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 385 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 386 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 387 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 388 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
e1404611 389 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
d38ac521 390 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 391 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
d7e5fcd2 392 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 393 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 394 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 395 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
24a4ae86 396 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 397 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 398 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
21b13791 399 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
c9c0ccae 400 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 401 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 402 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 403 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 404 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
37a5d028 405 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
eccf7e8a 406 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 407 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
aedf24ff 408 device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
a8f8b489 409 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 410 device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
9274f4a9
BS		 411 break;
412 case 0xa8:
2094dd82 413 device->cname = "GT218";
70c0f263 414 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 415 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 416 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 417 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 418 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
e1404611 419 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
d38ac521 420 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 421 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
d7e5fcd2 422 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 423 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 424 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 425 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
24a4ae86 426 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 427 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 428 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
21b13791 429 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
c9c0ccae 430 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 431 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 432 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 433 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 434 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
37a5d028 435 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
eccf7e8a 436 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 437 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
aedf24ff 438 device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
a8f8b489 439 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 440 device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
9274f4a9
BS		 441 break;
442 case 0xaf:
2094dd82 443 device->cname = "MCP89";
70c0f263 444 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
4e7659fc 445 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
b9ec1424 446 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
630ec6c0 447 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
7632b30e 448 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
e1404611 449 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
d38ac521 450 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 451 device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
d7e5fcd2 452 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
5f8824de 453 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
5a5c7432 454 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
639c308e 455 device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
24a4ae86 456 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 457 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
3863c9bc 458 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
21b13791 459 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
c9c0ccae 460 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 461 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 462 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
8700287b 463 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
b8bf04e1 464 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
37a5d028 465 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
eccf7e8a 466 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
fd8666f7 467 device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
aedf24ff 468 device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
a8f8b489 469 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 470 device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
9274f4a9
BS		 471 break;
472 default:
473 nv_fatal(device, "unknown Tesla chipset\n");
474 return -EINVAL;
475 }
476
477 return 0;
478}
Linux kernel - Deliverables
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