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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
70c0f263 | 25 | #include <subdev/bios.h> |
a10220bb | 26 | #include <subdev/bus.h> |
e0996aea | 27 | #include <subdev/gpio.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
3ca6cd43 | 29 | #include <subdev/fuse.h> |
f3867f43 | 30 | #include <subdev/clk.h> |
aa1b9b48 | 31 | #include <subdev/therm.h> |
d38ac521 | 32 | #include <subdev/mxm.h> |
cb75d97e | 33 | #include <subdev/devinit.h> |
7d9115de | 34 | #include <subdev/mc.h> |
5a5c7432 | 35 | #include <subdev/timer.h> |
861d2107 | 36 | #include <subdev/fb.h> |
95484b57 | 37 | #include <subdev/ltc.h> |
2c1a425e | 38 | #include <subdev/ibus.h> |
3863c9bc | 39 | #include <subdev/instmem.h> |
5ce3bf3c | 40 | #include <subdev/mmu.h> |
3863c9bc | 41 | #include <subdev/bar.h> |
ebb58dc2 | 42 | #include <subdev/pmu.h> |
c9c0ccae | 43 | #include <subdev/volt.h> |
9274f4a9 | 44 | |
dded35de | 45 | #include <engine/device.h> |
ebb945a9 BS |
46 | #include <engine/dmaobj.h> |
47 | #include <engine/fifo.h> | |
8700287b | 48 | #include <engine/sw.h> |
b8bf04e1 | 49 | #include <engine/gr.h> |
ebb945a9 | 50 | #include <engine/disp.h> |
aedf24ff | 51 | #include <engine/ce.h> |
b2f04fc6 | 52 | #include <engine/bsp.h> |
eccf7e8a | 53 | #include <engine/msvld.h> |
37a5d028 | 54 | #include <engine/mspdec.h> |
fd8666f7 | 55 | #include <engine/msppp.h> |
d5752b9b | 56 | #include <engine/pm.h> |
ebb945a9 | 57 | |
9274f4a9 BS |
58 | int |
59 | nve0_identify(struct nouveau_device *device) | |
60 | { | |
61 | switch (device->chipset) { | |
62 | case 0xe4: | |
2094dd82 | 63 | device->cname = "GK104"; |
70c0f263 | 64 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
d93174ec | 65 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; |
0ff32977 | 66 | device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; |
3ca6cd43 | 67 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
7632b30e | 68 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
bc79202f | 69 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
d38ac521 | 70 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 72 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
5f8824de | 73 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
5a5c7432 | 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
aae95ca7 | 75 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
95484b57 | 76 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
2c1a425e | 77 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
24a4ae86 | 78 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
5ce3bf3c | 79 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 80 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 81 | device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; |
c9c0ccae | 82 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
bc98540b | 83 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
16c4f227 | 84 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
8700287b | 85 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 86 | device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; |
a8f8b489 | 87 | device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; |
aedf24ff BS |
88 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
89 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
90 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 91 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 92 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 93 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
d5752b9b | 94 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
9274f4a9 BS |
95 | break; |
96 | case 0xe7: | |
2094dd82 | 97 | device->cname = "GK107"; |
70c0f263 | 98 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
d93174ec | 99 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; |
0ff32977 | 100 | device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; |
3ca6cd43 | 101 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
7632b30e | 102 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
bc79202f | 103 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
d38ac521 | 104 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 105 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 106 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
5f8824de | 107 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
5a5c7432 | 108 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
aae95ca7 | 109 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
95484b57 | 110 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
caba5570 | 111 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
24a4ae86 | 112 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
5ce3bf3c | 113 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 114 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 115 | device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; |
c9c0ccae | 116 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
bc98540b | 117 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
16c4f227 | 118 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
8700287b | 119 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 120 | device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; |
a8f8b489 | 121 | device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; |
aedf24ff BS |
122 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
123 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
124 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 125 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 126 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 127 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
d5752b9b | 128 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
caba5570 BS |
129 | break; |
130 | case 0xe6: | |
131 | device->cname = "GK106"; | |
132 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
d93174ec | 133 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; |
0ff32977 | 134 | device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; |
3ca6cd43 | 135 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
7632b30e | 136 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
bc79202f | 137 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
caba5570 | 138 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cf336014 | 139 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 140 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
5f8824de | 141 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
caba5570 | 142 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
aae95ca7 | 143 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
95484b57 | 144 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
2c1a425e | 145 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
24a4ae86 | 146 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
5ce3bf3c | 147 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 148 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 149 | device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; |
c9c0ccae | 150 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
bc98540b | 151 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
16c4f227 | 152 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
8700287b | 153 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 154 | device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; |
a8f8b489 | 155 | device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; |
aedf24ff BS |
156 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
157 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
158 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 159 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 160 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 161 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
d5752b9b | 162 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
9274f4a9 | 163 | break; |
52e98f1a AC |
164 | case 0xea: |
165 | device->cname = "GK20A"; | |
f3867f43 | 166 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; |
7d155dac | 167 | device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; |
5f8824de | 168 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
3ca6cd43 | 169 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
52e98f1a AC |
170 | device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; |
171 | device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; | |
5d6d94f7 | 172 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
52e98f1a AC |
173 | device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; |
174 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; | |
5ce3bf3c | 175 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
ec1afbf4 | 176 | device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; |
bc98540b | 177 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
52e98f1a | 178 | device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; |
8700287b | 179 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 180 | device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; |
aedf24ff | 181 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; |
d5752b9b | 182 | device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; |
ef1df1bc | 183 | device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; |
ebb58dc2 | 184 | device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; |
52e98f1a | 185 | break; |
7b4f638b BS |
186 | case 0xf0: |
187 | device->cname = "GK110"; | |
188 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
d93174ec | 189 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; |
0ff32977 | 190 | device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; |
3ca6cd43 | 191 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
7632b30e | 192 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
7b4f638b BS |
193 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
194 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
cf336014 | 195 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
1b4fea0f | 196 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
5f8824de | 197 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
7b4f638b | 198 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
aae95ca7 | 199 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
95484b57 | 200 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
9abdbab0 JR |
201 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
202 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; | |
5ce3bf3c | 203 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 204 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 205 | device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; |
9abdbab0 | 206 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
bc98540b | 207 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
9abdbab0 | 208 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
8700287b | 209 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 210 | device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass; |
9abdbab0 | 211 | device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; |
aedf24ff BS |
212 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
213 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
214 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 215 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 216 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 217 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
d5752b9b | 218 | device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; |
9abdbab0 JR |
219 | break; |
220 | case 0xf1: | |
221 | device->cname = "GK110B"; | |
222 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
d93174ec | 223 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; |
c26fe843 | 224 | device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; |
3ca6cd43 | 225 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
7632b30e | 226 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
9abdbab0 JR |
227 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
228 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
229 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; | |
230 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | |
5f8824de | 231 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
9abdbab0 JR |
232 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
233 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | |
95484b57 | 234 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
7b4f638b | 235 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
24a4ae86 | 236 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
5ce3bf3c | 237 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 238 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 239 | device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; |
c9c0ccae | 240 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
bc98540b | 241 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
16c4f227 | 242 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
8700287b | 243 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 244 | device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; |
a8f8b489 | 245 | device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; |
aedf24ff BS |
246 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
247 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
248 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 249 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 250 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 251 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
d5752b9b | 252 | device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; |
aabf19c2 | 253 | break; |
8d5e3af1 SK |
254 | case 0x106: |
255 | device->cname = "GK208B"; | |
256 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
257 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; | |
258 | device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; | |
259 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; | |
7632b30e | 260 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
8d5e3af1 SK |
261 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
262 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
263 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; | |
264 | device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; | |
5f8824de | 265 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
8d5e3af1 SK |
266 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
267 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | |
268 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; | |
269 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | |
270 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; | |
5ce3bf3c | 271 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 272 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 273 | device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; |
8d5e3af1 SK |
274 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; | |
276 | device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; | |
8700287b | 277 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 278 | device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; |
8d5e3af1 | 279 | device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; |
aedf24ff BS |
280 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
281 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
282 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 283 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 284 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 285 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
8d5e3af1 | 286 | break; |
aabf19c2 BS |
287 | case 0x108: |
288 | device->cname = "GK208"; | |
289 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
d93174ec | 290 | device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; |
0ff32977 | 291 | device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; |
3ca6cd43 | 292 | device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; |
7632b30e | 293 | device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; |
aabf19c2 BS |
294 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
295 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
cf336014 | 296 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
7d155dac | 297 | device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; |
5f8824de | 298 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
aabf19c2 | 299 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
aae95ca7 | 300 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
95484b57 | 301 | device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; |
aabf19c2 | 302 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
24a4ae86 | 303 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
5ce3bf3c | 304 | device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; |
245dcfe9 | 305 | device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; |
ebb58dc2 | 306 | device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; |
c9c0ccae | 307 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
bc98540b | 308 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; |
a763951a | 309 | device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; |
8700287b | 310 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; |
b8bf04e1 | 311 | device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; |
a8f8b489 | 312 | device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; |
aedf24ff BS |
313 | device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; |
314 | device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; | |
315 | device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; | |
eccf7e8a | 316 | device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; |
37a5d028 | 317 | device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; |
fd8666f7 | 318 | device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; |
7b4f638b | 319 | break; |
9274f4a9 BS |
320 | default: |
321 | nv_fatal(device, "unknown Kepler chipset\n"); | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | } |