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6ee73861 | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
6ee73861 | 3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
6ee73861 | 10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. | |
6ee73861 | 13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
6ee73861 | 21 | * |
ebb945a9 | 22 | * Authors: Ben Skeggs |
6ee73861 | 23 | */ |
05c7145d | 24 | #include "nv04.h" |
6ee73861 | 25 | |
bbf8906b | 26 | #include <core/client.h> |
ebb945a9 | 27 | #include <core/engctx.h> |
d8e83994 | 28 | #include <subdev/instmem.h> |
ebb945a9 | 29 | |
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30 | #include <nvif/class.h> |
31 | #include <nvif/unpack.h> | |
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32 | |
33 | static struct ramfc_desc | |
34 | nv10_ramfc[] = { | |
c420b2dc BS |
35 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, |
36 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, | |
37 | { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, | |
38 | { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, | |
39 | { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, | |
40 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, | |
41 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, | |
42 | { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, | |
43 | { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, | |
44 | {} | |
45 | }; | |
46 | ||
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47 | /******************************************************************************* |
48 | * FIFO channel objects | |
49 | ******************************************************************************/ | |
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50 | |
51 | static int | |
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52 | nv10_fifo_chan_ctor(struct nvkm_object *parent, |
53 | struct nvkm_object *engine, | |
54 | struct nvkm_oclass *oclass, void *data, u32 size, | |
55 | struct nvkm_object **pobject) | |
6ee73861 | 56 | { |
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57 | union { |
58 | struct nv03_channel_dma_v0 v0; | |
59 | } *args = data; | |
6189f1b0 | 60 | struct nv04_fifo *fifo = (void *)engine; |
5b1ab0c2 | 61 | struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; |
ebb945a9 | 62 | struct nv04_fifo_chan *chan; |
6ee73861 BS |
63 | int ret; |
64 | ||
53003941 | 65 | nvif_ioctl(parent, "create channel dma size %d\n", size); |
bbf8906b | 66 | if (nvif_unpack(args->v0, 0, 0, false)) { |
bf81df9b | 67 | nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " |
159045cd | 68 | "offset %08x\n", args->v0.version, |
53003941 | 69 | args->v0.pushbuf, args->v0.offset); |
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70 | } else |
71 | return ret; | |
ebb945a9 | 72 | |
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73 | ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
74 | 0x10000, args->v0.pushbuf, | |
75 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | |
76 | (1ULL << NVDEV_ENGINE_SW) | | |
77 | (1ULL << NVDEV_ENGINE_GR), &chan); | |
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78 | *pobject = nv_object(chan); |
79 | if (ret) | |
80 | return ret; | |
81 | ||
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82 | args->v0.chid = chan->base.chid; |
83 | ||
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84 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
85 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | |
4c2d4222 | 86 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
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87 | chan->ramfc = chan->base.chid * 32; |
88 | ||
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89 | nvkm_kmap(imem->ramfc); |
90 | nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); | |
91 | nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); | |
92 | nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); | |
93 | nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, | |
70ee6f1c BS |
94 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
95 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | | |
6ee73861 | 96 | #ifdef __BIG_ENDIAN |
70ee6f1c | 97 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
6ee73861 | 98 | #endif |
70ee6f1c | 99 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); |
5b1ab0c2 | 100 | nvkm_done(imem->ramfc); |
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101 | return 0; |
102 | } | |
6ee73861 | 103 | |
05c7145d | 104 | static struct nvkm_ofuncs |
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105 | nv10_fifo_ofuncs = { |
106 | .ctor = nv10_fifo_chan_ctor, | |
107 | .dtor = nv04_fifo_chan_dtor, | |
108 | .init = nv04_fifo_chan_init, | |
109 | .fini = nv04_fifo_chan_fini, | |
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110 | .map = _nvkm_fifo_channel_map, |
111 | .rd32 = _nvkm_fifo_channel_rd32, | |
112 | .wr32 = _nvkm_fifo_channel_wr32, | |
113 | .ntfy = _nvkm_fifo_channel_ntfy | |
ebb945a9 | 114 | }; |
6ee73861 | 115 | |
05c7145d | 116 | static struct nvkm_oclass |
ebb945a9 | 117 | nv10_fifo_sclass[] = { |
bbf8906b | 118 | { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, |
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119 | {} |
120 | }; | |
121 | ||
122 | /******************************************************************************* | |
123 | * FIFO context - basically just the instmem reserved for the channel | |
124 | ******************************************************************************/ | |
125 | ||
05c7145d | 126 | static struct nvkm_oclass |
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127 | nv10_fifo_cclass = { |
128 | .handle = NV_ENGCTX(FIFO, 0x10), | |
05c7145d | 129 | .ofuncs = &(struct nvkm_ofuncs) { |
ebb945a9 | 130 | .ctor = nv04_fifo_context_ctor, |
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131 | .dtor = _nvkm_fifo_context_dtor, |
132 | .init = _nvkm_fifo_context_init, | |
133 | .fini = _nvkm_fifo_context_fini, | |
134 | .rd32 = _nvkm_fifo_context_rd32, | |
135 | .wr32 = _nvkm_fifo_context_wr32, | |
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136 | }, |
137 | }; | |
138 | ||
139 | /******************************************************************************* | |
140 | * PFIFO engine | |
141 | ******************************************************************************/ | |
6ee73861 | 142 | |
ebb945a9 | 143 | static int |
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144 | nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
145 | struct nvkm_oclass *oclass, void *data, u32 size, | |
146 | struct nvkm_object **pobject) | |
6ee73861 | 147 | { |
6189f1b0 | 148 | struct nv04_fifo *fifo; |
ebb945a9 | 149 | int ret; |
6ee73861 | 150 | |
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151 | ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); |
152 | *pobject = nv_object(fifo); | |
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153 | if (ret) |
154 | return ret; | |
155 | ||
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156 | nv_subdev(fifo)->unit = 0x00000100; |
157 | nv_subdev(fifo)->intr = nv04_fifo_intr; | |
158 | nv_engine(fifo)->cclass = &nv10_fifo_cclass; | |
159 | nv_engine(fifo)->sclass = nv10_fifo_sclass; | |
160 | fifo->base.pause = nv04_fifo_pause; | |
161 | fifo->base.start = nv04_fifo_start; | |
162 | fifo->ramfc_desc = nv10_ramfc; | |
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163 | return 0; |
164 | } | |
ebb945a9 | 165 | |
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166 | struct nvkm_oclass * |
167 | nv10_fifo_oclass = &(struct nvkm_oclass) { | |
ebb945a9 | 168 | .handle = NV_ENGINE(FIFO, 0x10), |
05c7145d | 169 | .ofuncs = &(struct nvkm_ofuncs) { |
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170 | .ctor = nv10_fifo_ctor, |
171 | .dtor = nv04_fifo_dtor, | |
172 | .init = nv04_fifo_init, | |
05c7145d | 173 | .fini = _nvkm_fifo_fini, |
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174 | }, |
175 | }; |