[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / nv20.c

#include "nv20.h"
#include "regs.h"

#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
#include <subdev/timer.h>

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

int
nv20_gr_chan_init(struct nvkm_object *object)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	struct nv20_gr *gr = chan->gr;
	u32 inst = nvkm_memory_addr(chan->inst);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
	nvkm_done(gr->ctxtab);
	return 0;
}

int
nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	struct nv20_gr *gr = chan->gr;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	u32 inst = nvkm_memory_addr(chan->inst);
	int chid = -1;

	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	if (nvkm_rd32(device, 0x400144) & 0x00010000)
		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nvkm_wr32(device, 0x400784, inst >> 4);
		nvkm_wr32(device, 0x400788, 0x00000002);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
		nvkm_wr32(device, 0x400144, 0x10000000);
		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
	}
	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	nvkm_done(gr->ctxtab);
	return 0;
}

void *
nv20_gr_chan_dtor(struct nvkm_object *object)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	nvkm_memory_del(&chan->inst);
	return chan;
}

static const struct nvkm_object_func
nv20_gr_chan = {
	.dtor = nv20_gr_chan_dtor,
	.init = nv20_gr_chan_init,
	.fini = nv20_gr_chan_fini,
};

static int
nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
		 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
	struct nv20_gr *gr = nv20_gr(base);
	struct nv20_gr_chan *chan;
	int ret, i;

	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
		return -ENOMEM;
	nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
	chan->gr = gr;
	chan->chid = fifoch->chid;
	*pobject = &chan->object;

	ret = nvkm_memory_new(gr->base.engine.subdev.device,
			      NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
			      &chan->inst);
	if (ret)
		return ret;

	nvkm_kmap(chan->inst);
	nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
	nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
	nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
	nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
	nvkm_wo32(chan->inst, 0x047c, 0x00000101);
	nvkm_wo32(chan->inst, 0x0490, 0x00000111);
	nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
	for (i = 0x04d4; i <= 0x04e0; i += 4)
		nvkm_wo32(chan->inst, i, 0x00030303);
	for (i = 0x04f4; i <= 0x0500; i += 4)
		nvkm_wo32(chan->inst, i, 0x00080000);
	for (i = 0x050c; i <= 0x0518; i += 4)
		nvkm_wo32(chan->inst, i, 0x01012000);
	for (i = 0x051c; i <= 0x0528; i += 4)
		nvkm_wo32(chan->inst, i, 0x000105b8);
	for (i = 0x052c; i <= 0x0538; i += 4)
		nvkm_wo32(chan->inst, i, 0x00080008);
	for (i = 0x055c; i <= 0x0598; i += 4)
		nvkm_wo32(chan->inst, i, 0x07ff0000);
	nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
	nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
	nvkm_wo32(chan->inst, 0x0604, 0x00004000);
	nvkm_wo32(chan->inst, 0x0610, 0x00000001);
	nvkm_wo32(chan->inst, 0x0618, 0x00040000);
	nvkm_wo32(chan->inst, 0x061c, 0x00010000);
	for (i = 0x1c1c; i <= 0x248c; i += 16) {
		nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
		nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
		nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
	}
	nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
	nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
	nvkm_wo32(chan->inst, 0x285c, 0x40000000);
	nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
	nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
	nvkm_wo32(chan->inst, 0x286c, 0x40000000);
	nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
	nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
	nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
	nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
	nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
	nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
	for (i = 0x355c; i <= 0x3578; i += 4)
		nvkm_wo32(chan->inst, i, 0x001c527c);
	nvkm_done(chan->inst);
	return 0;
}

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

void
nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
{
	struct nv20_gr *gr = nv20_gr(base);
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fifo *fifo = device->fifo;
	unsigned long flags;

	nvkm_fifo_pause(fifo, &flags);
	nv04_gr_idle(&gr->base);

	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);

	if (device->chipset != 0x34) {
		nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	}

	nvkm_fifo_start(fifo, &flags);
}

void
nv20_gr_intr(struct nvkm_gr *base)
{
	struct nv20_gr *gr = nv20_gr(base);
	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	struct nvkm_device *device = subdev->device;
	struct nvkm_fifo_chan *chan;
	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
	u32 chid = (addr & 0x01f00000) >> 20;
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
	u32 show = stat;
	char msg[128], src[128], sta[128];
	unsigned long flags;

	chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);

	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
		nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
		nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
		nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
				   "nstatus %08x [%s] ch %d [%s] subc %d "
				   "class %04x mthd %04x data %08x\n",
			   show, msg, nsource, src, nstatus, sta, chid,
			   chan ? chan->object.client->name : "unknown",
			   subc, class, mthd, data);
	}

	nvkm_fifo_chan_put(device->fifo, flags, &chan);
}

int
nv20_gr_oneinit(struct nvkm_gr *base)
{
	struct nv20_gr *gr = nv20_gr(base);
	return nvkm_memory_new(gr->base.engine.subdev.device,
			       NVKM_MEM_TARGET_INST, 32 * 4, 16,
			       true, &gr->ctxtab);
}

int
nv20_gr_init(struct nvkm_gr *base)
{
	struct nv20_gr *gr = nv20_gr(base);
	struct nvkm_device *device = gr->base.engine.subdev.device;
	u32 tmp, vramsz;
	int i;

	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
			  nvkm_memory_addr(gr->ctxtab) >> 4);

	if (device->chipset == 0x20) {
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
		for (i = 0; i < 15; i++)
			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
	} else {
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
		for (i = 0; i < 32; i++)
			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
	}

	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
	nvkm_wr32(device, 0x40009C           , 0x00000040);

	if (device->chipset >= 0x25) {
		nvkm_wr32(device, 0x400890, 0x00a8cfff);
		nvkm_wr32(device, 0x400610, 0x304B1FB6);
		nvkm_wr32(device, 0x400B80, 0x1cbd3883);
		nvkm_wr32(device, 0x400B84, 0x44000000);
		nvkm_wr32(device, 0x400098, 0x40000080);
		nvkm_wr32(device, 0x400B88, 0x000000ff);

	} else {
		nvkm_wr32(device, 0x400880, 0x0008c7df);
		nvkm_wr32(device, 0x400094, 0x00000005);
		nvkm_wr32(device, 0x400B80, 0x45eae20e);
		nvkm_wr32(device, 0x400B84, 0x24000000);
		nvkm_wr32(device, 0x400098, 0x00000040);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
	}

	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));

	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);

	/* begin RAM config */
	vramsz = nv_device_resource_len(device, 1) - 1;
	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
	nvkm_wr32(device, 0x400820, 0);
	nvkm_wr32(device, 0x400824, 0);
	nvkm_wr32(device, 0x400864, vramsz - 1);
	nvkm_wr32(device, 0x400868, vramsz - 1);

	/* interesting.. the below overwrites some of the tile setup above.. */
	nvkm_wr32(device, 0x400B20, 0x00000000);
	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);

	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
	return 0;
}

void *
nv20_gr_dtor(struct nvkm_gr *base)
{
	struct nv20_gr *gr = nv20_gr(base);
	nvkm_memory_del(&gr->ctxtab);
	return gr;
}

int
nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
	     int index, struct nvkm_gr **pgr)
{
	struct nv20_gr *gr;

	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
		return -ENOMEM;
	*pgr = &gr->base;

	return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base);
}

static const struct nvkm_gr_func
nv20_gr = {
	.dtor = nv20_gr_dtor,
	.oneinit = nv20_gr_oneinit,
	.init = nv20_gr_init,
	.intr = nv20_gr_intr,
	.tile = nv20_gr_tile,
	.chan_new = nv20_gr_chan_new,
	.sclass = {
		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
		{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
		{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
		{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
		{}
	}
};

int
nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
{
	return nv20_gr_new_(&nv20_gr, device, index, pgr);
}
Commit	Line	Data
e3c71eb2 BS	1	#include "nv20.h"
	2	#include "regs.h"
	3
93260d3c	4	#include <core/client.h>
13de7f46	5	#include <core/gpuobj.h>
ebb945a9	6	#include <engine/fifo.h>
9a65a38c	7	#include <engine/fifo/chan.h>
e3c71eb2 BS	8	#include <subdev/fb.h>
e3c71eb2 BS	9	#include <subdev/timer.h>
ebb945a9	10
ebb945a9 BS	11	/*******************************************************************************
	12	* PGRAPH context
	13	******************************************************************************/
6ee73861	14
ebb945a9	15	int
27f3d6cf	16	nv20_gr_chan_init(struct nvkm_object *object)
6ee73861	17	{
27f3d6cf BS	18	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	19	struct nv20_gr *gr = chan->gr;
	20	u32 inst = nvkm_memory_addr(chan->inst);
6ee73861	21
142ea05f	22	nvkm_kmap(gr->ctxtab);
27f3d6cf	23	nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
142ea05f	24	nvkm_done(gr->ctxtab);
ebb945a9	25	return 0;
6ee73861 BS	26	}
6ee73861 BS	27
ebb945a9	28	int
27f3d6cf	29	nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
6ee73861	30	{
27f3d6cf BS	31	struct nv20_gr_chan *chan = nv20_gr_chan(object);
27f3d6cf BS	32	struct nv20_gr *gr = chan->gr;
276836d4	33	struct nvkm_device *device = gr->base.engine.subdev.device;
27f3d6cf	34	u32 inst = nvkm_memory_addr(chan->inst);
ebb945a9 BS	35	int chid = -1;
ebb945a9 BS	36
276836d4 BS	37	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	38	if (nvkm_rd32(device, 0x400144) & 0x00010000)
	39	chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
ebb945a9	40	if (chan->chid == chid) {
27f3d6cf	41	nvkm_wr32(device, 0x400784, inst >> 4);
276836d4	42	nvkm_wr32(device, 0x400788, 0x00000002);
c4584adc BS	43	nvkm_msec(device, 2000,
	44	if (!nvkm_rd32(device, 0x400700))
	45	break;
	46	);
276836d4 BS	47	nvkm_wr32(device, 0x400144, 0x10000000);
276836d4 BS	48	nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
6ee73861	49	}
276836d4	50	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
6ee73861	51
142ea05f BS	52	nvkm_kmap(gr->ctxtab);
	53	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	54	nvkm_done(gr->ctxtab);
27f3d6cf BS	55	return 0;
27f3d6cf BS	56	}
a65955e1	57
27f3d6cf BS	58	void *
	59	nv20_gr_chan_dtor(struct nvkm_object *object)
	60	{
	61	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	62	nvkm_memory_del(&chan->inst);
	63	return chan;
6ee73861 BS	64	}
6ee73861 BS	65
27f3d6cf BS	66	static const struct nvkm_object_func
	67	nv20_gr_chan = {
	68	.dtor = nv20_gr_chan_dtor,
	69	.init = nv20_gr_chan_init,
	70	.fini = nv20_gr_chan_fini,
ebb945a9	71	};
6ee73861	72
27f3d6cf BS	73	static int
	74	nv20_gr_chan_new(struct nvkm_gr base, struct nvkm_fifo_chan fifoch,
	75	const struct nvkm_oclass oclass, struct nvkm_object *pobject)
	76	{
	77	struct nv20_gr *gr = nv20_gr(base);
	78	struct nv20_gr_chan *chan;
	79	int ret, i;
	80
	81	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
	82	return -ENOMEM;
	83	nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
	84	chan->gr = gr;
	85	chan->chid = fifoch->chid;
	86	*pobject = &chan->object;
	87
	88	ret = nvkm_memory_new(gr->base.engine.subdev.device,
	89	NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
	90	&chan->inst);
	91	if (ret)
	92	return ret;
	93
	94	nvkm_kmap(chan->inst);
	95	nvkm_wo32(chan->inst, 0x0000, 0x00000001 \| (chan->chid << 24));
	96	nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
	97	nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
	98	nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
	99	nvkm_wo32(chan->inst, 0x047c, 0x00000101);
	100	nvkm_wo32(chan->inst, 0x0490, 0x00000111);
	101	nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
	102	for (i = 0x04d4; i <= 0x04e0; i += 4)
	103	nvkm_wo32(chan->inst, i, 0x00030303);
	104	for (i = 0x04f4; i <= 0x0500; i += 4)
	105	nvkm_wo32(chan->inst, i, 0x00080000);
	106	for (i = 0x050c; i <= 0x0518; i += 4)
	107	nvkm_wo32(chan->inst, i, 0x01012000);
	108	for (i = 0x051c; i <= 0x0528; i += 4)
	109	nvkm_wo32(chan->inst, i, 0x000105b8);
	110	for (i = 0x052c; i <= 0x0538; i += 4)
	111	nvkm_wo32(chan->inst, i, 0x00080008);
	112	for (i = 0x055c; i <= 0x0598; i += 4)
	113	nvkm_wo32(chan->inst, i, 0x07ff0000);
	114	nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
	115	nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
	116	nvkm_wo32(chan->inst, 0x0604, 0x00004000);
	117	nvkm_wo32(chan->inst, 0x0610, 0x00000001);
	118	nvkm_wo32(chan->inst, 0x0618, 0x00040000);
	119	nvkm_wo32(chan->inst, 0x061c, 0x00010000);
	120	for (i = 0x1c1c; i <= 0x248c; i += 16) {
	121	nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
	122	nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
	123	nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
	124	}
	125	nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
	126	nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
	127	nvkm_wo32(chan->inst, 0x285c, 0x40000000);
	128	nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
	129	nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
	130	nvkm_wo32(chan->inst, 0x286c, 0x40000000);
	131	nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
	132	nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
	133	nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
	134	nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
	135	nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
	136	nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
137	for (i = 0x355c; i <= 0x3578; i += 4)
138	nvkm_wo32(chan->inst, i, 0x001c527c);
139	nvkm_done(chan->inst);
140	return 0;
141	}
142
ebb945a9 BS	143	/*******************************************************************************
	144	* PGRAPH engine/subdev functions
	145	******************************************************************************/
6ee73861 BS	146
6ee73861 BS	147	void
c85ee6ca	148	nv20_gr_tile(struct nvkm_gr base, int i, struct nvkm_fb_tile tile)
6ee73861	149	{
c85ee6ca	150	struct nv20_gr *gr = nv20_gr(base);
276836d4 BS	151	struct nvkm_device *device = gr->base.engine.subdev.device;
276836d4 BS	152	struct nvkm_fifo *fifo = device->fifo;
3945e475	153	unsigned long flags;
6ee73861	154
13de7f46	155	nvkm_fifo_pause(fifo, &flags);
27f3d6cf	156	nv04_gr_idle(&gr->base);
3945e475	157
276836d4 BS	158	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
	159	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
	160	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
3945e475	161
276836d4 BS	162	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	163	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
	164	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	165	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
	166	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	167	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
3945e475	168
c85ee6ca	169	if (device->chipset != 0x34) {
276836d4 BS	170	nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
	171	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
	172	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
ebb945a9	173	}
6ee73861	174
13de7f46	175	nvkm_fifo_start(fifo, &flags);
6ee73861 BS	176	}
6ee73861 BS	177
ebb945a9	178	void
c85ee6ca	179	nv20_gr_intr(struct nvkm_gr *base)
0d87c100	180	{
c85ee6ca BS	181	struct nv20_gr *gr = nv20_gr(base);
	182	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
	183	struct nvkm_device *device = subdev->device;
a65955e1	184	struct nvkm_fifo_chan *chan;
276836d4 BS	185	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
	186	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
	187	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
	188	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
ebb945a9 BS	189	u32 chid = (addr & 0x01f00000) >> 20;
	190	u32 subc = (addr & 0x00070000) >> 16;
	191	u32 mthd = (addr & 0x00001ffc);
276836d4 BS	192	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
276836d4 BS	193	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
ebb945a9	194	u32 show = stat;
109c2f2f	195	char msg[128], src[128], sta[128];
a65955e1	196	unsigned long flags;
ebb945a9	197
a65955e1	198	chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);
87a326a3	199
276836d4 BS	200	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
276836d4 BS	201	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
ebb945a9 BS	202
ebb945a9 BS	203	if (show) {
109c2f2f BS	204	nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
	205	nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
	206	nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
	207	nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
	208	"nstatus %08x [%s] ch %d [%s] subc %d "
	209	"class %04x mthd %04x data %08x\n",
	210	show, msg, nsource, src, nstatus, sta, chid,
8f0649b5 BS	211	chan ? chan->object.client->name : "unknown",
8f0649b5 BS	212	subc, class, mthd, data);
6ee73861	213	}
72a14827	214
a65955e1	215	nvkm_fifo_chan_put(device->fifo, flags, &chan);
ebb945a9	216	}
6ee73861	217
c85ee6ca BS	218	int
c85ee6ca BS	219	nv20_gr_oneinit(struct nvkm_gr *base)
6ee73861	220	{
c85ee6ca BS	221	struct nv20_gr *gr = nv20_gr(base);
	222	return nvkm_memory_new(gr->base.engine.subdev.device,
	223	NVKM_MEM_TARGET_INST, 32 * 4, 16,
	224	true, &gr->ctxtab);
ebb945a9	225	}
6ee73861	226
ebb945a9	227	int
c85ee6ca	228	nv20_gr_init(struct nvkm_gr *base)
ebb945a9	229	{
c85ee6ca	230	struct nv20_gr *gr = nv20_gr(base);
276836d4	231	struct nvkm_device *device = gr->base.engine.subdev.device;
ebb945a9	232	u32 tmp, vramsz;
c85ee6ca	233	int i;
6ee73861	234
227c95d9 BS	235	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
227c95d9 BS	236	nvkm_memory_addr(gr->ctxtab) >> 4);
6ee73861	237
c85ee6ca	238	if (device->chipset == 0x20) {
276836d4	239	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
ebb945a9	240	for (i = 0; i < 15; i++)
276836d4	241	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
c4584adc BS	242	nvkm_msec(device, 2000,
	243	if (!nvkm_rd32(device, 0x400700))
	244	break;
	245	);
ebb945a9	246	} else {
276836d4	247	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
ebb945a9	248	for (i = 0; i < 32; i++)
276836d4	249	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
c4584adc BS	250	nvkm_msec(device, 2000,
	251	if (!nvkm_rd32(device, 0x400700))
	252	break;
	253	);
6ee73861 BS	254	}
6ee73861 BS	255
276836d4 BS	256	nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
276836d4 BS	257	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	258
276836d4 BS	259	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	260	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
	261	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
	262	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	263	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
	264	nvkm_wr32(device, 0x40009C , 0x00000040);
274fec93	265
c85ee6ca	266	if (device->chipset >= 0x25) {
276836d4 BS	267	nvkm_wr32(device, 0x400890, 0x00a8cfff);
	268	nvkm_wr32(device, 0x400610, 0x304B1FB6);
	269	nvkm_wr32(device, 0x400B80, 0x1cbd3883);
	270	nvkm_wr32(device, 0x400B84, 0x44000000);
	271	nvkm_wr32(device, 0x400098, 0x40000080);
	272	nvkm_wr32(device, 0x400B88, 0x000000ff);
274fec93	273
ebb945a9	274	} else {
276836d4 BS	275	nvkm_wr32(device, 0x400880, 0x0008c7df);
	276	nvkm_wr32(device, 0x400094, 0x00000005);
	277	nvkm_wr32(device, 0x400B80, 0x45eae20e);
	278	nvkm_wr32(device, 0x400B84, 0x24000000);
	279	nvkm_wr32(device, 0x400098, 0x00000040);
	280	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
	281	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
	282	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
	283	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
274fec93	284	}
a0b1de84	285
276836d4 BS	286	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
	287	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	288	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
a0b1de84	289
276836d4 BS	290	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
276836d4 BS	291	nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
a0b1de84	292
276836d4 BS	293	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	294	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
	295	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) \| 0x00020100;
	296	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
a0b1de84	297
ebb945a9	298	/* begin RAM config */
c85ee6ca	299	vramsz = nv_device_resource_len(device, 1) - 1;
276836d4 BS	300	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
	301	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
	302	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	303	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
	304	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	305	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
	306	nvkm_wr32(device, 0x400820, 0);
	307	nvkm_wr32(device, 0x400824, 0);
	308	nvkm_wr32(device, 0x400864, vramsz - 1);
	309	nvkm_wr32(device, 0x400868, vramsz - 1);
a0b1de84	310
ebb945a9	311	/* interesting.. the below overwrites some of the tile setup above.. */
276836d4 BS	312	nvkm_wr32(device, 0x400B20, 0x00000000);
276836d4 BS	313	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
a0b1de84	314
276836d4 BS	315	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	316	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	317	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	318	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
a0b1de84 BS	319	return 0;
a0b1de84 BS	320	}
ebb945a9	321
c85ee6ca BS	322	void *
	323	nv20_gr_dtor(struct nvkm_gr *base)
	324	{
	325	struct nv20_gr *gr = nv20_gr(base);
	326	nvkm_memory_del(&gr->ctxtab);
	327	return gr;
	328	}
	329
	330	int
	331	nv20_gr_new_(const struct nvkm_gr_func func, struct nvkm_device device,
	332	int index, struct nvkm_gr **pgr)
	333	{
	334	struct nv20_gr *gr;
	335
	336	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
	337	return -ENOMEM;
	338	*pgr = &gr->base;
	339
	340	return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base);
	341	}
	342
	343	static const struct nvkm_gr_func
	344	nv20_gr = {
	345	.dtor = nv20_gr_dtor,
	346	.oneinit = nv20_gr_oneinit,
	347	.init = nv20_gr_init,
	348	.intr = nv20_gr_intr,
	349	.tile = nv20_gr_tile,
	350	.chan_new = nv20_gr_chan_new,
	351	.sclass = {
	352	{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
	353	{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
	354	{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
	355	{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
	356	{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
	357	{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
	358	{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
	359	{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
	360	{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
	361	{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
	362	{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
	363	{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
	364	{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
	365	{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
	366	{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
	367	{}
	368	}
ebb945a9	369	};
c85ee6ca BS	370
	371	int
	372	nv20_gr_new(struct nvkm_device device, int index, struct nvkm_gr *pgr)
	373	{
	374	return nv20_gr_new_(&nv20_gr, device, index, pgr);
	375	}