[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / nv20.c

#include "nv20.h"
#include "regs.h"

#include <core/client.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
#include <subdev/timer.h>

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

int
nv20_gr_chan_init(struct nvkm_object *object)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	struct nv20_gr *gr = chan->gr;
	u32 inst = nvkm_memory_addr(chan->inst);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
	nvkm_done(gr->ctxtab);
	return 0;
}

int
nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	struct nv20_gr *gr = chan->gr;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	u32 inst = nvkm_memory_addr(chan->inst);
	int chid = -1;

	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	if (nvkm_rd32(device, 0x400144) & 0x00010000)
		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nvkm_wr32(device, 0x400784, inst >> 4);
		nvkm_wr32(device, 0x400788, 0x00000002);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
		nvkm_wr32(device, 0x400144, 0x10000000);
		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
	}
	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	nvkm_done(gr->ctxtab);
	return 0;
}

void *
nv20_gr_chan_dtor(struct nvkm_object *object)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	nvkm_memory_del(&chan->inst);
	return chan;
}

static const struct nvkm_object_func
nv20_gr_chan = {
	.dtor = nv20_gr_chan_dtor,
	.init = nv20_gr_chan_init,
	.fini = nv20_gr_chan_fini,
};

static int
nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
		 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
	struct nv20_gr *gr = nv20_gr(base);
	struct nv20_gr_chan *chan;
	int ret, i;

	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
		return -ENOMEM;
	nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
	chan->gr = gr;
	chan->chid = fifoch->chid;
	*pobject = &chan->object;

	ret = nvkm_memory_new(gr->base.engine.subdev.device,
			      NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
			      &chan->inst);
	if (ret)
		return ret;

	nvkm_kmap(chan->inst);
	nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
	nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
	nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
	nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
	nvkm_wo32(chan->inst, 0x047c, 0x00000101);
	nvkm_wo32(chan->inst, 0x0490, 0x00000111);
	nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
	for (i = 0x04d4; i <= 0x04e0; i += 4)
		nvkm_wo32(chan->inst, i, 0x00030303);
	for (i = 0x04f4; i <= 0x0500; i += 4)
		nvkm_wo32(chan->inst, i, 0x00080000);
	for (i = 0x050c; i <= 0x0518; i += 4)
		nvkm_wo32(chan->inst, i, 0x01012000);
	for (i = 0x051c; i <= 0x0528; i += 4)
		nvkm_wo32(chan->inst, i, 0x000105b8);
	for (i = 0x052c; i <= 0x0538; i += 4)
		nvkm_wo32(chan->inst, i, 0x00080008);
	for (i = 0x055c; i <= 0x0598; i += 4)
		nvkm_wo32(chan->inst, i, 0x07ff0000);
	nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
	nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
	nvkm_wo32(chan->inst, 0x0604, 0x00004000);
	nvkm_wo32(chan->inst, 0x0610, 0x00000001);
	nvkm_wo32(chan->inst, 0x0618, 0x00040000);
	nvkm_wo32(chan->inst, 0x061c, 0x00010000);
	for (i = 0x1c1c; i <= 0x248c; i += 16) {
		nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
		nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
		nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
	}
	nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
	nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
	nvkm_wo32(chan->inst, 0x285c, 0x40000000);
	nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
	nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
	nvkm_wo32(chan->inst, 0x286c, 0x40000000);
	nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
	nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
	nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
	nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
	nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
	nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
	for (i = 0x355c; i <= 0x3578; i += 4)
		nvkm_wo32(chan->inst, i, 0x001c527c);
	nvkm_done(chan->inst);
	return 0;
}

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

void
nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
{
	struct nv20_gr *gr = (void *)engine;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fifo *fifo = device->fifo;
	struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
	unsigned long flags;

	fifo->pause(fifo, &flags);
	nv04_gr_idle(&gr->base);

	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);

	if (nv_device(engine)->chipset != 0x34) {
		nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	}

	fifo->start(fifo, &flags);
}

void
nv20_gr_intr(struct nvkm_subdev *subdev)
{
	struct nv20_gr *gr = (void *)subdev;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fifo_chan *chan;
	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
	u32 chid = (addr & 0x01f00000) >> 20;
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
	u32 show = stat;
	char msg[128], src[128], sta[128];
	unsigned long flags;

	chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);

	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
		nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
		nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
		nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
				   "nstatus %08x [%s] ch %d [%s] subc %d "
				   "class %04x mthd %04x data %08x\n",
			   show, msg, nsource, src, nstatus, sta, chid,
			   chan ? chan->object.client->name : "unknown",
			   subc, class, mthd, data);
	}

	nvkm_fifo_chan_put(device->fifo, flags, &chan);
}

static const struct nvkm_gr_func
nv20_gr = {
	.chan_new = nv20_gr_chan_new,
	.sclass = {
		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
		{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
		{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
		{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
		{}
	}
};

static int
nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	     struct nvkm_oclass *oclass, void *data, u32 size,
	     struct nvkm_object **pobject)
{
	struct nvkm_device *device = (void *)parent;
	struct nv20_gr *gr;
	int ret;

	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
	*pobject = nv_object(gr);
	if (ret)
		return ret;

	gr->base.func = &nv20_gr;

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true,
			      &gr->ctxtab);
	if (ret)
		return ret;

	nv_subdev(gr)->unit = 0x00001000;
	nv_subdev(gr)->intr = nv20_gr_intr;
	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
	return 0;
}

void
nv20_gr_dtor(struct nvkm_object *object)
{
	struct nv20_gr *gr = (void *)object;
	nvkm_memory_del(&gr->ctxtab);
	nvkm_gr_destroy(&gr->base);
}

int
nv20_gr_init(struct nvkm_object *object)
{
	struct nvkm_engine *engine = nv_engine(object);
	struct nv20_gr *gr = (void *)engine;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fb *fb = device->fb;
	u32 tmp, vramsz;
	int ret, i;

	ret = nvkm_gr_init(&gr->base);
	if (ret)
		return ret;

	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
			  nvkm_memory_addr(gr->ctxtab) >> 4);

	if (nv_device(gr)->chipset == 0x20) {
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
		for (i = 0; i < 15; i++)
			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
	} else {
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
		for (i = 0; i < 32; i++)
			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
	}

	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
	nvkm_wr32(device, 0x40009C           , 0x00000040);

	if (nv_device(gr)->chipset >= 0x25) {
		nvkm_wr32(device, 0x400890, 0x00a8cfff);
		nvkm_wr32(device, 0x400610, 0x304B1FB6);
		nvkm_wr32(device, 0x400B80, 0x1cbd3883);
		nvkm_wr32(device, 0x400B84, 0x44000000);
		nvkm_wr32(device, 0x400098, 0x40000080);
		nvkm_wr32(device, 0x400B88, 0x000000ff);

	} else {
		nvkm_wr32(device, 0x400880, 0x0008c7df);
		nvkm_wr32(device, 0x400094, 0x00000005);
		nvkm_wr32(device, 0x400B80, 0x45eae20e);
		nvkm_wr32(device, 0x400B84, 0x24000000);
		nvkm_wr32(device, 0x400098, 0x00000040);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < fb->tile.regions; i++)
		engine->tile_prog(engine, i);

	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));

	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);

	/* begin RAM config */
	vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
	nvkm_wr32(device, 0x400820, 0);
	nvkm_wr32(device, 0x400824, 0);
	nvkm_wr32(device, 0x400864, vramsz - 1);
	nvkm_wr32(device, 0x400868, vramsz - 1);

	/* interesting.. the below overwrites some of the tile setup above.. */
	nvkm_wr32(device, 0x400B20, 0x00000000);
	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);

	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
	return 0;
}

struct nvkm_oclass
nv20_gr_oclass = {
	.handle = NV_ENGINE(GR, 0x20),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv20_gr_ctor,
		.dtor = nv20_gr_dtor,
		.init = nv20_gr_init,
		.fini = _nvkm_gr_fini,
	},
};
Commit	Line	Data
e3c71eb2 BS	1	#include "nv20.h"
	2	#include "regs.h"
	3
93260d3c	4	#include <core/client.h>
ebb945a9	5	#include <engine/fifo.h>
9a65a38c	6	#include <engine/fifo/chan.h>
e3c71eb2 BS	7	#include <subdev/fb.h>
e3c71eb2 BS	8	#include <subdev/timer.h>
ebb945a9	9
ebb945a9 BS	10	/*******************************************************************************
	11	* PGRAPH context
	12	******************************************************************************/
6ee73861	13
ebb945a9	14	int
27f3d6cf	15	nv20_gr_chan_init(struct nvkm_object *object)
6ee73861	16	{
27f3d6cf BS	17	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	18	struct nv20_gr *gr = chan->gr;
	19	u32 inst = nvkm_memory_addr(chan->inst);
6ee73861	20
142ea05f	21	nvkm_kmap(gr->ctxtab);
27f3d6cf	22	nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
142ea05f	23	nvkm_done(gr->ctxtab);
ebb945a9	24	return 0;
6ee73861 BS	25	}
6ee73861 BS	26
ebb945a9	27	int
27f3d6cf	28	nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
6ee73861	29	{
27f3d6cf BS	30	struct nv20_gr_chan *chan = nv20_gr_chan(object);
27f3d6cf BS	31	struct nv20_gr *gr = chan->gr;
276836d4	32	struct nvkm_device *device = gr->base.engine.subdev.device;
27f3d6cf	33	u32 inst = nvkm_memory_addr(chan->inst);
ebb945a9 BS	34	int chid = -1;
ebb945a9 BS	35
276836d4 BS	36	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	37	if (nvkm_rd32(device, 0x400144) & 0x00010000)
	38	chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
ebb945a9	39	if (chan->chid == chid) {
27f3d6cf	40	nvkm_wr32(device, 0x400784, inst >> 4);
276836d4	41	nvkm_wr32(device, 0x400788, 0x00000002);
c4584adc BS	42	nvkm_msec(device, 2000,
	43	if (!nvkm_rd32(device, 0x400700))
	44	break;
	45	);
276836d4 BS	46	nvkm_wr32(device, 0x400144, 0x10000000);
276836d4 BS	47	nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
6ee73861	48	}
276836d4	49	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
6ee73861	50
142ea05f BS	51	nvkm_kmap(gr->ctxtab);
	52	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	53	nvkm_done(gr->ctxtab);
27f3d6cf BS	54	return 0;
27f3d6cf BS	55	}
a65955e1	56
27f3d6cf BS	57	void *
	58	nv20_gr_chan_dtor(struct nvkm_object *object)
	59	{
	60	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	61	nvkm_memory_del(&chan->inst);
	62	return chan;
6ee73861 BS	63	}
6ee73861 BS	64
27f3d6cf BS	65	static const struct nvkm_object_func
	66	nv20_gr_chan = {
	67	.dtor = nv20_gr_chan_dtor,
	68	.init = nv20_gr_chan_init,
	69	.fini = nv20_gr_chan_fini,
ebb945a9	70	};
6ee73861	71
27f3d6cf BS	72	static int
	73	nv20_gr_chan_new(struct nvkm_gr base, struct nvkm_fifo_chan fifoch,
	74	const struct nvkm_oclass oclass, struct nvkm_object *pobject)
	75	{
	76	struct nv20_gr *gr = nv20_gr(base);
	77	struct nv20_gr_chan *chan;
	78	int ret, i;
	79
	80	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
	81	return -ENOMEM;
	82	nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
	83	chan->gr = gr;
	84	chan->chid = fifoch->chid;
	85	*pobject = &chan->object;
	86
	87	ret = nvkm_memory_new(gr->base.engine.subdev.device,
	88	NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
	89	&chan->inst);
	90	if (ret)
	91	return ret;
	92
	93	nvkm_kmap(chan->inst);
	94	nvkm_wo32(chan->inst, 0x0000, 0x00000001 \| (chan->chid << 24));
	95	nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
	96	nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
	97	nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
	98	nvkm_wo32(chan->inst, 0x047c, 0x00000101);
	99	nvkm_wo32(chan->inst, 0x0490, 0x00000111);
	100	nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
	101	for (i = 0x04d4; i <= 0x04e0; i += 4)
	102	nvkm_wo32(chan->inst, i, 0x00030303);
	103	for (i = 0x04f4; i <= 0x0500; i += 4)
	104	nvkm_wo32(chan->inst, i, 0x00080000);
	105	for (i = 0x050c; i <= 0x0518; i += 4)
	106	nvkm_wo32(chan->inst, i, 0x01012000);
	107	for (i = 0x051c; i <= 0x0528; i += 4)
	108	nvkm_wo32(chan->inst, i, 0x000105b8);
	109	for (i = 0x052c; i <= 0x0538; i += 4)
	110	nvkm_wo32(chan->inst, i, 0x00080008);
	111	for (i = 0x055c; i <= 0x0598; i += 4)
	112	nvkm_wo32(chan->inst, i, 0x07ff0000);
	113	nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
	114	nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
	115	nvkm_wo32(chan->inst, 0x0604, 0x00004000);
	116	nvkm_wo32(chan->inst, 0x0610, 0x00000001);
	117	nvkm_wo32(chan->inst, 0x0618, 0x00040000);
	118	nvkm_wo32(chan->inst, 0x061c, 0x00010000);
	119	for (i = 0x1c1c; i <= 0x248c; i += 16) {
	120	nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
	121	nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
	122	nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
	123	}
	124	nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
	125	nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
	126	nvkm_wo32(chan->inst, 0x285c, 0x40000000);
	127	nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
	128	nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
	129	nvkm_wo32(chan->inst, 0x286c, 0x40000000);
	130	nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
	131	nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
	132	nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
	133	nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
	134	nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
	135	nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
136	for (i = 0x355c; i <= 0x3578; i += 4)
137	nvkm_wo32(chan->inst, i, 0x001c527c);
138	nvkm_done(chan->inst);
139	return 0;
140	}
141
ebb945a9 BS	142	/*******************************************************************************
	143	* PGRAPH engine/subdev functions
	144	******************************************************************************/
6ee73861 BS	145
6ee73861 BS	146	void
e3c71eb2	147	nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
6ee73861	148	{
bfee3f3d	149	struct nv20_gr gr = (void )engine;
276836d4 BS	150	struct nvkm_device *device = gr->base.engine.subdev.device;
	151	struct nvkm_fifo *fifo = device->fifo;
	152	struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
3945e475	153	unsigned long flags;
6ee73861	154
6189f1b0	155	fifo->pause(fifo, &flags);
27f3d6cf	156	nv04_gr_idle(&gr->base);
3945e475	157
276836d4 BS	158	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
	159	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
	160	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
3945e475	161
276836d4 BS	162	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	163	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
	164	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	165	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
	166	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	167	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
3945e475	168
fafa0cb3	169	if (nv_device(engine)->chipset != 0x34) {
276836d4 BS	170	nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
	171	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
	172	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
ebb945a9	173	}
6ee73861	174
6189f1b0	175	fifo->start(fifo, &flags);
6ee73861 BS	176	}
6ee73861 BS	177
ebb945a9	178	void
e3c71eb2	179	nv20_gr_intr(struct nvkm_subdev *subdev)
0d87c100	180	{
bfee3f3d	181	struct nv20_gr gr = (void )subdev;
276836d4	182	struct nvkm_device *device = gr->base.engine.subdev.device;
a65955e1	183	struct nvkm_fifo_chan *chan;
276836d4 BS	184	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
	185	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
	186	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
	187	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
ebb945a9 BS	188	u32 chid = (addr & 0x01f00000) >> 20;
	189	u32 subc = (addr & 0x00070000) >> 16;
	190	u32 mthd = (addr & 0x00001ffc);
276836d4 BS	191	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
276836d4 BS	192	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
ebb945a9	193	u32 show = stat;
109c2f2f	194	char msg[128], src[128], sta[128];
a65955e1	195	unsigned long flags;
ebb945a9	196
a65955e1	197	chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);
87a326a3	198
276836d4 BS	199	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
276836d4 BS	200	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
ebb945a9 BS	201
ebb945a9 BS	202	if (show) {
109c2f2f BS	203	nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
	204	nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
	205	nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
	206	nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
	207	"nstatus %08x [%s] ch %d [%s] subc %d "
	208	"class %04x mthd %04x data %08x\n",
	209	show, msg, nsource, src, nstatus, sta, chid,
8f0649b5 BS	210	chan ? chan->object.client->name : "unknown",
8f0649b5 BS	211	subc, class, mthd, data);
6ee73861	212	}
72a14827	213
a65955e1	214	nvkm_fifo_chan_put(device->fifo, flags, &chan);
ebb945a9	215	}
6ee73861	216
27f3d6cf BS	217	static const struct nvkm_gr_func
	218	nv20_gr = {
	219	.chan_new = nv20_gr_chan_new,
	220	.sclass = {
	221	{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
	222	{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
	223	{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
	224	{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
	225	{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
	226	{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
	227	{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
	228	{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
	229	{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
	230	{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
	231	{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
	232	{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
	233	{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
	234	{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
	235	{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
	236	{}
	237	}
	238	};
	239
ebb945a9	240	static int
e3c71eb2 BS	241	nv20_gr_ctor(struct nvkm_object parent, struct nvkm_object engine,
	242	struct nvkm_oclass oclass, void data, u32 size,
	243	struct nvkm_object **pobject)
ebb945a9	244	{
227c95d9	245	struct nvkm_device device = (void )parent;
bfee3f3d	246	struct nv20_gr *gr;
ebb945a9	247	int ret;
6ee73861	248
bfee3f3d BS	249	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
bfee3f3d BS	250	*pobject = nv_object(gr);
ebb945a9 BS	251	if (ret)
ebb945a9 BS	252	return ret;
6ee73861	253
27f3d6cf BS	254	gr->base.func = &nv20_gr;
27f3d6cf BS	255
227c95d9 BS	256	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true,
227c95d9 BS	257	&gr->ctxtab);
ebb945a9 BS	258	if (ret)
ebb945a9 BS	259	return ret;
6ee73861	260
bfee3f3d BS	261	nv_subdev(gr)->unit = 0x00001000;
bfee3f3d BS	262	nv_subdev(gr)->intr = nv20_gr_intr;
bfee3f3d	263	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
6ee73861 BS	264	return 0;
	265	}
	266
ebb945a9	267	void
e3c71eb2	268	nv20_gr_dtor(struct nvkm_object *object)
6ee73861	269	{
bfee3f3d	270	struct nv20_gr gr = (void )object;
227c95d9	271	nvkm_memory_del(&gr->ctxtab);
bfee3f3d	272	nvkm_gr_destroy(&gr->base);
ebb945a9	273	}
6ee73861	274
ebb945a9	275	int
e3c71eb2	276	nv20_gr_init(struct nvkm_object *object)
ebb945a9	277	{
e3c71eb2	278	struct nvkm_engine *engine = nv_engine(object);
bfee3f3d	279	struct nv20_gr gr = (void )engine;
276836d4 BS	280	struct nvkm_device *device = gr->base.engine.subdev.device;
276836d4 BS	281	struct nvkm_fb *fb = device->fb;
ebb945a9 BS	282	u32 tmp, vramsz;
ebb945a9 BS	283	int ret, i;
6ee73861	284
bfee3f3d	285	ret = nvkm_gr_init(&gr->base);
ebb945a9 BS	286	if (ret)
ebb945a9 BS	287	return ret;
6ee73861	288
227c95d9 BS	289	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
227c95d9 BS	290	nvkm_memory_addr(gr->ctxtab) >> 4);
6ee73861	291
bfee3f3d	292	if (nv_device(gr)->chipset == 0x20) {
276836d4	293	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
ebb945a9	294	for (i = 0; i < 15; i++)
276836d4	295	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
c4584adc BS	296	nvkm_msec(device, 2000,
	297	if (!nvkm_rd32(device, 0x400700))
	298	break;
	299	);
ebb945a9	300	} else {
276836d4	301	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
ebb945a9	302	for (i = 0; i < 32; i++)
276836d4	303	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
c4584adc BS	304	nvkm_msec(device, 2000,
	305	if (!nvkm_rd32(device, 0x400700))
	306	break;
	307	);
6ee73861 BS	308	}
6ee73861 BS	309
276836d4 BS	310	nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
276836d4 BS	311	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	312
276836d4 BS	313	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	314	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
	315	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
	316	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	317	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
	318	nvkm_wr32(device, 0x40009C , 0x00000040);
274fec93	319
bfee3f3d	320	if (nv_device(gr)->chipset >= 0x25) {
276836d4 BS	321	nvkm_wr32(device, 0x400890, 0x00a8cfff);
	322	nvkm_wr32(device, 0x400610, 0x304B1FB6);
	323	nvkm_wr32(device, 0x400B80, 0x1cbd3883);
	324	nvkm_wr32(device, 0x400B84, 0x44000000);
	325	nvkm_wr32(device, 0x400098, 0x40000080);
	326	nvkm_wr32(device, 0x400B88, 0x000000ff);
274fec93	327
ebb945a9	328	} else {
276836d4 BS	329	nvkm_wr32(device, 0x400880, 0x0008c7df);
	330	nvkm_wr32(device, 0x400094, 0x00000005);
	331	nvkm_wr32(device, 0x400B80, 0x45eae20e);
	332	nvkm_wr32(device, 0x400B84, 0x24000000);
	333	nvkm_wr32(device, 0x400098, 0x00000040);
	334	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
	335	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
	336	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
	337	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
274fec93	338	}
a0b1de84	339
ebb945a9	340	/* Turn all the tiling regions off. */
b1e4553c	341	for (i = 0; i < fb->tile.regions; i++)
ebb945a9	342	engine->tile_prog(engine, i);
a0b1de84	343
276836d4 BS	344	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
	345	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	346	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
a0b1de84	347
276836d4 BS	348	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
276836d4 BS	349	nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
a0b1de84	350
276836d4 BS	351	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	352	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
	353	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) \| 0x00020100;
	354	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
a0b1de84	355
ebb945a9	356	/* begin RAM config */
bfee3f3d	357	vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
276836d4 BS	358	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
	359	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
	360	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	361	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
	362	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	363	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
	364	nvkm_wr32(device, 0x400820, 0);
	365	nvkm_wr32(device, 0x400824, 0);
	366	nvkm_wr32(device, 0x400864, vramsz - 1);
	367	nvkm_wr32(device, 0x400868, vramsz - 1);
a0b1de84	368
ebb945a9	369	/* interesting.. the below overwrites some of the tile setup above.. */
276836d4 BS	370	nvkm_wr32(device, 0x400B20, 0x00000000);
276836d4 BS	371	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
a0b1de84	372
276836d4 BS	373	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	374	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	375	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	376	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
a0b1de84 BS	377	return 0;
a0b1de84 BS	378	}
ebb945a9	379
e3c71eb2	380	struct nvkm_oclass
b8bf04e1	381	nv20_gr_oclass = {
ebb945a9	382	.handle = NV_ENGINE(GR, 0x20),
e3c71eb2	383	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1 BS	384	.ctor = nv20_gr_ctor,
	385	.dtor = nv20_gr_dtor,
	386	.init = nv20_gr_init,
e3c71eb2	387	.fini = _nvkm_gr_fini,
ebb945a9 BS	388	},
ebb945a9 BS	389	};