[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / nv20.c

#include "nv20.h"
#include "regs.h"

#include <core/client.h>
#include <core/handle.h>
#include <engine/fifo.h>
#include <subdev/fb.h>
#include <subdev/timer.h>

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

static struct nvkm_oclass
nv20_gr_sclass[] = {
	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
	{ 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
		     struct nvkm_oclass *oclass, void *data, u32 size,
		     struct nvkm_object **pobject)
{
	struct nv20_gr_chan *chan;
	struct nvkm_gpuobj *image;
	int ret, i;

	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
				     16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->chid = nvkm_fifo_chan(parent)->chid;
	image = &chan->base.base.gpuobj;

	nvkm_kmap(image);
	nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24));
	nvkm_wo32(image, 0x033c, 0xffff0000);
	nvkm_wo32(image, 0x03a0, 0x0fff0000);
	nvkm_wo32(image, 0x03a4, 0x0fff0000);
	nvkm_wo32(image, 0x047c, 0x00000101);
	nvkm_wo32(image, 0x0490, 0x00000111);
	nvkm_wo32(image, 0x04a8, 0x44400000);
	for (i = 0x04d4; i <= 0x04e0; i += 4)
		nvkm_wo32(image, i, 0x00030303);
	for (i = 0x04f4; i <= 0x0500; i += 4)
		nvkm_wo32(image, i, 0x00080000);
	for (i = 0x050c; i <= 0x0518; i += 4)
		nvkm_wo32(image, i, 0x01012000);
	for (i = 0x051c; i <= 0x0528; i += 4)
		nvkm_wo32(image, i, 0x000105b8);
	for (i = 0x052c; i <= 0x0538; i += 4)
		nvkm_wo32(image, i, 0x00080008);
	for (i = 0x055c; i <= 0x0598; i += 4)
		nvkm_wo32(image, i, 0x07ff0000);
	nvkm_wo32(image, 0x05a4, 0x4b7fffff);
	nvkm_wo32(image, 0x05fc, 0x00000001);
	nvkm_wo32(image, 0x0604, 0x00004000);
	nvkm_wo32(image, 0x0610, 0x00000001);
	nvkm_wo32(image, 0x0618, 0x00040000);
	nvkm_wo32(image, 0x061c, 0x00010000);
	for (i = 0x1c1c; i <= 0x248c; i += 16) {
		nvkm_wo32(image, (i + 0), 0x10700ff9);
		nvkm_wo32(image, (i + 4), 0x0436086c);
		nvkm_wo32(image, (i + 8), 0x000c001b);
	}
	nvkm_wo32(image, 0x281c, 0x3f800000);
	nvkm_wo32(image, 0x2830, 0x3f800000);
	nvkm_wo32(image, 0x285c, 0x40000000);
	nvkm_wo32(image, 0x2860, 0x3f800000);
	nvkm_wo32(image, 0x2864, 0x3f000000);
	nvkm_wo32(image, 0x286c, 0x40000000);
	nvkm_wo32(image, 0x2870, 0x3f800000);
	nvkm_wo32(image, 0x2878, 0xbf800000);
	nvkm_wo32(image, 0x2880, 0xbf800000);
	nvkm_wo32(image, 0x34a4, 0x000fe000);
	nvkm_wo32(image, 0x3530, 0x000003f8);
	nvkm_wo32(image, 0x3540, 0x002fe000);
	for (i = 0x355c; i <= 0x3578; i += 4)
		nvkm_wo32(image, i, 0x001c527c);
	nvkm_done(image);
	return 0;
}

int
nv20_gr_context_init(struct nvkm_object *object)
{
	struct nv20_gr *gr = (void *)object->engine;
	struct nv20_gr_chan *chan = (void *)object;
	int ret;

	ret = nvkm_gr_context_init(&chan->base);
	if (ret)
		return ret;

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
	nvkm_done(gr->ctxtab);
	return 0;
}

int
nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
{
	struct nv20_gr *gr = (void *)object->engine;
	struct nv20_gr_chan *chan = (void *)object;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	int chid = -1;

	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	if (nvkm_rd32(device, 0x400144) & 0x00010000)
		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4);
		nvkm_wr32(device, 0x400788, 0x00000002);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
		nvkm_wr32(device, 0x400144, 0x10000000);
		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
	}
	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	nvkm_done(gr->ctxtab);
	return nvkm_gr_context_fini(&chan->base, suspend);
}

static struct nvkm_oclass
nv20_gr_cclass = {
	.handle = NV_ENGCTX(GR, 0x20),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv20_gr_context_ctor,
		.dtor = _nvkm_gr_context_dtor,
		.init = nv20_gr_context_init,
		.fini = nv20_gr_context_fini,
		.rd32 = _nvkm_gr_context_rd32,
		.wr32 = _nvkm_gr_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

void
nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
{
	struct nv20_gr *gr = (void *)engine;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fifo *fifo = device->fifo;
	struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
	unsigned long flags;

	fifo->pause(fifo, &flags);
	nv04_gr_idle(gr);

	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);

	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);

	if (nv_device(engine)->chipset != 0x34) {
		nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	}

	fifo->start(fifo, &flags);
}

void
nv20_gr_intr(struct nvkm_subdev *subdev)
{
	struct nvkm_engine *engine = nv_engine(subdev);
	struct nvkm_object *engctx;
	struct nvkm_handle *handle;
	struct nv20_gr *gr = (void *)subdev;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
	u32 chid = (addr & 0x01f00000) >> 20;
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
	u32 show = stat;
	char msg[128], src[128], sta[128];

	engctx = nvkm_engctx_get(engine, chid);
	if (stat & NV_PGRAPH_INTR_ERROR) {
		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
			handle = nvkm_handle_get_class(engctx, class);
			if (handle && !nv_call(handle->object, mthd, data))
				show &= ~NV_PGRAPH_INTR_ERROR;
			nvkm_handle_put(handle);
		}
	}

	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
		nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
		nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
		nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
				   "nstatus %08x [%s] ch %d [%s] subc %d "
				   "class %04x mthd %04x data %08x\n",
			   show, msg, nsource, src, nstatus, sta, chid,
			   nvkm_client_name(engctx), subc, class, mthd, data);
	}

	nvkm_engctx_put(engctx);
}

static int
nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	     struct nvkm_oclass *oclass, void *data, u32 size,
	     struct nvkm_object **pobject)
{
	struct nvkm_device *device = (void *)parent;
	struct nv20_gr *gr;
	int ret;

	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
	*pobject = nv_object(gr);
	if (ret)
		return ret;

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true,
			      &gr->ctxtab);
	if (ret)
		return ret;

	nv_subdev(gr)->unit = 0x00001000;
	nv_subdev(gr)->intr = nv20_gr_intr;
	nv_engine(gr)->cclass = &nv20_gr_cclass;
	nv_engine(gr)->sclass = nv20_gr_sclass;
	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
	return 0;
}

void
nv20_gr_dtor(struct nvkm_object *object)
{
	struct nv20_gr *gr = (void *)object;
	nvkm_memory_del(&gr->ctxtab);
	nvkm_gr_destroy(&gr->base);
}

int
nv20_gr_init(struct nvkm_object *object)
{
	struct nvkm_engine *engine = nv_engine(object);
	struct nv20_gr *gr = (void *)engine;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fb *fb = device->fb;
	u32 tmp, vramsz;
	int ret, i;

	ret = nvkm_gr_init(&gr->base);
	if (ret)
		return ret;

	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
			  nvkm_memory_addr(gr->ctxtab) >> 4);

	if (nv_device(gr)->chipset == 0x20) {
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
		for (i = 0; i < 15; i++)
			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
	} else {
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
		for (i = 0; i < 32; i++)
			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
	}

	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
	nvkm_wr32(device, 0x40009C           , 0x00000040);

	if (nv_device(gr)->chipset >= 0x25) {
		nvkm_wr32(device, 0x400890, 0x00a8cfff);
		nvkm_wr32(device, 0x400610, 0x304B1FB6);
		nvkm_wr32(device, 0x400B80, 0x1cbd3883);
		nvkm_wr32(device, 0x400B84, 0x44000000);
		nvkm_wr32(device, 0x400098, 0x40000080);
		nvkm_wr32(device, 0x400B88, 0x000000ff);

	} else {
		nvkm_wr32(device, 0x400880, 0x0008c7df);
		nvkm_wr32(device, 0x400094, 0x00000005);
		nvkm_wr32(device, 0x400B80, 0x45eae20e);
		nvkm_wr32(device, 0x400B84, 0x24000000);
		nvkm_wr32(device, 0x400098, 0x00000040);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < fb->tile.regions; i++)
		engine->tile_prog(engine, i);

	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));

	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);

	/* begin RAM config */
	vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
	nvkm_wr32(device, 0x400820, 0);
	nvkm_wr32(device, 0x400824, 0);
	nvkm_wr32(device, 0x400864, vramsz - 1);
	nvkm_wr32(device, 0x400868, vramsz - 1);

	/* interesting.. the below overwrites some of the tile setup above.. */
	nvkm_wr32(device, 0x400B20, 0x00000000);
	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);

	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
	return 0;
}

struct nvkm_oclass
nv20_gr_oclass = {
	.handle = NV_ENGINE(GR, 0x20),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv20_gr_ctor,
		.dtor = nv20_gr_dtor,
		.init = nv20_gr_init,
		.fini = _nvkm_gr_fini,
	},
};
Commit	Line	Data
e3c71eb2 BS	1	#include "nv20.h"
	2	#include "regs.h"
	3
93260d3c	4	#include <core/client.h>
ebb945a9	5	#include <core/handle.h>
ebb945a9	6	#include <engine/fifo.h>
e3c71eb2 BS	7	#include <subdev/fb.h>
e3c71eb2 BS	8	#include <subdev/timer.h>
ebb945a9 BS	9
	10	/*******************************************************************************
	11	* Graphics object classes
	12	******************************************************************************/
	13
e3c71eb2	14	static struct nvkm_oclass
b8bf04e1 BS	15	nv20_gr_sclass[] = {
	16	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	17	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	18	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	19	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	20	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	21	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	22	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	23	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	24	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	25	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	26	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	27	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
	28	{ 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
	29	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
	30	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
ebb945a9	31	{},
a0b1de84 BS	32	};
a0b1de84 BS	33
ebb945a9 BS	34	/*******************************************************************************
	35	* PGRAPH context
	36	******************************************************************************/
6ee73861	37
ebb945a9	38	static int
e3c71eb2 BS	39	nv20_gr_context_ctor(struct nvkm_object parent, struct nvkm_object engine,
	40	struct nvkm_oclass oclass, void data, u32 size,
	41	struct nvkm_object **pobject)
a0b1de84	42	{
b8bf04e1	43	struct nv20_gr_chan *chan;
142ea05f	44	struct nvkm_gpuobj *image;
ebb945a9	45	int ret, i;
a0b1de84	46
e3c71eb2 BS	47	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
e3c71eb2 BS	48	16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
ebb945a9 BS	49	*pobject = nv_object(chan);
	50	if (ret)
	51	return ret;
a0b1de84	52
e3c71eb2	53	chan->chid = nvkm_fifo_chan(parent)->chid;
142ea05f BS	54	image = &chan->base.base.gpuobj;
	55
	56	nvkm_kmap(image);
	57	nvkm_wo32(image, 0x0000, 0x00000001 \| (chan->chid << 24));
	58	nvkm_wo32(image, 0x033c, 0xffff0000);
	59	nvkm_wo32(image, 0x03a0, 0x0fff0000);
	60	nvkm_wo32(image, 0x03a4, 0x0fff0000);
	61	nvkm_wo32(image, 0x047c, 0x00000101);
	62	nvkm_wo32(image, 0x0490, 0x00000111);
	63	nvkm_wo32(image, 0x04a8, 0x44400000);
6ee73861	64	for (i = 0x04d4; i <= 0x04e0; i += 4)
142ea05f	65	nvkm_wo32(image, i, 0x00030303);
6ee73861	66	for (i = 0x04f4; i <= 0x0500; i += 4)
142ea05f	67	nvkm_wo32(image, i, 0x00080000);
6ee73861	68	for (i = 0x050c; i <= 0x0518; i += 4)
142ea05f	69	nvkm_wo32(image, i, 0x01012000);
6ee73861	70	for (i = 0x051c; i <= 0x0528; i += 4)
142ea05f	71	nvkm_wo32(image, i, 0x000105b8);
6ee73861	72	for (i = 0x052c; i <= 0x0538; i += 4)
142ea05f	73	nvkm_wo32(image, i, 0x00080008);
6ee73861	74	for (i = 0x055c; i <= 0x0598; i += 4)
142ea05f BS	75	nvkm_wo32(image, i, 0x07ff0000);
	76	nvkm_wo32(image, 0x05a4, 0x4b7fffff);
	77	nvkm_wo32(image, 0x05fc, 0x00000001);
	78	nvkm_wo32(image, 0x0604, 0x00004000);
	79	nvkm_wo32(image, 0x0610, 0x00000001);
	80	nvkm_wo32(image, 0x0618, 0x00040000);
	81	nvkm_wo32(image, 0x061c, 0x00010000);
6ee73861	82	for (i = 0x1c1c; i <= 0x248c; i += 16) {
142ea05f BS	83	nvkm_wo32(image, (i + 0), 0x10700ff9);
	84	nvkm_wo32(image, (i + 4), 0x0436086c);
	85	nvkm_wo32(image, (i + 8), 0x000c001b);
6ee73861	86	}
142ea05f BS	87	nvkm_wo32(image, 0x281c, 0x3f800000);
	88	nvkm_wo32(image, 0x2830, 0x3f800000);
	89	nvkm_wo32(image, 0x285c, 0x40000000);
	90	nvkm_wo32(image, 0x2860, 0x3f800000);
	91	nvkm_wo32(image, 0x2864, 0x3f000000);
	92	nvkm_wo32(image, 0x286c, 0x40000000);
	93	nvkm_wo32(image, 0x2870, 0x3f800000);
	94	nvkm_wo32(image, 0x2878, 0xbf800000);
	95	nvkm_wo32(image, 0x2880, 0xbf800000);
	96	nvkm_wo32(image, 0x34a4, 0x000fe000);
	97	nvkm_wo32(image, 0x3530, 0x000003f8);
	98	nvkm_wo32(image, 0x3540, 0x002fe000);
6ee73861	99	for (i = 0x355c; i <= 0x3578; i += 4)
142ea05f BS	100	nvkm_wo32(image, i, 0x001c527c);
142ea05f BS	101	nvkm_done(image);
ebb945a9	102	return 0;
6ee73861 BS	103	}
6ee73861 BS	104
ebb945a9	105	int
e3c71eb2	106	nv20_gr_context_init(struct nvkm_object *object)
6ee73861	107	{
bfee3f3d	108	struct nv20_gr gr = (void )object->engine;
b8bf04e1	109	struct nv20_gr_chan chan = (void )object;
ebb945a9	110	int ret;
6ee73861	111
e3c71eb2	112	ret = nvkm_gr_context_init(&chan->base);
ebb945a9 BS	113	if (ret)
ebb945a9 BS	114	return ret;
6ee73861	115
142ea05f BS	116	nvkm_kmap(gr->ctxtab);
	117	nvkm_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
	118	nvkm_done(gr->ctxtab);
ebb945a9	119	return 0;
6ee73861 BS	120	}
6ee73861 BS	121
ebb945a9	122	int
e3c71eb2	123	nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
6ee73861	124	{
bfee3f3d	125	struct nv20_gr gr = (void )object->engine;
b8bf04e1	126	struct nv20_gr_chan chan = (void )object;
276836d4	127	struct nvkm_device *device = gr->base.engine.subdev.device;
ebb945a9 BS	128	int chid = -1;
ebb945a9 BS	129
276836d4 BS	130	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	131	if (nvkm_rd32(device, 0x400144) & 0x00010000)
	132	chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
ebb945a9	133	if (chan->chid == chid) {
276836d4 BS	134	nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4);
276836d4 BS	135	nvkm_wr32(device, 0x400788, 0x00000002);
c4584adc BS	136	nvkm_msec(device, 2000,
	137	if (!nvkm_rd32(device, 0x400700))
	138	break;
	139	);
276836d4 BS	140	nvkm_wr32(device, 0x400144, 0x10000000);
276836d4 BS	141	nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
6ee73861	142	}
276836d4	143	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
6ee73861	144
142ea05f BS	145	nvkm_kmap(gr->ctxtab);
	146	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	147	nvkm_done(gr->ctxtab);
e3c71eb2	148	return nvkm_gr_context_fini(&chan->base, suspend);
6ee73861 BS	149	}
6ee73861 BS	150
e3c71eb2	151	static struct nvkm_oclass
b8bf04e1	152	nv20_gr_cclass = {
ebb945a9	153	.handle = NV_ENGCTX(GR, 0x20),
e3c71eb2	154	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1	155	.ctor = nv20_gr_context_ctor,
e3c71eb2	156	.dtor = _nvkm_gr_context_dtor,
b8bf04e1 BS	157	.init = nv20_gr_context_init,
b8bf04e1 BS	158	.fini = nv20_gr_context_fini,
e3c71eb2 BS	159	.rd32 = _nvkm_gr_context_rd32,
e3c71eb2 BS	160	.wr32 = _nvkm_gr_context_wr32,
ebb945a9 BS	161	},
ebb945a9 BS	162	};
6ee73861	163
ebb945a9 BS	164	/*******************************************************************************
	165	* PGRAPH engine/subdev functions
	166	******************************************************************************/
6ee73861 BS	167
6ee73861 BS	168	void
e3c71eb2	169	nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
6ee73861	170	{
bfee3f3d	171	struct nv20_gr gr = (void )engine;
276836d4 BS	172	struct nvkm_device *device = gr->base.engine.subdev.device;
	173	struct nvkm_fifo *fifo = device->fifo;
	174	struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
3945e475	175	unsigned long flags;
6ee73861	176
6189f1b0	177	fifo->pause(fifo, &flags);
bfee3f3d	178	nv04_gr_idle(gr);
3945e475	179
276836d4 BS	180	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
	181	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
	182	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
3945e475	183
276836d4 BS	184	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	185	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
	186	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	187	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
	188	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	189	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
3945e475	190
fafa0cb3	191	if (nv_device(engine)->chipset != 0x34) {
276836d4 BS	192	nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
	193	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
	194	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
ebb945a9	195	}
6ee73861	196
6189f1b0	197	fifo->start(fifo, &flags);
6ee73861 BS	198	}
6ee73861 BS	199
ebb945a9	200	void
e3c71eb2	201	nv20_gr_intr(struct nvkm_subdev *subdev)
0d87c100	202	{
e3c71eb2 BS	203	struct nvkm_engine *engine = nv_engine(subdev);
	204	struct nvkm_object *engctx;
	205	struct nvkm_handle *handle;
bfee3f3d	206	struct nv20_gr gr = (void )subdev;
276836d4 BS	207	struct nvkm_device *device = gr->base.engine.subdev.device;
	208	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
	209	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
	210	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
	211	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
ebb945a9 BS	212	u32 chid = (addr & 0x01f00000) >> 20;
	213	u32 subc = (addr & 0x00070000) >> 16;
	214	u32 mthd = (addr & 0x00001ffc);
276836d4 BS	215	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
276836d4 BS	216	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
ebb945a9	217	u32 show = stat;
109c2f2f	218	char msg[128], src[128], sta[128];
ebb945a9	219
e3c71eb2	220	engctx = nvkm_engctx_get(engine, chid);
ebb945a9 BS	221	if (stat & NV_PGRAPH_INTR_ERROR) {
ebb945a9 BS	222	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
e3c71eb2	223	handle = nvkm_handle_get_class(engctx, class);
ebb945a9 BS	224	if (handle && !nv_call(handle->object, mthd, data))
ebb945a9 BS	225	show &= ~NV_PGRAPH_INTR_ERROR;
e3c71eb2	226	nvkm_handle_put(handle);
ebb945a9	227	}
87a326a3	228	}
87a326a3	229
276836d4 BS	230	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
276836d4 BS	231	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
ebb945a9 BS	232
ebb945a9 BS	233	if (show) {
109c2f2f BS	234	nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
	235	nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
	236	nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
	237	nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
	238	"nstatus %08x [%s] ch %d [%s] subc %d "
	239	"class %04x mthd %04x data %08x\n",
	240	show, msg, nsource, src, nstatus, sta, chid,
	241	nvkm_client_name(engctx), subc, class, mthd, data);
6ee73861	242	}
72a14827	243
e3c71eb2	244	nvkm_engctx_put(engctx);
ebb945a9	245	}
6ee73861	246
ebb945a9	247	static int
e3c71eb2 BS	248	nv20_gr_ctor(struct nvkm_object parent, struct nvkm_object engine,
	249	struct nvkm_oclass oclass, void data, u32 size,
	250	struct nvkm_object **pobject)
ebb945a9	251	{
227c95d9	252	struct nvkm_device device = (void )parent;
bfee3f3d	253	struct nv20_gr *gr;
ebb945a9	254	int ret;
6ee73861	255
bfee3f3d BS	256	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
bfee3f3d BS	257	*pobject = nv_object(gr);
ebb945a9 BS	258	if (ret)
ebb945a9 BS	259	return ret;
6ee73861	260
227c95d9 BS	261	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true,
227c95d9 BS	262	&gr->ctxtab);
ebb945a9 BS	263	if (ret)
ebb945a9 BS	264	return ret;
6ee73861	265
bfee3f3d BS	266	nv_subdev(gr)->unit = 0x00001000;
	267	nv_subdev(gr)->intr = nv20_gr_intr;
	268	nv_engine(gr)->cclass = &nv20_gr_cclass;
	269	nv_engine(gr)->sclass = nv20_gr_sclass;
	270	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
6ee73861 BS	271	return 0;
	272	}
	273
ebb945a9	274	void
e3c71eb2	275	nv20_gr_dtor(struct nvkm_object *object)
6ee73861	276	{
bfee3f3d	277	struct nv20_gr gr = (void )object;
227c95d9	278	nvkm_memory_del(&gr->ctxtab);
bfee3f3d	279	nvkm_gr_destroy(&gr->base);
ebb945a9	280	}
6ee73861	281
ebb945a9	282	int
e3c71eb2	283	nv20_gr_init(struct nvkm_object *object)
ebb945a9	284	{
e3c71eb2	285	struct nvkm_engine *engine = nv_engine(object);
bfee3f3d	286	struct nv20_gr gr = (void )engine;
276836d4 BS	287	struct nvkm_device *device = gr->base.engine.subdev.device;
276836d4 BS	288	struct nvkm_fb *fb = device->fb;
ebb945a9 BS	289	u32 tmp, vramsz;
ebb945a9 BS	290	int ret, i;
6ee73861	291
bfee3f3d	292	ret = nvkm_gr_init(&gr->base);
ebb945a9 BS	293	if (ret)
ebb945a9 BS	294	return ret;
6ee73861	295
227c95d9 BS	296	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
227c95d9 BS	297	nvkm_memory_addr(gr->ctxtab) >> 4);
6ee73861	298
bfee3f3d	299	if (nv_device(gr)->chipset == 0x20) {
276836d4	300	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
ebb945a9	301	for (i = 0; i < 15; i++)
276836d4	302	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
c4584adc BS	303	nvkm_msec(device, 2000,
	304	if (!nvkm_rd32(device, 0x400700))
	305	break;
	306	);
ebb945a9	307	} else {
276836d4	308	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
ebb945a9	309	for (i = 0; i < 32; i++)
276836d4	310	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
c4584adc BS	311	nvkm_msec(device, 2000,
	312	if (!nvkm_rd32(device, 0x400700))
	313	break;
	314	);
6ee73861 BS	315	}
6ee73861 BS	316
276836d4 BS	317	nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
276836d4 BS	318	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	319
276836d4 BS	320	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	321	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
	322	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
	323	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	324	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
	325	nvkm_wr32(device, 0x40009C , 0x00000040);
274fec93	326
bfee3f3d	327	if (nv_device(gr)->chipset >= 0x25) {
276836d4 BS	328	nvkm_wr32(device, 0x400890, 0x00a8cfff);
	329	nvkm_wr32(device, 0x400610, 0x304B1FB6);
	330	nvkm_wr32(device, 0x400B80, 0x1cbd3883);
	331	nvkm_wr32(device, 0x400B84, 0x44000000);
	332	nvkm_wr32(device, 0x400098, 0x40000080);
	333	nvkm_wr32(device, 0x400B88, 0x000000ff);
274fec93	334
ebb945a9	335	} else {
276836d4 BS	336	nvkm_wr32(device, 0x400880, 0x0008c7df);
	337	nvkm_wr32(device, 0x400094, 0x00000005);
	338	nvkm_wr32(device, 0x400B80, 0x45eae20e);
	339	nvkm_wr32(device, 0x400B84, 0x24000000);
	340	nvkm_wr32(device, 0x400098, 0x00000040);
	341	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
	342	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
	343	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
	344	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
274fec93	345	}
a0b1de84	346
ebb945a9	347	/* Turn all the tiling regions off. */
b1e4553c	348	for (i = 0; i < fb->tile.regions; i++)
ebb945a9	349	engine->tile_prog(engine, i);
a0b1de84	350
276836d4 BS	351	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
	352	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	353	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
a0b1de84	354
276836d4 BS	355	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
276836d4 BS	356	nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
a0b1de84	357
276836d4 BS	358	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	359	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
	360	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) \| 0x00020100;
	361	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
a0b1de84	362
ebb945a9	363	/* begin RAM config */
bfee3f3d	364	vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
276836d4 BS	365	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
	366	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
	367	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	368	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
	369	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	370	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
	371	nvkm_wr32(device, 0x400820, 0);
	372	nvkm_wr32(device, 0x400824, 0);
	373	nvkm_wr32(device, 0x400864, vramsz - 1);
	374	nvkm_wr32(device, 0x400868, vramsz - 1);
a0b1de84	375
ebb945a9	376	/* interesting.. the below overwrites some of the tile setup above.. */
276836d4 BS	377	nvkm_wr32(device, 0x400B20, 0x00000000);
276836d4 BS	378	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
a0b1de84	379
276836d4 BS	380	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	381	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	382	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	383	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
a0b1de84 BS	384	return 0;
a0b1de84 BS	385	}
ebb945a9	386
e3c71eb2	387	struct nvkm_oclass
b8bf04e1	388	nv20_gr_oclass = {
ebb945a9	389	.handle = NV_ENGINE(GR, 0x20),
e3c71eb2	390	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1 BS	391	.ctor = nv20_gr_ctor,
	392	.dtor = nv20_gr_dtor,
	393	.init = nv20_gr_init,
e3c71eb2	394	.fini = _nvkm_gr_fini,
ebb945a9 BS	395	},
ebb945a9 BS	396	};