[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / nv25.c

#include <core/os.h>
#include <core/engctx.h>
#include <core/enum.h>

#include <subdev/timer.h>
#include <subdev/fb.h>

#include <engine/gr.h>

#include "nv20.h"
#include "regs.h"

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

struct nouveau_oclass
nv25_gr_sclass[] = {
	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
	{ 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv25_gr_context_ctor(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, void *data, u32 size,
			struct nouveau_object **pobject)
{
	struct nv20_gr_chan *chan;
	int ret, i;

	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724,
					   16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->chid = nouveau_fifo_chan(parent)->chid;

	nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
	nv_wo32(chan, 0x035c, 0xffff0000);
	nv_wo32(chan, 0x03c0, 0x0fff0000);
	nv_wo32(chan, 0x03c4, 0x0fff0000);
	nv_wo32(chan, 0x049c, 0x00000101);
	nv_wo32(chan, 0x04b0, 0x00000111);
	nv_wo32(chan, 0x04c8, 0x00000080);
	nv_wo32(chan, 0x04cc, 0xffff0000);
	nv_wo32(chan, 0x04d0, 0x00000001);
	nv_wo32(chan, 0x04e4, 0x44400000);
	nv_wo32(chan, 0x04fc, 0x4b800000);
	for (i = 0x0510; i <= 0x051c; i += 4)
		nv_wo32(chan, i, 0x00030303);
	for (i = 0x0530; i <= 0x053c; i += 4)
		nv_wo32(chan, i, 0x00080000);
	for (i = 0x0548; i <= 0x0554; i += 4)
		nv_wo32(chan, i, 0x01012000);
	for (i = 0x0558; i <= 0x0564; i += 4)
		nv_wo32(chan, i, 0x000105b8);
	for (i = 0x0568; i <= 0x0574; i += 4)
		nv_wo32(chan, i, 0x00080008);
	for (i = 0x0598; i <= 0x05d4; i += 4)
		nv_wo32(chan, i, 0x07ff0000);
	nv_wo32(chan, 0x05e0, 0x4b7fffff);
	nv_wo32(chan, 0x0620, 0x00000080);
	nv_wo32(chan, 0x0624, 0x30201000);
	nv_wo32(chan, 0x0628, 0x70605040);
	nv_wo32(chan, 0x062c, 0xb0a09080);
	nv_wo32(chan, 0x0630, 0xf0e0d0c0);
	nv_wo32(chan, 0x0664, 0x00000001);
	nv_wo32(chan, 0x066c, 0x00004000);
	nv_wo32(chan, 0x0678, 0x00000001);
	nv_wo32(chan, 0x0680, 0x00040000);
	nv_wo32(chan, 0x0684, 0x00010000);
	for (i = 0x1b04; i <= 0x2374; i += 16) {
		nv_wo32(chan, (i + 0), 0x10700ff9);
		nv_wo32(chan, (i + 4), 0x0436086c);
		nv_wo32(chan, (i + 8), 0x000c001b);
	}
	nv_wo32(chan, 0x2704, 0x3f800000);
	nv_wo32(chan, 0x2718, 0x3f800000);
	nv_wo32(chan, 0x2744, 0x40000000);
	nv_wo32(chan, 0x2748, 0x3f800000);
	nv_wo32(chan, 0x274c, 0x3f000000);
	nv_wo32(chan, 0x2754, 0x40000000);
	nv_wo32(chan, 0x2758, 0x3f800000);
	nv_wo32(chan, 0x2760, 0xbf800000);
	nv_wo32(chan, 0x2768, 0xbf800000);
	nv_wo32(chan, 0x308c, 0x000fe000);
	nv_wo32(chan, 0x3108, 0x000003f8);
	nv_wo32(chan, 0x3468, 0x002fe000);
	for (i = 0x3484; i <= 0x34a0; i += 4)
		nv_wo32(chan, i, 0x001c527c);
	return 0;
}

static struct nouveau_oclass
nv25_gr_cclass = {
	.handle = NV_ENGCTX(GR, 0x25),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv25_gr_context_ctor,
		.dtor = _nouveau_gr_context_dtor,
		.init = nv20_gr_context_init,
		.fini = nv20_gr_context_fini,
		.rd32 = _nouveau_gr_context_rd32,
		.wr32 = _nouveau_gr_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

static int
nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv20_gr_priv *priv;
	int ret;

	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv20_gr_intr;
	nv_engine(priv)->cclass = &nv25_gr_cclass;
	nv_engine(priv)->sclass = nv25_gr_sclass;
	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
	return 0;
}

struct nouveau_oclass
nv25_gr_oclass = {
	.handle = NV_ENGINE(GR, 0x25),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv25_gr_ctor,
		.dtor = nv20_gr_dtor,
		.init = nv20_gr_init,
		.fini = _nouveau_gr_fini,
	},
};
Commit	Line	Data
ebb945a9	1	#include <core/os.h>
ebb945a9 BS	2	#include <core/engctx.h>
	3	#include <core/enum.h>
	4
	5	#include <subdev/timer.h>
	6	#include <subdev/fb.h>
	7
b8bf04e1	8	#include <engine/gr.h>
ebb945a9 BS	9
	10	#include "nv20.h"
	11	#include "regs.h"
	12
	13	/*******************************************************************************
	14	* Graphics object classes
	15	******************************************************************************/
	16
	17	struct nouveau_oclass
b8bf04e1 BS	18	nv25_gr_sclass[] = {
	19	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	20	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	21	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	22	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	23	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	24	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	25	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	26	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	27	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	28	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	29	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	30	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
	31	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
	32	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
	33	{ 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */
ebb945a9 BS	34	{},
	35	};
	36
	37	/*******************************************************************************
	38	* PGRAPH context
	39	******************************************************************************/
	40
	41	static int
b8bf04e1	42	nv25_gr_context_ctor(struct nouveau_object *parent,
ebb945a9 BS	43	struct nouveau_object *engine,
	44	struct nouveau_oclass oclass, void data, u32 size,
	45	struct nouveau_object **pobject)
	46	{
b8bf04e1	47	struct nv20_gr_chan *chan;
ebb945a9 BS	48	int ret, i;
ebb945a9 BS	49
b8bf04e1	50	ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724,
ebb945a9 BS	51	16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
	52	*pobject = nv_object(chan);
	53	if (ret)
	54	return ret;
	55
	56	chan->chid = nouveau_fifo_chan(parent)->chid;
	57
	58	nv_wo32(chan, 0x0028, 0x00000001 \| (chan->chid << 24));
	59	nv_wo32(chan, 0x035c, 0xffff0000);
	60	nv_wo32(chan, 0x03c0, 0x0fff0000);
	61	nv_wo32(chan, 0x03c4, 0x0fff0000);
	62	nv_wo32(chan, 0x049c, 0x00000101);
	63	nv_wo32(chan, 0x04b0, 0x00000111);
	64	nv_wo32(chan, 0x04c8, 0x00000080);
	65	nv_wo32(chan, 0x04cc, 0xffff0000);
	66	nv_wo32(chan, 0x04d0, 0x00000001);
	67	nv_wo32(chan, 0x04e4, 0x44400000);
	68	nv_wo32(chan, 0x04fc, 0x4b800000);
	69	for (i = 0x0510; i <= 0x051c; i += 4)
	70	nv_wo32(chan, i, 0x00030303);
	71	for (i = 0x0530; i <= 0x053c; i += 4)
	72	nv_wo32(chan, i, 0x00080000);
	73	for (i = 0x0548; i <= 0x0554; i += 4)
	74	nv_wo32(chan, i, 0x01012000);
	75	for (i = 0x0558; i <= 0x0564; i += 4)
	76	nv_wo32(chan, i, 0x000105b8);
	77	for (i = 0x0568; i <= 0x0574; i += 4)
	78	nv_wo32(chan, i, 0x00080008);
	79	for (i = 0x0598; i <= 0x05d4; i += 4)
	80	nv_wo32(chan, i, 0x07ff0000);
	81	nv_wo32(chan, 0x05e0, 0x4b7fffff);
	82	nv_wo32(chan, 0x0620, 0x00000080);
	83	nv_wo32(chan, 0x0624, 0x30201000);
	84	nv_wo32(chan, 0x0628, 0x70605040);
	85	nv_wo32(chan, 0x062c, 0xb0a09080);
	86	nv_wo32(chan, 0x0630, 0xf0e0d0c0);
	87	nv_wo32(chan, 0x0664, 0x00000001);
	88	nv_wo32(chan, 0x066c, 0x00004000);
	89	nv_wo32(chan, 0x0678, 0x00000001);
	90	nv_wo32(chan, 0x0680, 0x00040000);
	91	nv_wo32(chan, 0x0684, 0x00010000);
	92	for (i = 0x1b04; i <= 0x2374; i += 16) {
	93	nv_wo32(chan, (i + 0), 0x10700ff9);
	94	nv_wo32(chan, (i + 4), 0x0436086c);
	95	nv_wo32(chan, (i + 8), 0x000c001b);
	96	}
	97	nv_wo32(chan, 0x2704, 0x3f800000);
	98	nv_wo32(chan, 0x2718, 0x3f800000);
	99	nv_wo32(chan, 0x2744, 0x40000000);
	100	nv_wo32(chan, 0x2748, 0x3f800000);
	101	nv_wo32(chan, 0x274c, 0x3f000000);
	102	nv_wo32(chan, 0x2754, 0x40000000);
	103	nv_wo32(chan, 0x2758, 0x3f800000);
	104	nv_wo32(chan, 0x2760, 0xbf800000);
	105	nv_wo32(chan, 0x2768, 0xbf800000);
	106	nv_wo32(chan, 0x308c, 0x000fe000);
	107	nv_wo32(chan, 0x3108, 0x000003f8);
	108	nv_wo32(chan, 0x3468, 0x002fe000);
	109	for (i = 0x3484; i <= 0x34a0; i += 4)
	110	nv_wo32(chan, i, 0x001c527c);
	111	return 0;
	112	}
	113
	114	static struct nouveau_oclass
b8bf04e1	115	nv25_gr_cclass = {
ebb945a9 BS	116	.handle = NV_ENGCTX(GR, 0x25),
ebb945a9 BS	117	.ofuncs = &(struct nouveau_ofuncs) {
b8bf04e1 BS	118	.ctor = nv25_gr_context_ctor,
	119	.dtor = _nouveau_gr_context_dtor,
	120	.init = nv20_gr_context_init,
	121	.fini = nv20_gr_context_fini,
	122	.rd32 = _nouveau_gr_context_rd32,
	123	.wr32 = _nouveau_gr_context_wr32,
ebb945a9 BS	124	},
	125	};
	126
	127	/*******************************************************************************
	128	* PGRAPH engine/subdev functions
	129	******************************************************************************/
	130
	131	static int
b8bf04e1	132	nv25_gr_ctor(struct nouveau_object parent, struct nouveau_object engine,
ebb945a9 BS	133	struct nouveau_oclass oclass, void data, u32 size,
	134	struct nouveau_object **pobject)
	135	{
b8bf04e1	136	struct nv20_gr_priv *priv;
ebb945a9 BS	137	int ret;
ebb945a9 BS	138
b8bf04e1	139	ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
ebb945a9 BS	140	*pobject = nv_object(priv);
	141	if (ret)
	142	return ret;
	143
a3e6789a	144	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
ebb945a9 BS	145	NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	146	if (ret)
	147	return ret;
	148
	149	nv_subdev(priv)->unit = 0x00001000;
b8bf04e1 BS	150	nv_subdev(priv)->intr = nv20_gr_intr;
	151	nv_engine(priv)->cclass = &nv25_gr_cclass;
	152	nv_engine(priv)->sclass = nv25_gr_sclass;
	153	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
ebb945a9 BS	154	return 0;
	155	}
	156
	157	struct nouveau_oclass
b8bf04e1	158	nv25_gr_oclass = {
ebb945a9 BS	159	.handle = NV_ENGINE(GR, 0x25),
ebb945a9 BS	160	.ofuncs = &(struct nouveau_ofuncs) {
b8bf04e1 BS	161	.ctor = nv25_gr_ctor,
	162	.dtor = nv20_gr_dtor,
	163	.init = nv20_gr_init,
	164	.fini = _nouveau_gr_fini,
ebb945a9 BS	165	},
ebb945a9 BS	166	};