[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / nv30.c

#include "nv20.h"
#include "regs.h"

#include <engine/fifo.h>
#include <subdev/fb.h>

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

static struct nvkm_oclass
nv30_gr_sclass[] = {
	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
	{ 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
	{ 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
	{ 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
	{ 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
	{ 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
		     struct nvkm_oclass *oclass, void *data, u32 size,
		     struct nvkm_object **pobject)
{
	struct nv20_gr_chan *chan;
	int ret, i;

	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
				     16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->chid = nvkm_fifo_chan(parent)->chid;

	nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
	nv_wo32(chan, 0x0410, 0x00000101);
	nv_wo32(chan, 0x0424, 0x00000111);
	nv_wo32(chan, 0x0428, 0x00000060);
	nv_wo32(chan, 0x0444, 0x00000080);
	nv_wo32(chan, 0x0448, 0xffff0000);
	nv_wo32(chan, 0x044c, 0x00000001);
	nv_wo32(chan, 0x0460, 0x44400000);
	nv_wo32(chan, 0x048c, 0xffff0000);
	for (i = 0x04e0; i < 0x04e8; i += 4)
		nv_wo32(chan, i, 0x0fff0000);
	nv_wo32(chan, 0x04ec, 0x00011100);
	for (i = 0x0508; i < 0x0548; i += 4)
		nv_wo32(chan, i, 0x07ff0000);
	nv_wo32(chan, 0x0550, 0x4b7fffff);
	nv_wo32(chan, 0x058c, 0x00000080);
	nv_wo32(chan, 0x0590, 0x30201000);
	nv_wo32(chan, 0x0594, 0x70605040);
	nv_wo32(chan, 0x0598, 0xb8a89888);
	nv_wo32(chan, 0x059c, 0xf8e8d8c8);
	nv_wo32(chan, 0x05b0, 0xb0000000);
	for (i = 0x0600; i < 0x0640; i += 4)
		nv_wo32(chan, i, 0x00010588);
	for (i = 0x0640; i < 0x0680; i += 4)
		nv_wo32(chan, i, 0x00030303);
	for (i = 0x06c0; i < 0x0700; i += 4)
		nv_wo32(chan, i, 0x0008aae4);
	for (i = 0x0700; i < 0x0740; i += 4)
		nv_wo32(chan, i, 0x01012000);
	for (i = 0x0740; i < 0x0780; i += 4)
		nv_wo32(chan, i, 0x00080008);
	nv_wo32(chan, 0x085c, 0x00040000);
	nv_wo32(chan, 0x0860, 0x00010000);
	for (i = 0x0864; i < 0x0874; i += 4)
		nv_wo32(chan, i, 0x00040004);
	for (i = 0x1f18; i <= 0x3088 ; i += 16) {
		nv_wo32(chan, i + 0, 0x10700ff9);
		nv_wo32(chan, i + 1, 0x0436086c);
		nv_wo32(chan, i + 2, 0x000c001b);
	}
	for (i = 0x30b8; i < 0x30c8; i += 4)
		nv_wo32(chan, i, 0x0000ffff);
	nv_wo32(chan, 0x344c, 0x3f800000);
	nv_wo32(chan, 0x3808, 0x3f800000);
	nv_wo32(chan, 0x381c, 0x3f800000);
	nv_wo32(chan, 0x3848, 0x40000000);
	nv_wo32(chan, 0x384c, 0x3f800000);
	nv_wo32(chan, 0x3850, 0x3f000000);
	nv_wo32(chan, 0x3858, 0x40000000);
	nv_wo32(chan, 0x385c, 0x3f800000);
	nv_wo32(chan, 0x3864, 0xbf800000);
	nv_wo32(chan, 0x386c, 0xbf800000);
	return 0;
}

static struct nvkm_oclass
nv30_gr_cclass = {
	.handle = NV_ENGCTX(GR, 0x30),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv30_gr_context_ctor,
		.dtor = _nvkm_gr_context_dtor,
		.init = nv20_gr_context_init,
		.fini = nv20_gr_context_fini,
		.rd32 = _nvkm_gr_context_rd32,
		.wr32 = _nvkm_gr_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

static int
nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	     struct nvkm_oclass *oclass, void *data, u32 size,
	     struct nvkm_object **pobject)
{
	struct nv20_gr_priv *priv;
	int ret;

	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
			      NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv20_gr_intr;
	nv_engine(priv)->cclass = &nv30_gr_cclass;
	nv_engine(priv)->sclass = nv30_gr_sclass;
	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
	return 0;
}

int
nv30_gr_init(struct nvkm_object *object)
{
	struct nvkm_engine *engine = nv_engine(object);
	struct nv20_gr_priv *priv = (void *)engine;
	struct nvkm_fb *fb = nvkm_fb(object);
	int ret, i;

	ret = nvkm_gr_init(&priv->base);
	if (ret)
		return ret;

	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);

	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(priv, 0x400890, 0x01b463ff);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
	nv_wr32(priv, 0x400B80, 0x1003d888);
	nv_wr32(priv, 0x400B84, 0x0c000000);
	nv_wr32(priv, 0x400098, 0x00000000);
	nv_wr32(priv, 0x40009C, 0x0005ad00);
	nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
	nv_wr32(priv, 0x4000a0, 0x00000000);
	nv_wr32(priv, 0x4000a4, 0x00000008);
	nv_wr32(priv, 0x4008a8, 0xb784a400);
	nv_wr32(priv, 0x400ba0, 0x002f8685);
	nv_wr32(priv, 0x400ba4, 0x00231f3f);
	nv_wr32(priv, 0x4008a4, 0x40000020);

	if (nv_device(priv)->chipset == 0x34) {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);
	}

	nv_wr32(priv, 0x4000c0, 0x00000016);

	/* Turn all the tiling regions off. */
	for (i = 0; i < fb->tile.regions; i++)
		engine->tile_prog(engine, i);

	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
	nv_wr32(priv, 0x0040075c             , 0x00000001);

	/* begin RAM config */
	/* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	if (nv_device(priv)->chipset != 0x34) {
		nv_wr32(priv, 0x400750, 0x00EA0000);
		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));
		nv_wr32(priv, 0x400750, 0x00EA0004);
		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));
	}
	return 0;
}

struct nvkm_oclass
nv30_gr_oclass = {
	.handle = NV_ENGINE(GR, 0x30),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv30_gr_ctor,
		.dtor = nv20_gr_dtor,
		.init = nv30_gr_init,
		.fini = _nvkm_gr_fini,
	},
};
Commit	Line	Data
ebb945a9 BS	1	#include "nv20.h"
	2	#include "regs.h"
	3
e3c71eb2 BS	4	#include <engine/fifo.h>
	5	#include <subdev/fb.h>
	6
ebb945a9 BS	7	/*******************************************************************************
	8	* Graphics object classes
	9	******************************************************************************/
	10
e3c71eb2	11	static struct nvkm_oclass
b8bf04e1 BS	12	nv30_gr_sclass[] = {
	13	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	14	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	15	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	16	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	17	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	18	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	19	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	20	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	21	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	22	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	23	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	24	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
	25	{ 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
	26	{ 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
	27	{ 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
	28	{ 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
	29	{ 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */
ebb945a9 BS	30	{},
	31	};
	32
	33	/*******************************************************************************
	34	* PGRAPH context
	35	******************************************************************************/
	36
	37	static int
e3c71eb2 BS	38	nv30_gr_context_ctor(struct nvkm_object parent, struct nvkm_object engine,
	39	struct nvkm_oclass oclass, void data, u32 size,
	40	struct nvkm_object **pobject)
ebb945a9	41	{
b8bf04e1	42	struct nv20_gr_chan *chan;
ebb945a9 BS	43	int ret, i;
ebb945a9 BS	44
e3c71eb2 BS	45	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
e3c71eb2 BS	46	16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
ebb945a9 BS	47	*pobject = nv_object(chan);
	48	if (ret)
	49	return ret;
	50
e3c71eb2	51	chan->chid = nvkm_fifo_chan(parent)->chid;
ebb945a9 BS	52
	53	nv_wo32(chan, 0x0028, 0x00000001 \| (chan->chid << 24));
	54	nv_wo32(chan, 0x0410, 0x00000101);
	55	nv_wo32(chan, 0x0424, 0x00000111);
	56	nv_wo32(chan, 0x0428, 0x00000060);
	57	nv_wo32(chan, 0x0444, 0x00000080);
	58	nv_wo32(chan, 0x0448, 0xffff0000);
	59	nv_wo32(chan, 0x044c, 0x00000001);
	60	nv_wo32(chan, 0x0460, 0x44400000);
	61	nv_wo32(chan, 0x048c, 0xffff0000);
	62	for (i = 0x04e0; i < 0x04e8; i += 4)
	63	nv_wo32(chan, i, 0x0fff0000);
	64	nv_wo32(chan, 0x04ec, 0x00011100);
	65	for (i = 0x0508; i < 0x0548; i += 4)
	66	nv_wo32(chan, i, 0x07ff0000);
	67	nv_wo32(chan, 0x0550, 0x4b7fffff);
	68	nv_wo32(chan, 0x058c, 0x00000080);
	69	nv_wo32(chan, 0x0590, 0x30201000);
	70	nv_wo32(chan, 0x0594, 0x70605040);
	71	nv_wo32(chan, 0x0598, 0xb8a89888);
	72	nv_wo32(chan, 0x059c, 0xf8e8d8c8);
	73	nv_wo32(chan, 0x05b0, 0xb0000000);
	74	for (i = 0x0600; i < 0x0640; i += 4)
	75	nv_wo32(chan, i, 0x00010588);
	76	for (i = 0x0640; i < 0x0680; i += 4)
	77	nv_wo32(chan, i, 0x00030303);
	78	for (i = 0x06c0; i < 0x0700; i += 4)
	79	nv_wo32(chan, i, 0x0008aae4);
	80	for (i = 0x0700; i < 0x0740; i += 4)
	81	nv_wo32(chan, i, 0x01012000);
	82	for (i = 0x0740; i < 0x0780; i += 4)
	83	nv_wo32(chan, i, 0x00080008);
	84	nv_wo32(chan, 0x085c, 0x00040000);
	85	nv_wo32(chan, 0x0860, 0x00010000);
	86	for (i = 0x0864; i < 0x0874; i += 4)
	87	nv_wo32(chan, i, 0x00040004);
	88	for (i = 0x1f18; i <= 0x3088 ; i += 16) {
	89	nv_wo32(chan, i + 0, 0x10700ff9);
	90	nv_wo32(chan, i + 1, 0x0436086c);
	91	nv_wo32(chan, i + 2, 0x000c001b);
	92	}
	93	for (i = 0x30b8; i < 0x30c8; i += 4)
	94	nv_wo32(chan, i, 0x0000ffff);
	95	nv_wo32(chan, 0x344c, 0x3f800000);
	96	nv_wo32(chan, 0x3808, 0x3f800000);
	97	nv_wo32(chan, 0x381c, 0x3f800000);
	98	nv_wo32(chan, 0x3848, 0x40000000);
	99	nv_wo32(chan, 0x384c, 0x3f800000);
	100	nv_wo32(chan, 0x3850, 0x3f000000);
	101	nv_wo32(chan, 0x3858, 0x40000000);
	102	nv_wo32(chan, 0x385c, 0x3f800000);
	103	nv_wo32(chan, 0x3864, 0xbf800000);
	104	nv_wo32(chan, 0x386c, 0xbf800000);
	105	return 0;
	106	}
	107
e3c71eb2	108	static struct nvkm_oclass
b8bf04e1	109	nv30_gr_cclass = {
ebb945a9	110	.handle = NV_ENGCTX(GR, 0x30),
e3c71eb2	111	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1	112	.ctor = nv30_gr_context_ctor,
e3c71eb2	113	.dtor = _nvkm_gr_context_dtor,
b8bf04e1 BS	114	.init = nv20_gr_context_init,
b8bf04e1 BS	115	.fini = nv20_gr_context_fini,
e3c71eb2 BS	116	.rd32 = _nvkm_gr_context_rd32,
e3c71eb2 BS	117	.wr32 = _nvkm_gr_context_wr32,
ebb945a9 BS	118	},
	119	};
	120
	121	/*******************************************************************************
	122	* PGRAPH engine/subdev functions
	123	******************************************************************************/
	124
	125	static int
e3c71eb2 BS	126	nv30_gr_ctor(struct nvkm_object parent, struct nvkm_object engine,
	127	struct nvkm_oclass oclass, void data, u32 size,
	128	struct nvkm_object **pobject)
ebb945a9	129	{
b8bf04e1	130	struct nv20_gr_priv *priv;
ebb945a9 BS	131	int ret;
ebb945a9 BS	132
e3c71eb2	133	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
ebb945a9 BS	134	*pobject = nv_object(priv);
	135	if (ret)
	136	return ret;
	137
e3c71eb2 BS	138	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
e3c71eb2 BS	139	NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
ebb945a9 BS	140	if (ret)
	141	return ret;
	142
	143	nv_subdev(priv)->unit = 0x00001000;
b8bf04e1 BS	144	nv_subdev(priv)->intr = nv20_gr_intr;
	145	nv_engine(priv)->cclass = &nv30_gr_cclass;
	146	nv_engine(priv)->sclass = nv30_gr_sclass;
	147	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
ebb945a9 BS	148	return 0;
	149	}
	150
	151	int
e3c71eb2	152	nv30_gr_init(struct nvkm_object *object)
ebb945a9	153	{
e3c71eb2	154	struct nvkm_engine *engine = nv_engine(object);
b8bf04e1	155	struct nv20_gr_priv priv = (void )engine;
b1e4553c	156	struct nvkm_fb *fb = nvkm_fb(object);
ebb945a9 BS	157	int ret, i;
ebb945a9 BS	158
e3c71eb2	159	ret = nvkm_gr_init(&priv->base);
ebb945a9 BS	160	if (ret)
	161	return ret;
	162
	163	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
	164
	165	nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
	166	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
	167
	168	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	169	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	170	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	171	nv_wr32(priv, 0x400890, 0x01b463ff);
	172	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
	173	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
	174	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
	175	nv_wr32(priv, 0x400B80, 0x1003d888);
	176	nv_wr32(priv, 0x400B84, 0x0c000000);
	177	nv_wr32(priv, 0x400098, 0x00000000);
	178	nv_wr32(priv, 0x40009C, 0x0005ad00);
	179	nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
	180	nv_wr32(priv, 0x4000a0, 0x00000000);
	181	nv_wr32(priv, 0x4000a4, 0x00000008);
	182	nv_wr32(priv, 0x4008a8, 0xb784a400);
	183	nv_wr32(priv, 0x400ba0, 0x002f8685);
	184	nv_wr32(priv, 0x400ba4, 0x00231f3f);
	185	nv_wr32(priv, 0x4008a4, 0x40000020);
	186
	187	if (nv_device(priv)->chipset == 0x34) {
	188	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	189	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);
	190	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
	191	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);
	192	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	193	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);
	194	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
	195	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);
	196	}
	197
	198	nv_wr32(priv, 0x4000c0, 0x00000016);
	199
	200	/* Turn all the tiling regions off. */
b1e4553c	201	for (i = 0; i < fb->tile.regions; i++)
ebb945a9 BS	202	engine->tile_prog(engine, i);
	203
	204	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	205	nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
	206	nv_wr32(priv, 0x0040075c , 0x00000001);
	207
	208	/* begin RAM config */
	209	/* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
	210	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	211	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	212	if (nv_device(priv)->chipset != 0x34) {
	213	nv_wr32(priv, 0x400750, 0x00EA0000);
	214	nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));
	215	nv_wr32(priv, 0x400750, 0x00EA0004);
	216	nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));
	217	}
	218	return 0;
	219	}
	220
e3c71eb2	221	struct nvkm_oclass
b8bf04e1	222	nv30_gr_oclass = {
ebb945a9	223	.handle = NV_ENGINE(GR, 0x30),
e3c71eb2	224	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1 BS	225	.ctor = nv30_gr_ctor,
	226	.dtor = nv20_gr_dtor,
	227	.init = nv30_gr_init,
e3c71eb2	228	.fini = _nvkm_gr_fini,
ebb945a9 BS	229	},
ebb945a9 BS	230	};