Commit | Line | Data |
---|---|---|
88524bc0 BS |
1 | /* |
2 | * Copyright 2013 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
cf336014 | 24 | #include "nv50.h" |
88524bc0 | 25 | |
a8c4362b BS |
26 | #include <subdev/bios.h> |
27 | #include <subdev/bios/init.h> | |
28 | #include <subdev/bios/pll.h> | |
29 | #include <subdev/clk/pll.h> | |
30 | ||
4bf23ead | 31 | int |
8ac3f64f | 32 | gf100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) |
88524bc0 | 33 | { |
8ac3f64f BS |
34 | struct nvkm_subdev *subdev = &init->subdev; |
35 | struct nvkm_device *device = subdev->device; | |
88524bc0 BS |
36 | struct nvbios_pll info; |
37 | int N, fN, M, P; | |
38 | int ret; | |
39 | ||
8ac3f64f | 40 | ret = nvbios_pll_parse(device->bios, type, &info); |
88524bc0 BS |
41 | if (ret) |
42 | return ret; | |
43 | ||
8ac3f64f | 44 | ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); |
88524bc0 BS |
45 | if (ret < 0) |
46 | return ret; | |
47 | ||
48 | switch (info.type) { | |
49 | case PLL_VPLL0: | |
50 | case PLL_VPLL1: | |
51 | case PLL_VPLL2: | |
52 | case PLL_VPLL3: | |
8ac3f64f BS |
53 | nvkm_mask(device, info.reg + 0x0c, 0x00000000, 0x00000100); |
54 | nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M); | |
55 | nvkm_wr32(device, info.reg + 0x10, fN << 16); | |
88524bc0 BS |
56 | break; |
57 | default: | |
aa860e4b | 58 | nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq); |
88524bc0 BS |
59 | ret = -EINVAL; |
60 | break; | |
61 | } | |
62 | ||
63 | return ret; | |
64 | } | |
65 | ||
4019aaa2 | 66 | static u64 |
8ac3f64f | 67 | gf100_devinit_disable(struct nvkm_devinit *init) |
4019aaa2 | 68 | { |
8ac3f64f BS |
69 | struct nvkm_device *device = init->subdev.device; |
70 | u32 r022500 = nvkm_rd32(device, 0x022500); | |
4019aaa2 IM |
71 | u64 disable = 0ULL; |
72 | ||
73 | if (r022500 & 0x00000001) | |
74 | disable |= (1ULL << NVDEV_ENGINE_DISP); | |
75 | ||
76 | if (r022500 & 0x00000002) { | |
37a5d028 | 77 | disable |= (1ULL << NVDEV_ENGINE_MSPDEC); |
fd8666f7 | 78 | disable |= (1ULL << NVDEV_ENGINE_MSPPP); |
4019aaa2 IM |
79 | } |
80 | ||
81 | if (r022500 & 0x00000004) | |
eccf7e8a | 82 | disable |= (1ULL << NVDEV_ENGINE_MSVLD); |
4019aaa2 | 83 | if (r022500 & 0x00000008) |
bd8369ec | 84 | disable |= (1ULL << NVDEV_ENGINE_MSENC); |
4019aaa2 | 85 | if (r022500 & 0x00000100) |
aedf24ff | 86 | disable |= (1ULL << NVDEV_ENGINE_CE0); |
4019aaa2 | 87 | if (r022500 & 0x00000200) |
aedf24ff | 88 | disable |= (1ULL << NVDEV_ENGINE_CE1); |
4019aaa2 IM |
89 | |
90 | return disable; | |
91 | } | |
92 | ||
4d4d6f75 | 93 | int |
a8c4362b BS |
94 | gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
95 | struct nvkm_oclass *oclass, void *data, u32 size, | |
96 | struct nvkm_object **pobject) | |
88524bc0 | 97 | { |
c9ab50d2 | 98 | struct nvkm_devinit_impl *impl = (void *)oclass; |
266f8b5e | 99 | struct nv50_devinit *init; |
c9ab50d2 | 100 | u64 disable; |
88524bc0 BS |
101 | int ret; |
102 | ||
266f8b5e BS |
103 | ret = nvkm_devinit_create(parent, engine, oclass, &init); |
104 | *pobject = nv_object(init); | |
88524bc0 BS |
105 | if (ret) |
106 | return ret; | |
107 | ||
266f8b5e | 108 | disable = impl->disable(&init->base); |
c9ab50d2 | 109 | if (disable & (1ULL << NVDEV_ENGINE_DISP)) |
266f8b5e | 110 | init->base.post = true; |
a8c4362b | 111 | |
88524bc0 BS |
112 | return 0; |
113 | } | |
114 | ||
a8c4362b BS |
115 | struct nvkm_oclass * |
116 | gf100_devinit_oclass = &(struct nvkm_devinit_impl) { | |
cf336014 | 117 | .base.handle = NV_SUBDEV(DEVINIT, 0xc0), |
a8c4362b BS |
118 | .base.ofuncs = &(struct nvkm_ofuncs) { |
119 | .ctor = gf100_devinit_ctor, | |
120 | .dtor = _nvkm_devinit_dtor, | |
88524bc0 | 121 | .init = nv50_devinit_init, |
a8c4362b | 122 | .fini = _nvkm_devinit_fini, |
88524bc0 | 123 | }, |
a8c4362b BS |
124 | .pll_set = gf100_devinit_pll_set, |
125 | .disable = gf100_devinit_disable, | |
e21fd7c4 | 126 | .post = nvbios_init, |
cf336014 | 127 | }.base; |