projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f648cab0 RS |
1 | /* |
| 2 | * Copyright 2013 Red Hat Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
| 23 | * Roy Spliet <rspliet@eclipso.eu> | |
| 24 | */ | |
| f648cab0 RS |
25 | #include "priv.h" |
| 26 | ||
| 27 | struct ramxlat { | |
| 28 | int id; | |
| 29 | u8 enc; | |
| 30 | }; | |
| 31 | ||
| 32 | static inline int | |
| 33 | ramxlat(const struct ramxlat *xlat, int id) | |
| 34 | { | |
| 35 | while (xlat->id >= 0) { | |
| 36 | if (xlat->id == id) | |
| 37 | return xlat->enc; | |
| 38 | xlat++; | |
| 39 | } | |
| 40 | return -EINVAL; | |
| 41 | } | |
| 42 | ||
| 43 | static const struct ramxlat | |
| 44 | ramgddr3_cl_lo[] = { | |
| 45 | { 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 }, | |
| 46 | /* the below are mentioned in some, but not all, gddr3 docs */ | |
| 47 | { 12, 4 }, { 13, 5 }, { 14, 6 }, | |
| 48 | /* XXX: Per Samsung docs, are these used? They overlap with Qimonda */ | |
| 49 | /* { 4, 4 }, { 5, 5 }, { 6, 6 }, { 12, 8 }, { 13, 9 }, { 14, 10 }, | |
| 50 | * { 15, 11 }, */ | |
| 51 | { -1 } | |
| 52 | }; | |
| 53 | ||
| 54 | static const struct ramxlat | |
| 55 | ramgddr3_cl_hi[] = { | |
| 56 | { 10, 2 }, { 11, 3 }, { 12, 4 }, { 13, 5 }, { 14, 6 }, { 15, 7 }, | |
| 57 | { 16, 0 }, { 17, 1 }, | |
| 58 | { -1 } | |
| 59 | }; | |
| 60 | ||
| 61 | static const struct ramxlat | |
| 62 | ramgddr3_wr_lo[] = { | |
| 63 | { 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 }, | |
| 64 | { 11, 0 }, | |
| 65 | /* the below are mentioned in some, but not all, gddr3 docs */ | |
| 66 | { 4, 1 }, { 6, 3 }, { 12, 1 }, { 13 , 2 }, | |
| 67 | { -1 } | |
| 68 | }; | |
| 69 | ||
| 70 | int | |
| 639c308e | 71 | nvkm_gddr3_calc(struct nvkm_ram *ram) |
| f648cab0 RS |
72 | { |
| 73 | int CL, WR, CWL, DLL = 0, ODT = 0, hi; | |
| 74 | ||
| 75 | switch (ram->next->bios.timing_ver) { | |
| 76 | case 0x10: | |
| 77 | CWL = ram->next->bios.timing_10_CWL; | |
| 78 | CL = ram->next->bios.timing_10_CL; | |
| 79 | WR = ram->next->bios.timing_10_WR; | |
| 7164f4c5 | 80 | DLL = !ram->next->bios.ramcfg_DLLoff; |
| f648cab0 RS |
81 | ODT = ram->next->bios.timing_10_ODT; |
| 82 | break; | |
| 83 | case 0x20: | |
| 84 | CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; | |
| 85 | CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; | |
| 86 | WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; | |
| 87 | /* XXX: Get these values from the VBIOS instead */ | |
| 88 | DLL = !(ram->mr[1] & 0x1); | |
| 89 | ODT = (ram->mr[1] & 0x004) >> 2 | | |
| 90 | (ram->mr[1] & 0x040) >> 5 | | |
| 91 | (ram->mr[1] & 0x200) >> 7; | |
| 92 | break; | |
| 93 | default: | |
| 94 | return -ENOSYS; | |
| 95 | } | |
| 96 | ||
| 97 | hi = ram->mr[2] & 0x1; | |
| 98 | CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL); | |
| 99 | WR = ramxlat(ramgddr3_wr_lo, WR); | |
| 100 | if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) | |
| 101 | return -EINVAL; | |
| 102 | ||
| 103 | ram->mr[0] &= ~0xf74; | |
| 104 | ram->mr[0] |= (CWL & 0x07) << 9; | |
| 105 | ram->mr[0] |= (CL & 0x07) << 4; | |
| 106 | ram->mr[0] |= (CL & 0x08) >> 1; | |
| 107 | ||
| 108 | ram->mr[1] &= ~0x3fc; | |
| 109 | ram->mr[1] |= (ODT & 0x03) << 2; | |
| 110 | ram->mr[1] |= (ODT & 0x03) << 8; | |
| 111 | ram->mr[1] |= (WR & 0x03) << 4; | |
| 112 | ram->mr[1] |= (WR & 0x04) << 5; | |
| 113 | ram->mr[1] |= !DLL << 6; | |
| 114 | return 0; | |
| 115 | } |