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6ee73861 | 1 | /* |
7d9115de | 2 | * Copyright 2012 Red Hat Inc. |
6ee73861 | 3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
6ee73861 | 10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. | |
6ee73861 | 13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
6ee73861 | 21 | * |
7d9115de | 22 | * Authors: Ben Skeggs |
6ee73861 | 23 | */ |
08f6fbdb | 24 | #include "nv04.h" |
7d9115de | 25 | |
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26 | #include <core/device.h> |
27 | ||
28 | const struct nvkm_mc_intr | |
7d9115de | 29 | nv50_mc_intr[] = { |
dcfb1009 | 30 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ |
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31 | { 0x00000001, NVDEV_ENGINE_MPEG }, |
32 | { 0x00000100, NVDEV_ENGINE_FIFO }, | |
33 | { 0x00001000, NVDEV_ENGINE_GR }, | |
93d90ad7 | 34 | { 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */ |
7d9115de | 35 | { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */ |
a0376b14 | 36 | { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */ |
7d9115de | 37 | { 0x00100000, NVDEV_SUBDEV_TIMER }, |
febb8449 BS |
38 | { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ |
39 | { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ | |
a10220bb | 40 | { 0x10000000, NVDEV_SUBDEV_BUS }, |
7d9115de | 41 | { 0x80000000, NVDEV_ENGINE_SW }, |
92183763 | 42 | { 0x0002d101, NVDEV_SUBDEV_FB }, |
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43 | {}, |
44 | }; | |
45 | ||
9a9d5c64 | 46 | static void |
d7e5fcd2 | 47 | nv50_mc_msi_rearm(struct nvkm_mc *pmc) |
9a9d5c64 | 48 | { |
d7e5fcd2 | 49 | struct nvkm_device *device = nv_device(pmc); |
9a9d5c64 BS |
50 | pci_write_config_byte(device->pdev, 0x68, 0xff); |
51 | } | |
52 | ||
7d9115de | 53 | int |
d7e5fcd2 | 54 | nv50_mc_init(struct nvkm_object *object) |
6ee73861 | 55 | { |
08f6fbdb | 56 | struct nv04_mc_priv *priv = (void *)object; |
7d9115de | 57 | nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ |
d7e5fcd2 | 58 | return nvkm_mc_init(&priv->base); |
6ee73861 | 59 | } |
7d9115de | 60 | |
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61 | struct nvkm_oclass * |
62 | nv50_mc_oclass = &(struct nvkm_mc_oclass) { | |
08f6fbdb | 63 | .base.handle = NV_SUBDEV(MC, 0x50), |
d7e5fcd2 | 64 | .base.ofuncs = &(struct nvkm_ofuncs) { |
08f6fbdb | 65 | .ctor = nv04_mc_ctor, |
d7e5fcd2 | 66 | .dtor = _nvkm_mc_dtor, |
7d9115de | 67 | .init = nv50_mc_init, |
d7e5fcd2 | 68 | .fini = _nvkm_mc_fini, |
7d9115de | 69 | }, |
08f6fbdb | 70 | .intr = nv50_mc_intr, |
9a9d5c64 | 71 | .msi_rearm = nv50_mc_msi_rearm, |
08f6fbdb | 72 | }.base; |