[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / therm / g84.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 * 	    Martin Peres
 */
#include "priv.h"

#include <subdev/fuse.h>

struct g84_therm_priv {
	struct nvkm_therm_priv base;
};

int
g84_temp_get(struct nvkm_therm *therm)
{
	struct nvkm_fuse *fuse = nvkm_fuse(therm);

	if (nv_ro32(fuse, 0x1a8) == 1)
		return nv_rd32(therm, 0x20400);
	else
		return -ENODEV;
}

void
g84_sensor_setup(struct nvkm_therm *therm)
{
	struct nvkm_fuse *fuse = nvkm_fuse(therm);

	/* enable temperature reading for cards with insane defaults */
	if (nv_ro32(fuse, 0x1a8) == 1) {
		nv_mask(therm, 0x20008, 0x80008000, 0x80000000);
		nv_mask(therm, 0x2000c, 0x80000003, 0x00000000);
		mdelay(20); /* wait for the temperature to stabilize */
	}
}

static void
g84_therm_program_alarms(struct nvkm_therm *therm)
{
	struct nvkm_therm_priv *priv = (void *)therm;
	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
	unsigned long flags;

	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);

	/* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */
	nv_wr32(therm, 0x20000, 0x000003ff);

	/* shutdown: The computer should be shutdown when reached */
	nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis);
	nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp);

	/* THRS_1 : fan boost*/
	nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp);

	/* THRS_2 : critical */
	nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp);

	/* THRS_4 : down clock */
	nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp);
	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);

	nv_debug(therm,
		 "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
		 sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
		 sensor->thrs_down_clock.temp,
		 sensor->thrs_down_clock.hysteresis,
		 sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
		 sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);

}

/* must be called with alarm_program_lock taken ! */
static void
g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm,
				   uint32_t thrs_reg, u8 status_bit,
				   const struct nvbios_therm_threshold *thrs,
				   enum nvkm_therm_thrs thrs_name)
{
	enum nvkm_therm_thrs_direction direction;
	enum nvkm_therm_thrs_state prev_state, new_state;
	int temp, cur;

	prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name);
	temp = nv_rd32(therm, thrs_reg);

	/* program the next threshold */
	if (temp == thrs->temp) {
		nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
		new_state = NVKM_THERM_THRS_HIGHER;
	} else {
		nv_wr32(therm, thrs_reg, thrs->temp);
		new_state = NVKM_THERM_THRS_LOWER;
	}

	/* fix the state (in case someone reprogrammed the alarms) */
	cur = therm->temp_get(therm);
	if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp)
		new_state = NVKM_THERM_THRS_HIGHER;
	else if (new_state == NVKM_THERM_THRS_HIGHER &&
		cur < thrs->temp - thrs->hysteresis)
		new_state = NVKM_THERM_THRS_LOWER;
	nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state);

	/* find the direction */
	if (prev_state < new_state)
		direction = NVKM_THERM_THRS_RISING;
	else if (prev_state > new_state)
		direction = NVKM_THERM_THRS_FALLING;
	else
		return;

	/* advertise a change in direction */
	nvkm_therm_sensor_event(therm, thrs_name, direction);
}

static void
g84_therm_intr(struct nvkm_subdev *subdev)
{
	struct nvkm_therm *therm = nvkm_therm(subdev);
	struct nvkm_therm_priv *priv = (void *)therm;
	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
	unsigned long flags;
	uint32_t intr;

	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);

	intr = nv_rd32(therm, 0x20100) & 0x3ff;

	/* THRS_4: downclock */
	if (intr & 0x002) {
		g84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
						   &sensor->thrs_down_clock,
						   NVKM_THERM_THRS_DOWNCLOCK);
		intr &= ~0x002;
	}

	/* shutdown */
	if (intr & 0x004) {
		g84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
						   &sensor->thrs_shutdown,
						   NVKM_THERM_THRS_SHUTDOWN);
		intr &= ~0x004;
	}

	/* THRS_1 : fan boost */
	if (intr & 0x008) {
		g84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
						   &sensor->thrs_fan_boost,
						   NVKM_THERM_THRS_FANBOOST);
		intr &= ~0x008;
	}

	/* THRS_2 : critical */
	if (intr & 0x010) {
		g84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
						   &sensor->thrs_critical,
						   NVKM_THERM_THRS_CRITICAL);
		intr &= ~0x010;
	}

	if (intr)
		nv_error(therm, "unhandled intr 0x%08x\n", intr);

	/* ACK everything */
	nv_wr32(therm, 0x20100, 0xffffffff);
	nv_wr32(therm, 0x1100, 0x10000); /* PBUS */

	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
}

static int
g84_therm_init(struct nvkm_object *object)
{
	struct g84_therm_priv *priv = (void *)object;
	int ret;

	ret = nvkm_therm_init(&priv->base.base);
	if (ret)
		return ret;

	g84_sensor_setup(&priv->base.base);
	return 0;
}

static int
g84_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	       struct nvkm_oclass *oclass, void *data, u32 size,
	       struct nvkm_object **pobject)
{
	struct g84_therm_priv *priv;
	int ret;

	ret = nvkm_therm_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
	priv->base.base.pwm_get = nv50_fan_pwm_get;
	priv->base.base.pwm_set = nv50_fan_pwm_set;
	priv->base.base.pwm_clock = nv50_fan_pwm_clock;
	priv->base.base.temp_get = g84_temp_get;
	priv->base.sensor.program_alarms = g84_therm_program_alarms;
	nv_subdev(priv)->intr = g84_therm_intr;

	/* init the thresholds */
	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
					      NVKM_THERM_THRS_SHUTDOWN,
					      NVKM_THERM_THRS_LOWER);
	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
					      NVKM_THERM_THRS_FANBOOST,
					      NVKM_THERM_THRS_LOWER);
	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
					      NVKM_THERM_THRS_CRITICAL,
					      NVKM_THERM_THRS_LOWER);
	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
					      NVKM_THERM_THRS_DOWNCLOCK,
					      NVKM_THERM_THRS_LOWER);

	return nvkm_therm_preinit(&priv->base.base);
}

int
g84_therm_fini(struct nvkm_object *object, bool suspend)
{
	/* Disable PTherm IRQs */
	nv_wr32(object, 0x20000, 0x00000000);

	/* ACK all PTherm IRQs */
	nv_wr32(object, 0x20100, 0xffffffff);
	nv_wr32(object, 0x1100, 0x10000); /* PBUS */

	return _nvkm_therm_fini(object, suspend);
}

struct nvkm_oclass
g84_therm_oclass = {
	.handle = NV_SUBDEV(THERM, 0x84),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = g84_therm_ctor,
		.dtor = _nvkm_therm_dtor,
		.init = g84_therm_init,
		.fini = g84_therm_fini,
	},
};
Commit	Line	Data
2f457367 MP	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	* Martin Peres
	24	*/
2f457367	25	#include "priv.h"
e1404611	26
c5b4865e	27	#include <subdev/fuse.h>
2f457367	28
e1404611 BS	29	struct g84_therm_priv {
e1404611 BS	30	struct nvkm_therm_priv base;
2f457367 MP	31	};
	32
	33	int
e1404611	34	g84_temp_get(struct nvkm_therm *therm)
2f457367	35	{
e1404611	36	struct nvkm_fuse *fuse = nvkm_fuse(therm);
3a405258 MP	37
	38	if (nv_ro32(fuse, 0x1a8) == 1)
	39	return nv_rd32(therm, 0x20400);
	40	else
	41	return -ENODEV;
2f457367 MP	42	}
2f457367 MP	43
c5b4865e	44	void
e1404611	45	g84_sensor_setup(struct nvkm_therm *therm)
c5b4865e	46	{
e1404611	47	struct nvkm_fuse *fuse = nvkm_fuse(therm);
c5b4865e MP	48
	49	/* enable temperature reading for cards with insane defaults */
	50	if (nv_ro32(fuse, 0x1a8) == 1) {
	51	nv_mask(therm, 0x20008, 0x80008000, 0x80000000);
	52	nv_mask(therm, 0x2000c, 0x80000003, 0x00000000);
	53	mdelay(20); /* wait for the temperature to stabilize */
	54	}
	55	}
	56
2f457367	57	static void
e1404611	58	g84_therm_program_alarms(struct nvkm_therm *therm)
2f457367	59	{
e1404611	60	struct nvkm_therm_priv priv = (void )therm;
2f457367 MP	61	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
	62	unsigned long flags;
	63
	64	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
	65
	66	/* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */
	67	nv_wr32(therm, 0x20000, 0x000003ff);
	68
	69	/* shutdown: The computer should be shutdown when reached */
	70	nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis);
	71	nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp);
	72
	73	/* THRS_1 : fan boost*/
	74	nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp);
	75
	76	/* THRS_2 : critical */
	77	nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp);
	78
	79	/* THRS_4 : down clock */
	80	nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp);
	81	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
	82
bdd4e843 BS	83	nv_debug(therm,
	84	"Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
	85	sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
	86	sensor->thrs_down_clock.temp,
	87	sensor->thrs_down_clock.hysteresis,
	88	sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
	89	sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);
2f457367 MP	90
	91	}
	92
	93	/* must be called with alarm_program_lock taken ! */
	94	static void
e1404611	95	g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm,
2f457367 MP	96	uint32_t thrs_reg, u8 status_bit,
2f457367 MP	97	const struct nvbios_therm_threshold *thrs,
e1404611	98	enum nvkm_therm_thrs thrs_name)
2f457367	99	{
e1404611 BS	100	enum nvkm_therm_thrs_direction direction;
e1404611 BS	101	enum nvkm_therm_thrs_state prev_state, new_state;
2f457367 MP	102	int temp, cur;
2f457367 MP	103
e1404611	104	prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name);
2f457367 MP	105	temp = nv_rd32(therm, thrs_reg);
	106
	107	/* program the next threshold */
	108	if (temp == thrs->temp) {
	109	nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
e1404611	110	new_state = NVKM_THERM_THRS_HIGHER;
2f457367 MP	111	} else {
2f457367 MP	112	nv_wr32(therm, thrs_reg, thrs->temp);
e1404611	113	new_state = NVKM_THERM_THRS_LOWER;
2f457367 MP	114	}
	115
	116	/* fix the state (in case someone reprogrammed the alarms) */
	117	cur = therm->temp_get(therm);
e1404611 BS	118	if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp)
	119	new_state = NVKM_THERM_THRS_HIGHER;
	120	else if (new_state == NVKM_THERM_THRS_HIGHER &&
2f457367	121	cur < thrs->temp - thrs->hysteresis)
e1404611 BS	122	new_state = NVKM_THERM_THRS_LOWER;
e1404611 BS	123	nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
2f457367 MP	124
	125	/* find the direction */
	126	if (prev_state < new_state)
e1404611	127	direction = NVKM_THERM_THRS_RISING;
2f457367	128	else if (prev_state > new_state)
e1404611	129	direction = NVKM_THERM_THRS_FALLING;
2f457367 MP	130	else
	131	return;
	132
	133	/* advertise a change in direction */
e1404611	134	nvkm_therm_sensor_event(therm, thrs_name, direction);
2f457367 MP	135	}
	136
	137	static void
e1404611	138	g84_therm_intr(struct nvkm_subdev *subdev)
2f457367	139	{
e1404611 BS	140	struct nvkm_therm *therm = nvkm_therm(subdev);
e1404611 BS	141	struct nvkm_therm_priv priv = (void )therm;
2f457367 MP	142	struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
	143	unsigned long flags;
	144	uint32_t intr;
	145
	146	spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
	147
b449a43f	148	intr = nv_rd32(therm, 0x20100) & 0x3ff;
2f457367 MP	149
	150	/* THRS_4: downclock */
	151	if (intr & 0x002) {
e1404611 BS	152	g84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
	153	&sensor->thrs_down_clock,
	154	NVKM_THERM_THRS_DOWNCLOCK);
2f457367 MP	155	intr &= ~0x002;
	156	}
	157
	158	/* shutdown */
	159	if (intr & 0x004) {
e1404611	160	g84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
2f457367	161	&sensor->thrs_shutdown,
e1404611	162	NVKM_THERM_THRS_SHUTDOWN);
2f457367 MP	163	intr &= ~0x004;
	164	}
	165
	166	/* THRS_1 : fan boost */
	167	if (intr & 0x008) {
e1404611	168	g84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
2f457367	169	&sensor->thrs_fan_boost,
e1404611	170	NVKM_THERM_THRS_FANBOOST);
2f457367 MP	171	intr &= ~0x008;
	172	}
	173
	174	/* THRS_2 : critical */
	175	if (intr & 0x010) {
e1404611	176	g84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
2f457367	177	&sensor->thrs_critical,
e1404611	178	NVKM_THERM_THRS_CRITICAL);
2f457367 MP	179	intr &= ~0x010;
	180	}
	181
	182	if (intr)
	183	nv_error(therm, "unhandled intr 0x%08x\n", intr);
	184
	185	/* ACK everything */
	186	nv_wr32(therm, 0x20100, 0xffffffff);
	187	nv_wr32(therm, 0x1100, 0x10000); /* PBUS */
	188
	189	spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
	190	}
	191
c5b4865e	192	static int
e1404611	193	g84_therm_init(struct nvkm_object *object)
c5b4865e	194	{
e1404611	195	struct g84_therm_priv priv = (void )object;
c5b4865e MP	196	int ret;
c5b4865e MP	197
e1404611	198	ret = nvkm_therm_init(&priv->base.base);
c5b4865e MP	199	if (ret)
	200	return ret;
	201
e1404611	202	g84_sensor_setup(&priv->base.base);
c5b4865e MP	203	return 0;
	204	}
	205
2f457367	206	static int
e1404611 BS	207	g84_therm_ctor(struct nvkm_object parent, struct nvkm_object engine,
	208	struct nvkm_oclass oclass, void data, u32 size,
	209	struct nvkm_object **pobject)
2f457367	210	{
e1404611	211	struct g84_therm_priv *priv;
2f457367 MP	212	int ret;
2f457367 MP	213
e1404611	214	ret = nvkm_therm_create(parent, engine, oclass, &priv);
2f457367 MP	215	*pobject = nv_object(priv);
	216	if (ret)
	217	return ret;
	218
	219	priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
	220	priv->base.base.pwm_get = nv50_fan_pwm_get;
	221	priv->base.base.pwm_set = nv50_fan_pwm_set;
	222	priv->base.base.pwm_clock = nv50_fan_pwm_clock;
e1404611 BS	223	priv->base.base.temp_get = g84_temp_get;
	224	priv->base.sensor.program_alarms = g84_therm_program_alarms;
	225	nv_subdev(priv)->intr = g84_therm_intr;
2f457367 MP	226
2f457367 MP	227	/* init the thresholds */
e1404611 BS	228	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
	229	NVKM_THERM_THRS_SHUTDOWN,
	230	NVKM_THERM_THRS_LOWER);
	231	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
	232	NVKM_THERM_THRS_FANBOOST,
	233	NVKM_THERM_THRS_LOWER);
	234	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
	235	NVKM_THERM_THRS_CRITICAL,
	236	NVKM_THERM_THRS_LOWER);
	237	nvkm_therm_sensor_set_threshold_state(&priv->base.base,
	238	NVKM_THERM_THRS_DOWNCLOCK,
	239	NVKM_THERM_THRS_LOWER);
	240
	241	return nvkm_therm_preinit(&priv->base.base);
2f457367 MP	242	}
2f457367 MP	243
b449a43f	244	int
e1404611	245	g84_therm_fini(struct nvkm_object *object, bool suspend)
b449a43f MP	246	{
	247	/* Disable PTherm IRQs */
	248	nv_wr32(object, 0x20000, 0x00000000);
	249
	250	/* ACK all PTherm IRQs */
	251	nv_wr32(object, 0x20100, 0xffffffff);
	252	nv_wr32(object, 0x1100, 0x10000); /* PBUS */
	253
e1404611	254	return _nvkm_therm_fini(object, suspend);
b449a43f MP	255	}
b449a43f MP	256
e1404611 BS	257	struct nvkm_oclass
e1404611 BS	258	g84_therm_oclass = {
2f457367	259	.handle = NV_SUBDEV(THERM, 0x84),
e1404611 BS	260	.ofuncs = &(struct nvkm_ofuncs) {
	261	.ctor = g84_therm_ctor,
	262	.dtor = _nvkm_therm_dtor,
	263	.init = g84_therm_init,
	264	.fini = g84_therm_fini,
2f457367 MP	265	},
2f457367 MP	266	};