Commit | Line | Data |
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80c39712 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dispc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DISPC" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/vmalloc.h> | |
a8a35931 | 28 | #include <linux/export.h> |
80c39712 TV |
29 | #include <linux/clk.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/workqueue.h> | |
ab83b14c | 35 | #include <linux/hardirq.h> |
24e6289c | 36 | #include <linux/platform_device.h> |
4fbafaf3 | 37 | #include <linux/pm_runtime.h> |
33366d0e | 38 | #include <linux/sizes.h> |
0006fd63 TV |
39 | #include <linux/mfd/syscon.h> |
40 | #include <linux/regmap.h> | |
41 | #include <linux/of.h> | |
736e60dd | 42 | #include <linux/component.h> |
80c39712 | 43 | |
a0b38cc4 | 44 | #include <video/omapdss.h> |
80c39712 TV |
45 | |
46 | #include "dss.h" | |
a0acb557 | 47 | #include "dss_features.h" |
9b372c2d | 48 | #include "dispc.h" |
80c39712 TV |
49 | |
50 | /* DISPC */ | |
8613b000 | 51 | #define DISPC_SZ_REGS SZ_4K |
80c39712 | 52 | |
5ed8cf5b TV |
53 | enum omap_burst_size { |
54 | BURST_SIZE_X2 = 0, | |
55 | BURST_SIZE_X4 = 1, | |
56 | BURST_SIZE_X8 = 2, | |
57 | }; | |
58 | ||
80c39712 TV |
59 | #define REG_GET(idx, start, end) \ |
60 | FLD_GET(dispc_read_reg(idx), start, end) | |
61 | ||
62 | #define REG_FLD_MOD(idx, val, start, end) \ | |
63 | dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) | |
64 | ||
dcbe765b CM |
65 | struct dispc_features { |
66 | u8 sw_start; | |
67 | u8 fp_start; | |
68 | u8 bp_start; | |
69 | u16 sw_max; | |
70 | u16 vp_max; | |
71 | u16 hp_max; | |
33b89928 AT |
72 | u8 mgr_width_start; |
73 | u8 mgr_height_start; | |
74 | u16 mgr_width_max; | |
75 | u16 mgr_height_max; | |
ca5ca69c AT |
76 | unsigned long max_lcd_pclk; |
77 | unsigned long max_tv_pclk; | |
0c6921de | 78 | int (*calc_scaling) (unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
79 | const struct omap_video_timings *mgr_timings, |
80 | u16 width, u16 height, u16 out_width, u16 out_height, | |
81 | enum omap_color_mode color_mode, bool *five_taps, | |
82 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 83 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem); |
8702ee50 | 84 | unsigned long (*calc_core_clk) (unsigned long pclk, |
8ba85306 AT |
85 | u16 width, u16 height, u16 out_width, u16 out_height, |
86 | bool mem_to_mem); | |
42a6961c | 87 | u8 num_fifos; |
66a0f9e4 TV |
88 | |
89 | /* swap GFX & WB fifos */ | |
90 | bool gfx_fifo_workaround:1; | |
cffa947d TV |
91 | |
92 | /* no DISPC_IRQ_FRAMEDONETV on this SoC */ | |
93 | bool no_framedone_tv:1; | |
d0df9a2c AT |
94 | |
95 | /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ | |
96 | bool mstandby_workaround:1; | |
8bc65552 AT |
97 | |
98 | bool set_max_preload:1; | |
f2aee319 TV |
99 | |
100 | /* PIXEL_INC is not added to the last pixel of a line */ | |
101 | bool last_pixel_inc_missing:1; | |
e5f80917 TV |
102 | |
103 | /* POL_FREQ has ALIGN bit */ | |
104 | bool supports_sync_align:1; | |
20efbc35 TV |
105 | |
106 | bool has_writeback:1; | |
3a38ed53 TV |
107 | |
108 | bool supports_double_pixel:1; | |
b7536d67 TV |
109 | |
110 | /* | |
111 | * Field order for VENC is different than HDMI. We should handle this in | |
112 | * some intelligent manner, but as the SoCs have either HDMI or VENC, | |
113 | * never both, we can just use this flag for now. | |
114 | */ | |
115 | bool reverse_ilace_field_order:1; | |
dcbe765b CM |
116 | }; |
117 | ||
42a6961c TV |
118 | #define DISPC_MAX_NR_FIFOS 5 |
119 | ||
80c39712 | 120 | static struct { |
060b6d9c | 121 | struct platform_device *pdev; |
80c39712 | 122 | void __iomem *base; |
4fbafaf3 | 123 | |
affe360d | 124 | int irq; |
0925afc9 TV |
125 | irq_handler_t user_handler; |
126 | void *user_data; | |
80c39712 | 127 | |
7b3926b3 | 128 | unsigned long core_clk_rate; |
5391e87d | 129 | unsigned long tv_pclk_rate; |
7b3926b3 | 130 | |
42a6961c TV |
131 | u32 fifo_size[DISPC_MAX_NR_FIFOS]; |
132 | /* maps which plane is using a fifo. fifo-id -> plane-id */ | |
133 | int fifo_assignment[DISPC_MAX_NR_FIFOS]; | |
80c39712 | 134 | |
49ea86f3 | 135 | bool ctx_valid; |
80c39712 | 136 | u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; |
dfc0fd8d | 137 | |
dcbe765b | 138 | const struct dispc_features *feat; |
0925afc9 TV |
139 | |
140 | bool is_enabled; | |
0006fd63 TV |
141 | |
142 | struct regmap *syscon_pol; | |
143 | u32 syscon_pol_offset; | |
d49cd155 TV |
144 | |
145 | /* DISPC_CONTROL & DISPC_CONFIG lock*/ | |
146 | spinlock_t control_lock; | |
80c39712 TV |
147 | } dispc; |
148 | ||
0d66cbb5 AJ |
149 | enum omap_color_component { |
150 | /* used for all color formats for OMAP3 and earlier | |
151 | * and for RGB and Y color component on OMAP4 | |
152 | */ | |
153 | DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, | |
154 | /* used for UV component for | |
155 | * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 | |
156 | * color formats on OMAP4 | |
157 | */ | |
158 | DISPC_COLOR_COMPONENT_UV = 1 << 1, | |
159 | }; | |
160 | ||
efa70b3b CM |
161 | enum mgr_reg_fields { |
162 | DISPC_MGR_FLD_ENABLE, | |
163 | DISPC_MGR_FLD_STNTFT, | |
164 | DISPC_MGR_FLD_GO, | |
165 | DISPC_MGR_FLD_TFTDATALINES, | |
166 | DISPC_MGR_FLD_STALLMODE, | |
167 | DISPC_MGR_FLD_TCKENABLE, | |
168 | DISPC_MGR_FLD_TCKSELECTION, | |
169 | DISPC_MGR_FLD_CPR, | |
170 | DISPC_MGR_FLD_FIFOHANDCHECK, | |
171 | /* used to maintain a count of the above fields */ | |
172 | DISPC_MGR_FLD_NUM, | |
173 | }; | |
174 | ||
5c348ba9 JS |
175 | struct dispc_reg_field { |
176 | u16 reg; | |
177 | u8 high; | |
178 | u8 low; | |
179 | }; | |
180 | ||
efa70b3b CM |
181 | static const struct { |
182 | const char *name; | |
183 | u32 vsync_irq; | |
184 | u32 framedone_irq; | |
185 | u32 sync_lost_irq; | |
5c348ba9 | 186 | struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; |
efa70b3b CM |
187 | } mgr_desc[] = { |
188 | [OMAP_DSS_CHANNEL_LCD] = { | |
189 | .name = "LCD", | |
190 | .vsync_irq = DISPC_IRQ_VSYNC, | |
191 | .framedone_irq = DISPC_IRQ_FRAMEDONE, | |
192 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST, | |
193 | .reg_desc = { | |
194 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, | |
195 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, | |
196 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, | |
197 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, | |
198 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, | |
199 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, | |
200 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, | |
201 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, | |
202 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
203 | }, | |
204 | }, | |
205 | [OMAP_DSS_CHANNEL_DIGIT] = { | |
206 | .name = "DIGIT", | |
207 | .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, | |
cffa947d | 208 | .framedone_irq = DISPC_IRQ_FRAMEDONETV, |
efa70b3b CM |
209 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, |
210 | .reg_desc = { | |
211 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, | |
212 | [DISPC_MGR_FLD_STNTFT] = { }, | |
213 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, | |
214 | [DISPC_MGR_FLD_TFTDATALINES] = { }, | |
215 | [DISPC_MGR_FLD_STALLMODE] = { }, | |
216 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, | |
217 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, | |
218 | [DISPC_MGR_FLD_CPR] = { }, | |
219 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
220 | }, | |
221 | }, | |
222 | [OMAP_DSS_CHANNEL_LCD2] = { | |
223 | .name = "LCD2", | |
224 | .vsync_irq = DISPC_IRQ_VSYNC2, | |
225 | .framedone_irq = DISPC_IRQ_FRAMEDONE2, | |
226 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, | |
227 | .reg_desc = { | |
228 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, | |
229 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, | |
230 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, | |
231 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, | |
232 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, | |
233 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, | |
234 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, | |
235 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, | |
236 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, | |
237 | }, | |
238 | }, | |
e86d456a CM |
239 | [OMAP_DSS_CHANNEL_LCD3] = { |
240 | .name = "LCD3", | |
241 | .vsync_irq = DISPC_IRQ_VSYNC3, | |
242 | .framedone_irq = DISPC_IRQ_FRAMEDONE3, | |
243 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, | |
244 | .reg_desc = { | |
245 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, | |
246 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, | |
247 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, | |
248 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, | |
249 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, | |
250 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, | |
251 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, | |
252 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, | |
253 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, | |
254 | }, | |
255 | }, | |
efa70b3b CM |
256 | }; |
257 | ||
6e5264b0 AT |
258 | struct color_conv_coef { |
259 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; | |
260 | int full_range; | |
261 | }; | |
262 | ||
65904155 TV |
263 | static unsigned long dispc_fclk_rate(void); |
264 | static unsigned long dispc_core_clk_rate(void); | |
265 | static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); | |
266 | static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); | |
267 | ||
3e8a6ff2 AT |
268 | static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); |
269 | static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); | |
80c39712 | 270 | |
55978cc2 | 271 | static inline void dispc_write_reg(const u16 idx, u32 val) |
80c39712 | 272 | { |
55978cc2 | 273 | __raw_writel(val, dispc.base + idx); |
80c39712 TV |
274 | } |
275 | ||
55978cc2 | 276 | static inline u32 dispc_read_reg(const u16 idx) |
80c39712 | 277 | { |
55978cc2 | 278 | return __raw_readl(dispc.base + idx); |
80c39712 TV |
279 | } |
280 | ||
efa70b3b CM |
281 | static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) |
282 | { | |
5c348ba9 | 283 | const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; |
efa70b3b CM |
284 | return REG_GET(rfld.reg, rfld.high, rfld.low); |
285 | } | |
286 | ||
287 | static void mgr_fld_write(enum omap_channel channel, | |
288 | enum mgr_reg_fields regfld, int val) { | |
5c348ba9 | 289 | const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; |
d49cd155 TV |
290 | const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; |
291 | unsigned long flags; | |
292 | ||
293 | if (need_lock) | |
294 | spin_lock_irqsave(&dispc.control_lock, flags); | |
295 | ||
efa70b3b | 296 | REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); |
d49cd155 TV |
297 | |
298 | if (need_lock) | |
299 | spin_unlock_irqrestore(&dispc.control_lock, flags); | |
efa70b3b CM |
300 | } |
301 | ||
80c39712 | 302 | #define SR(reg) \ |
55978cc2 | 303 | dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) |
80c39712 | 304 | #define RR(reg) \ |
55978cc2 | 305 | dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) |
80c39712 | 306 | |
4fbafaf3 | 307 | static void dispc_save_context(void) |
80c39712 | 308 | { |
c6104b8e | 309 | int i, j; |
80c39712 | 310 | |
4fbafaf3 TV |
311 | DSSDBG("dispc_save_context\n"); |
312 | ||
80c39712 TV |
313 | SR(IRQENABLE); |
314 | SR(CONTROL); | |
315 | SR(CONFIG); | |
80c39712 | 316 | SR(LINE_NUMBER); |
11354dd5 AT |
317 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
318 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 319 | SR(GLOBAL_ALPHA); |
2a205f34 SS |
320 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
321 | SR(CONTROL2); | |
2a205f34 SS |
322 | SR(CONFIG2); |
323 | } | |
e86d456a CM |
324 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
325 | SR(CONTROL3); | |
326 | SR(CONFIG3); | |
327 | } | |
80c39712 | 328 | |
c6104b8e AT |
329 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
330 | SR(DEFAULT_COLOR(i)); | |
331 | SR(TRANS_COLOR(i)); | |
332 | SR(SIZE_MGR(i)); | |
333 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
334 | continue; | |
335 | SR(TIMING_H(i)); | |
336 | SR(TIMING_V(i)); | |
337 | SR(POL_FREQ(i)); | |
338 | SR(DIVISORo(i)); | |
339 | ||
340 | SR(DATA_CYCLE1(i)); | |
341 | SR(DATA_CYCLE2(i)); | |
342 | SR(DATA_CYCLE3(i)); | |
343 | ||
332e9d70 | 344 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
345 | SR(CPR_COEF_R(i)); |
346 | SR(CPR_COEF_G(i)); | |
347 | SR(CPR_COEF_B(i)); | |
332e9d70 | 348 | } |
2a205f34 | 349 | } |
80c39712 | 350 | |
c6104b8e AT |
351 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
352 | SR(OVL_BA0(i)); | |
353 | SR(OVL_BA1(i)); | |
354 | SR(OVL_POSITION(i)); | |
355 | SR(OVL_SIZE(i)); | |
356 | SR(OVL_ATTRIBUTES(i)); | |
357 | SR(OVL_FIFO_THRESHOLD(i)); | |
358 | SR(OVL_ROW_INC(i)); | |
359 | SR(OVL_PIXEL_INC(i)); | |
360 | if (dss_has_feature(FEAT_PRELOAD)) | |
361 | SR(OVL_PRELOAD(i)); | |
362 | if (i == OMAP_DSS_GFX) { | |
363 | SR(OVL_WINDOW_SKIP(i)); | |
364 | SR(OVL_TABLE_BA(i)); | |
365 | continue; | |
366 | } | |
367 | SR(OVL_FIR(i)); | |
368 | SR(OVL_PICTURE_SIZE(i)); | |
369 | SR(OVL_ACCU0(i)); | |
370 | SR(OVL_ACCU1(i)); | |
9b372c2d | 371 | |
c6104b8e AT |
372 | for (j = 0; j < 8; j++) |
373 | SR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 374 | |
c6104b8e AT |
375 | for (j = 0; j < 8; j++) |
376 | SR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 377 | |
c6104b8e AT |
378 | for (j = 0; j < 5; j++) |
379 | SR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 380 | |
c6104b8e AT |
381 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
382 | for (j = 0; j < 8; j++) | |
383 | SR(OVL_FIR_COEF_V(i, j)); | |
384 | } | |
9b372c2d | 385 | |
c6104b8e AT |
386 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
387 | SR(OVL_BA0_UV(i)); | |
388 | SR(OVL_BA1_UV(i)); | |
389 | SR(OVL_FIR2(i)); | |
390 | SR(OVL_ACCU2_0(i)); | |
391 | SR(OVL_ACCU2_1(i)); | |
ab5ca071 | 392 | |
c6104b8e AT |
393 | for (j = 0; j < 8; j++) |
394 | SR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 395 | |
c6104b8e AT |
396 | for (j = 0; j < 8; j++) |
397 | SR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 398 | |
c6104b8e AT |
399 | for (j = 0; j < 8; j++) |
400 | SR(OVL_FIR_COEF_V2(i, j)); | |
401 | } | |
402 | if (dss_has_feature(FEAT_ATTR2)) | |
403 | SR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 404 | } |
0cf35df3 MR |
405 | |
406 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
407 | SR(DIVISOR); | |
49ea86f3 | 408 | |
49ea86f3 TV |
409 | dispc.ctx_valid = true; |
410 | ||
9229b516 | 411 | DSSDBG("context saved\n"); |
80c39712 TV |
412 | } |
413 | ||
4fbafaf3 | 414 | static void dispc_restore_context(void) |
80c39712 | 415 | { |
9229b516 | 416 | int i, j; |
4fbafaf3 TV |
417 | |
418 | DSSDBG("dispc_restore_context\n"); | |
419 | ||
49ea86f3 TV |
420 | if (!dispc.ctx_valid) |
421 | return; | |
422 | ||
75c7d59d | 423 | /*RR(IRQENABLE);*/ |
80c39712 TV |
424 | /*RR(CONTROL);*/ |
425 | RR(CONFIG); | |
80c39712 | 426 | RR(LINE_NUMBER); |
11354dd5 AT |
427 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
428 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 429 | RR(GLOBAL_ALPHA); |
c6104b8e | 430 | if (dss_has_feature(FEAT_MGR_LCD2)) |
2a205f34 | 431 | RR(CONFIG2); |
e86d456a CM |
432 | if (dss_has_feature(FEAT_MGR_LCD3)) |
433 | RR(CONFIG3); | |
80c39712 | 434 | |
c6104b8e AT |
435 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
436 | RR(DEFAULT_COLOR(i)); | |
437 | RR(TRANS_COLOR(i)); | |
438 | RR(SIZE_MGR(i)); | |
439 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
440 | continue; | |
441 | RR(TIMING_H(i)); | |
442 | RR(TIMING_V(i)); | |
443 | RR(POL_FREQ(i)); | |
444 | RR(DIVISORo(i)); | |
445 | ||
446 | RR(DATA_CYCLE1(i)); | |
447 | RR(DATA_CYCLE2(i)); | |
448 | RR(DATA_CYCLE3(i)); | |
2a205f34 | 449 | |
332e9d70 | 450 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
451 | RR(CPR_COEF_R(i)); |
452 | RR(CPR_COEF_G(i)); | |
453 | RR(CPR_COEF_B(i)); | |
332e9d70 | 454 | } |
2a205f34 | 455 | } |
80c39712 | 456 | |
c6104b8e AT |
457 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
458 | RR(OVL_BA0(i)); | |
459 | RR(OVL_BA1(i)); | |
460 | RR(OVL_POSITION(i)); | |
461 | RR(OVL_SIZE(i)); | |
462 | RR(OVL_ATTRIBUTES(i)); | |
463 | RR(OVL_FIFO_THRESHOLD(i)); | |
464 | RR(OVL_ROW_INC(i)); | |
465 | RR(OVL_PIXEL_INC(i)); | |
466 | if (dss_has_feature(FEAT_PRELOAD)) | |
467 | RR(OVL_PRELOAD(i)); | |
468 | if (i == OMAP_DSS_GFX) { | |
469 | RR(OVL_WINDOW_SKIP(i)); | |
470 | RR(OVL_TABLE_BA(i)); | |
471 | continue; | |
472 | } | |
473 | RR(OVL_FIR(i)); | |
474 | RR(OVL_PICTURE_SIZE(i)); | |
475 | RR(OVL_ACCU0(i)); | |
476 | RR(OVL_ACCU1(i)); | |
9b372c2d | 477 | |
c6104b8e AT |
478 | for (j = 0; j < 8; j++) |
479 | RR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 480 | |
c6104b8e AT |
481 | for (j = 0; j < 8; j++) |
482 | RR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 483 | |
c6104b8e AT |
484 | for (j = 0; j < 5; j++) |
485 | RR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 486 | |
c6104b8e AT |
487 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
488 | for (j = 0; j < 8; j++) | |
489 | RR(OVL_FIR_COEF_V(i, j)); | |
490 | } | |
9b372c2d | 491 | |
c6104b8e AT |
492 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
493 | RR(OVL_BA0_UV(i)); | |
494 | RR(OVL_BA1_UV(i)); | |
495 | RR(OVL_FIR2(i)); | |
496 | RR(OVL_ACCU2_0(i)); | |
497 | RR(OVL_ACCU2_1(i)); | |
ab5ca071 | 498 | |
c6104b8e AT |
499 | for (j = 0; j < 8; j++) |
500 | RR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 501 | |
c6104b8e AT |
502 | for (j = 0; j < 8; j++) |
503 | RR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 504 | |
c6104b8e AT |
505 | for (j = 0; j < 8; j++) |
506 | RR(OVL_FIR_COEF_V2(i, j)); | |
507 | } | |
508 | if (dss_has_feature(FEAT_ATTR2)) | |
509 | RR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 510 | } |
80c39712 | 511 | |
0cf35df3 MR |
512 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
513 | RR(DIVISOR); | |
514 | ||
80c39712 TV |
515 | /* enable last, because LCD & DIGIT enable are here */ |
516 | RR(CONTROL); | |
2a205f34 SS |
517 | if (dss_has_feature(FEAT_MGR_LCD2)) |
518 | RR(CONTROL2); | |
e86d456a CM |
519 | if (dss_has_feature(FEAT_MGR_LCD3)) |
520 | RR(CONTROL3); | |
75c7d59d | 521 | /* clear spurious SYNC_LOST_DIGIT interrupts */ |
4e0397cf | 522 | dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); |
75c7d59d VS |
523 | |
524 | /* | |
525 | * enable last so IRQs won't trigger before | |
526 | * the context is fully restored | |
527 | */ | |
528 | RR(IRQENABLE); | |
49ea86f3 TV |
529 | |
530 | DSSDBG("context restored\n"); | |
80c39712 TV |
531 | } |
532 | ||
533 | #undef SR | |
534 | #undef RR | |
535 | ||
4fbafaf3 TV |
536 | int dispc_runtime_get(void) |
537 | { | |
538 | int r; | |
539 | ||
540 | DSSDBG("dispc_runtime_get\n"); | |
541 | ||
542 | r = pm_runtime_get_sync(&dispc.pdev->dev); | |
543 | WARN_ON(r < 0); | |
544 | return r < 0 ? r : 0; | |
545 | } | |
348be69d | 546 | EXPORT_SYMBOL(dispc_runtime_get); |
4fbafaf3 TV |
547 | |
548 | void dispc_runtime_put(void) | |
549 | { | |
550 | int r; | |
551 | ||
552 | DSSDBG("dispc_runtime_put\n"); | |
553 | ||
0eaf9f52 | 554 | r = pm_runtime_put_sync(&dispc.pdev->dev); |
5be3aebd | 555 | WARN_ON(r < 0 && r != -ENOSYS); |
80c39712 | 556 | } |
348be69d | 557 | EXPORT_SYMBOL(dispc_runtime_put); |
80c39712 | 558 | |
3dcec4d6 TV |
559 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) |
560 | { | |
efa70b3b | 561 | return mgr_desc[channel].vsync_irq; |
3dcec4d6 | 562 | } |
348be69d | 563 | EXPORT_SYMBOL(dispc_mgr_get_vsync_irq); |
3dcec4d6 | 564 | |
7d1365c9 TV |
565 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) |
566 | { | |
cffa947d TV |
567 | if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) |
568 | return 0; | |
569 | ||
efa70b3b | 570 | return mgr_desc[channel].framedone_irq; |
7d1365c9 | 571 | } |
348be69d | 572 | EXPORT_SYMBOL(dispc_mgr_get_framedone_irq); |
7d1365c9 | 573 | |
cb699200 TV |
574 | u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) |
575 | { | |
576 | return mgr_desc[channel].sync_lost_irq; | |
577 | } | |
348be69d | 578 | EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq); |
cb699200 | 579 | |
0b23e5b8 AT |
580 | u32 dispc_wb_get_framedone_irq(void) |
581 | { | |
582 | return DISPC_IRQ_FRAMEDONEWB; | |
583 | } | |
584 | ||
26d9dd0d | 585 | bool dispc_mgr_go_busy(enum omap_channel channel) |
80c39712 | 586 | { |
efa70b3b | 587 | return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; |
80c39712 | 588 | } |
348be69d | 589 | EXPORT_SYMBOL(dispc_mgr_go_busy); |
80c39712 | 590 | |
26d9dd0d | 591 | void dispc_mgr_go(enum omap_channel channel) |
80c39712 | 592 | { |
0bcfdba6 | 593 | WARN_ON(!dispc_mgr_is_enabled(channel)); |
3c91ee8c | 594 | WARN_ON(dispc_mgr_go_busy(channel)); |
80c39712 | 595 | |
efa70b3b | 596 | DSSDBG("GO %s\n", mgr_desc[channel].name); |
80c39712 | 597 | |
efa70b3b | 598 | mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); |
80c39712 | 599 | } |
348be69d | 600 | EXPORT_SYMBOL(dispc_mgr_go); |
80c39712 | 601 | |
0b23e5b8 AT |
602 | bool dispc_wb_go_busy(void) |
603 | { | |
604 | return REG_GET(DISPC_CONTROL2, 6, 6) == 1; | |
605 | } | |
606 | ||
607 | void dispc_wb_go(void) | |
608 | { | |
609 | enum omap_plane plane = OMAP_DSS_WB; | |
610 | bool enable, go; | |
611 | ||
612 | enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; | |
613 | ||
614 | if (!enable) | |
615 | return; | |
616 | ||
617 | go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; | |
618 | if (go) { | |
619 | DSSERR("GO bit not down for WB\n"); | |
620 | return; | |
621 | } | |
622 | ||
623 | REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); | |
624 | } | |
625 | ||
f0e5caab | 626 | static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 627 | { |
9b372c2d | 628 | dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); |
80c39712 TV |
629 | } |
630 | ||
f0e5caab | 631 | static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 632 | { |
9b372c2d | 633 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); |
80c39712 TV |
634 | } |
635 | ||
f0e5caab | 636 | static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 637 | { |
9b372c2d | 638 | dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); |
80c39712 TV |
639 | } |
640 | ||
f0e5caab | 641 | static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
642 | { |
643 | BUG_ON(plane == OMAP_DSS_GFX); | |
644 | ||
645 | dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); | |
646 | } | |
647 | ||
f0e5caab TV |
648 | static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, |
649 | u32 value) | |
ab5ca071 AJ |
650 | { |
651 | BUG_ON(plane == OMAP_DSS_GFX); | |
652 | ||
653 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); | |
654 | } | |
655 | ||
f0e5caab | 656 | static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
657 | { |
658 | BUG_ON(plane == OMAP_DSS_GFX); | |
659 | ||
660 | dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); | |
661 | } | |
662 | ||
debd9074 CM |
663 | static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, |
664 | int fir_vinc, int five_taps, | |
665 | enum omap_color_component color_comp) | |
80c39712 | 666 | { |
debd9074 | 667 | const struct dispc_coef *h_coef, *v_coef; |
80c39712 TV |
668 | int i; |
669 | ||
debd9074 CM |
670 | h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); |
671 | v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); | |
80c39712 TV |
672 | |
673 | for (i = 0; i < 8; i++) { | |
674 | u32 h, hv; | |
675 | ||
debd9074 CM |
676 | h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) |
677 | | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) | |
678 | | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) | |
679 | | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); | |
680 | hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) | |
681 | | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) | |
682 | | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) | |
683 | | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); | |
80c39712 | 684 | |
0d66cbb5 | 685 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
f0e5caab TV |
686 | dispc_ovl_write_firh_reg(plane, i, h); |
687 | dispc_ovl_write_firhv_reg(plane, i, hv); | |
0d66cbb5 | 688 | } else { |
f0e5caab TV |
689 | dispc_ovl_write_firh2_reg(plane, i, h); |
690 | dispc_ovl_write_firhv2_reg(plane, i, hv); | |
0d66cbb5 AJ |
691 | } |
692 | ||
80c39712 TV |
693 | } |
694 | ||
66be8f6c GI |
695 | if (five_taps) { |
696 | for (i = 0; i < 8; i++) { | |
697 | u32 v; | |
debd9074 CM |
698 | v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) |
699 | | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); | |
0d66cbb5 | 700 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) |
f0e5caab | 701 | dispc_ovl_write_firv_reg(plane, i, v); |
0d66cbb5 | 702 | else |
f0e5caab | 703 | dispc_ovl_write_firv2_reg(plane, i, v); |
66be8f6c | 704 | } |
80c39712 TV |
705 | } |
706 | } | |
707 | ||
80c39712 | 708 | |
6e5264b0 AT |
709 | static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, |
710 | const struct color_conv_coef *ct) | |
711 | { | |
80c39712 TV |
712 | #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) |
713 | ||
6e5264b0 AT |
714 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); |
715 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); | |
716 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); | |
717 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); | |
718 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); | |
80c39712 | 719 | |
6e5264b0 | 720 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); |
80c39712 TV |
721 | |
722 | #undef CVAL | |
80c39712 TV |
723 | } |
724 | ||
6e5264b0 AT |
725 | static void dispc_setup_color_conv_coef(void) |
726 | { | |
727 | int i; | |
728 | int num_ovl = dss_feat_get_num_ovls(); | |
6e5264b0 | 729 | const struct color_conv_coef ctbl_bt601_5_ovl = { |
7d18bbee | 730 | /* YUV -> RGB */ |
6e5264b0 AT |
731 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, |
732 | }; | |
733 | const struct color_conv_coef ctbl_bt601_5_wb = { | |
7d18bbee TV |
734 | /* RGB -> YUV */ |
735 | 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, | |
6e5264b0 AT |
736 | }; |
737 | ||
738 | for (i = 1; i < num_ovl; i++) | |
739 | dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); | |
740 | ||
20efbc35 TV |
741 | if (dispc.feat->has_writeback) |
742 | dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); | |
6e5264b0 | 743 | } |
80c39712 | 744 | |
f0e5caab | 745 | static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) |
80c39712 | 746 | { |
9b372c2d | 747 | dispc_write_reg(DISPC_OVL_BA0(plane), paddr); |
80c39712 TV |
748 | } |
749 | ||
f0e5caab | 750 | static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) |
80c39712 | 751 | { |
9b372c2d | 752 | dispc_write_reg(DISPC_OVL_BA1(plane), paddr); |
80c39712 TV |
753 | } |
754 | ||
f0e5caab | 755 | static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
756 | { |
757 | dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); | |
758 | } | |
759 | ||
f0e5caab | 760 | static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
761 | { |
762 | dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); | |
763 | } | |
764 | ||
d79db853 AT |
765 | static void dispc_ovl_set_pos(enum omap_plane plane, |
766 | enum omap_overlay_caps caps, int x, int y) | |
80c39712 | 767 | { |
d79db853 AT |
768 | u32 val; |
769 | ||
770 | if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) | |
771 | return; | |
772 | ||
773 | val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); | |
9b372c2d AT |
774 | |
775 | dispc_write_reg(DISPC_OVL_POSITION(plane), val); | |
80c39712 TV |
776 | } |
777 | ||
78b687fc AT |
778 | static void dispc_ovl_set_input_size(enum omap_plane plane, int width, |
779 | int height) | |
80c39712 | 780 | { |
80c39712 | 781 | u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
9b372c2d | 782 | |
36d87d95 | 783 | if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) |
9b372c2d AT |
784 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); |
785 | else | |
786 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
80c39712 TV |
787 | } |
788 | ||
78b687fc AT |
789 | static void dispc_ovl_set_output_size(enum omap_plane plane, int width, |
790 | int height) | |
80c39712 TV |
791 | { |
792 | u32 val; | |
80c39712 TV |
793 | |
794 | BUG_ON(plane == OMAP_DSS_GFX); | |
795 | ||
796 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
9b372c2d | 797 | |
36d87d95 AT |
798 | if (plane == OMAP_DSS_WB) |
799 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
800 | else | |
801 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
80c39712 TV |
802 | } |
803 | ||
5b54ed3e AT |
804 | static void dispc_ovl_set_zorder(enum omap_plane plane, |
805 | enum omap_overlay_caps caps, u8 zorder) | |
54128701 | 806 | { |
5b54ed3e | 807 | if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) |
54128701 AT |
808 | return; |
809 | ||
810 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); | |
811 | } | |
812 | ||
813 | static void dispc_ovl_enable_zorder_planes(void) | |
814 | { | |
815 | int i; | |
816 | ||
817 | if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
818 | return; | |
819 | ||
820 | for (i = 0; i < dss_feat_get_num_ovls(); i++) | |
821 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); | |
822 | } | |
823 | ||
5b54ed3e AT |
824 | static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, |
825 | enum omap_overlay_caps caps, bool enable) | |
fd28a390 | 826 | { |
5b54ed3e | 827 | if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) |
fd28a390 R |
828 | return; |
829 | ||
9b372c2d | 830 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); |
fd28a390 R |
831 | } |
832 | ||
5b54ed3e AT |
833 | static void dispc_ovl_setup_global_alpha(enum omap_plane plane, |
834 | enum omap_overlay_caps caps, u8 global_alpha) | |
80c39712 | 835 | { |
b8c095b4 | 836 | static const unsigned shifts[] = { 0, 8, 16, 24, }; |
fe3cc9d6 TV |
837 | int shift; |
838 | ||
5b54ed3e | 839 | if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) |
fd28a390 | 840 | return; |
a0acb557 | 841 | |
fe3cc9d6 TV |
842 | shift = shifts[plane]; |
843 | REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); | |
80c39712 TV |
844 | } |
845 | ||
f0e5caab | 846 | static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) |
80c39712 | 847 | { |
9b372c2d | 848 | dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); |
80c39712 TV |
849 | } |
850 | ||
f0e5caab | 851 | static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) |
80c39712 | 852 | { |
9b372c2d | 853 | dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); |
80c39712 TV |
854 | } |
855 | ||
f0e5caab | 856 | static void dispc_ovl_set_color_mode(enum omap_plane plane, |
80c39712 TV |
857 | enum omap_color_mode color_mode) |
858 | { | |
859 | u32 m = 0; | |
f20e4220 AJ |
860 | if (plane != OMAP_DSS_GFX) { |
861 | switch (color_mode) { | |
862 | case OMAP_DSS_COLOR_NV12: | |
863 | m = 0x0; break; | |
08f3267e | 864 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 AJ |
865 | m = 0x1; break; |
866 | case OMAP_DSS_COLOR_RGBA16: | |
867 | m = 0x2; break; | |
08f3267e | 868 | case OMAP_DSS_COLOR_RGB12U: |
f20e4220 AJ |
869 | m = 0x4; break; |
870 | case OMAP_DSS_COLOR_ARGB16: | |
871 | m = 0x5; break; | |
872 | case OMAP_DSS_COLOR_RGB16: | |
873 | m = 0x6; break; | |
874 | case OMAP_DSS_COLOR_ARGB16_1555: | |
875 | m = 0x7; break; | |
876 | case OMAP_DSS_COLOR_RGB24U: | |
877 | m = 0x8; break; | |
878 | case OMAP_DSS_COLOR_RGB24P: | |
879 | m = 0x9; break; | |
880 | case OMAP_DSS_COLOR_YUV2: | |
881 | m = 0xa; break; | |
882 | case OMAP_DSS_COLOR_UYVY: | |
883 | m = 0xb; break; | |
884 | case OMAP_DSS_COLOR_ARGB32: | |
885 | m = 0xc; break; | |
886 | case OMAP_DSS_COLOR_RGBA32: | |
887 | m = 0xd; break; | |
888 | case OMAP_DSS_COLOR_RGBX32: | |
889 | m = 0xe; break; | |
890 | case OMAP_DSS_COLOR_XRGB16_1555: | |
891 | m = 0xf; break; | |
892 | default: | |
c6eee968 | 893 | BUG(); return; |
f20e4220 AJ |
894 | } |
895 | } else { | |
896 | switch (color_mode) { | |
897 | case OMAP_DSS_COLOR_CLUT1: | |
898 | m = 0x0; break; | |
899 | case OMAP_DSS_COLOR_CLUT2: | |
900 | m = 0x1; break; | |
901 | case OMAP_DSS_COLOR_CLUT4: | |
902 | m = 0x2; break; | |
903 | case OMAP_DSS_COLOR_CLUT8: | |
904 | m = 0x3; break; | |
905 | case OMAP_DSS_COLOR_RGB12U: | |
906 | m = 0x4; break; | |
907 | case OMAP_DSS_COLOR_ARGB16: | |
908 | m = 0x5; break; | |
909 | case OMAP_DSS_COLOR_RGB16: | |
910 | m = 0x6; break; | |
911 | case OMAP_DSS_COLOR_ARGB16_1555: | |
912 | m = 0x7; break; | |
913 | case OMAP_DSS_COLOR_RGB24U: | |
914 | m = 0x8; break; | |
915 | case OMAP_DSS_COLOR_RGB24P: | |
916 | m = 0x9; break; | |
08f3267e | 917 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 | 918 | m = 0xa; break; |
08f3267e | 919 | case OMAP_DSS_COLOR_RGBA16: |
f20e4220 AJ |
920 | m = 0xb; break; |
921 | case OMAP_DSS_COLOR_ARGB32: | |
922 | m = 0xc; break; | |
923 | case OMAP_DSS_COLOR_RGBA32: | |
924 | m = 0xd; break; | |
925 | case OMAP_DSS_COLOR_RGBX32: | |
926 | m = 0xe; break; | |
927 | case OMAP_DSS_COLOR_XRGB16_1555: | |
928 | m = 0xf; break; | |
929 | default: | |
c6eee968 | 930 | BUG(); return; |
f20e4220 | 931 | } |
80c39712 TV |
932 | } |
933 | ||
9b372c2d | 934 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); |
80c39712 TV |
935 | } |
936 | ||
65e006ff CM |
937 | static void dispc_ovl_configure_burst_type(enum omap_plane plane, |
938 | enum omap_dss_rotation_type rotation_type) | |
939 | { | |
940 | if (dss_has_feature(FEAT_BURST_2D) == 0) | |
941 | return; | |
942 | ||
943 | if (rotation_type == OMAP_DSS_ROT_TILER) | |
944 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); | |
945 | else | |
946 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); | |
947 | } | |
948 | ||
f427984e | 949 | void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) |
80c39712 TV |
950 | { |
951 | int shift; | |
952 | u32 val; | |
2a205f34 | 953 | int chan = 0, chan2 = 0; |
80c39712 TV |
954 | |
955 | switch (plane) { | |
956 | case OMAP_DSS_GFX: | |
957 | shift = 8; | |
958 | break; | |
959 | case OMAP_DSS_VIDEO1: | |
960 | case OMAP_DSS_VIDEO2: | |
b8c095b4 | 961 | case OMAP_DSS_VIDEO3: |
80c39712 TV |
962 | shift = 16; |
963 | break; | |
964 | default: | |
965 | BUG(); | |
966 | return; | |
967 | } | |
968 | ||
9b372c2d | 969 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
2a205f34 SS |
970 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
971 | switch (channel) { | |
972 | case OMAP_DSS_CHANNEL_LCD: | |
973 | chan = 0; | |
974 | chan2 = 0; | |
975 | break; | |
976 | case OMAP_DSS_CHANNEL_DIGIT: | |
977 | chan = 1; | |
978 | chan2 = 0; | |
979 | break; | |
980 | case OMAP_DSS_CHANNEL_LCD2: | |
981 | chan = 0; | |
982 | chan2 = 1; | |
983 | break; | |
e86d456a CM |
984 | case OMAP_DSS_CHANNEL_LCD3: |
985 | if (dss_has_feature(FEAT_MGR_LCD3)) { | |
986 | chan = 0; | |
987 | chan2 = 2; | |
988 | } else { | |
989 | BUG(); | |
990 | return; | |
991 | } | |
992 | break; | |
c2665c41 TV |
993 | case OMAP_DSS_CHANNEL_WB: |
994 | chan = 0; | |
995 | chan2 = 3; | |
996 | break; | |
2a205f34 SS |
997 | default: |
998 | BUG(); | |
c6eee968 | 999 | return; |
2a205f34 SS |
1000 | } |
1001 | ||
1002 | val = FLD_MOD(val, chan, shift, shift); | |
1003 | val = FLD_MOD(val, chan2, 31, 30); | |
1004 | } else { | |
1005 | val = FLD_MOD(val, channel, shift, shift); | |
1006 | } | |
9b372c2d | 1007 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 | 1008 | } |
348be69d | 1009 | EXPORT_SYMBOL(dispc_ovl_set_channel_out); |
80c39712 | 1010 | |
2cc5d1af TV |
1011 | static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) |
1012 | { | |
1013 | int shift; | |
1014 | u32 val; | |
2cc5d1af TV |
1015 | |
1016 | switch (plane) { | |
1017 | case OMAP_DSS_GFX: | |
1018 | shift = 8; | |
1019 | break; | |
1020 | case OMAP_DSS_VIDEO1: | |
1021 | case OMAP_DSS_VIDEO2: | |
1022 | case OMAP_DSS_VIDEO3: | |
1023 | shift = 16; | |
1024 | break; | |
1025 | default: | |
1026 | BUG(); | |
c6eee968 | 1027 | return 0; |
2cc5d1af TV |
1028 | } |
1029 | ||
1030 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
1031 | ||
d7df5ad4 TV |
1032 | if (FLD_GET(val, shift, shift) == 1) |
1033 | return OMAP_DSS_CHANNEL_DIGIT; | |
2cc5d1af | 1034 | |
d7df5ad4 TV |
1035 | if (!dss_has_feature(FEAT_MGR_LCD2)) |
1036 | return OMAP_DSS_CHANNEL_LCD; | |
1037 | ||
1038 | switch (FLD_GET(val, 31, 30)) { | |
1039 | case 0: | |
1040 | default: | |
1041 | return OMAP_DSS_CHANNEL_LCD; | |
1042 | case 1: | |
1043 | return OMAP_DSS_CHANNEL_LCD2; | |
1044 | case 2: | |
1045 | return OMAP_DSS_CHANNEL_LCD3; | |
c2665c41 TV |
1046 | case 3: |
1047 | return OMAP_DSS_CHANNEL_WB; | |
d7df5ad4 | 1048 | } |
2cc5d1af TV |
1049 | } |
1050 | ||
d9ac773c AT |
1051 | void dispc_wb_set_channel_in(enum dss_writeback_channel channel) |
1052 | { | |
1053 | enum omap_plane plane = OMAP_DSS_WB; | |
1054 | ||
1055 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); | |
1056 | } | |
1057 | ||
f0e5caab | 1058 | static void dispc_ovl_set_burst_size(enum omap_plane plane, |
80c39712 TV |
1059 | enum omap_burst_size burst_size) |
1060 | { | |
8bbe09ee | 1061 | static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; |
80c39712 | 1062 | int shift; |
80c39712 | 1063 | |
fe3cc9d6 | 1064 | shift = shifts[plane]; |
5ed8cf5b | 1065 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); |
80c39712 TV |
1066 | } |
1067 | ||
5ed8cf5b TV |
1068 | static void dispc_configure_burst_sizes(void) |
1069 | { | |
1070 | int i; | |
1071 | const int burst_size = BURST_SIZE_X8; | |
1072 | ||
1073 | /* Configure burst size always to maximum size */ | |
392faa0e | 1074 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) |
f0e5caab | 1075 | dispc_ovl_set_burst_size(i, burst_size); |
5b354af9 TV |
1076 | if (dispc.feat->has_writeback) |
1077 | dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); | |
5ed8cf5b TV |
1078 | } |
1079 | ||
83fa2f2e | 1080 | static u32 dispc_ovl_get_burst_size(enum omap_plane plane) |
5ed8cf5b TV |
1081 | { |
1082 | unsigned unit = dss_feat_get_burst_size_unit(); | |
1083 | /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ | |
1084 | return unit * 8; | |
1085 | } | |
1086 | ||
d3862610 M |
1087 | void dispc_enable_gamma_table(bool enable) |
1088 | { | |
1089 | /* | |
1090 | * This is partially implemented to support only disabling of | |
1091 | * the gamma table. | |
1092 | */ | |
1093 | if (enable) { | |
1094 | DSSWARN("Gamma table enabling for TV not yet supported"); | |
1095 | return; | |
1096 | } | |
1097 | ||
1098 | REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); | |
1099 | } | |
1100 | ||
c64dca40 | 1101 | static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) |
3c07cae2 | 1102 | { |
efa70b3b | 1103 | if (channel == OMAP_DSS_CHANNEL_DIGIT) |
3c07cae2 TV |
1104 | return; |
1105 | ||
efa70b3b | 1106 | mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); |
3c07cae2 TV |
1107 | } |
1108 | ||
c64dca40 | 1109 | static void dispc_mgr_set_cpr_coef(enum omap_channel channel, |
a8f3fcd1 | 1110 | const struct omap_dss_cpr_coefs *coefs) |
3c07cae2 TV |
1111 | { |
1112 | u32 coef_r, coef_g, coef_b; | |
1113 | ||
dd88b7a6 | 1114 | if (!dss_mgr_is_lcd(channel)) |
3c07cae2 TV |
1115 | return; |
1116 | ||
1117 | coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | | |
1118 | FLD_VAL(coefs->rb, 9, 0); | |
1119 | coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | | |
1120 | FLD_VAL(coefs->gb, 9, 0); | |
1121 | coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | | |
1122 | FLD_VAL(coefs->bb, 9, 0); | |
1123 | ||
1124 | dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); | |
1125 | dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); | |
1126 | dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); | |
1127 | } | |
1128 | ||
f0e5caab | 1129 | static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) |
80c39712 TV |
1130 | { |
1131 | u32 val; | |
1132 | ||
1133 | BUG_ON(plane == OMAP_DSS_GFX); | |
1134 | ||
9b372c2d | 1135 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1136 | val = FLD_MOD(val, enable, 9, 9); |
9b372c2d | 1137 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
1138 | } |
1139 | ||
d79db853 AT |
1140 | static void dispc_ovl_enable_replication(enum omap_plane plane, |
1141 | enum omap_overlay_caps caps, bool enable) | |
80c39712 | 1142 | { |
b8c095b4 | 1143 | static const unsigned shifts[] = { 5, 10, 10, 10 }; |
fe3cc9d6 | 1144 | int shift; |
80c39712 | 1145 | |
d79db853 AT |
1146 | if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) |
1147 | return; | |
1148 | ||
fe3cc9d6 TV |
1149 | shift = shifts[plane]; |
1150 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); | |
80c39712 TV |
1151 | } |
1152 | ||
8f366162 | 1153 | static void dispc_mgr_set_size(enum omap_channel channel, u16 width, |
e5c09e06 | 1154 | u16 height) |
80c39712 TV |
1155 | { |
1156 | u32 val; | |
80c39712 | 1157 | |
33b89928 AT |
1158 | val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | |
1159 | FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); | |
1160 | ||
8f366162 | 1161 | dispc_write_reg(DISPC_SIZE_MGR(channel), val); |
80c39712 TV |
1162 | } |
1163 | ||
42a6961c | 1164 | static void dispc_init_fifos(void) |
80c39712 | 1165 | { |
80c39712 | 1166 | u32 size; |
42a6961c | 1167 | int fifo; |
a0acb557 | 1168 | u8 start, end; |
5ed8cf5b | 1169 | u32 unit; |
47fc469b | 1170 | int i; |
5ed8cf5b TV |
1171 | |
1172 | unit = dss_feat_get_buffer_size_unit(); | |
80c39712 | 1173 | |
a0acb557 | 1174 | dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); |
80c39712 | 1175 | |
42a6961c TV |
1176 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { |
1177 | size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); | |
5ed8cf5b | 1178 | size *= unit; |
42a6961c TV |
1179 | dispc.fifo_size[fifo] = size; |
1180 | ||
1181 | /* | |
1182 | * By default fifos are mapped directly to overlays, fifo 0 to | |
1183 | * ovl 0, fifo 1 to ovl 1, etc. | |
1184 | */ | |
1185 | dispc.fifo_assignment[fifo] = fifo; | |
80c39712 | 1186 | } |
66a0f9e4 TV |
1187 | |
1188 | /* | |
1189 | * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo | |
1190 | * causes problems with certain use cases, like using the tiler in 2D | |
1191 | * mode. The below hack swaps the fifos of GFX and WB planes, thus | |
1192 | * giving GFX plane a larger fifo. WB but should work fine with a | |
1193 | * smaller fifo. | |
1194 | */ | |
1195 | if (dispc.feat->gfx_fifo_workaround) { | |
1196 | u32 v; | |
1197 | ||
1198 | v = dispc_read_reg(DISPC_GLOBAL_BUFFER); | |
1199 | ||
1200 | v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ | |
1201 | v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ | |
1202 | v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ | |
1203 | v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ | |
1204 | ||
1205 | dispc_write_reg(DISPC_GLOBAL_BUFFER, v); | |
1206 | ||
1207 | dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; | |
1208 | dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; | |
1209 | } | |
47fc469b TV |
1210 | |
1211 | /* | |
1212 | * Setup default fifo thresholds. | |
1213 | */ | |
1214 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) { | |
1215 | u32 low, high; | |
1216 | const bool use_fifomerge = false; | |
1217 | const bool manual_update = false; | |
1218 | ||
1219 | dispc_ovl_compute_fifo_thresholds(i, &low, &high, | |
1220 | use_fifomerge, manual_update); | |
1221 | ||
1222 | dispc_ovl_set_fifo_threshold(i, low, high); | |
1223 | } | |
65e116e1 TV |
1224 | |
1225 | if (dispc.feat->has_writeback) { | |
1226 | u32 low, high; | |
1227 | const bool use_fifomerge = false; | |
1228 | const bool manual_update = false; | |
1229 | ||
1230 | dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high, | |
1231 | use_fifomerge, manual_update); | |
1232 | ||
1233 | dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high); | |
1234 | } | |
80c39712 TV |
1235 | } |
1236 | ||
83fa2f2e | 1237 | static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) |
80c39712 | 1238 | { |
42a6961c TV |
1239 | int fifo; |
1240 | u32 size = 0; | |
1241 | ||
1242 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { | |
1243 | if (dispc.fifo_assignment[fifo] == plane) | |
1244 | size += dispc.fifo_size[fifo]; | |
1245 | } | |
1246 | ||
1247 | return size; | |
80c39712 TV |
1248 | } |
1249 | ||
6f04e1bf | 1250 | void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) |
80c39712 | 1251 | { |
a0acb557 | 1252 | u8 hi_start, hi_end, lo_start, lo_end; |
5ed8cf5b TV |
1253 | u32 unit; |
1254 | ||
1255 | unit = dss_feat_get_buffer_size_unit(); | |
1256 | ||
1257 | WARN_ON(low % unit != 0); | |
1258 | WARN_ON(high % unit != 0); | |
1259 | ||
1260 | low /= unit; | |
1261 | high /= unit; | |
a0acb557 | 1262 | |
9b372c2d AT |
1263 | dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); |
1264 | dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); | |
1265 | ||
3cb5d966 | 1266 | DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", |
80c39712 | 1267 | plane, |
9b372c2d | 1268 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 | 1269 | lo_start, lo_end) * unit, |
9b372c2d | 1270 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 TV |
1271 | hi_start, hi_end) * unit, |
1272 | low * unit, high * unit); | |
80c39712 | 1273 | |
9b372c2d | 1274 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
a0acb557 AT |
1275 | FLD_VAL(high, hi_start, hi_end) | |
1276 | FLD_VAL(low, lo_start, lo_end)); | |
8bc65552 AT |
1277 | |
1278 | /* | |
1279 | * configure the preload to the pipeline's high threhold, if HT it's too | |
1280 | * large for the preload field, set the threshold to the maximum value | |
1281 | * that can be held by the preload register | |
1282 | */ | |
1283 | if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && | |
1284 | plane != OMAP_DSS_WB) | |
1285 | dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); | |
80c39712 TV |
1286 | } |
1287 | ||
1288 | void dispc_enable_fifomerge(bool enable) | |
1289 | { | |
e6b0f884 TV |
1290 | if (!dss_has_feature(FEAT_FIFO_MERGE)) { |
1291 | WARN_ON(enable); | |
1292 | return; | |
1293 | } | |
1294 | ||
80c39712 TV |
1295 | DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); |
1296 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); | |
80c39712 TV |
1297 | } |
1298 | ||
83fa2f2e | 1299 | void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, |
3568f2a4 TV |
1300 | u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, |
1301 | bool manual_update) | |
83fa2f2e TV |
1302 | { |
1303 | /* | |
1304 | * All sizes are in bytes. Both the buffer and burst are made of | |
1305 | * buffer_units, and the fifo thresholds must be buffer_unit aligned. | |
1306 | */ | |
1307 | ||
1308 | unsigned buf_unit = dss_feat_get_buffer_size_unit(); | |
e0e405b9 TV |
1309 | unsigned ovl_fifo_size, total_fifo_size, burst_size; |
1310 | int i; | |
83fa2f2e TV |
1311 | |
1312 | burst_size = dispc_ovl_get_burst_size(plane); | |
e0e405b9 | 1313 | ovl_fifo_size = dispc_ovl_get_fifo_size(plane); |
83fa2f2e | 1314 | |
e0e405b9 TV |
1315 | if (use_fifomerge) { |
1316 | total_fifo_size = 0; | |
392faa0e | 1317 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) |
e0e405b9 TV |
1318 | total_fifo_size += dispc_ovl_get_fifo_size(i); |
1319 | } else { | |
1320 | total_fifo_size = ovl_fifo_size; | |
1321 | } | |
1322 | ||
1323 | /* | |
1324 | * We use the same low threshold for both fifomerge and non-fifomerge | |
1325 | * cases, but for fifomerge we calculate the high threshold using the | |
1326 | * combined fifo size | |
1327 | */ | |
1328 | ||
3568f2a4 | 1329 | if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { |
e0e405b9 TV |
1330 | *fifo_low = ovl_fifo_size - burst_size * 2; |
1331 | *fifo_high = total_fifo_size - burst_size; | |
8bbe09ee AT |
1332 | } else if (plane == OMAP_DSS_WB) { |
1333 | /* | |
1334 | * Most optimal configuration for writeback is to push out data | |
1335 | * to the interconnect the moment writeback pushes enough pixels | |
1336 | * in the FIFO to form a burst | |
1337 | */ | |
1338 | *fifo_low = 0; | |
1339 | *fifo_high = burst_size; | |
e0e405b9 TV |
1340 | } else { |
1341 | *fifo_low = ovl_fifo_size - burst_size; | |
1342 | *fifo_high = total_fifo_size - buf_unit; | |
1343 | } | |
83fa2f2e TV |
1344 | } |
1345 | ||
c64aa3a6 TV |
1346 | static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) |
1347 | { | |
1348 | int bit; | |
1349 | ||
1350 | if (plane == OMAP_DSS_GFX) | |
1351 | bit = 14; | |
1352 | else | |
1353 | bit = 23; | |
1354 | ||
1355 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); | |
1356 | } | |
1357 | ||
1358 | static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, | |
1359 | int low, int high) | |
1360 | { | |
1361 | dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), | |
1362 | FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); | |
1363 | } | |
1364 | ||
1365 | static void dispc_init_mflag(void) | |
1366 | { | |
1367 | int i; | |
1368 | ||
fe59e5cf TV |
1369 | /* |
1370 | * HACK: NV12 color format and MFLAG seem to have problems working | |
1371 | * together: using two displays, and having an NV12 overlay on one of | |
1372 | * the displays will cause underflows/synclosts when MFLAG_CTRL=2. | |
1373 | * Changing MFLAG thresholds and PRELOAD to certain values seem to | |
1374 | * remove the errors, but there doesn't seem to be a clear logic on | |
1375 | * which values work and which not. | |
1376 | * | |
1377 | * As a work-around, set force MFLAG to always on. | |
1378 | */ | |
c64aa3a6 | 1379 | dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, |
fe59e5cf | 1380 | (1 << 0) | /* MFLAG_CTRL = force always on */ |
c64aa3a6 TV |
1381 | (0 << 2)); /* MFLAG_START = disable */ |
1382 | ||
1383 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) { | |
1384 | u32 size = dispc_ovl_get_fifo_size(i); | |
1385 | u32 unit = dss_feat_get_buffer_size_unit(); | |
1386 | u32 low, high; | |
1387 | ||
1388 | dispc_ovl_set_mflag(i, true); | |
1389 | ||
1390 | /* | |
1391 | * Simulation team suggests below thesholds: | |
1392 | * HT = fifosize * 5 / 8; | |
1393 | * LT = fifosize * 4 / 8; | |
1394 | */ | |
1395 | ||
1396 | low = size * 4 / 8 / unit; | |
1397 | high = size * 5 / 8 / unit; | |
1398 | ||
1399 | dispc_ovl_set_mflag_threshold(i, low, high); | |
1400 | } | |
ecb0b366 TV |
1401 | |
1402 | if (dispc.feat->has_writeback) { | |
1403 | u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); | |
1404 | u32 unit = dss_feat_get_buffer_size_unit(); | |
1405 | u32 low, high; | |
1406 | ||
1407 | dispc_ovl_set_mflag(OMAP_DSS_WB, true); | |
1408 | ||
1409 | /* | |
1410 | * Simulation team suggests below thesholds: | |
1411 | * HT = fifosize * 5 / 8; | |
1412 | * LT = fifosize * 4 / 8; | |
1413 | */ | |
1414 | ||
1415 | low = size * 4 / 8 / unit; | |
1416 | high = size * 5 / 8 / unit; | |
1417 | ||
1418 | dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high); | |
1419 | } | |
c64aa3a6 TV |
1420 | } |
1421 | ||
f0e5caab | 1422 | static void dispc_ovl_set_fir(enum omap_plane plane, |
0d66cbb5 AJ |
1423 | int hinc, int vinc, |
1424 | enum omap_color_component color_comp) | |
80c39712 TV |
1425 | { |
1426 | u32 val; | |
80c39712 | 1427 | |
0d66cbb5 AJ |
1428 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
1429 | u8 hinc_start, hinc_end, vinc_start, vinc_end; | |
a0acb557 | 1430 | |
0d66cbb5 AJ |
1431 | dss_feat_get_reg_field(FEAT_REG_FIRHINC, |
1432 | &hinc_start, &hinc_end); | |
1433 | dss_feat_get_reg_field(FEAT_REG_FIRVINC, | |
1434 | &vinc_start, &vinc_end); | |
1435 | val = FLD_VAL(vinc, vinc_start, vinc_end) | | |
1436 | FLD_VAL(hinc, hinc_start, hinc_end); | |
a0acb557 | 1437 | |
0d66cbb5 AJ |
1438 | dispc_write_reg(DISPC_OVL_FIR(plane), val); |
1439 | } else { | |
1440 | val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); | |
1441 | dispc_write_reg(DISPC_OVL_FIR2(plane), val); | |
1442 | } | |
80c39712 TV |
1443 | } |
1444 | ||
f0e5caab | 1445 | static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1446 | { |
1447 | u32 val; | |
87a7484b | 1448 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1449 | |
87a7484b AT |
1450 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1451 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1452 | ||
1453 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1454 | FLD_VAL(haccu, hor_start, hor_end); | |
1455 | ||
9b372c2d | 1456 | dispc_write_reg(DISPC_OVL_ACCU0(plane), val); |
80c39712 TV |
1457 | } |
1458 | ||
f0e5caab | 1459 | static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1460 | { |
1461 | u32 val; | |
87a7484b | 1462 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1463 | |
87a7484b AT |
1464 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1465 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1466 | ||
1467 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1468 | FLD_VAL(haccu, hor_start, hor_end); | |
1469 | ||
9b372c2d | 1470 | dispc_write_reg(DISPC_OVL_ACCU1(plane), val); |
80c39712 TV |
1471 | } |
1472 | ||
f0e5caab TV |
1473 | static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, |
1474 | int vaccu) | |
ab5ca071 AJ |
1475 | { |
1476 | u32 val; | |
1477 | ||
1478 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1479 | dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); | |
1480 | } | |
1481 | ||
f0e5caab TV |
1482 | static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, |
1483 | int vaccu) | |
ab5ca071 AJ |
1484 | { |
1485 | u32 val; | |
1486 | ||
1487 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1488 | dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); | |
1489 | } | |
80c39712 | 1490 | |
f0e5caab | 1491 | static void dispc_ovl_set_scale_param(enum omap_plane plane, |
80c39712 TV |
1492 | u16 orig_width, u16 orig_height, |
1493 | u16 out_width, u16 out_height, | |
0d66cbb5 AJ |
1494 | bool five_taps, u8 rotation, |
1495 | enum omap_color_component color_comp) | |
80c39712 | 1496 | { |
0d66cbb5 | 1497 | int fir_hinc, fir_vinc; |
80c39712 | 1498 | |
ed14a3ce AJ |
1499 | fir_hinc = 1024 * orig_width / out_width; |
1500 | fir_vinc = 1024 * orig_height / out_height; | |
80c39712 | 1501 | |
debd9074 CM |
1502 | dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, |
1503 | color_comp); | |
f0e5caab | 1504 | dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); |
0d66cbb5 AJ |
1505 | } |
1506 | ||
05dd0f53 CM |
1507 | static void dispc_ovl_set_accu_uv(enum omap_plane plane, |
1508 | u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, | |
1509 | bool ilace, enum omap_color_mode color_mode, u8 rotation) | |
1510 | { | |
1511 | int h_accu2_0, h_accu2_1; | |
1512 | int v_accu2_0, v_accu2_1; | |
1513 | int chroma_hinc, chroma_vinc; | |
1514 | int idx; | |
1515 | ||
1516 | struct accu { | |
1517 | s8 h0_m, h0_n; | |
1518 | s8 h1_m, h1_n; | |
1519 | s8 v0_m, v0_n; | |
1520 | s8 v1_m, v1_n; | |
1521 | }; | |
1522 | ||
1523 | const struct accu *accu_table; | |
1524 | const struct accu *accu_val; | |
1525 | ||
1526 | static const struct accu accu_nv12[4] = { | |
1527 | { 0, 1, 0, 1 , -1, 2, 0, 1 }, | |
1528 | { 1, 2, -3, 4 , 0, 1, 0, 1 }, | |
1529 | { -1, 1, 0, 1 , -1, 2, 0, 1 }, | |
1530 | { -1, 2, -1, 2 , -1, 1, 0, 1 }, | |
1531 | }; | |
1532 | ||
1533 | static const struct accu accu_nv12_ilace[4] = { | |
1534 | { 0, 1, 0, 1 , -3, 4, -1, 4 }, | |
1535 | { -1, 4, -3, 4 , 0, 1, 0, 1 }, | |
1536 | { -1, 1, 0, 1 , -1, 4, -3, 4 }, | |
1537 | { -3, 4, -3, 4 , -1, 1, 0, 1 }, | |
1538 | }; | |
1539 | ||
1540 | static const struct accu accu_yuv[4] = { | |
1541 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1542 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1543 | { -1, 1, 0, 1, 0, 1, 0, 1 }, | |
1544 | { 0, 1, 0, 1, -1, 1, 0, 1 }, | |
1545 | }; | |
1546 | ||
1547 | switch (rotation) { | |
1548 | case OMAP_DSS_ROT_0: | |
1549 | idx = 0; | |
1550 | break; | |
1551 | case OMAP_DSS_ROT_90: | |
1552 | idx = 1; | |
1553 | break; | |
1554 | case OMAP_DSS_ROT_180: | |
1555 | idx = 2; | |
1556 | break; | |
1557 | case OMAP_DSS_ROT_270: | |
1558 | idx = 3; | |
1559 | break; | |
1560 | default: | |
1561 | BUG(); | |
c6eee968 | 1562 | return; |
05dd0f53 CM |
1563 | } |
1564 | ||
1565 | switch (color_mode) { | |
1566 | case OMAP_DSS_COLOR_NV12: | |
1567 | if (ilace) | |
1568 | accu_table = accu_nv12_ilace; | |
1569 | else | |
1570 | accu_table = accu_nv12; | |
1571 | break; | |
1572 | case OMAP_DSS_COLOR_YUV2: | |
1573 | case OMAP_DSS_COLOR_UYVY: | |
1574 | accu_table = accu_yuv; | |
1575 | break; | |
1576 | default: | |
1577 | BUG(); | |
c6eee968 | 1578 | return; |
05dd0f53 CM |
1579 | } |
1580 | ||
1581 | accu_val = &accu_table[idx]; | |
1582 | ||
1583 | chroma_hinc = 1024 * orig_width / out_width; | |
1584 | chroma_vinc = 1024 * orig_height / out_height; | |
1585 | ||
1586 | h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; | |
1587 | h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; | |
1588 | v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; | |
1589 | v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; | |
1590 | ||
1591 | dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); | |
1592 | dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); | |
1593 | } | |
1594 | ||
f0e5caab | 1595 | static void dispc_ovl_set_scaling_common(enum omap_plane plane, |
0d66cbb5 AJ |
1596 | u16 orig_width, u16 orig_height, |
1597 | u16 out_width, u16 out_height, | |
1598 | bool ilace, bool five_taps, | |
1599 | bool fieldmode, enum omap_color_mode color_mode, | |
1600 | u8 rotation) | |
1601 | { | |
1602 | int accu0 = 0; | |
1603 | int accu1 = 0; | |
1604 | u32 l; | |
80c39712 | 1605 | |
f0e5caab | 1606 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1607 | out_width, out_height, five_taps, |
1608 | rotation, DISPC_COLOR_COMPONENT_RGB_Y); | |
9b372c2d | 1609 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1610 | |
87a7484b AT |
1611 | /* RESIZEENABLE and VERTICALTAPS */ |
1612 | l &= ~((0x3 << 5) | (0x1 << 21)); | |
ed14a3ce AJ |
1613 | l |= (orig_width != out_width) ? (1 << 5) : 0; |
1614 | l |= (orig_height != out_height) ? (1 << 6) : 0; | |
87a7484b | 1615 | l |= five_taps ? (1 << 21) : 0; |
80c39712 | 1616 | |
87a7484b AT |
1617 | /* VRESIZECONF and HRESIZECONF */ |
1618 | if (dss_has_feature(FEAT_RESIZECONF)) { | |
1619 | l &= ~(0x3 << 7); | |
0d66cbb5 AJ |
1620 | l |= (orig_width <= out_width) ? 0 : (1 << 7); |
1621 | l |= (orig_height <= out_height) ? 0 : (1 << 8); | |
87a7484b | 1622 | } |
80c39712 | 1623 | |
87a7484b AT |
1624 | /* LINEBUFFERSPLIT */ |
1625 | if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { | |
1626 | l &= ~(0x1 << 22); | |
1627 | l |= five_taps ? (1 << 22) : 0; | |
1628 | } | |
80c39712 | 1629 | |
9b372c2d | 1630 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
80c39712 TV |
1631 | |
1632 | /* | |
1633 | * field 0 = even field = bottom field | |
1634 | * field 1 = odd field = top field | |
1635 | */ | |
1636 | if (ilace && !fieldmode) { | |
1637 | accu1 = 0; | |
0d66cbb5 | 1638 | accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; |
80c39712 TV |
1639 | if (accu0 >= 1024/2) { |
1640 | accu1 = 1024/2; | |
1641 | accu0 -= accu1; | |
1642 | } | |
1643 | } | |
1644 | ||
f0e5caab TV |
1645 | dispc_ovl_set_vid_accu0(plane, 0, accu0); |
1646 | dispc_ovl_set_vid_accu1(plane, 0, accu1); | |
80c39712 TV |
1647 | } |
1648 | ||
f0e5caab | 1649 | static void dispc_ovl_set_scaling_uv(enum omap_plane plane, |
0d66cbb5 AJ |
1650 | u16 orig_width, u16 orig_height, |
1651 | u16 out_width, u16 out_height, | |
1652 | bool ilace, bool five_taps, | |
1653 | bool fieldmode, enum omap_color_mode color_mode, | |
1654 | u8 rotation) | |
1655 | { | |
1656 | int scale_x = out_width != orig_width; | |
1657 | int scale_y = out_height != orig_height; | |
f92afae2 | 1658 | bool chroma_upscale = plane != OMAP_DSS_WB ? true : false; |
0d66cbb5 AJ |
1659 | |
1660 | if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) | |
1661 | return; | |
1662 | if ((color_mode != OMAP_DSS_COLOR_YUV2 && | |
1663 | color_mode != OMAP_DSS_COLOR_UYVY && | |
1664 | color_mode != OMAP_DSS_COLOR_NV12)) { | |
1665 | /* reset chroma resampling for RGB formats */ | |
2a5561b1 AT |
1666 | if (plane != OMAP_DSS_WB) |
1667 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); | |
0d66cbb5 AJ |
1668 | return; |
1669 | } | |
36377357 TV |
1670 | |
1671 | dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, | |
1672 | out_height, ilace, color_mode, rotation); | |
1673 | ||
0d66cbb5 AJ |
1674 | switch (color_mode) { |
1675 | case OMAP_DSS_COLOR_NV12: | |
20fbb50b AT |
1676 | if (chroma_upscale) { |
1677 | /* UV is subsampled by 2 horizontally and vertically */ | |
1678 | orig_height >>= 1; | |
1679 | orig_width >>= 1; | |
1680 | } else { | |
1681 | /* UV is downsampled by 2 horizontally and vertically */ | |
1682 | orig_height <<= 1; | |
1683 | orig_width <<= 1; | |
1684 | } | |
1685 | ||
0d66cbb5 AJ |
1686 | break; |
1687 | case OMAP_DSS_COLOR_YUV2: | |
1688 | case OMAP_DSS_COLOR_UYVY: | |
20fbb50b | 1689 | /* For YUV422 with 90/270 rotation, we don't upsample chroma */ |
0d66cbb5 | 1690 | if (rotation == OMAP_DSS_ROT_0 || |
20fbb50b AT |
1691 | rotation == OMAP_DSS_ROT_180) { |
1692 | if (chroma_upscale) | |
1693 | /* UV is subsampled by 2 horizontally */ | |
1694 | orig_width >>= 1; | |
1695 | else | |
1696 | /* UV is downsampled by 2 horizontally */ | |
1697 | orig_width <<= 1; | |
1698 | } | |
1699 | ||
0d66cbb5 AJ |
1700 | /* must use FIR for YUV422 if rotated */ |
1701 | if (rotation != OMAP_DSS_ROT_0) | |
1702 | scale_x = scale_y = true; | |
20fbb50b | 1703 | |
0d66cbb5 AJ |
1704 | break; |
1705 | default: | |
1706 | BUG(); | |
c6eee968 | 1707 | return; |
0d66cbb5 AJ |
1708 | } |
1709 | ||
1710 | if (out_width != orig_width) | |
1711 | scale_x = true; | |
1712 | if (out_height != orig_height) | |
1713 | scale_y = true; | |
1714 | ||
f0e5caab | 1715 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1716 | out_width, out_height, five_taps, |
1717 | rotation, DISPC_COLOR_COMPONENT_UV); | |
1718 | ||
2a5561b1 AT |
1719 | if (plane != OMAP_DSS_WB) |
1720 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), | |
1721 | (scale_x || scale_y) ? 1 : 0, 8, 8); | |
1722 | ||
0d66cbb5 AJ |
1723 | /* set H scaling */ |
1724 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); | |
1725 | /* set V scaling */ | |
1726 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); | |
0d66cbb5 AJ |
1727 | } |
1728 | ||
f0e5caab | 1729 | static void dispc_ovl_set_scaling(enum omap_plane plane, |
0d66cbb5 AJ |
1730 | u16 orig_width, u16 orig_height, |
1731 | u16 out_width, u16 out_height, | |
1732 | bool ilace, bool five_taps, | |
1733 | bool fieldmode, enum omap_color_mode color_mode, | |
1734 | u8 rotation) | |
1735 | { | |
1736 | BUG_ON(plane == OMAP_DSS_GFX); | |
1737 | ||
f0e5caab | 1738 | dispc_ovl_set_scaling_common(plane, |
0d66cbb5 AJ |
1739 | orig_width, orig_height, |
1740 | out_width, out_height, | |
1741 | ilace, five_taps, | |
1742 | fieldmode, color_mode, | |
1743 | rotation); | |
1744 | ||
f0e5caab | 1745 | dispc_ovl_set_scaling_uv(plane, |
0d66cbb5 AJ |
1746 | orig_width, orig_height, |
1747 | out_width, out_height, | |
1748 | ilace, five_taps, | |
1749 | fieldmode, color_mode, | |
1750 | rotation); | |
1751 | } | |
1752 | ||
f0e5caab | 1753 | static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, |
c35eeb2e | 1754 | enum omap_dss_rotation_type rotation_type, |
80c39712 TV |
1755 | bool mirroring, enum omap_color_mode color_mode) |
1756 | { | |
87a7484b AT |
1757 | bool row_repeat = false; |
1758 | int vidrot = 0; | |
1759 | ||
80c39712 TV |
1760 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1761 | color_mode == OMAP_DSS_COLOR_UYVY) { | |
80c39712 TV |
1762 | |
1763 | if (mirroring) { | |
1764 | switch (rotation) { | |
1765 | case OMAP_DSS_ROT_0: | |
1766 | vidrot = 2; | |
1767 | break; | |
1768 | case OMAP_DSS_ROT_90: | |
1769 | vidrot = 1; | |
1770 | break; | |
1771 | case OMAP_DSS_ROT_180: | |
1772 | vidrot = 0; | |
1773 | break; | |
1774 | case OMAP_DSS_ROT_270: | |
1775 | vidrot = 3; | |
1776 | break; | |
1777 | } | |
1778 | } else { | |
1779 | switch (rotation) { | |
1780 | case OMAP_DSS_ROT_0: | |
1781 | vidrot = 0; | |
1782 | break; | |
1783 | case OMAP_DSS_ROT_90: | |
1784 | vidrot = 1; | |
1785 | break; | |
1786 | case OMAP_DSS_ROT_180: | |
1787 | vidrot = 2; | |
1788 | break; | |
1789 | case OMAP_DSS_ROT_270: | |
1790 | vidrot = 3; | |
1791 | break; | |
1792 | } | |
1793 | } | |
1794 | ||
80c39712 | 1795 | if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) |
87a7484b | 1796 | row_repeat = true; |
80c39712 | 1797 | else |
87a7484b | 1798 | row_repeat = false; |
80c39712 | 1799 | } |
87a7484b | 1800 | |
3397cc6a TV |
1801 | /* |
1802 | * OMAP4/5 Errata i631: | |
1803 | * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra | |
1804 | * rows beyond the framebuffer, which may cause OCP error. | |
1805 | */ | |
1806 | if (color_mode == OMAP_DSS_COLOR_NV12 && | |
1807 | rotation_type != OMAP_DSS_ROT_TILER) | |
1808 | vidrot = 1; | |
1809 | ||
9b372c2d | 1810 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
87a7484b | 1811 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
9b372c2d AT |
1812 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
1813 | row_repeat ? 1 : 0, 18, 18); | |
c35eeb2e AT |
1814 | |
1815 | if (color_mode == OMAP_DSS_COLOR_NV12) { | |
1816 | bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) && | |
1817 | (rotation == OMAP_DSS_ROT_0 || | |
1818 | rotation == OMAP_DSS_ROT_180); | |
1819 | /* DOUBLESTRIDE */ | |
1820 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); | |
1821 | } | |
1822 | ||
80c39712 TV |
1823 | } |
1824 | ||
1825 | static int color_mode_to_bpp(enum omap_color_mode color_mode) | |
1826 | { | |
1827 | switch (color_mode) { | |
1828 | case OMAP_DSS_COLOR_CLUT1: | |
1829 | return 1; | |
1830 | case OMAP_DSS_COLOR_CLUT2: | |
1831 | return 2; | |
1832 | case OMAP_DSS_COLOR_CLUT4: | |
1833 | return 4; | |
1834 | case OMAP_DSS_COLOR_CLUT8: | |
f20e4220 | 1835 | case OMAP_DSS_COLOR_NV12: |
80c39712 TV |
1836 | return 8; |
1837 | case OMAP_DSS_COLOR_RGB12U: | |
1838 | case OMAP_DSS_COLOR_RGB16: | |
1839 | case OMAP_DSS_COLOR_ARGB16: | |
1840 | case OMAP_DSS_COLOR_YUV2: | |
1841 | case OMAP_DSS_COLOR_UYVY: | |
f20e4220 AJ |
1842 | case OMAP_DSS_COLOR_RGBA16: |
1843 | case OMAP_DSS_COLOR_RGBX16: | |
1844 | case OMAP_DSS_COLOR_ARGB16_1555: | |
1845 | case OMAP_DSS_COLOR_XRGB16_1555: | |
80c39712 TV |
1846 | return 16; |
1847 | case OMAP_DSS_COLOR_RGB24P: | |
1848 | return 24; | |
1849 | case OMAP_DSS_COLOR_RGB24U: | |
1850 | case OMAP_DSS_COLOR_ARGB32: | |
1851 | case OMAP_DSS_COLOR_RGBA32: | |
1852 | case OMAP_DSS_COLOR_RGBX32: | |
1853 | return 32; | |
1854 | default: | |
1855 | BUG(); | |
c6eee968 | 1856 | return 0; |
80c39712 TV |
1857 | } |
1858 | } | |
1859 | ||
1860 | static s32 pixinc(int pixels, u8 ps) | |
1861 | { | |
1862 | if (pixels == 1) | |
1863 | return 1; | |
1864 | else if (pixels > 1) | |
1865 | return 1 + (pixels - 1) * ps; | |
1866 | else if (pixels < 0) | |
1867 | return 1 - (-pixels + 1) * ps; | |
1868 | else | |
1869 | BUG(); | |
c6eee968 | 1870 | return 0; |
80c39712 TV |
1871 | } |
1872 | ||
1873 | static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, | |
1874 | u16 screen_width, | |
1875 | u16 width, u16 height, | |
1876 | enum omap_color_mode color_mode, bool fieldmode, | |
1877 | unsigned int field_offset, | |
1878 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1879 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1880 | { |
1881 | u8 ps; | |
1882 | ||
1883 | /* FIXME CLUT formats */ | |
1884 | switch (color_mode) { | |
1885 | case OMAP_DSS_COLOR_CLUT1: | |
1886 | case OMAP_DSS_COLOR_CLUT2: | |
1887 | case OMAP_DSS_COLOR_CLUT4: | |
1888 | case OMAP_DSS_COLOR_CLUT8: | |
1889 | BUG(); | |
1890 | return; | |
1891 | case OMAP_DSS_COLOR_YUV2: | |
1892 | case OMAP_DSS_COLOR_UYVY: | |
1893 | ps = 4; | |
1894 | break; | |
1895 | default: | |
1896 | ps = color_mode_to_bpp(color_mode) / 8; | |
1897 | break; | |
1898 | } | |
1899 | ||
1900 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1901 | width, height); | |
1902 | ||
1903 | /* | |
1904 | * field 0 = even field = bottom field | |
1905 | * field 1 = odd field = top field | |
1906 | */ | |
1907 | switch (rotation + mirror * 4) { | |
1908 | case OMAP_DSS_ROT_0: | |
1909 | case OMAP_DSS_ROT_180: | |
1910 | /* | |
1911 | * If the pixel format is YUV or UYVY divide the width | |
1912 | * of the image by 2 for 0 and 180 degree rotation. | |
1913 | */ | |
1914 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1915 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1916 | width = width >> 1; | |
1917 | case OMAP_DSS_ROT_90: | |
1918 | case OMAP_DSS_ROT_270: | |
1919 | *offset1 = 0; | |
1920 | if (field_offset) | |
1921 | *offset0 = field_offset * screen_width * ps; | |
1922 | else | |
1923 | *offset0 = 0; | |
1924 | ||
aed74b55 CM |
1925 | *row_inc = pixinc(1 + |
1926 | (y_predecim * screen_width - x_predecim * width) + | |
1927 | (fieldmode ? screen_width : 0), ps); | |
1928 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1929 | break; |
1930 | ||
1931 | case OMAP_DSS_ROT_0 + 4: | |
1932 | case OMAP_DSS_ROT_180 + 4: | |
1933 | /* If the pixel format is YUV or UYVY divide the width | |
1934 | * of the image by 2 for 0 degree and 180 degree | |
1935 | */ | |
1936 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1937 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1938 | width = width >> 1; | |
1939 | case OMAP_DSS_ROT_90 + 4: | |
1940 | case OMAP_DSS_ROT_270 + 4: | |
1941 | *offset1 = 0; | |
1942 | if (field_offset) | |
1943 | *offset0 = field_offset * screen_width * ps; | |
1944 | else | |
1945 | *offset0 = 0; | |
aed74b55 CM |
1946 | *row_inc = pixinc(1 - |
1947 | (y_predecim * screen_width + x_predecim * width) - | |
1948 | (fieldmode ? screen_width : 0), ps); | |
1949 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1950 | break; |
1951 | ||
1952 | default: | |
1953 | BUG(); | |
c6eee968 | 1954 | return; |
80c39712 TV |
1955 | } |
1956 | } | |
1957 | ||
1958 | static void calc_dma_rotation_offset(u8 rotation, bool mirror, | |
1959 | u16 screen_width, | |
1960 | u16 width, u16 height, | |
1961 | enum omap_color_mode color_mode, bool fieldmode, | |
1962 | unsigned int field_offset, | |
1963 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1964 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1965 | { |
1966 | u8 ps; | |
1967 | u16 fbw, fbh; | |
1968 | ||
1969 | /* FIXME CLUT formats */ | |
1970 | switch (color_mode) { | |
1971 | case OMAP_DSS_COLOR_CLUT1: | |
1972 | case OMAP_DSS_COLOR_CLUT2: | |
1973 | case OMAP_DSS_COLOR_CLUT4: | |
1974 | case OMAP_DSS_COLOR_CLUT8: | |
1975 | BUG(); | |
1976 | return; | |
1977 | default: | |
1978 | ps = color_mode_to_bpp(color_mode) / 8; | |
1979 | break; | |
1980 | } | |
1981 | ||
1982 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1983 | width, height); | |
1984 | ||
1985 | /* width & height are overlay sizes, convert to fb sizes */ | |
1986 | ||
1987 | if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { | |
1988 | fbw = width; | |
1989 | fbh = height; | |
1990 | } else { | |
1991 | fbw = height; | |
1992 | fbh = width; | |
1993 | } | |
1994 | ||
1995 | /* | |
1996 | * field 0 = even field = bottom field | |
1997 | * field 1 = odd field = top field | |
1998 | */ | |
1999 | switch (rotation + mirror * 4) { | |
2000 | case OMAP_DSS_ROT_0: | |
2001 | *offset1 = 0; | |
2002 | if (field_offset) | |
2003 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
2004 | else | |
2005 | *offset0 = *offset1; | |
aed74b55 CM |
2006 | *row_inc = pixinc(1 + |
2007 | (y_predecim * screen_width - fbw * x_predecim) + | |
2008 | (fieldmode ? screen_width : 0), ps); | |
2009 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
2010 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2011 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
2012 | else | |
2013 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
2014 | break; |
2015 | case OMAP_DSS_ROT_90: | |
2016 | *offset1 = screen_width * (fbh - 1) * ps; | |
2017 | if (field_offset) | |
2018 | *offset0 = *offset1 + field_offset * ps; | |
2019 | else | |
2020 | *offset0 = *offset1; | |
aed74b55 CM |
2021 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + |
2022 | y_predecim + (fieldmode ? 1 : 0), ps); | |
2023 | *pix_inc = pixinc(-x_predecim * screen_width, ps); | |
80c39712 TV |
2024 | break; |
2025 | case OMAP_DSS_ROT_180: | |
2026 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
2027 | if (field_offset) | |
2028 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
2029 | else | |
2030 | *offset0 = *offset1; | |
2031 | *row_inc = pixinc(-1 - | |
aed74b55 CM |
2032 | (y_predecim * screen_width - fbw * x_predecim) - |
2033 | (fieldmode ? screen_width : 0), ps); | |
2034 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
2035 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2036 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
2037 | else | |
2038 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
2039 | break; |
2040 | case OMAP_DSS_ROT_270: | |
2041 | *offset1 = (fbw - 1) * ps; | |
2042 | if (field_offset) | |
2043 | *offset0 = *offset1 - field_offset * ps; | |
2044 | else | |
2045 | *offset0 = *offset1; | |
aed74b55 CM |
2046 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - |
2047 | y_predecim - (fieldmode ? 1 : 0), ps); | |
2048 | *pix_inc = pixinc(x_predecim * screen_width, ps); | |
80c39712 TV |
2049 | break; |
2050 | ||
2051 | /* mirroring */ | |
2052 | case OMAP_DSS_ROT_0 + 4: | |
2053 | *offset1 = (fbw - 1) * ps; | |
2054 | if (field_offset) | |
2055 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
2056 | else | |
2057 | *offset0 = *offset1; | |
aed74b55 | 2058 | *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + |
80c39712 TV |
2059 | (fieldmode ? screen_width : 0), |
2060 | ps); | |
aed74b55 CM |
2061 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2062 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2063 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
2064 | else | |
2065 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
2066 | break; |
2067 | ||
2068 | case OMAP_DSS_ROT_90 + 4: | |
2069 | *offset1 = 0; | |
2070 | if (field_offset) | |
2071 | *offset0 = *offset1 + field_offset * ps; | |
2072 | else | |
2073 | *offset0 = *offset1; | |
aed74b55 CM |
2074 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + |
2075 | y_predecim + (fieldmode ? 1 : 0), | |
80c39712 | 2076 | ps); |
aed74b55 | 2077 | *pix_inc = pixinc(x_predecim * screen_width, ps); |
80c39712 TV |
2078 | break; |
2079 | ||
2080 | case OMAP_DSS_ROT_180 + 4: | |
2081 | *offset1 = screen_width * (fbh - 1) * ps; | |
2082 | if (field_offset) | |
2083 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
2084 | else | |
2085 | *offset0 = *offset1; | |
aed74b55 | 2086 | *row_inc = pixinc(1 - y_predecim * screen_width * 2 - |
80c39712 TV |
2087 | (fieldmode ? screen_width : 0), |
2088 | ps); | |
aed74b55 CM |
2089 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2090 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2091 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
2092 | else | |
2093 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
2094 | break; |
2095 | ||
2096 | case OMAP_DSS_ROT_270 + 4: | |
2097 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
2098 | if (field_offset) | |
2099 | *offset0 = *offset1 - field_offset * ps; | |
2100 | else | |
2101 | *offset0 = *offset1; | |
aed74b55 CM |
2102 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - |
2103 | y_predecim - (fieldmode ? 1 : 0), | |
80c39712 | 2104 | ps); |
aed74b55 | 2105 | *pix_inc = pixinc(-x_predecim * screen_width, ps); |
80c39712 TV |
2106 | break; |
2107 | ||
2108 | default: | |
2109 | BUG(); | |
c6eee968 | 2110 | return; |
80c39712 TV |
2111 | } |
2112 | } | |
2113 | ||
65e006ff CM |
2114 | static void calc_tiler_rotation_offset(u16 screen_width, u16 width, |
2115 | enum omap_color_mode color_mode, bool fieldmode, | |
2116 | unsigned int field_offset, unsigned *offset0, unsigned *offset1, | |
2117 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) | |
2118 | { | |
2119 | u8 ps; | |
2120 | ||
2121 | switch (color_mode) { | |
2122 | case OMAP_DSS_COLOR_CLUT1: | |
2123 | case OMAP_DSS_COLOR_CLUT2: | |
2124 | case OMAP_DSS_COLOR_CLUT4: | |
2125 | case OMAP_DSS_COLOR_CLUT8: | |
2126 | BUG(); | |
2127 | return; | |
2128 | default: | |
2129 | ps = color_mode_to_bpp(color_mode) / 8; | |
2130 | break; | |
2131 | } | |
2132 | ||
2133 | DSSDBG("scrw %d, width %d\n", screen_width, width); | |
2134 | ||
2135 | /* | |
2136 | * field 0 = even field = bottom field | |
2137 | * field 1 = odd field = top field | |
2138 | */ | |
2139 | *offset1 = 0; | |
2140 | if (field_offset) | |
2141 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
2142 | else | |
2143 | *offset0 = *offset1; | |
2144 | *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + | |
2145 | (fieldmode ? screen_width : 0), ps); | |
2146 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
2147 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2148 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
2149 | else | |
2150 | *pix_inc = pixinc(x_predecim, ps); | |
2151 | } | |
2152 | ||
7faa9233 CM |
2153 | /* |
2154 | * This function is used to avoid synclosts in OMAP3, because of some | |
2155 | * undocumented horizontal position and timing related limitations. | |
2156 | */ | |
465ec13f | 2157 | static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, |
81ab95b7 | 2158 | const struct omap_video_timings *t, u16 pos_x, |
e4998634 ID |
2159 | u16 width, u16 height, u16 out_width, u16 out_height, |
2160 | bool five_taps) | |
7faa9233 | 2161 | { |
230edc03 | 2162 | const int ds = DIV_ROUND_UP(height, out_height); |
3e8a6ff2 | 2163 | unsigned long nonactive; |
7faa9233 CM |
2164 | static const u8 limits[3] = { 8, 10, 20 }; |
2165 | u64 val, blank; | |
2166 | int i; | |
2167 | ||
81ab95b7 | 2168 | nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; |
7faa9233 CM |
2169 | |
2170 | i = 0; | |
2171 | if (out_height < height) | |
2172 | i++; | |
2173 | if (out_width < width) | |
2174 | i++; | |
81ab95b7 | 2175 | blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); |
7faa9233 CM |
2176 | DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); |
2177 | if (blank <= limits[i]) | |
2178 | return -EINVAL; | |
2179 | ||
e4998634 ID |
2180 | /* FIXME add checks for 3-tap filter once the limitations are known */ |
2181 | if (!five_taps) | |
2182 | return 0; | |
2183 | ||
7faa9233 CM |
2184 | /* |
2185 | * Pixel data should be prepared before visible display point starts. | |
2186 | * So, atleast DS-2 lines must have already been fetched by DISPC | |
2187 | * during nonactive - pos_x period. | |
2188 | */ | |
2189 | val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); | |
2190 | DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", | |
230edc03 TV |
2191 | val, max(0, ds - 2) * width); |
2192 | if (val < max(0, ds - 2) * width) | |
7faa9233 CM |
2193 | return -EINVAL; |
2194 | ||
2195 | /* | |
2196 | * All lines need to be refilled during the nonactive period of which | |
2197 | * only one line can be loaded during the active period. So, atleast | |
2198 | * DS - 1 lines should be loaded during nonactive period. | |
2199 | */ | |
2200 | val = div_u64((u64)nonactive * lclk, pclk); | |
2201 | DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", | |
230edc03 TV |
2202 | val, max(0, ds - 1) * width); |
2203 | if (val < max(0, ds - 1) * width) | |
7faa9233 CM |
2204 | return -EINVAL; |
2205 | ||
2206 | return 0; | |
2207 | } | |
2208 | ||
8702ee50 | 2209 | static unsigned long calc_core_clk_five_taps(unsigned long pclk, |
81ab95b7 AT |
2210 | const struct omap_video_timings *mgr_timings, u16 width, |
2211 | u16 height, u16 out_width, u16 out_height, | |
ff1b2cde | 2212 | enum omap_color_mode color_mode) |
80c39712 | 2213 | { |
8b53d991 | 2214 | u32 core_clk = 0; |
3e8a6ff2 | 2215 | u64 tmp; |
80c39712 | 2216 | |
7282f1b7 CM |
2217 | if (height <= out_height && width <= out_width) |
2218 | return (unsigned long) pclk; | |
2219 | ||
80c39712 | 2220 | if (height > out_height) { |
81ab95b7 | 2221 | unsigned int ppl = mgr_timings->x_res; |
80c39712 | 2222 | |
c582935c | 2223 | tmp = (u64)pclk * height * out_width; |
80c39712 | 2224 | do_div(tmp, 2 * out_height * ppl); |
8b53d991 | 2225 | core_clk = tmp; |
80c39712 | 2226 | |
2d9c5597 VS |
2227 | if (height > 2 * out_height) { |
2228 | if (ppl == out_width) | |
2229 | return 0; | |
2230 | ||
c582935c | 2231 | tmp = (u64)pclk * (height - 2 * out_height) * out_width; |
80c39712 | 2232 | do_div(tmp, 2 * out_height * (ppl - out_width)); |
8b53d991 | 2233 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
2234 | } |
2235 | } | |
2236 | ||
2237 | if (width > out_width) { | |
c582935c | 2238 | tmp = (u64)pclk * width; |
80c39712 | 2239 | do_div(tmp, out_width); |
8b53d991 | 2240 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
2241 | |
2242 | if (color_mode == OMAP_DSS_COLOR_RGB24U) | |
8b53d991 | 2243 | core_clk <<= 1; |
80c39712 TV |
2244 | } |
2245 | ||
8b53d991 | 2246 | return core_clk; |
80c39712 TV |
2247 | } |
2248 | ||
8702ee50 | 2249 | static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, |
8ba85306 | 2250 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
dcbe765b | 2251 | { |
dcbe765b CM |
2252 | if (height > out_height && width > out_width) |
2253 | return pclk * 4; | |
2254 | else | |
2255 | return pclk * 2; | |
2256 | } | |
2257 | ||
8702ee50 | 2258 | static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, |
8ba85306 | 2259 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
80c39712 TV |
2260 | { |
2261 | unsigned int hf, vf; | |
2262 | ||
2263 | /* | |
2264 | * FIXME how to determine the 'A' factor | |
2265 | * for the no downscaling case ? | |
2266 | */ | |
2267 | ||
2268 | if (width > 3 * out_width) | |
2269 | hf = 4; | |
2270 | else if (width > 2 * out_width) | |
2271 | hf = 3; | |
2272 | else if (width > out_width) | |
2273 | hf = 2; | |
2274 | else | |
2275 | hf = 1; | |
80c39712 TV |
2276 | if (height > out_height) |
2277 | vf = 2; | |
2278 | else | |
2279 | vf = 1; | |
2280 | ||
dcbe765b CM |
2281 | return pclk * vf * hf; |
2282 | } | |
2283 | ||
8702ee50 | 2284 | static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, |
8ba85306 | 2285 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
dcbe765b | 2286 | { |
8ba85306 AT |
2287 | /* |
2288 | * If the overlay/writeback is in mem to mem mode, there are no | |
2289 | * downscaling limitations with respect to pixel clock, return 1 as | |
2290 | * required core clock to represent that we have sufficient enough | |
2291 | * core clock to do maximum downscaling | |
2292 | */ | |
2293 | if (mem_to_mem) | |
2294 | return 1; | |
2295 | ||
dcbe765b CM |
2296 | if (width > out_width) |
2297 | return DIV_ROUND_UP(pclk, out_width) * width; | |
2298 | else | |
2299 | return pclk; | |
2300 | } | |
2301 | ||
0c6921de | 2302 | static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2303 | const struct omap_video_timings *mgr_timings, |
2304 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2305 | enum omap_color_mode color_mode, bool *five_taps, | |
2306 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2307 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2308 | { |
2309 | int error; | |
2310 | u16 in_width, in_height; | |
2311 | int min_factor = min(*decim_x, *decim_y); | |
2312 | const int maxsinglelinewidth = | |
2313 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
3e8a6ff2 | 2314 | |
dcbe765b CM |
2315 | *five_taps = false; |
2316 | ||
2317 | do { | |
eec77da2 TV |
2318 | in_height = height / *decim_y; |
2319 | in_width = width / *decim_x; | |
8702ee50 | 2320 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
8ba85306 | 2321 | in_height, out_width, out_height, mem_to_mem); |
dcbe765b CM |
2322 | error = (in_width > maxsinglelinewidth || !*core_clk || |
2323 | *core_clk > dispc_core_clk_rate()); | |
2324 | if (error) { | |
2325 | if (*decim_x == *decim_y) { | |
2326 | *decim_x = min_factor; | |
2327 | ++*decim_y; | |
2328 | } else { | |
2329 | swap(*decim_x, *decim_y); | |
2330 | if (*decim_x < *decim_y) | |
2331 | ++*decim_x; | |
2332 | } | |
2333 | } | |
2334 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | |
2335 | ||
3ce17b48 TV |
2336 | if (error) { |
2337 | DSSERR("failed to find scaling settings\n"); | |
2338 | return -EINVAL; | |
2339 | } | |
2340 | ||
dcbe765b CM |
2341 | if (in_width > maxsinglelinewidth) { |
2342 | DSSERR("Cannot scale max input width exceeded"); | |
2343 | return -EINVAL; | |
2344 | } | |
2345 | return 0; | |
2346 | } | |
2347 | ||
0c6921de | 2348 | static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2349 | const struct omap_video_timings *mgr_timings, |
2350 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2351 | enum omap_color_mode color_mode, bool *five_taps, | |
2352 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2353 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2354 | { |
2355 | int error; | |
2356 | u16 in_width, in_height; | |
dcbe765b CM |
2357 | const int maxsinglelinewidth = |
2358 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
2359 | ||
2360 | do { | |
eec77da2 TV |
2361 | in_height = height / *decim_y; |
2362 | in_width = width / *decim_x; | |
e4998634 | 2363 | *five_taps = in_height > out_height; |
dcbe765b CM |
2364 | |
2365 | if (in_width > maxsinglelinewidth) | |
2366 | if (in_height > out_height && | |
2367 | in_height < out_height * 2) | |
2368 | *five_taps = false; | |
e4998634 ID |
2369 | again: |
2370 | if (*five_taps) | |
2371 | *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, | |
2372 | in_width, in_height, out_width, | |
2373 | out_height, color_mode); | |
2374 | else | |
8702ee50 | 2375 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
8ba85306 AT |
2376 | in_height, out_width, out_height, |
2377 | mem_to_mem); | |
dcbe765b | 2378 | |
e4998634 ID |
2379 | error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, |
2380 | pos_x, in_width, in_height, out_width, | |
2381 | out_height, *five_taps); | |
2382 | if (error && *five_taps) { | |
2383 | *five_taps = false; | |
2384 | goto again; | |
2385 | } | |
2386 | ||
dcbe765b CM |
2387 | error = (error || in_width > maxsinglelinewidth * 2 || |
2388 | (in_width > maxsinglelinewidth && *five_taps) || | |
2389 | !*core_clk || *core_clk > dispc_core_clk_rate()); | |
ab6b2582 TV |
2390 | |
2391 | if (!error) { | |
2392 | /* verify that we're inside the limits of scaler */ | |
2393 | if (in_width / 4 > out_width) | |
2394 | error = 1; | |
2395 | ||
2396 | if (*five_taps) { | |
2397 | if (in_height / 4 > out_height) | |
2398 | error = 1; | |
dcbe765b | 2399 | } else { |
ab6b2582 TV |
2400 | if (in_height / 2 > out_height) |
2401 | error = 1; | |
dcbe765b CM |
2402 | } |
2403 | } | |
ab6b2582 | 2404 | |
7059e3d8 TV |
2405 | if (error) |
2406 | ++*decim_y; | |
dcbe765b CM |
2407 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); |
2408 | ||
3ce17b48 TV |
2409 | if (error) { |
2410 | DSSERR("failed to find scaling settings\n"); | |
2411 | return -EINVAL; | |
2412 | } | |
2413 | ||
f5a73482 TV |
2414 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, |
2415 | in_height, out_width, out_height, *five_taps)) { | |
dcbe765b CM |
2416 | DSSERR("horizontal timing too tight\n"); |
2417 | return -EINVAL; | |
7282f1b7 | 2418 | } |
dcbe765b CM |
2419 | |
2420 | if (in_width > (maxsinglelinewidth * 2)) { | |
2421 | DSSERR("Cannot setup scaling"); | |
2422 | DSSERR("width exceeds maximum width possible"); | |
2423 | return -EINVAL; | |
2424 | } | |
2425 | ||
2426 | if (in_width > maxsinglelinewidth && *five_taps) { | |
2427 | DSSERR("cannot setup scaling with five taps"); | |
2428 | return -EINVAL; | |
2429 | } | |
2430 | return 0; | |
2431 | } | |
2432 | ||
0c6921de | 2433 | static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2434 | const struct omap_video_timings *mgr_timings, |
2435 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2436 | enum omap_color_mode color_mode, bool *five_taps, | |
2437 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2438 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2439 | { |
2440 | u16 in_width, in_width_max; | |
2441 | int decim_x_min = *decim_x; | |
eec77da2 | 2442 | u16 in_height = height / *decim_y; |
dcbe765b CM |
2443 | const int maxsinglelinewidth = |
2444 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
8ba85306 | 2445 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
3e8a6ff2 | 2446 | |
5d501085 AT |
2447 | if (mem_to_mem) { |
2448 | in_width_max = out_width * maxdownscale; | |
2449 | } else { | |
8ba85306 AT |
2450 | in_width_max = dispc_core_clk_rate() / |
2451 | DIV_ROUND_UP(pclk, out_width); | |
5d501085 | 2452 | } |
dcbe765b | 2453 | |
dcbe765b CM |
2454 | *decim_x = DIV_ROUND_UP(width, in_width_max); |
2455 | ||
2456 | *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; | |
2457 | if (*decim_x > *x_predecim) | |
2458 | return -EINVAL; | |
2459 | ||
2460 | do { | |
eec77da2 | 2461 | in_width = width / *decim_x; |
dcbe765b CM |
2462 | } while (*decim_x <= *x_predecim && |
2463 | in_width > maxsinglelinewidth && ++*decim_x); | |
2464 | ||
2465 | if (in_width > maxsinglelinewidth) { | |
2466 | DSSERR("Cannot scale width exceeds max line width"); | |
2467 | return -EINVAL; | |
2468 | } | |
2469 | ||
8702ee50 | 2470 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, |
8ba85306 | 2471 | out_width, out_height, mem_to_mem); |
dcbe765b | 2472 | return 0; |
80c39712 TV |
2473 | } |
2474 | ||
e4c5ae7f TV |
2475 | #define DIV_FRAC(dividend, divisor) \ |
2476 | ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) | |
2477 | ||
74e16458 | 2478 | static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, |
3e8a6ff2 | 2479 | enum omap_overlay_caps caps, |
81ab95b7 AT |
2480 | const struct omap_video_timings *mgr_timings, |
2481 | u16 width, u16 height, u16 out_width, u16 out_height, | |
aed74b55 | 2482 | enum omap_color_mode color_mode, bool *five_taps, |
d557a9cf | 2483 | int *x_predecim, int *y_predecim, u16 pos_x, |
8ba85306 | 2484 | enum omap_dss_rotation_type rotation_type, bool mem_to_mem) |
79ad75f2 | 2485 | { |
0373cac6 | 2486 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
aed74b55 | 2487 | const int max_decim_limit = 16; |
8b53d991 | 2488 | unsigned long core_clk = 0; |
dcbe765b | 2489 | int decim_x, decim_y, ret; |
79ad75f2 | 2490 | |
f95cb5eb TV |
2491 | if (width == out_width && height == out_height) |
2492 | return 0; | |
2493 | ||
fd2eac5a | 2494 | if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { |
4e1d3ca0 TV |
2495 | DSSERR("cannot calculate scaling settings: pclk is zero\n"); |
2496 | return -EINVAL; | |
2497 | } | |
2498 | ||
5b54ed3e | 2499 | if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) |
f95cb5eb | 2500 | return -EINVAL; |
79ad75f2 | 2501 | |
74e16458 | 2502 | if (mem_to_mem) { |
1c031441 AT |
2503 | *x_predecim = *y_predecim = 1; |
2504 | } else { | |
2505 | *x_predecim = max_decim_limit; | |
2506 | *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && | |
2507 | dss_has_feature(FEAT_BURST_2D)) ? | |
2508 | 2 : max_decim_limit; | |
2509 | } | |
aed74b55 CM |
2510 | |
2511 | if (color_mode == OMAP_DSS_COLOR_CLUT1 || | |
2512 | color_mode == OMAP_DSS_COLOR_CLUT2 || | |
2513 | color_mode == OMAP_DSS_COLOR_CLUT4 || | |
2514 | color_mode == OMAP_DSS_COLOR_CLUT8) { | |
2515 | *x_predecim = 1; | |
2516 | *y_predecim = 1; | |
2517 | *five_taps = false; | |
2518 | return 0; | |
2519 | } | |
2520 | ||
2521 | decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); | |
2522 | decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); | |
2523 | ||
aed74b55 | 2524 | if (decim_x > *x_predecim || out_width > width * 8) |
79ad75f2 AT |
2525 | return -EINVAL; |
2526 | ||
aed74b55 | 2527 | if (decim_y > *y_predecim || out_height > height * 8) |
79ad75f2 AT |
2528 | return -EINVAL; |
2529 | ||
0c6921de | 2530 | ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, |
3e8a6ff2 | 2531 | out_width, out_height, color_mode, five_taps, |
8ba85306 AT |
2532 | x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, |
2533 | mem_to_mem); | |
dcbe765b CM |
2534 | if (ret) |
2535 | return ret; | |
79ad75f2 | 2536 | |
e4c5ae7f TV |
2537 | DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", |
2538 | width, height, | |
2539 | out_width, out_height, | |
2540 | out_width / width, DIV_FRAC(out_width, width), | |
2541 | out_height / height, DIV_FRAC(out_height, height), | |
2542 | ||
2543 | decim_x, decim_y, | |
2544 | width / decim_x, height / decim_y, | |
2545 | out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), | |
2546 | out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), | |
2547 | ||
2548 | *five_taps ? 5 : 3, | |
2549 | core_clk, dispc_core_clk_rate()); | |
79ad75f2 | 2550 | |
8b53d991 | 2551 | if (!core_clk || core_clk > dispc_core_clk_rate()) { |
79ad75f2 | 2552 | DSSERR("failed to set up scaling, " |
8b53d991 CM |
2553 | "required core clk rate = %lu Hz, " |
2554 | "current core clk rate = %lu Hz\n", | |
2555 | core_clk, dispc_core_clk_rate()); | |
79ad75f2 AT |
2556 | return -EINVAL; |
2557 | } | |
2558 | ||
aed74b55 CM |
2559 | *x_predecim = decim_x; |
2560 | *y_predecim = decim_y; | |
79ad75f2 AT |
2561 | return 0; |
2562 | } | |
2563 | ||
f9b719b6 TV |
2564 | int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, |
2565 | const struct omap_overlay_info *oi, | |
2566 | const struct omap_video_timings *timings, | |
2567 | int *x_predecim, int *y_predecim) | |
2568 | { | |
2569 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); | |
2570 | bool five_taps = true; | |
62a83183 | 2571 | bool fieldmode = false; |
f9b719b6 TV |
2572 | u16 in_height = oi->height; |
2573 | u16 in_width = oi->width; | |
2574 | bool ilace = timings->interlace; | |
2575 | u16 out_width, out_height; | |
2576 | int pos_x = oi->pos_x; | |
2577 | unsigned long pclk = dispc_mgr_pclk_rate(channel); | |
2578 | unsigned long lclk = dispc_mgr_lclk_rate(channel); | |
2579 | ||
2580 | out_width = oi->out_width == 0 ? oi->width : oi->out_width; | |
2581 | out_height = oi->out_height == 0 ? oi->height : oi->out_height; | |
2582 | ||
2583 | if (ilace && oi->height == out_height) | |
62a83183 | 2584 | fieldmode = true; |
f9b719b6 TV |
2585 | |
2586 | if (ilace) { | |
2587 | if (fieldmode) | |
2588 | in_height /= 2; | |
2589 | out_height /= 2; | |
2590 | ||
2591 | DSSDBG("adjusting for ilace: height %d, out_height %d\n", | |
2592 | in_height, out_height); | |
2593 | } | |
2594 | ||
2595 | if (!dss_feat_color_mode_supported(plane, oi->color_mode)) | |
2596 | return -EINVAL; | |
2597 | ||
2598 | return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width, | |
2599 | in_height, out_width, out_height, oi->color_mode, | |
2600 | &five_taps, x_predecim, y_predecim, pos_x, | |
2601 | oi->rotation_type, false); | |
2602 | } | |
348be69d | 2603 | EXPORT_SYMBOL(dispc_ovl_check); |
f9b719b6 | 2604 | |
84a880fd | 2605 | static int dispc_ovl_setup_common(enum omap_plane plane, |
3e8a6ff2 AT |
2606 | enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, |
2607 | u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, | |
2608 | u16 out_width, u16 out_height, enum omap_color_mode color_mode, | |
2609 | u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, | |
2610 | u8 global_alpha, enum omap_dss_rotation_type rotation_type, | |
8ba85306 AT |
2611 | bool replication, const struct omap_video_timings *mgr_timings, |
2612 | bool mem_to_mem) | |
80c39712 | 2613 | { |
7282f1b7 | 2614 | bool five_taps = true; |
62a83183 | 2615 | bool fieldmode = false; |
79ad75f2 | 2616 | int r, cconv = 0; |
80c39712 TV |
2617 | unsigned offset0, offset1; |
2618 | s32 row_inc; | |
2619 | s32 pix_inc; | |
6be0d73e | 2620 | u16 frame_width, frame_height; |
80c39712 | 2621 | unsigned int field_offset = 0; |
84a880fd AT |
2622 | u16 in_height = height; |
2623 | u16 in_width = width; | |
aed74b55 | 2624 | int x_predecim = 1, y_predecim = 1; |
8050cbe4 | 2625 | bool ilace = mgr_timings->interlace; |
74e16458 TV |
2626 | unsigned long pclk = dispc_plane_pclk_rate(plane); |
2627 | unsigned long lclk = dispc_plane_lclk_rate(plane); | |
e6d80f95 | 2628 | |
e566658f | 2629 | if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) |
80c39712 TV |
2630 | return -EINVAL; |
2631 | ||
c4661b33 TV |
2632 | switch (color_mode) { |
2633 | case OMAP_DSS_COLOR_YUV2: | |
2634 | case OMAP_DSS_COLOR_UYVY: | |
2635 | case OMAP_DSS_COLOR_NV12: | |
2636 | if (in_width & 1) { | |
2637 | DSSERR("input width %d is not even for YUV format\n", | |
2638 | in_width); | |
2639 | return -EINVAL; | |
2640 | } | |
2641 | break; | |
2642 | ||
2643 | default: | |
2644 | break; | |
2645 | } | |
2646 | ||
84a880fd AT |
2647 | out_width = out_width == 0 ? width : out_width; |
2648 | out_height = out_height == 0 ? height : out_height; | |
cf073668 | 2649 | |
84a880fd | 2650 | if (ilace && height == out_height) |
62a83183 | 2651 | fieldmode = true; |
80c39712 TV |
2652 | |
2653 | if (ilace) { | |
2654 | if (fieldmode) | |
aed74b55 | 2655 | in_height /= 2; |
8eeb7019 | 2656 | pos_y /= 2; |
aed74b55 | 2657 | out_height /= 2; |
80c39712 TV |
2658 | |
2659 | DSSDBG("adjusting for ilace: height %d, pos_y %d, " | |
84a880fd AT |
2660 | "out_height %d\n", in_height, pos_y, |
2661 | out_height); | |
80c39712 TV |
2662 | } |
2663 | ||
84a880fd | 2664 | if (!dss_feat_color_mode_supported(plane, color_mode)) |
8dad2ab6 AT |
2665 | return -EINVAL; |
2666 | ||
74e16458 | 2667 | r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, |
84a880fd AT |
2668 | in_height, out_width, out_height, color_mode, |
2669 | &five_taps, &x_predecim, &y_predecim, pos_x, | |
8ba85306 | 2670 | rotation_type, mem_to_mem); |
79ad75f2 AT |
2671 | if (r) |
2672 | return r; | |
80c39712 | 2673 | |
eec77da2 TV |
2674 | in_width = in_width / x_predecim; |
2675 | in_height = in_height / y_predecim; | |
aed74b55 | 2676 | |
c4661b33 TV |
2677 | if (x_predecim > 1 || y_predecim > 1) |
2678 | DSSDBG("predecimation %d x %x, new input size %d x %d\n", | |
2679 | x_predecim, y_predecim, in_width, in_height); | |
2680 | ||
2681 | switch (color_mode) { | |
2682 | case OMAP_DSS_COLOR_YUV2: | |
2683 | case OMAP_DSS_COLOR_UYVY: | |
2684 | case OMAP_DSS_COLOR_NV12: | |
2685 | if (in_width & 1) { | |
2686 | DSSDBG("predecimated input width is not even for YUV format\n"); | |
2687 | DSSDBG("adjusting input width %d -> %d\n", | |
2688 | in_width, in_width & ~1); | |
2689 | ||
2690 | in_width &= ~1; | |
2691 | } | |
2692 | break; | |
2693 | ||
2694 | default: | |
2695 | break; | |
2696 | } | |
2697 | ||
84a880fd AT |
2698 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2699 | color_mode == OMAP_DSS_COLOR_UYVY || | |
2700 | color_mode == OMAP_DSS_COLOR_NV12) | |
79ad75f2 | 2701 | cconv = 1; |
80c39712 TV |
2702 | |
2703 | if (ilace && !fieldmode) { | |
2704 | /* | |
2705 | * when downscaling the bottom field may have to start several | |
2706 | * source lines below the top field. Unfortunately ACCUI | |
2707 | * registers will only hold the fractional part of the offset | |
2708 | * so the integer part must be added to the base address of the | |
2709 | * bottom field. | |
2710 | */ | |
aed74b55 | 2711 | if (!in_height || in_height == out_height) |
80c39712 TV |
2712 | field_offset = 0; |
2713 | else | |
aed74b55 | 2714 | field_offset = in_height / out_height / 2; |
80c39712 TV |
2715 | } |
2716 | ||
2717 | /* Fields are independent but interleaved in memory. */ | |
2718 | if (fieldmode) | |
2719 | field_offset = 1; | |
2720 | ||
c6eee968 TV |
2721 | offset0 = 0; |
2722 | offset1 = 0; | |
2723 | row_inc = 0; | |
2724 | pix_inc = 0; | |
2725 | ||
6be0d73e AT |
2726 | if (plane == OMAP_DSS_WB) { |
2727 | frame_width = out_width; | |
2728 | frame_height = out_height; | |
2729 | } else { | |
2730 | frame_width = in_width; | |
2731 | frame_height = height; | |
2732 | } | |
2733 | ||
84a880fd | 2734 | if (rotation_type == OMAP_DSS_ROT_TILER) |
6be0d73e | 2735 | calc_tiler_rotation_offset(screen_width, frame_width, |
84a880fd | 2736 | color_mode, fieldmode, field_offset, |
65e006ff CM |
2737 | &offset0, &offset1, &row_inc, &pix_inc, |
2738 | x_predecim, y_predecim); | |
84a880fd | 2739 | else if (rotation_type == OMAP_DSS_ROT_DMA) |
6be0d73e AT |
2740 | calc_dma_rotation_offset(rotation, mirror, screen_width, |
2741 | frame_width, frame_height, | |
84a880fd | 2742 | color_mode, fieldmode, field_offset, |
aed74b55 CM |
2743 | &offset0, &offset1, &row_inc, &pix_inc, |
2744 | x_predecim, y_predecim); | |
80c39712 | 2745 | else |
84a880fd | 2746 | calc_vrfb_rotation_offset(rotation, mirror, |
6be0d73e | 2747 | screen_width, frame_width, frame_height, |
84a880fd | 2748 | color_mode, fieldmode, field_offset, |
aed74b55 CM |
2749 | &offset0, &offset1, &row_inc, &pix_inc, |
2750 | x_predecim, y_predecim); | |
80c39712 TV |
2751 | |
2752 | DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", | |
2753 | offset0, offset1, row_inc, pix_inc); | |
2754 | ||
84a880fd | 2755 | dispc_ovl_set_color_mode(plane, color_mode); |
80c39712 | 2756 | |
84a880fd | 2757 | dispc_ovl_configure_burst_type(plane, rotation_type); |
65e006ff | 2758 | |
b7536d67 TV |
2759 | if (dispc.feat->reverse_ilace_field_order) |
2760 | swap(offset0, offset1); | |
2761 | ||
84a880fd AT |
2762 | dispc_ovl_set_ba0(plane, paddr + offset0); |
2763 | dispc_ovl_set_ba1(plane, paddr + offset1); | |
80c39712 | 2764 | |
84a880fd AT |
2765 | if (OMAP_DSS_COLOR_NV12 == color_mode) { |
2766 | dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); | |
2767 | dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); | |
0d66cbb5 AJ |
2768 | } |
2769 | ||
f2aee319 TV |
2770 | if (dispc.feat->last_pixel_inc_missing) |
2771 | row_inc += pix_inc - 1; | |
2772 | ||
f0e5caab TV |
2773 | dispc_ovl_set_row_inc(plane, row_inc); |
2774 | dispc_ovl_set_pix_inc(plane, pix_inc); | |
80c39712 | 2775 | |
84a880fd | 2776 | DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, |
aed74b55 | 2777 | in_height, out_width, out_height); |
80c39712 | 2778 | |
84a880fd | 2779 | dispc_ovl_set_pos(plane, caps, pos_x, pos_y); |
80c39712 | 2780 | |
78b687fc | 2781 | dispc_ovl_set_input_size(plane, in_width, in_height); |
80c39712 | 2782 | |
5b54ed3e | 2783 | if (caps & OMAP_DSS_OVL_CAP_SCALE) { |
aed74b55 CM |
2784 | dispc_ovl_set_scaling(plane, in_width, in_height, out_width, |
2785 | out_height, ilace, five_taps, fieldmode, | |
84a880fd | 2786 | color_mode, rotation); |
78b687fc | 2787 | dispc_ovl_set_output_size(plane, out_width, out_height); |
f0e5caab | 2788 | dispc_ovl_set_vid_color_conv(plane, cconv); |
80c39712 TV |
2789 | } |
2790 | ||
c35eeb2e AT |
2791 | dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, |
2792 | color_mode); | |
80c39712 | 2793 | |
84a880fd AT |
2794 | dispc_ovl_set_zorder(plane, caps, zorder); |
2795 | dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); | |
2796 | dispc_ovl_setup_global_alpha(plane, caps, global_alpha); | |
80c39712 | 2797 | |
d79db853 | 2798 | dispc_ovl_enable_replication(plane, caps, replication); |
c3d92529 | 2799 | |
80c39712 TV |
2800 | return 0; |
2801 | } | |
2802 | ||
84a880fd | 2803 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, |
8ba85306 AT |
2804 | bool replication, const struct omap_video_timings *mgr_timings, |
2805 | bool mem_to_mem) | |
84a880fd AT |
2806 | { |
2807 | int r; | |
16bf20c7 | 2808 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); |
84a880fd AT |
2809 | enum omap_channel channel; |
2810 | ||
2811 | channel = dispc_ovl_get_channel_out(plane); | |
2812 | ||
24f13a66 AB |
2813 | DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" |
2814 | " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", | |
2815 | plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, | |
84a880fd AT |
2816 | oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, |
2817 | oi->color_mode, oi->rotation, oi->mirror, channel, replication); | |
2818 | ||
16bf20c7 | 2819 | r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, |
3e8a6ff2 AT |
2820 | oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, |
2821 | oi->out_width, oi->out_height, oi->color_mode, oi->rotation, | |
2822 | oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, | |
8ba85306 | 2823 | oi->rotation_type, replication, mgr_timings, mem_to_mem); |
84a880fd AT |
2824 | |
2825 | return r; | |
2826 | } | |
348be69d | 2827 | EXPORT_SYMBOL(dispc_ovl_setup); |
84a880fd | 2828 | |
749feffa | 2829 | int dispc_wb_setup(const struct omap_dss_writeback_info *wi, |
9e4a0fc7 | 2830 | bool mem_to_mem, const struct omap_video_timings *mgr_timings) |
749feffa AT |
2831 | { |
2832 | int r; | |
9e4a0fc7 | 2833 | u32 l; |
749feffa AT |
2834 | enum omap_plane plane = OMAP_DSS_WB; |
2835 | const int pos_x = 0, pos_y = 0; | |
2836 | const u8 zorder = 0, global_alpha = 0; | |
2837 | const bool replication = false; | |
9e4a0fc7 | 2838 | bool truncation; |
749feffa AT |
2839 | int in_width = mgr_timings->x_res; |
2840 | int in_height = mgr_timings->y_res; | |
2841 | enum omap_overlay_caps caps = | |
2842 | OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; | |
2843 | ||
2844 | DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " | |
2845 | "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width, | |
2846 | in_height, wi->width, wi->height, wi->color_mode, wi->rotation, | |
2847 | wi->mirror); | |
2848 | ||
2849 | r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, | |
2850 | wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, | |
2851 | wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder, | |
2852 | wi->pre_mult_alpha, global_alpha, wi->rotation_type, | |
9e4a0fc7 AT |
2853 | replication, mgr_timings, mem_to_mem); |
2854 | ||
2855 | switch (wi->color_mode) { | |
2856 | case OMAP_DSS_COLOR_RGB16: | |
2857 | case OMAP_DSS_COLOR_RGB24P: | |
2858 | case OMAP_DSS_COLOR_ARGB16: | |
2859 | case OMAP_DSS_COLOR_RGBA16: | |
2860 | case OMAP_DSS_COLOR_RGB12U: | |
2861 | case OMAP_DSS_COLOR_ARGB16_1555: | |
2862 | case OMAP_DSS_COLOR_XRGB16_1555: | |
2863 | case OMAP_DSS_COLOR_RGBX16: | |
2864 | truncation = true; | |
2865 | break; | |
2866 | default: | |
2867 | truncation = false; | |
2868 | break; | |
2869 | } | |
2870 | ||
2871 | /* setup extra DISPC_WB_ATTRIBUTES */ | |
2872 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
2873 | l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ | |
2874 | l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ | |
4c055ce0 TV |
2875 | if (mem_to_mem) |
2876 | l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ | |
98cd5796 TV |
2877 | else |
2878 | l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ | |
9e4a0fc7 | 2879 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
749feffa | 2880 | |
98cd5796 TV |
2881 | if (mem_to_mem) { |
2882 | /* WBDELAYCOUNT */ | |
2883 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); | |
2884 | } else { | |
2885 | int wbdelay; | |
2886 | ||
2887 | wbdelay = min(mgr_timings->vfp + mgr_timings->vsw + | |
2888 | mgr_timings->vbp, 255); | |
2889 | ||
2890 | /* WBDELAYCOUNT */ | |
2891 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); | |
2892 | } | |
2893 | ||
749feffa AT |
2894 | return r; |
2895 | } | |
2896 | ||
f0e5caab | 2897 | int dispc_ovl_enable(enum omap_plane plane, bool enable) |
80c39712 | 2898 | { |
e6d80f95 TV |
2899 | DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); |
2900 | ||
9b372c2d | 2901 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); |
e6d80f95 TV |
2902 | |
2903 | return 0; | |
80c39712 | 2904 | } |
348be69d | 2905 | EXPORT_SYMBOL(dispc_ovl_enable); |
80c39712 | 2906 | |
04bd8ac1 TV |
2907 | bool dispc_ovl_enabled(enum omap_plane plane) |
2908 | { | |
2909 | return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); | |
2910 | } | |
348be69d | 2911 | EXPORT_SYMBOL(dispc_ovl_enabled); |
04bd8ac1 | 2912 | |
f1a813d3 | 2913 | void dispc_mgr_enable(enum omap_channel channel, bool enable) |
80c39712 | 2914 | { |
efa70b3b CM |
2915 | mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); |
2916 | /* flush posted write */ | |
2917 | mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
80c39712 | 2918 | } |
348be69d | 2919 | EXPORT_SYMBOL(dispc_mgr_enable); |
80c39712 | 2920 | |
65398511 TV |
2921 | bool dispc_mgr_is_enabled(enum omap_channel channel) |
2922 | { | |
2923 | return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
2924 | } | |
348be69d | 2925 | EXPORT_SYMBOL(dispc_mgr_is_enabled); |
65398511 | 2926 | |
0b23e5b8 AT |
2927 | void dispc_wb_enable(bool enable) |
2928 | { | |
916188a4 | 2929 | dispc_ovl_enable(OMAP_DSS_WB, enable); |
0b23e5b8 AT |
2930 | } |
2931 | ||
2932 | bool dispc_wb_is_enabled(void) | |
2933 | { | |
916188a4 | 2934 | return dispc_ovl_enabled(OMAP_DSS_WB); |
0b23e5b8 AT |
2935 | } |
2936 | ||
fb2cec1f | 2937 | static void dispc_lcd_enable_signal_polarity(bool act_high) |
80c39712 | 2938 | { |
6ced40bf AT |
2939 | if (!dss_has_feature(FEAT_LCDENABLEPOL)) |
2940 | return; | |
2941 | ||
80c39712 | 2942 | REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); |
80c39712 TV |
2943 | } |
2944 | ||
2945 | void dispc_lcd_enable_signal(bool enable) | |
2946 | { | |
6ced40bf AT |
2947 | if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) |
2948 | return; | |
2949 | ||
80c39712 | 2950 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); |
80c39712 TV |
2951 | } |
2952 | ||
2953 | void dispc_pck_free_enable(bool enable) | |
2954 | { | |
6ced40bf AT |
2955 | if (!dss_has_feature(FEAT_PCKFREEENABLE)) |
2956 | return; | |
2957 | ||
80c39712 | 2958 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); |
80c39712 TV |
2959 | } |
2960 | ||
fb2cec1f | 2961 | static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) |
80c39712 | 2962 | { |
efa70b3b | 2963 | mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); |
80c39712 TV |
2964 | } |
2965 | ||
2966 | ||
fb2cec1f | 2967 | static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) |
80c39712 | 2968 | { |
d21f43bc | 2969 | mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); |
80c39712 TV |
2970 | } |
2971 | ||
65904155 | 2972 | static void dispc_set_loadmode(enum omap_dss_load_mode mode) |
80c39712 | 2973 | { |
80c39712 | 2974 | REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); |
80c39712 TV |
2975 | } |
2976 | ||
2977 | ||
c64dca40 | 2978 | static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) |
80c39712 | 2979 | { |
8613b000 | 2980 | dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); |
80c39712 TV |
2981 | } |
2982 | ||
c64dca40 | 2983 | static void dispc_mgr_set_trans_key(enum omap_channel ch, |
80c39712 TV |
2984 | enum omap_dss_trans_key_type type, |
2985 | u32 trans_key) | |
2986 | { | |
efa70b3b | 2987 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); |
80c39712 | 2988 | |
8613b000 | 2989 | dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); |
80c39712 TV |
2990 | } |
2991 | ||
c64dca40 | 2992 | static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) |
80c39712 | 2993 | { |
efa70b3b | 2994 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); |
80c39712 | 2995 | } |
11354dd5 | 2996 | |
c64dca40 TV |
2997 | static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, |
2998 | bool enable) | |
80c39712 | 2999 | { |
11354dd5 | 3000 | if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) |
80c39712 TV |
3001 | return; |
3002 | ||
80c39712 TV |
3003 | if (ch == OMAP_DSS_CHANNEL_LCD) |
3004 | REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); | |
2a205f34 | 3005 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 3006 | REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); |
80c39712 | 3007 | } |
11354dd5 | 3008 | |
c64dca40 | 3009 | void dispc_mgr_setup(enum omap_channel channel, |
a8f3fcd1 | 3010 | const struct omap_overlay_manager_info *info) |
c64dca40 TV |
3011 | { |
3012 | dispc_mgr_set_default_color(channel, info->default_color); | |
3013 | dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); | |
3014 | dispc_mgr_enable_trans_key(channel, info->trans_enabled); | |
3015 | dispc_mgr_enable_alpha_fixed_zorder(channel, | |
3016 | info->partial_alpha_enabled); | |
3017 | if (dss_has_feature(FEAT_CPR)) { | |
3018 | dispc_mgr_enable_cpr(channel, info->cpr_enable); | |
3019 | dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); | |
3020 | } | |
3021 | } | |
348be69d | 3022 | EXPORT_SYMBOL(dispc_mgr_setup); |
80c39712 | 3023 | |
fb2cec1f | 3024 | static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) |
80c39712 TV |
3025 | { |
3026 | int code; | |
3027 | ||
3028 | switch (data_lines) { | |
3029 | case 12: | |
3030 | code = 0; | |
3031 | break; | |
3032 | case 16: | |
3033 | code = 1; | |
3034 | break; | |
3035 | case 18: | |
3036 | code = 2; | |
3037 | break; | |
3038 | case 24: | |
3039 | code = 3; | |
3040 | break; | |
3041 | default: | |
3042 | BUG(); | |
3043 | return; | |
3044 | } | |
3045 | ||
efa70b3b | 3046 | mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); |
80c39712 TV |
3047 | } |
3048 | ||
fb2cec1f | 3049 | static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) |
80c39712 TV |
3050 | { |
3051 | u32 l; | |
569969d6 | 3052 | int gpout0, gpout1; |
80c39712 TV |
3053 | |
3054 | switch (mode) { | |
569969d6 AT |
3055 | case DSS_IO_PAD_MODE_RESET: |
3056 | gpout0 = 0; | |
3057 | gpout1 = 0; | |
80c39712 | 3058 | break; |
569969d6 AT |
3059 | case DSS_IO_PAD_MODE_RFBI: |
3060 | gpout0 = 1; | |
80c39712 TV |
3061 | gpout1 = 0; |
3062 | break; | |
569969d6 AT |
3063 | case DSS_IO_PAD_MODE_BYPASS: |
3064 | gpout0 = 1; | |
80c39712 TV |
3065 | gpout1 = 1; |
3066 | break; | |
80c39712 TV |
3067 | default: |
3068 | BUG(); | |
3069 | return; | |
3070 | } | |
3071 | ||
569969d6 AT |
3072 | l = dispc_read_reg(DISPC_CONTROL); |
3073 | l = FLD_MOD(l, gpout0, 15, 15); | |
3074 | l = FLD_MOD(l, gpout1, 16, 16); | |
3075 | dispc_write_reg(DISPC_CONTROL, l); | |
3076 | } | |
3077 | ||
fb2cec1f | 3078 | static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) |
569969d6 | 3079 | { |
efa70b3b | 3080 | mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); |
80c39712 TV |
3081 | } |
3082 | ||
fb2cec1f TV |
3083 | void dispc_mgr_set_lcd_config(enum omap_channel channel, |
3084 | const struct dss_lcd_mgr_config *config) | |
3085 | { | |
3086 | dispc_mgr_set_io_pad_mode(config->io_pad_mode); | |
3087 | ||
3088 | dispc_mgr_enable_stallmode(channel, config->stallmode); | |
3089 | dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); | |
3090 | ||
3091 | dispc_mgr_set_clock_div(channel, &config->clock_info); | |
3092 | ||
3093 | dispc_mgr_set_tft_data_lines(channel, config->video_port_width); | |
3094 | ||
3095 | dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); | |
3096 | ||
3097 | dispc_mgr_set_lcd_type_tft(channel); | |
3098 | } | |
348be69d | 3099 | EXPORT_SYMBOL(dispc_mgr_set_lcd_config); |
fb2cec1f | 3100 | |
8f366162 AT |
3101 | static bool _dispc_mgr_size_ok(u16 width, u16 height) |
3102 | { | |
33b89928 AT |
3103 | return width <= dispc.feat->mgr_width_max && |
3104 | height <= dispc.feat->mgr_height_max; | |
8f366162 AT |
3105 | } |
3106 | ||
80c39712 TV |
3107 | static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, |
3108 | int vsw, int vfp, int vbp) | |
3109 | { | |
dcbe765b CM |
3110 | if (hsw < 1 || hsw > dispc.feat->sw_max || |
3111 | hfp < 1 || hfp > dispc.feat->hp_max || | |
3112 | hbp < 1 || hbp > dispc.feat->hp_max || | |
3113 | vsw < 1 || vsw > dispc.feat->sw_max || | |
3114 | vfp < 0 || vfp > dispc.feat->vp_max || | |
3115 | vbp < 0 || vbp > dispc.feat->vp_max) | |
3116 | return false; | |
80c39712 TV |
3117 | return true; |
3118 | } | |
3119 | ||
ca5ca69c AT |
3120 | static bool _dispc_mgr_pclk_ok(enum omap_channel channel, |
3121 | unsigned long pclk) | |
3122 | { | |
3123 | if (dss_mgr_is_lcd(channel)) | |
3124 | return pclk <= dispc.feat->max_lcd_pclk ? true : false; | |
3125 | else | |
3126 | return pclk <= dispc.feat->max_tv_pclk ? true : false; | |
3127 | } | |
3128 | ||
8f366162 | 3129 | bool dispc_mgr_timings_ok(enum omap_channel channel, |
b917fa39 | 3130 | const struct omap_video_timings *timings) |
80c39712 | 3131 | { |
eadd33bb TV |
3132 | if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) |
3133 | return false; | |
8f366162 | 3134 | |
eadd33bb TV |
3135 | if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) |
3136 | return false; | |
ca5ca69c AT |
3137 | |
3138 | if (dss_mgr_is_lcd(channel)) { | |
beb8384d | 3139 | /* TODO: OMAP4+ supports interlace for LCD outputs */ |
eadd33bb TV |
3140 | if (timings->interlace) |
3141 | return false; | |
beb8384d | 3142 | |
eadd33bb | 3143 | if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, |
ca5ca69c | 3144 | timings->hbp, timings->vsw, timings->vfp, |
eadd33bb TV |
3145 | timings->vbp)) |
3146 | return false; | |
ca5ca69c | 3147 | } |
8f366162 | 3148 | |
eadd33bb | 3149 | return true; |
80c39712 TV |
3150 | } |
3151 | ||
26d9dd0d | 3152 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
655e2941 AT |
3153 | int hfp, int hbp, int vsw, int vfp, int vbp, |
3154 | enum omap_dss_signal_level vsync_level, | |
3155 | enum omap_dss_signal_level hsync_level, | |
3156 | enum omap_dss_signal_edge data_pclk_edge, | |
3157 | enum omap_dss_signal_level de_level, | |
3158 | enum omap_dss_signal_edge sync_pclk_edge) | |
3159 | ||
80c39712 | 3160 | { |
655e2941 | 3161 | u32 timing_h, timing_v, l; |
ed351881 | 3162 | bool onoff, rf, ipc, vs, hs, de; |
80c39712 | 3163 | |
dcbe765b CM |
3164 | timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | |
3165 | FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | | |
3166 | FLD_VAL(hbp-1, dispc.feat->bp_start, 20); | |
3167 | timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | | |
3168 | FLD_VAL(vfp, dispc.feat->fp_start, 8) | | |
3169 | FLD_VAL(vbp, dispc.feat->bp_start, 20); | |
80c39712 | 3170 | |
64ba4f74 SS |
3171 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
3172 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); | |
655e2941 | 3173 | |
ed351881 TV |
3174 | switch (vsync_level) { |
3175 | case OMAPDSS_SIG_ACTIVE_LOW: | |
3176 | vs = true; | |
3177 | break; | |
3178 | case OMAPDSS_SIG_ACTIVE_HIGH: | |
3179 | vs = false; | |
3180 | break; | |
3181 | default: | |
3182 | BUG(); | |
3183 | } | |
3184 | ||
3185 | switch (hsync_level) { | |
3186 | case OMAPDSS_SIG_ACTIVE_LOW: | |
3187 | hs = true; | |
3188 | break; | |
3189 | case OMAPDSS_SIG_ACTIVE_HIGH: | |
3190 | hs = false; | |
3191 | break; | |
3192 | default: | |
3193 | BUG(); | |
3194 | } | |
3195 | ||
3196 | switch (de_level) { | |
3197 | case OMAPDSS_SIG_ACTIVE_LOW: | |
3198 | de = true; | |
3199 | break; | |
3200 | case OMAPDSS_SIG_ACTIVE_HIGH: | |
3201 | de = false; | |
3202 | break; | |
3203 | default: | |
3204 | BUG(); | |
3205 | } | |
3206 | ||
655e2941 AT |
3207 | switch (data_pclk_edge) { |
3208 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
3209 | ipc = false; | |
3210 | break; | |
3211 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | |
3212 | ipc = true; | |
3213 | break; | |
655e2941 AT |
3214 | default: |
3215 | BUG(); | |
3216 | } | |
3217 | ||
7a16360d TV |
3218 | /* always use the 'rf' setting */ |
3219 | onoff = true; | |
3220 | ||
655e2941 | 3221 | switch (sync_pclk_edge) { |
655e2941 | 3222 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: |
655e2941 AT |
3223 | rf = false; |
3224 | break; | |
3225 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
655e2941 AT |
3226 | rf = true; |
3227 | break; | |
3228 | default: | |
3229 | BUG(); | |
cf6ac4ce | 3230 | } |
655e2941 | 3231 | |
d80e02ef TV |
3232 | l = FLD_VAL(onoff, 17, 17) | |
3233 | FLD_VAL(rf, 16, 16) | | |
ed351881 | 3234 | FLD_VAL(de, 15, 15) | |
d80e02ef | 3235 | FLD_VAL(ipc, 14, 14) | |
ed351881 TV |
3236 | FLD_VAL(hs, 13, 13) | |
3237 | FLD_VAL(vs, 12, 12); | |
d80e02ef | 3238 | |
e5f80917 TV |
3239 | /* always set ALIGN bit when available */ |
3240 | if (dispc.feat->supports_sync_align) | |
3241 | l |= (1 << 18); | |
3242 | ||
655e2941 | 3243 | dispc_write_reg(DISPC_POL_FREQ(channel), l); |
0006fd63 TV |
3244 | |
3245 | if (dispc.syscon_pol) { | |
3246 | const int shifts[] = { | |
3247 | [OMAP_DSS_CHANNEL_LCD] = 0, | |
3248 | [OMAP_DSS_CHANNEL_LCD2] = 1, | |
3249 | [OMAP_DSS_CHANNEL_LCD3] = 2, | |
3250 | }; | |
3251 | ||
3252 | u32 mask, val; | |
3253 | ||
3254 | mask = (1 << 0) | (1 << 3) | (1 << 6); | |
3255 | val = (rf << 0) | (ipc << 3) | (onoff << 6); | |
3256 | ||
3257 | mask <<= 16 + shifts[channel]; | |
3258 | val <<= 16 + shifts[channel]; | |
3259 | ||
3260 | regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, | |
3261 | mask, val); | |
3262 | } | |
80c39712 TV |
3263 | } |
3264 | ||
3265 | /* change name to mode? */ | |
c51d921a | 3266 | void dispc_mgr_set_timings(enum omap_channel channel, |
a8f3fcd1 | 3267 | const struct omap_video_timings *timings) |
80c39712 TV |
3268 | { |
3269 | unsigned xtot, ytot; | |
3270 | unsigned long ht, vt; | |
2aefad49 | 3271 | struct omap_video_timings t = *timings; |
80c39712 | 3272 | |
2aefad49 | 3273 | DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); |
80c39712 | 3274 | |
2aefad49 | 3275 | if (!dispc_mgr_timings_ok(channel, &t)) { |
8f366162 | 3276 | BUG(); |
c6eee968 TV |
3277 | return; |
3278 | } | |
80c39712 | 3279 | |
dd88b7a6 | 3280 | if (dss_mgr_is_lcd(channel)) { |
2aefad49 | 3281 | _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, |
655e2941 AT |
3282 | t.vfp, t.vbp, t.vsync_level, t.hsync_level, |
3283 | t.data_pclk_edge, t.de_level, t.sync_pclk_edge); | |
80c39712 | 3284 | |
2aefad49 AT |
3285 | xtot = t.x_res + t.hfp + t.hsw + t.hbp; |
3286 | ytot = t.y_res + t.vfp + t.vsw + t.vbp; | |
80c39712 | 3287 | |
d8d78941 TV |
3288 | ht = timings->pixelclock / xtot; |
3289 | vt = timings->pixelclock / xtot / ytot; | |
c51d921a | 3290 | |
d8d78941 | 3291 | DSSDBG("pck %u\n", timings->pixelclock); |
c51d921a | 3292 | DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", |
2aefad49 | 3293 | t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); |
655e2941 AT |
3294 | DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", |
3295 | t.vsync_level, t.hsync_level, t.data_pclk_edge, | |
3296 | t.de_level, t.sync_pclk_edge); | |
80c39712 | 3297 | |
c51d921a | 3298 | DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); |
2aefad49 | 3299 | } else { |
0bcfdba6 | 3300 | if (t.interlace) |
2aefad49 | 3301 | t.y_res /= 2; |
3a38ed53 TV |
3302 | |
3303 | if (dispc.feat->supports_double_pixel) | |
3304 | REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0, | |
3305 | 19, 17); | |
c51d921a | 3306 | } |
8f366162 | 3307 | |
2aefad49 | 3308 | dispc_mgr_set_size(channel, t.x_res, t.y_res); |
80c39712 | 3309 | } |
348be69d | 3310 | EXPORT_SYMBOL(dispc_mgr_set_timings); |
80c39712 | 3311 | |
26d9dd0d | 3312 | static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, |
ff1b2cde | 3313 | u16 pck_div) |
80c39712 TV |
3314 | { |
3315 | BUG_ON(lck_div < 1); | |
9eaaf207 | 3316 | BUG_ON(pck_div < 1); |
80c39712 | 3317 | |
ce7fa5eb | 3318 | dispc_write_reg(DISPC_DIVISORo(channel), |
80c39712 | 3319 | FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); |
7b3926b3 | 3320 | |
0bcfdba6 | 3321 | if (!dss_has_feature(FEAT_CORE_CLK_DIV) && |
7b3926b3 TV |
3322 | channel == OMAP_DSS_CHANNEL_LCD) |
3323 | dispc.core_clk_rate = dispc_fclk_rate() / lck_div; | |
80c39712 TV |
3324 | } |
3325 | ||
26d9dd0d | 3326 | static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, |
2a205f34 | 3327 | int *pck_div) |
80c39712 TV |
3328 | { |
3329 | u32 l; | |
ce7fa5eb | 3330 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
3331 | *lck_div = FLD_GET(l, 23, 16); |
3332 | *pck_div = FLD_GET(l, 7, 0); | |
3333 | } | |
3334 | ||
65904155 | 3335 | static unsigned long dispc_fclk_rate(void) |
80c39712 | 3336 | { |
2daea7af | 3337 | struct dss_pll *pll; |
80c39712 TV |
3338 | unsigned long r = 0; |
3339 | ||
66534e8e | 3340 | switch (dss_get_dispc_clk_source()) { |
89a35e51 | 3341 | case OMAP_DSS_CLK_SRC_FCK: |
5aaee69d | 3342 | r = dss_get_dispc_clk_rate(); |
66534e8e | 3343 | break; |
89a35e51 | 3344 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
2daea7af | 3345 | pll = dss_pll_find("dsi0"); |
93550927 TV |
3346 | if (!pll) |
3347 | pll = dss_pll_find("video0"); | |
3348 | ||
2daea7af | 3349 | r = pll->cinfo.clkout[0]; |
66534e8e | 3350 | break; |
5a8b572d | 3351 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
2daea7af | 3352 | pll = dss_pll_find("dsi1"); |
93550927 TV |
3353 | if (!pll) |
3354 | pll = dss_pll_find("video1"); | |
3355 | ||
2daea7af | 3356 | r = pll->cinfo.clkout[0]; |
5a8b572d | 3357 | break; |
66534e8e TA |
3358 | default: |
3359 | BUG(); | |
c6eee968 | 3360 | return 0; |
66534e8e TA |
3361 | } |
3362 | ||
80c39712 TV |
3363 | return r; |
3364 | } | |
3365 | ||
65904155 | 3366 | static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
80c39712 | 3367 | { |
2daea7af | 3368 | struct dss_pll *pll; |
80c39712 TV |
3369 | int lcd; |
3370 | unsigned long r; | |
3371 | u32 l; | |
3372 | ||
c31cba8a TV |
3373 | if (dss_mgr_is_lcd(channel)) { |
3374 | l = dispc_read_reg(DISPC_DIVISORo(channel)); | |
80c39712 | 3375 | |
c31cba8a | 3376 | lcd = FLD_GET(l, 23, 16); |
80c39712 | 3377 | |
c31cba8a TV |
3378 | switch (dss_get_lcd_clk_source(channel)) { |
3379 | case OMAP_DSS_CLK_SRC_FCK: | |
5aaee69d | 3380 | r = dss_get_dispc_clk_rate(); |
c31cba8a TV |
3381 | break; |
3382 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | |
2daea7af | 3383 | pll = dss_pll_find("dsi0"); |
93550927 TV |
3384 | if (!pll) |
3385 | pll = dss_pll_find("video0"); | |
3386 | ||
2daea7af | 3387 | r = pll->cinfo.clkout[0]; |
c31cba8a TV |
3388 | break; |
3389 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | |
2daea7af | 3390 | pll = dss_pll_find("dsi1"); |
93550927 TV |
3391 | if (!pll) |
3392 | pll = dss_pll_find("video1"); | |
3393 | ||
2daea7af | 3394 | r = pll->cinfo.clkout[0]; |
c31cba8a TV |
3395 | break; |
3396 | default: | |
3397 | BUG(); | |
3398 | return 0; | |
3399 | } | |
80c39712 | 3400 | |
c31cba8a TV |
3401 | return r / lcd; |
3402 | } else { | |
3403 | return dispc_fclk_rate(); | |
3404 | } | |
80c39712 TV |
3405 | } |
3406 | ||
65904155 | 3407 | static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |
80c39712 | 3408 | { |
80c39712 | 3409 | unsigned long r; |
80c39712 | 3410 | |
dd88b7a6 | 3411 | if (dss_mgr_is_lcd(channel)) { |
c3dc6a7a AT |
3412 | int pcd; |
3413 | u32 l; | |
80c39712 | 3414 | |
c3dc6a7a | 3415 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 | 3416 | |
c3dc6a7a | 3417 | pcd = FLD_GET(l, 7, 0); |
80c39712 | 3418 | |
c3dc6a7a AT |
3419 | r = dispc_mgr_lclk_rate(channel); |
3420 | ||
3421 | return r / pcd; | |
3422 | } else { | |
5391e87d | 3423 | return dispc.tv_pclk_rate; |
c3dc6a7a | 3424 | } |
80c39712 TV |
3425 | } |
3426 | ||
5391e87d TV |
3427 | void dispc_set_tv_pclk(unsigned long pclk) |
3428 | { | |
3429 | dispc.tv_pclk_rate = pclk; | |
3430 | } | |
3431 | ||
65904155 | 3432 | static unsigned long dispc_core_clk_rate(void) |
8b53d991 | 3433 | { |
7b3926b3 | 3434 | return dispc.core_clk_rate; |
8b53d991 CM |
3435 | } |
3436 | ||
3e8a6ff2 AT |
3437 | static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) |
3438 | { | |
251886d8 TV |
3439 | enum omap_channel channel; |
3440 | ||
3441 | if (plane == OMAP_DSS_WB) | |
3442 | return 0; | |
3443 | ||
3444 | channel = dispc_ovl_get_channel_out(plane); | |
3e8a6ff2 AT |
3445 | |
3446 | return dispc_mgr_pclk_rate(channel); | |
3447 | } | |
3448 | ||
3449 | static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) | |
3450 | { | |
251886d8 TV |
3451 | enum omap_channel channel; |
3452 | ||
3453 | if (plane == OMAP_DSS_WB) | |
3454 | return 0; | |
3455 | ||
3456 | channel = dispc_ovl_get_channel_out(plane); | |
3e8a6ff2 | 3457 | |
c31cba8a | 3458 | return dispc_mgr_lclk_rate(channel); |
3e8a6ff2 | 3459 | } |
c31cba8a | 3460 | |
6f1891fc | 3461 | static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) |
80c39712 TV |
3462 | { |
3463 | int lcd, pcd; | |
6f1891fc CM |
3464 | enum omap_dss_clk_source lcd_clk_src; |
3465 | ||
3466 | seq_printf(s, "- %s -\n", mgr_desc[channel].name); | |
3467 | ||
3468 | lcd_clk_src = dss_get_lcd_clk_source(channel); | |
3469 | ||
3470 | seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, | |
3471 | dss_get_generic_clk_source_name(lcd_clk_src), | |
3472 | dss_feat_get_clk_source_name(lcd_clk_src)); | |
3473 | ||
3474 | dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); | |
3475 | ||
3476 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3477 | dispc_mgr_lclk_rate(channel), lcd); | |
3478 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", | |
3479 | dispc_mgr_pclk_rate(channel), pcd); | |
3480 | } | |
3481 | ||
3482 | void dispc_dump_clocks(struct seq_file *s) | |
3483 | { | |
3484 | int lcd; | |
0cf35df3 | 3485 | u32 l; |
89a35e51 | 3486 | enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); |
80c39712 | 3487 | |
4fbafaf3 TV |
3488 | if (dispc_runtime_get()) |
3489 | return; | |
80c39712 | 3490 | |
80c39712 TV |
3491 | seq_printf(s, "- DISPC -\n"); |
3492 | ||
067a57e4 AT |
3493 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
3494 | dss_get_generic_clk_source_name(dispc_clk_src), | |
3495 | dss_feat_get_clk_source_name(dispc_clk_src)); | |
80c39712 TV |
3496 | |
3497 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); | |
2a205f34 | 3498 | |
0cf35df3 MR |
3499 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
3500 | seq_printf(s, "- DISPC-CORE-CLK -\n"); | |
3501 | l = dispc_read_reg(DISPC_DIVISOR); | |
3502 | lcd = FLD_GET(l, 23, 16); | |
3503 | ||
3504 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3505 | (dispc_fclk_rate()/lcd), lcd); | |
3506 | } | |
2a205f34 | 3507 | |
6f1891fc | 3508 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); |
ea75159e | 3509 | |
6f1891fc CM |
3510 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3511 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); | |
3512 | if (dss_has_feature(FEAT_MGR_LCD3)) | |
3513 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); | |
4fbafaf3 TV |
3514 | |
3515 | dispc_runtime_put(); | |
80c39712 TV |
3516 | } |
3517 | ||
e40402cf | 3518 | static void dispc_dump_regs(struct seq_file *s) |
80c39712 | 3519 | { |
4dd2da15 AT |
3520 | int i, j; |
3521 | const char *mgr_names[] = { | |
3522 | [OMAP_DSS_CHANNEL_LCD] = "LCD", | |
3523 | [OMAP_DSS_CHANNEL_DIGIT] = "TV", | |
3524 | [OMAP_DSS_CHANNEL_LCD2] = "LCD2", | |
6f1891fc | 3525 | [OMAP_DSS_CHANNEL_LCD3] = "LCD3", |
4dd2da15 AT |
3526 | }; |
3527 | const char *ovl_names[] = { | |
3528 | [OMAP_DSS_GFX] = "GFX", | |
3529 | [OMAP_DSS_VIDEO1] = "VID1", | |
3530 | [OMAP_DSS_VIDEO2] = "VID2", | |
b8c095b4 | 3531 | [OMAP_DSS_VIDEO3] = "VID3", |
06c525fe | 3532 | [OMAP_DSS_WB] = "WB", |
4dd2da15 AT |
3533 | }; |
3534 | const char **p_names; | |
3535 | ||
9b372c2d | 3536 | #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) |
80c39712 | 3537 | |
4fbafaf3 TV |
3538 | if (dispc_runtime_get()) |
3539 | return; | |
80c39712 | 3540 | |
5010be80 | 3541 | /* DISPC common registers */ |
80c39712 TV |
3542 | DUMPREG(DISPC_REVISION); |
3543 | DUMPREG(DISPC_SYSCONFIG); | |
3544 | DUMPREG(DISPC_SYSSTATUS); | |
3545 | DUMPREG(DISPC_IRQSTATUS); | |
3546 | DUMPREG(DISPC_IRQENABLE); | |
3547 | DUMPREG(DISPC_CONTROL); | |
3548 | DUMPREG(DISPC_CONFIG); | |
3549 | DUMPREG(DISPC_CAPABLE); | |
80c39712 TV |
3550 | DUMPREG(DISPC_LINE_STATUS); |
3551 | DUMPREG(DISPC_LINE_NUMBER); | |
11354dd5 AT |
3552 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
3553 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 3554 | DUMPREG(DISPC_GLOBAL_ALPHA); |
2a205f34 SS |
3555 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
3556 | DUMPREG(DISPC_CONTROL2); | |
3557 | DUMPREG(DISPC_CONFIG2); | |
5010be80 | 3558 | } |
6f1891fc CM |
3559 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
3560 | DUMPREG(DISPC_CONTROL3); | |
3561 | DUMPREG(DISPC_CONFIG3); | |
3562 | } | |
29fceeeb TV |
3563 | if (dss_has_feature(FEAT_MFLAG)) |
3564 | DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); | |
5010be80 AT |
3565 | |
3566 | #undef DUMPREG | |
3567 | ||
3568 | #define DISPC_REG(i, name) name(i) | |
4dd2da15 | 3569 | #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ |
311d5ce8 | 3570 | (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ |
5010be80 AT |
3571 | dispc_read_reg(DISPC_REG(i, r))) |
3572 | ||
4dd2da15 | 3573 | p_names = mgr_names; |
5010be80 | 3574 | |
4dd2da15 AT |
3575 | /* DISPC channel specific registers */ |
3576 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { | |
3577 | DUMPREG(i, DISPC_DEFAULT_COLOR); | |
3578 | DUMPREG(i, DISPC_TRANS_COLOR); | |
3579 | DUMPREG(i, DISPC_SIZE_MGR); | |
80c39712 | 3580 | |
4dd2da15 AT |
3581 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
3582 | continue; | |
5010be80 | 3583 | |
4dd2da15 AT |
3584 | DUMPREG(i, DISPC_TIMING_H); |
3585 | DUMPREG(i, DISPC_TIMING_V); | |
3586 | DUMPREG(i, DISPC_POL_FREQ); | |
3587 | DUMPREG(i, DISPC_DIVISORo); | |
5010be80 | 3588 | |
4dd2da15 AT |
3589 | DUMPREG(i, DISPC_DATA_CYCLE1); |
3590 | DUMPREG(i, DISPC_DATA_CYCLE2); | |
3591 | DUMPREG(i, DISPC_DATA_CYCLE3); | |
2a205f34 | 3592 | |
332e9d70 | 3593 | if (dss_has_feature(FEAT_CPR)) { |
4dd2da15 AT |
3594 | DUMPREG(i, DISPC_CPR_COEF_R); |
3595 | DUMPREG(i, DISPC_CPR_COEF_G); | |
3596 | DUMPREG(i, DISPC_CPR_COEF_B); | |
332e9d70 | 3597 | } |
2a205f34 | 3598 | } |
80c39712 | 3599 | |
4dd2da15 AT |
3600 | p_names = ovl_names; |
3601 | ||
3602 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { | |
3603 | DUMPREG(i, DISPC_OVL_BA0); | |
3604 | DUMPREG(i, DISPC_OVL_BA1); | |
3605 | DUMPREG(i, DISPC_OVL_POSITION); | |
3606 | DUMPREG(i, DISPC_OVL_SIZE); | |
3607 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); | |
3608 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); | |
3609 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); | |
3610 | DUMPREG(i, DISPC_OVL_ROW_INC); | |
3611 | DUMPREG(i, DISPC_OVL_PIXEL_INC); | |
aba837a2 | 3612 | |
4dd2da15 AT |
3613 | if (dss_has_feature(FEAT_PRELOAD)) |
3614 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
aba837a2 TV |
3615 | if (dss_has_feature(FEAT_MFLAG)) |
3616 | DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); | |
4dd2da15 AT |
3617 | |
3618 | if (i == OMAP_DSS_GFX) { | |
3619 | DUMPREG(i, DISPC_OVL_WINDOW_SKIP); | |
3620 | DUMPREG(i, DISPC_OVL_TABLE_BA); | |
3621 | continue; | |
3622 | } | |
3623 | ||
3624 | DUMPREG(i, DISPC_OVL_FIR); | |
3625 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); | |
3626 | DUMPREG(i, DISPC_OVL_ACCU0); | |
3627 | DUMPREG(i, DISPC_OVL_ACCU1); | |
3628 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3629 | DUMPREG(i, DISPC_OVL_BA0_UV); | |
3630 | DUMPREG(i, DISPC_OVL_BA1_UV); | |
3631 | DUMPREG(i, DISPC_OVL_FIR2); | |
3632 | DUMPREG(i, DISPC_OVL_ACCU2_0); | |
3633 | DUMPREG(i, DISPC_OVL_ACCU2_1); | |
3634 | } | |
3635 | if (dss_has_feature(FEAT_ATTR2)) | |
3636 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | |
ab5ca071 | 3637 | } |
5010be80 | 3638 | |
20efbc35 | 3639 | if (dispc.feat->has_writeback) { |
06c525fe TV |
3640 | i = OMAP_DSS_WB; |
3641 | DUMPREG(i, DISPC_OVL_BA0); | |
3642 | DUMPREG(i, DISPC_OVL_BA1); | |
3643 | DUMPREG(i, DISPC_OVL_SIZE); | |
3644 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); | |
3645 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); | |
3646 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); | |
3647 | DUMPREG(i, DISPC_OVL_ROW_INC); | |
3648 | DUMPREG(i, DISPC_OVL_PIXEL_INC); | |
3649 | ||
3650 | if (dss_has_feature(FEAT_MFLAG)) | |
3651 | DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); | |
3652 | ||
3653 | DUMPREG(i, DISPC_OVL_FIR); | |
3654 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); | |
3655 | DUMPREG(i, DISPC_OVL_ACCU0); | |
3656 | DUMPREG(i, DISPC_OVL_ACCU1); | |
3657 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3658 | DUMPREG(i, DISPC_OVL_BA0_UV); | |
3659 | DUMPREG(i, DISPC_OVL_BA1_UV); | |
3660 | DUMPREG(i, DISPC_OVL_FIR2); | |
3661 | DUMPREG(i, DISPC_OVL_ACCU2_0); | |
3662 | DUMPREG(i, DISPC_OVL_ACCU2_1); | |
3663 | } | |
3664 | if (dss_has_feature(FEAT_ATTR2)) | |
3665 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | |
3666 | } | |
3667 | ||
5010be80 AT |
3668 | #undef DISPC_REG |
3669 | #undef DUMPREG | |
3670 | ||
3671 | #define DISPC_REG(plane, name, i) name(plane, i) | |
3672 | #define DUMPREG(plane, name, i) \ | |
4dd2da15 | 3673 | seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ |
311d5ce8 | 3674 | (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ |
5010be80 AT |
3675 | dispc_read_reg(DISPC_REG(plane, name, i))) |
3676 | ||
4dd2da15 | 3677 | /* Video pipeline coefficient registers */ |
332e9d70 | 3678 | |
4dd2da15 AT |
3679 | /* start from OMAP_DSS_VIDEO1 */ |
3680 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { | |
3681 | for (j = 0; j < 8; j++) | |
3682 | DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); | |
9b372c2d | 3683 | |
4dd2da15 AT |
3684 | for (j = 0; j < 8; j++) |
3685 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); | |
5010be80 | 3686 | |
4dd2da15 AT |
3687 | for (j = 0; j < 5; j++) |
3688 | DUMPREG(i, DISPC_OVL_CONV_COEF, j); | |
ab5ca071 | 3689 | |
4dd2da15 AT |
3690 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
3691 | for (j = 0; j < 8; j++) | |
3692 | DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); | |
3693 | } | |
3694 | ||
3695 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3696 | for (j = 0; j < 8; j++) | |
3697 | DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); | |
3698 | ||
3699 | for (j = 0; j < 8; j++) | |
3700 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); | |
3701 | ||
3702 | for (j = 0; j < 8; j++) | |
3703 | DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); | |
3704 | } | |
332e9d70 | 3705 | } |
80c39712 | 3706 | |
4fbafaf3 | 3707 | dispc_runtime_put(); |
5010be80 AT |
3708 | |
3709 | #undef DISPC_REG | |
80c39712 TV |
3710 | #undef DUMPREG |
3711 | } | |
3712 | ||
80c39712 TV |
3713 | /* calculate clock rates using dividers in cinfo */ |
3714 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, | |
80c39712 TV |
3715 | struct dispc_clock_info *cinfo) |
3716 | { | |
80c39712 TV |
3717 | if (cinfo->lck_div > 255 || cinfo->lck_div == 0) |
3718 | return -EINVAL; | |
9eaaf207 | 3719 | if (cinfo->pck_div < 1 || cinfo->pck_div > 255) |
80c39712 | 3720 | return -EINVAL; |
80c39712 | 3721 | |
80c39712 TV |
3722 | cinfo->lck = dispc_fclk_rate / cinfo->lck_div; |
3723 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
9eaaf207 | 3724 | |
80c39712 TV |
3725 | return 0; |
3726 | } | |
80c39712 | 3727 | |
7c284e6e TV |
3728 | bool dispc_div_calc(unsigned long dispc, |
3729 | unsigned long pck_min, unsigned long pck_max, | |
3730 | dispc_div_calc_func func, void *data) | |
3731 | { | |
3732 | int lckd, lckd_start, lckd_stop; | |
3733 | int pckd, pckd_start, pckd_stop; | |
3734 | unsigned long pck, lck; | |
3735 | unsigned long lck_max; | |
3736 | unsigned long pckd_hw_min, pckd_hw_max; | |
3737 | unsigned min_fck_per_pck; | |
3738 | unsigned long fck; | |
80c39712 | 3739 | |
7c284e6e TV |
3740 | #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK |
3741 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
3742 | #else | |
3743 | min_fck_per_pck = 0; | |
3744 | #endif | |
80c39712 | 3745 | |
7c284e6e TV |
3746 | pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); |
3747 | pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); | |
80c39712 | 3748 | |
7c284e6e | 3749 | lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
80c39712 | 3750 | |
7c284e6e TV |
3751 | pck_min = pck_min ? pck_min : 1; |
3752 | pck_max = pck_max ? pck_max : ULONG_MAX; | |
80c39712 | 3753 | |
7c284e6e TV |
3754 | lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); |
3755 | lckd_stop = min(dispc / pck_min, 255ul); | |
80c39712 | 3756 | |
7c284e6e TV |
3757 | for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { |
3758 | lck = dispc / lckd; | |
80c39712 | 3759 | |
7c284e6e TV |
3760 | pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); |
3761 | pckd_stop = min(lck / pck_min, pckd_hw_max); | |
80c39712 | 3762 | |
7c284e6e TV |
3763 | for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { |
3764 | pck = lck / pckd; | |
80c39712 | 3765 | |
7c284e6e TV |
3766 | /* |
3767 | * For OMAP2/3 the DISPC fclk is the same as LCD's logic | |
3768 | * clock, which means we're configuring DISPC fclk here | |
3769 | * also. Thus we need to use the calculated lck. For | |
3770 | * OMAP4+ the DISPC fclk is a separate clock. | |
3771 | */ | |
3772 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
3773 | fck = dispc_core_clk_rate(); | |
3774 | else | |
3775 | fck = lck; | |
3776 | ||
3777 | if (fck < pck * min_fck_per_pck) | |
3778 | continue; | |
3779 | ||
3780 | if (func(lckd, pckd, lck, pck, data)) | |
3781 | return true; | |
3782 | } | |
3783 | } | |
3784 | ||
3785 | return false; | |
80c39712 TV |
3786 | } |
3787 | ||
f0d08f89 | 3788 | void dispc_mgr_set_clock_div(enum omap_channel channel, |
a8f3fcd1 | 3789 | const struct dispc_clock_info *cinfo) |
80c39712 TV |
3790 | { |
3791 | DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); | |
3792 | DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); | |
3793 | ||
26d9dd0d | 3794 | dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); |
80c39712 TV |
3795 | } |
3796 | ||
26d9dd0d | 3797 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
ff1b2cde | 3798 | struct dispc_clock_info *cinfo) |
80c39712 TV |
3799 | { |
3800 | unsigned long fck; | |
3801 | ||
3802 | fck = dispc_fclk_rate(); | |
3803 | ||
ce7fa5eb MR |
3804 | cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); |
3805 | cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); | |
80c39712 TV |
3806 | |
3807 | cinfo->lck = fck / cinfo->lck_div; | |
3808 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
3809 | ||
3810 | return 0; | |
3811 | } | |
3812 | ||
4e0397cf TV |
3813 | u32 dispc_read_irqstatus(void) |
3814 | { | |
3815 | return dispc_read_reg(DISPC_IRQSTATUS); | |
3816 | } | |
348be69d | 3817 | EXPORT_SYMBOL(dispc_read_irqstatus); |
4e0397cf TV |
3818 | |
3819 | void dispc_clear_irqstatus(u32 mask) | |
3820 | { | |
3821 | dispc_write_reg(DISPC_IRQSTATUS, mask); | |
3822 | } | |
348be69d | 3823 | EXPORT_SYMBOL(dispc_clear_irqstatus); |
4e0397cf TV |
3824 | |
3825 | u32 dispc_read_irqenable(void) | |
3826 | { | |
3827 | return dispc_read_reg(DISPC_IRQENABLE); | |
3828 | } | |
348be69d | 3829 | EXPORT_SYMBOL(dispc_read_irqenable); |
4e0397cf TV |
3830 | |
3831 | void dispc_write_irqenable(u32 mask) | |
3832 | { | |
3833 | u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); | |
3834 | ||
3835 | /* clear the irqstatus for newly enabled irqs */ | |
3836 | dispc_clear_irqstatus((mask ^ old_mask) & mask); | |
3837 | ||
3838 | dispc_write_reg(DISPC_IRQENABLE, mask); | |
3839 | } | |
348be69d | 3840 | EXPORT_SYMBOL(dispc_write_irqenable); |
4e0397cf | 3841 | |
80c39712 TV |
3842 | void dispc_enable_sidle(void) |
3843 | { | |
3844 | REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ | |
3845 | } | |
3846 | ||
3847 | void dispc_disable_sidle(void) | |
3848 | { | |
3849 | REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ | |
3850 | } | |
3851 | ||
3852 | static void _omap_dispc_initial_config(void) | |
3853 | { | |
3854 | u32 l; | |
3855 | ||
0cf35df3 MR |
3856 | /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ |
3857 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { | |
3858 | l = dispc_read_reg(DISPC_DIVISOR); | |
3859 | /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ | |
3860 | l = FLD_MOD(l, 1, 0, 0); | |
3861 | l = FLD_MOD(l, 1, 23, 16); | |
3862 | dispc_write_reg(DISPC_DIVISOR, l); | |
7b3926b3 TV |
3863 | |
3864 | dispc.core_clk_rate = dispc_fclk_rate(); | |
0cf35df3 MR |
3865 | } |
3866 | ||
80c39712 | 3867 | /* FUNCGATED */ |
6ced40bf AT |
3868 | if (dss_has_feature(FEAT_FUNCGATED)) |
3869 | REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); | |
80c39712 | 3870 | |
6e5264b0 | 3871 | dispc_setup_color_conv_coef(); |
80c39712 TV |
3872 | |
3873 | dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); | |
3874 | ||
42a6961c | 3875 | dispc_init_fifos(); |
5ed8cf5b TV |
3876 | |
3877 | dispc_configure_burst_sizes(); | |
54128701 AT |
3878 | |
3879 | dispc_ovl_enable_zorder_planes(); | |
d0df9a2c AT |
3880 | |
3881 | if (dispc.feat->mstandby_workaround) | |
3882 | REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); | |
c64aa3a6 TV |
3883 | |
3884 | if (dss_has_feature(FEAT_MFLAG)) | |
3885 | dispc_init_mflag(); | |
80c39712 TV |
3886 | } |
3887 | ||
ede92695 | 3888 | static const struct dispc_features omap24xx_dispc_feats = { |
dcbe765b CM |
3889 | .sw_start = 5, |
3890 | .fp_start = 15, | |
3891 | .bp_start = 27, | |
3892 | .sw_max = 64, | |
3893 | .vp_max = 255, | |
3894 | .hp_max = 256, | |
33b89928 AT |
3895 | .mgr_width_start = 10, |
3896 | .mgr_height_start = 26, | |
3897 | .mgr_width_max = 2048, | |
3898 | .mgr_height_max = 2048, | |
ca5ca69c | 3899 | .max_lcd_pclk = 66500000, |
dcbe765b CM |
3900 | .calc_scaling = dispc_ovl_calc_scaling_24xx, |
3901 | .calc_core_clk = calc_core_clk_24xx, | |
42a6961c | 3902 | .num_fifos = 3, |
cffa947d | 3903 | .no_framedone_tv = true, |
8bc65552 | 3904 | .set_max_preload = false, |
f2aee319 | 3905 | .last_pixel_inc_missing = true, |
dcbe765b CM |
3906 | }; |
3907 | ||
ede92695 | 3908 | static const struct dispc_features omap34xx_rev1_0_dispc_feats = { |
dcbe765b CM |
3909 | .sw_start = 5, |
3910 | .fp_start = 15, | |
3911 | .bp_start = 27, | |
3912 | .sw_max = 64, | |
3913 | .vp_max = 255, | |
3914 | .hp_max = 256, | |
33b89928 AT |
3915 | .mgr_width_start = 10, |
3916 | .mgr_height_start = 26, | |
3917 | .mgr_width_max = 2048, | |
3918 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3919 | .max_lcd_pclk = 173000000, |
3920 | .max_tv_pclk = 59000000, | |
dcbe765b CM |
3921 | .calc_scaling = dispc_ovl_calc_scaling_34xx, |
3922 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3923 | .num_fifos = 3, |
cffa947d | 3924 | .no_framedone_tv = true, |
8bc65552 | 3925 | .set_max_preload = false, |
f2aee319 | 3926 | .last_pixel_inc_missing = true, |
dcbe765b CM |
3927 | }; |
3928 | ||
ede92695 | 3929 | static const struct dispc_features omap34xx_rev3_0_dispc_feats = { |
dcbe765b CM |
3930 | .sw_start = 7, |
3931 | .fp_start = 19, | |
3932 | .bp_start = 31, | |
3933 | .sw_max = 256, | |
3934 | .vp_max = 4095, | |
3935 | .hp_max = 4096, | |
33b89928 AT |
3936 | .mgr_width_start = 10, |
3937 | .mgr_height_start = 26, | |
3938 | .mgr_width_max = 2048, | |
3939 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3940 | .max_lcd_pclk = 173000000, |
3941 | .max_tv_pclk = 59000000, | |
dcbe765b CM |
3942 | .calc_scaling = dispc_ovl_calc_scaling_34xx, |
3943 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3944 | .num_fifos = 3, |
cffa947d | 3945 | .no_framedone_tv = true, |
8bc65552 | 3946 | .set_max_preload = false, |
f2aee319 | 3947 | .last_pixel_inc_missing = true, |
dcbe765b CM |
3948 | }; |
3949 | ||
ede92695 | 3950 | static const struct dispc_features omap44xx_dispc_feats = { |
dcbe765b CM |
3951 | .sw_start = 7, |
3952 | .fp_start = 19, | |
3953 | .bp_start = 31, | |
3954 | .sw_max = 256, | |
3955 | .vp_max = 4095, | |
3956 | .hp_max = 4096, | |
33b89928 AT |
3957 | .mgr_width_start = 10, |
3958 | .mgr_height_start = 26, | |
3959 | .mgr_width_max = 2048, | |
3960 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3961 | .max_lcd_pclk = 170000000, |
3962 | .max_tv_pclk = 185625000, | |
dcbe765b CM |
3963 | .calc_scaling = dispc_ovl_calc_scaling_44xx, |
3964 | .calc_core_clk = calc_core_clk_44xx, | |
42a6961c | 3965 | .num_fifos = 5, |
66a0f9e4 | 3966 | .gfx_fifo_workaround = true, |
8bc65552 | 3967 | .set_max_preload = true, |
e5f80917 | 3968 | .supports_sync_align = true, |
20efbc35 | 3969 | .has_writeback = true, |
3a38ed53 | 3970 | .supports_double_pixel = true, |
b7536d67 | 3971 | .reverse_ilace_field_order = true, |
dcbe765b CM |
3972 | }; |
3973 | ||
ede92695 | 3974 | static const struct dispc_features omap54xx_dispc_feats = { |
264236f8 AT |
3975 | .sw_start = 7, |
3976 | .fp_start = 19, | |
3977 | .bp_start = 31, | |
3978 | .sw_max = 256, | |
3979 | .vp_max = 4095, | |
3980 | .hp_max = 4096, | |
3981 | .mgr_width_start = 11, | |
3982 | .mgr_height_start = 27, | |
3983 | .mgr_width_max = 4096, | |
3984 | .mgr_height_max = 4096, | |
ca5ca69c AT |
3985 | .max_lcd_pclk = 170000000, |
3986 | .max_tv_pclk = 186000000, | |
264236f8 AT |
3987 | .calc_scaling = dispc_ovl_calc_scaling_44xx, |
3988 | .calc_core_clk = calc_core_clk_44xx, | |
3989 | .num_fifos = 5, | |
3990 | .gfx_fifo_workaround = true, | |
d0df9a2c | 3991 | .mstandby_workaround = true, |
8bc65552 | 3992 | .set_max_preload = true, |
e5f80917 | 3993 | .supports_sync_align = true, |
20efbc35 | 3994 | .has_writeback = true, |
3a38ed53 | 3995 | .supports_double_pixel = true, |
b7536d67 | 3996 | .reverse_ilace_field_order = true, |
264236f8 AT |
3997 | }; |
3998 | ||
ede92695 | 3999 | static int dispc_init_features(struct platform_device *pdev) |
dcbe765b CM |
4000 | { |
4001 | const struct dispc_features *src; | |
4002 | struct dispc_features *dst; | |
4003 | ||
84b47623 | 4004 | dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); |
dcbe765b | 4005 | if (!dst) { |
84b47623 | 4006 | dev_err(&pdev->dev, "Failed to allocate DISPC Features\n"); |
dcbe765b CM |
4007 | return -ENOMEM; |
4008 | } | |
4009 | ||
b2c7d54f | 4010 | switch (omapdss_get_version()) { |
84b47623 | 4011 | case OMAPDSS_VER_OMAP24xx: |
dcbe765b | 4012 | src = &omap24xx_dispc_feats; |
84b47623 TV |
4013 | break; |
4014 | ||
4015 | case OMAPDSS_VER_OMAP34xx_ES1: | |
4016 | src = &omap34xx_rev1_0_dispc_feats; | |
4017 | break; | |
4018 | ||
4019 | case OMAPDSS_VER_OMAP34xx_ES3: | |
4020 | case OMAPDSS_VER_OMAP3630: | |
4021 | case OMAPDSS_VER_AM35xx: | |
d6279d4a | 4022 | case OMAPDSS_VER_AM43xx: |
84b47623 TV |
4023 | src = &omap34xx_rev3_0_dispc_feats; |
4024 | break; | |
4025 | ||
4026 | case OMAPDSS_VER_OMAP4430_ES1: | |
4027 | case OMAPDSS_VER_OMAP4430_ES2: | |
4028 | case OMAPDSS_VER_OMAP4: | |
dcbe765b | 4029 | src = &omap44xx_dispc_feats; |
84b47623 TV |
4030 | break; |
4031 | ||
4032 | case OMAPDSS_VER_OMAP5: | |
93550927 | 4033 | case OMAPDSS_VER_DRA7xx: |
264236f8 | 4034 | src = &omap54xx_dispc_feats; |
84b47623 TV |
4035 | break; |
4036 | ||
4037 | default: | |
dcbe765b CM |
4038 | return -ENODEV; |
4039 | } | |
4040 | ||
4041 | memcpy(dst, src, sizeof(*dst)); | |
4042 | dispc.feat = dst; | |
4043 | ||
4044 | return 0; | |
4045 | } | |
4046 | ||
0925afc9 TV |
4047 | static irqreturn_t dispc_irq_handler(int irq, void *arg) |
4048 | { | |
4049 | if (!dispc.is_enabled) | |
4050 | return IRQ_NONE; | |
4051 | ||
4052 | return dispc.user_handler(irq, dispc.user_data); | |
4053 | } | |
4054 | ||
96e2e637 TV |
4055 | int dispc_request_irq(irq_handler_t handler, void *dev_id) |
4056 | { | |
0925afc9 TV |
4057 | int r; |
4058 | ||
4059 | if (dispc.user_handler != NULL) | |
4060 | return -EBUSY; | |
4061 | ||
4062 | dispc.user_handler = handler; | |
4063 | dispc.user_data = dev_id; | |
4064 | ||
4065 | /* ensure the dispc_irq_handler sees the values above */ | |
4066 | smp_wmb(); | |
4067 | ||
4068 | r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, | |
4069 | IRQF_SHARED, "OMAP DISPC", &dispc); | |
4070 | if (r) { | |
4071 | dispc.user_handler = NULL; | |
4072 | dispc.user_data = NULL; | |
4073 | } | |
4074 | ||
4075 | return r; | |
96e2e637 | 4076 | } |
348be69d | 4077 | EXPORT_SYMBOL(dispc_request_irq); |
96e2e637 TV |
4078 | |
4079 | void dispc_free_irq(void *dev_id) | |
4080 | { | |
0925afc9 TV |
4081 | devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); |
4082 | ||
4083 | dispc.user_handler = NULL; | |
4084 | dispc.user_data = NULL; | |
96e2e637 | 4085 | } |
348be69d | 4086 | EXPORT_SYMBOL(dispc_free_irq); |
96e2e637 | 4087 | |
060b6d9c | 4088 | /* DISPC HW IP initialisation */ |
736e60dd | 4089 | static int dispc_bind(struct device *dev, struct device *master, void *data) |
060b6d9c | 4090 | { |
736e60dd | 4091 | struct platform_device *pdev = to_platform_device(dev); |
060b6d9c | 4092 | u32 rev; |
affe360d | 4093 | int r = 0; |
ea9da36a | 4094 | struct resource *dispc_mem; |
0006fd63 | 4095 | struct device_node *np = pdev->dev.of_node; |
ea9da36a | 4096 | |
060b6d9c SG |
4097 | dispc.pdev = pdev; |
4098 | ||
d49cd155 TV |
4099 | spin_lock_init(&dispc.control_lock); |
4100 | ||
84b47623 | 4101 | r = dispc_init_features(dispc.pdev); |
dcbe765b CM |
4102 | if (r) |
4103 | return r; | |
4104 | ||
ea9da36a SG |
4105 | dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); |
4106 | if (!dispc_mem) { | |
4107 | DSSERR("can't get IORESOURCE_MEM DISPC\n"); | |
cd3b3449 | 4108 | return -EINVAL; |
ea9da36a | 4109 | } |
cd3b3449 | 4110 | |
6e2a14d2 JL |
4111 | dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, |
4112 | resource_size(dispc_mem)); | |
060b6d9c SG |
4113 | if (!dispc.base) { |
4114 | DSSERR("can't ioremap DISPC\n"); | |
cd3b3449 | 4115 | return -ENOMEM; |
affe360d | 4116 | } |
cd3b3449 | 4117 | |
affe360d | 4118 | dispc.irq = platform_get_irq(dispc.pdev, 0); |
4119 | if (dispc.irq < 0) { | |
4120 | DSSERR("platform_get_irq failed\n"); | |
cd3b3449 | 4121 | return -ENODEV; |
affe360d | 4122 | } |
4123 | ||
0006fd63 TV |
4124 | if (np && of_property_read_bool(np, "syscon-pol")) { |
4125 | dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); | |
4126 | if (IS_ERR(dispc.syscon_pol)) { | |
4127 | dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); | |
4128 | return PTR_ERR(dispc.syscon_pol); | |
4129 | } | |
4130 | ||
4131 | if (of_property_read_u32_index(np, "syscon-pol", 1, | |
4132 | &dispc.syscon_pol_offset)) { | |
4133 | dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); | |
4134 | return -EINVAL; | |
4135 | } | |
4136 | } | |
4137 | ||
4fbafaf3 TV |
4138 | pm_runtime_enable(&pdev->dev); |
4139 | ||
4140 | r = dispc_runtime_get(); | |
4141 | if (r) | |
4142 | goto err_runtime_get; | |
060b6d9c SG |
4143 | |
4144 | _omap_dispc_initial_config(); | |
4145 | ||
060b6d9c | 4146 | rev = dispc_read_reg(DISPC_REVISION); |
a06b62f8 | 4147 | dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", |
060b6d9c SG |
4148 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
4149 | ||
4fbafaf3 | 4150 | dispc_runtime_put(); |
060b6d9c | 4151 | |
04b1fc02 TV |
4152 | dss_init_overlay_managers(); |
4153 | ||
e40402cf TV |
4154 | dss_debugfs_create_file("dispc", dispc_dump_regs); |
4155 | ||
060b6d9c | 4156 | return 0; |
4fbafaf3 TV |
4157 | |
4158 | err_runtime_get: | |
4159 | pm_runtime_disable(&pdev->dev); | |
affe360d | 4160 | return r; |
060b6d9c SG |
4161 | } |
4162 | ||
736e60dd TV |
4163 | static void dispc_unbind(struct device *dev, struct device *master, |
4164 | void *data) | |
060b6d9c | 4165 | { |
736e60dd | 4166 | pm_runtime_disable(dev); |
4fbafaf3 | 4167 | |
04b1fc02 | 4168 | dss_uninit_overlay_managers(); |
736e60dd TV |
4169 | } |
4170 | ||
4171 | static const struct component_ops dispc_component_ops = { | |
4172 | .bind = dispc_bind, | |
4173 | .unbind = dispc_unbind, | |
4174 | }; | |
04b1fc02 | 4175 | |
736e60dd TV |
4176 | static int dispc_probe(struct platform_device *pdev) |
4177 | { | |
4178 | return component_add(&pdev->dev, &dispc_component_ops); | |
4179 | } | |
4180 | ||
4181 | static int dispc_remove(struct platform_device *pdev) | |
4182 | { | |
4183 | component_del(&pdev->dev, &dispc_component_ops); | |
060b6d9c SG |
4184 | return 0; |
4185 | } | |
4186 | ||
4fbafaf3 TV |
4187 | static int dispc_runtime_suspend(struct device *dev) |
4188 | { | |
0925afc9 TV |
4189 | dispc.is_enabled = false; |
4190 | /* ensure the dispc_irq_handler sees the is_enabled value */ | |
4191 | smp_wmb(); | |
4192 | /* wait for current handler to finish before turning the DISPC off */ | |
4193 | synchronize_irq(dispc.irq); | |
4194 | ||
4fbafaf3 | 4195 | dispc_save_context(); |
4fbafaf3 TV |
4196 | |
4197 | return 0; | |
4198 | } | |
4199 | ||
4200 | static int dispc_runtime_resume(struct device *dev) | |
4201 | { | |
9229b516 TV |
4202 | /* |
4203 | * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) | |
4204 | * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in | |
4205 | * _omap_dispc_initial_config(). We can thus use it to detect if | |
4206 | * we have lost register context. | |
4207 | */ | |
0925afc9 TV |
4208 | if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { |
4209 | _omap_dispc_initial_config(); | |
9229b516 | 4210 | |
0925afc9 TV |
4211 | dispc_restore_context(); |
4212 | } | |
be07dcd7 | 4213 | |
0925afc9 TV |
4214 | dispc.is_enabled = true; |
4215 | /* ensure the dispc_irq_handler sees the is_enabled value */ | |
4216 | smp_wmb(); | |
4fbafaf3 TV |
4217 | |
4218 | return 0; | |
4219 | } | |
4220 | ||
4221 | static const struct dev_pm_ops dispc_pm_ops = { | |
4222 | .runtime_suspend = dispc_runtime_suspend, | |
4223 | .runtime_resume = dispc_runtime_resume, | |
4224 | }; | |
4225 | ||
d7977f88 TV |
4226 | static const struct of_device_id dispc_of_match[] = { |
4227 | { .compatible = "ti,omap2-dispc", }, | |
4228 | { .compatible = "ti,omap3-dispc", }, | |
4229 | { .compatible = "ti,omap4-dispc", }, | |
2e7e6b68 | 4230 | { .compatible = "ti,omap5-dispc", }, |
93550927 | 4231 | { .compatible = "ti,dra7-dispc", }, |
d7977f88 TV |
4232 | {}, |
4233 | }; | |
4234 | ||
060b6d9c | 4235 | static struct platform_driver omap_dispchw_driver = { |
736e60dd TV |
4236 | .probe = dispc_probe, |
4237 | .remove = dispc_remove, | |
060b6d9c SG |
4238 | .driver = { |
4239 | .name = "omapdss_dispc", | |
4fbafaf3 | 4240 | .pm = &dispc_pm_ops, |
d7977f88 | 4241 | .of_match_table = dispc_of_match, |
422ccbd5 | 4242 | .suppress_bind_attrs = true, |
060b6d9c SG |
4243 | }, |
4244 | }; | |
4245 | ||
6e7e8f06 | 4246 | int __init dispc_init_platform_driver(void) |
060b6d9c | 4247 | { |
736e60dd | 4248 | return platform_driver_register(&omap_dispchw_driver); |
060b6d9c SG |
4249 | } |
4250 | ||
ede92695 | 4251 | void dispc_uninit_platform_driver(void) |
060b6d9c | 4252 | { |
04c742c3 | 4253 | platform_driver_unregister(&omap_dispchw_driver); |
060b6d9c | 4254 | } |