[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / dss.h

/*
 * linux/drivers/video/omap2/dss/dss.h
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OMAP2_DSS_H
#define __OMAP2_DSS_H

#include <linux/interrupt.h>

#include "omapdss.h"

#ifdef pr_fmt
#undef pr_fmt
#endif

#ifdef DSS_SUBSYS_NAME
#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
#else
#define pr_fmt(fmt) fmt
#endif

#define DSSDBG(format, ...) \
	pr_debug(format, ## __VA_ARGS__)

#ifdef DSS_SUBSYS_NAME
#define DSSERR(format, ...) \
	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
	## __VA_ARGS__)
#else
#define DSSERR(format, ...) \
	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSINFO(format, ...) \
	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
	## __VA_ARGS__)
#else
#define DSSINFO(format, ...) \
	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSWARN(format, ...) \
	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
	## __VA_ARGS__)
#else
#define DSSWARN(format, ...) \
	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
#endif

/* OMAP TRM gives bitfields as start:end, where start is the higher bit
   number. For example 7:0 */
#define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
#define FLD_MOD(orig, val, start, end) \
	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))

enum dss_io_pad_mode {
	DSS_IO_PAD_MODE_RESET,
	DSS_IO_PAD_MODE_RFBI,
	DSS_IO_PAD_MODE_BYPASS,
};

enum dss_hdmi_venc_clk_source_select {
	DSS_VENC_TV_CLK = 0,
	DSS_HDMI_M_PCLK = 1,
};

enum dss_dsi_content_type {
	DSS_DSI_CONTENT_DCS,
	DSS_DSI_CONTENT_GENERIC,
};

enum dss_writeback_channel {
	DSS_WB_LCD1_MGR =	0,
	DSS_WB_LCD2_MGR =	1,
	DSS_WB_TV_MGR =		2,
	DSS_WB_OVL0 =		3,
	DSS_WB_OVL1 =		4,
	DSS_WB_OVL2 =		5,
	DSS_WB_OVL3 =		6,
	DSS_WB_LCD3_MGR =	7,
};

enum dss_pll_id {
	DSS_PLL_DSI1,
	DSS_PLL_DSI2,
	DSS_PLL_HDMI,
	DSS_PLL_VIDEO1,
	DSS_PLL_VIDEO2,
};

struct dss_pll;

#define DSS_PLL_MAX_HSDIVS 4

/*
 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 * Type-B PLLs: clkout[0] refers to m2.
 */
struct dss_pll_clock_info {
	/* rates that we get with dividers below */
	unsigned long fint;
	unsigned long clkdco;
	unsigned long clkout[DSS_PLL_MAX_HSDIVS];

	/* dividers */
	u16 n;
	u16 m;
	u32 mf;
	u16 mX[DSS_PLL_MAX_HSDIVS];
	u16 sd;
};

struct dss_pll_ops {
	int (*enable)(struct dss_pll *pll);
	void (*disable)(struct dss_pll *pll);
	int (*set_config)(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
};

struct dss_pll_hw {
	unsigned n_max;
	unsigned m_min;
	unsigned m_max;
	unsigned mX_max;

	unsigned long fint_min, fint_max;
	unsigned long clkdco_min, clkdco_low, clkdco_max;

	u8 n_msb, n_lsb;
	u8 m_msb, m_lsb;
	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];

	bool has_stopmode;
	bool has_freqsel;
	bool has_selfreqdco;
	bool has_refsel;
};

struct dss_pll {
	const char *name;
	enum dss_pll_id id;

	struct clk *clkin;
	struct regulator *regulator;

	void __iomem *base;

	const struct dss_pll_hw *hw;

	const struct dss_pll_ops *ops;

	struct dss_pll_clock_info cinfo;
};

struct dispc_clock_info {
	/* rates that we get with dividers below */
	unsigned long lck;
	unsigned long pck;

	/* dividers */
	u16 lck_div;
	u16 pck_div;
};

struct dss_lcd_mgr_config {
	enum dss_io_pad_mode io_pad_mode;

	bool stallmode;
	bool fifohandcheck;

	struct dispc_clock_info clock_info;

	int video_port_width;

	int lcden_sig_polarity;
};

struct seq_file;
struct platform_device;

/* core */
struct platform_device *dss_get_core_pdev(void);
int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));

/* display */
int display_init_sysfs(struct platform_device *pdev);
void display_uninit_sysfs(struct platform_device *pdev);

/* manager */
int dss_init_overlay_managers(void);
void dss_uninit_overlay_managers(void);
int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
		const struct omap_overlay_manager_info *info);
int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
		const struct omap_video_timings *timings);
int dss_mgr_check(struct omap_overlay_manager *mgr,
		struct omap_overlay_manager_info *info,
		const struct omap_video_timings *mgr_timings,
		const struct dss_lcd_mgr_config *config,
		struct omap_overlay_info **overlay_infos);

static inline bool dss_mgr_is_lcd(enum omap_channel id)
{
	if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
			id == OMAP_DSS_CHANNEL_LCD3)
		return true;
	else
		return false;
}

int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
		struct platform_device *pdev);
void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);

/* overlay */
void dss_init_overlays(struct platform_device *pdev);
void dss_uninit_overlays(struct platform_device *pdev);
void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
int dss_ovl_simple_check(struct omap_overlay *ovl,
		const struct omap_overlay_info *info);
int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
		const struct omap_video_timings *mgr_timings);
bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
		enum omap_color_mode mode);
int dss_overlay_kobj_init(struct omap_overlay *ovl,
		struct platform_device *pdev);
void dss_overlay_kobj_uninit(struct omap_overlay *ovl);

/* DSS */
int dss_init_platform_driver(void) __init;
void dss_uninit_platform_driver(void);

int dss_runtime_get(void);
void dss_runtime_put(void);

unsigned long dss_get_dispc_clk_rate(void);
int dss_dpi_select_source(int port, enum omap_channel channel);
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
void dss_dump_clocks(struct seq_file *s);

/* DSS VIDEO PLL */
struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
	struct regulator *regulator);
void dss_video_pll_uninit(struct dss_pll *pll);

/* dss-of */
struct device_node *dss_of_port_get_parent_device(struct device_node *port);
u32 dss_of_port_get_port_number(struct device_node *port);

#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
void dss_debug_dump_clocks(struct seq_file *s);
#endif

void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
	enum omap_channel channel);

void dss_sdi_init(int datapairs);
int dss_sdi_enable(void);
void dss_sdi_disable(void);

void dss_select_dsi_clk_source(int dsi_module,
		enum omap_dss_clk_source clk_src);
void dss_select_lcd_clk_source(enum omap_channel channel,
		enum omap_dss_clk_source clk_src);
enum omap_dss_clk_source dss_get_dispc_clk_source(void);
enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);

void dss_set_venc_output(enum omap_dss_venc_type type);
void dss_set_dac_pwrdn_bgz(bool enable);

int dss_set_fck_rate(unsigned long rate);

typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
bool dss_div_calc(unsigned long pck, unsigned long fck_min,
		dss_div_calc_func func, void *data);

/* SDI */
int sdi_init_platform_driver(void) __init;
void sdi_uninit_platform_driver(void);

#ifdef CONFIG_OMAP2_DSS_SDI
int sdi_init_port(struct platform_device *pdev, struct device_node *port);
void sdi_uninit_port(struct device_node *port);
#else
static inline int sdi_init_port(struct platform_device *pdev,
		struct device_node *port)
{
	return 0;
}
static inline void sdi_uninit_port(struct device_node *port)
{
}
#endif

/* DSI */

#ifdef CONFIG_OMAP2_DSS_DSI

struct dentry;
struct file_operations;

int dsi_init_platform_driver(void) __init;
void dsi_uninit_platform_driver(void);

void dsi_dump_clocks(struct seq_file *s);

void dsi_irq_handler(void);
u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);

#else
static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
	WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
	     __func__);
	return 0;
}
#endif

/* DPI */
int dpi_init_platform_driver(void) __init;
void dpi_uninit_platform_driver(void);

#ifdef CONFIG_OMAP2_DSS_DPI
int dpi_init_port(struct platform_device *pdev, struct device_node *port);
void dpi_uninit_port(struct device_node *port);
#else
static inline int dpi_init_port(struct platform_device *pdev,
		struct device_node *port)
{
	return 0;
}
static inline void dpi_uninit_port(struct device_node *port)
{
}
#endif

/* DISPC */
int dispc_init_platform_driver(void) __init;
void dispc_uninit_platform_driver(void);
void dispc_dump_clocks(struct seq_file *s);

void dispc_enable_sidle(void);
void dispc_disable_sidle(void);

void dispc_lcd_enable_signal(bool enable);
void dispc_pck_free_enable(bool enable);
void dispc_enable_fifomerge(bool enable);
void dispc_enable_gamma_table(bool enable);

typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
		unsigned long pck, void *data);
bool dispc_div_calc(unsigned long dispc,
		unsigned long pck_min, unsigned long pck_max,
		dispc_div_calc_func func, void *data);

bool dispc_mgr_timings_ok(enum omap_channel channel,
		const struct omap_video_timings *timings);
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
		struct dispc_clock_info *cinfo);


void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
		u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
		bool manual_update);

void dispc_mgr_set_clock_div(enum omap_channel channel,
		const struct dispc_clock_info *cinfo);
int dispc_mgr_get_clock_div(enum omap_channel channel,
		struct dispc_clock_info *cinfo);
void dispc_set_tv_pclk(unsigned long pclk);

u32 dispc_wb_get_framedone_irq(void);
bool dispc_wb_go_busy(void);
void dispc_wb_go(void);
void dispc_wb_enable(bool enable);
bool dispc_wb_is_enabled(void);
void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
		bool mem_to_mem, const struct omap_video_timings *timings);

/* VENC */
int venc_init_platform_driver(void) __init;
void venc_uninit_platform_driver(void);

/* HDMI */
int hdmi4_init_platform_driver(void) __init;
void hdmi4_uninit_platform_driver(void);

int hdmi5_init_platform_driver(void) __init;
void hdmi5_uninit_platform_driver(void);

/* RFBI */
int rfbi_init_platform_driver(void) __init;
void rfbi_uninit_platform_driver(void);


#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
{
	int b;
	for (b = 0; b < 32; ++b) {
		if (irqstatus & (1 << b))
			irq_arr[b]++;
	}
}
#endif

/* PLL */
typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
		unsigned long clkdco, void *data);
typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
		void *data);

int dss_pll_register(struct dss_pll *pll);
void dss_pll_unregister(struct dss_pll *pll);
struct dss_pll *dss_pll_find(const char *name);
int dss_pll_enable(struct dss_pll *pll);
void dss_pll_disable(struct dss_pll *pll);
int dss_pll_set_config(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);

bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
		unsigned long out_min, unsigned long out_max,
		dss_hsdiv_calc_func func, void *data);
bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
		unsigned long pll_min, unsigned long pll_max,
		dss_pll_calc_func func, void *data);
int dss_pll_write_config_type_a(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_write_config_type_b(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_wait_reset_done(struct dss_pll *pll);

#endif
Commit	Line	Data
559d6701 TV	1	/*
	2	* linux/drivers/video/omap2/dss/dss.h
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* Some code and ideas taken from drivers/video/omap/ driver
	8	* by Imre Deak.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#ifndef __OMAP2_DSS_H
	24	#define __OMAP2_DSS_H
	25
96e2e637 TV	26	#include <linux/interrupt.h>
96e2e637 TV	27
35a339ac TV	28	#include "omapdss.h"
35a339ac TV	29
702d267e CM	30	#ifdef pr_fmt
702d267e CM	31	#undef pr_fmt
559d6701 TV	32	#endif
559d6701 TV	33
702d267e CM	34	#ifdef DSS_SUBSYS_NAME
	35	#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
	36	#else
	37	#define pr_fmt(fmt) fmt
559d6701 TV	38	#endif
559d6701 TV	39
702d267e CM	40	#define DSSDBG(format, ...) \
702d267e CM	41	pr_debug(format, ## __VA_ARGS__)
559d6701 TV	42
	43	#ifdef DSS_SUBSYS_NAME
	44	#define DSSERR(format, ...) \
	45	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
	46	## __VA_ARGS__)
	47	#else
	48	#define DSSERR(format, ...) \
	49	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
	50	#endif
	51
	52	#ifdef DSS_SUBSYS_NAME
	53	#define DSSINFO(format, ...) \
	54	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
	55	## __VA_ARGS__)
	56	#else
	57	#define DSSINFO(format, ...) \
	58	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
	59	#endif
	60
	61	#ifdef DSS_SUBSYS_NAME
	62	#define DSSWARN(format, ...) \
	63	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
	64	## __VA_ARGS__)
	65	#else
	66	#define DSSWARN(format, ...) \
	67	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
	68	#endif
	69
	70	/* OMAP TRM gives bitfields as start:end, where start is the higher bit
	71	number. For example 7:0 */
	72	#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
	73	#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
	74	#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
	75	#define FLD_MOD(orig, val, start, end) \
	76	(((orig) & ~FLD_MASK(start, end)) \| FLD_VAL(val, start, end))
	77
569969d6 AT	78	enum dss_io_pad_mode {
	79	DSS_IO_PAD_MODE_RESET,
	80	DSS_IO_PAD_MODE_RFBI,
	81	DSS_IO_PAD_MODE_BYPASS,
559d6701 TV	82	};
559d6701 TV	83
7ed024aa M	84	enum dss_hdmi_venc_clk_source_select {
	85	DSS_VENC_TV_CLK = 0,
	86	DSS_HDMI_M_PCLK = 1,
	87	};
	88
6ff8aa31 AT	89	enum dss_dsi_content_type {
	90	DSS_DSI_CONTENT_DCS,
	91	DSS_DSI_CONTENT_GENERIC,
	92	};
	93
d9ac773c AT	94	enum dss_writeback_channel {
	95	DSS_WB_LCD1_MGR = 0,
	96	DSS_WB_LCD2_MGR = 1,
	97	DSS_WB_TV_MGR = 2,
	98	DSS_WB_OVL0 = 3,
	99	DSS_WB_OVL1 = 4,
	100	DSS_WB_OVL2 = 5,
	101	DSS_WB_OVL3 = 6,
	102	DSS_WB_LCD3_MGR = 7,
	103	};
	104
64e22ffd TV	105	enum dss_pll_id {
	106	DSS_PLL_DSI1,
	107	DSS_PLL_DSI2,
	108	DSS_PLL_HDMI,
6d817880 TV	109	DSS_PLL_VIDEO1,
6d817880 TV	110	DSS_PLL_VIDEO2,
64e22ffd TV	111	};
64e22ffd TV	112
0a20170a TV	113	struct dss_pll;
	114
	115	#define DSS_PLL_MAX_HSDIVS 4
	116
	117	/*
	118	* Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
	119	* Type-B PLLs: clkout[0] refers to m2.
	120	*/
	121	struct dss_pll_clock_info {
	122	/* rates that we get with dividers below */
	123	unsigned long fint;
	124	unsigned long clkdco;
	125	unsigned long clkout[DSS_PLL_MAX_HSDIVS];
	126
	127	/* dividers */
	128	u16 n;
	129	u16 m;
	130	u32 mf;
	131	u16 mX[DSS_PLL_MAX_HSDIVS];
	132	u16 sd;
	133	};
	134
	135	struct dss_pll_ops {
	136	int (enable)(struct dss_pll pll);
	137	void (disable)(struct dss_pll pll);
	138	int (set_config)(struct dss_pll pll,
	139	const struct dss_pll_clock_info *cinfo);
	140	};
	141
	142	struct dss_pll_hw {
	143	unsigned n_max;
	144	unsigned m_min;
	145	unsigned m_max;
	146	unsigned mX_max;
	147
	148	unsigned long fint_min, fint_max;
	149	unsigned long clkdco_min, clkdco_low, clkdco_max;
	150
	151	u8 n_msb, n_lsb;
	152	u8 m_msb, m_lsb;
	153	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
	154
	155	bool has_stopmode;
	156	bool has_freqsel;
	157	bool has_selfreqdco;
	158	bool has_refsel;
	159	};
	160
	161	struct dss_pll {
	162	const char *name;
64e22ffd	163	enum dss_pll_id id;
0a20170a TV	164
	165	struct clk *clkin;
	166	struct regulator *regulator;
	167
	168	void __iomem *base;
	169
	170	const struct dss_pll_hw *hw;
	171
	172	const struct dss_pll_ops *ops;
	173
	174	struct dss_pll_clock_info cinfo;
	175	};
	176
559d6701 TV	177	struct dispc_clock_info {
	178	/* rates that we get with dividers below */
	179	unsigned long lck;
	180	unsigned long pck;
	181
	182	/* dividers */
	183	u16 lck_div;
	184	u16 pck_div;
	185	};
	186
c56fb3ef AT	187	struct dss_lcd_mgr_config {
	188	enum dss_io_pad_mode io_pad_mode;
	189
	190	bool stallmode;
	191	bool fifohandcheck;
	192
	193	struct dispc_clock_info clock_info;
	194
	195	int video_port_width;
	196
	197	int lcden_sig_polarity;
	198	};
	199
559d6701 TV	200	struct seq_file;
	201	struct platform_device;
	202
	203	/* core */
8f46efad	204	struct platform_device *dss_get_core_pdev(void);
00928eaf TV	205	int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
00928eaf TV	206	void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
a8081d31	207	int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
e40402cf	208	int dss_debugfs_create_file(const char name, void (write)(struct seq_file *));
559d6701 TV	209
559d6701 TV	210	/* display */
94140f0d TV	211	int display_init_sysfs(struct platform_device *pdev);
94140f0d TV	212	void display_uninit_sysfs(struct platform_device *pdev);
559d6701 TV	213
559d6701 TV	214	/* manager */
7f7cdbd6 TV	215	int dss_init_overlay_managers(void);
	216	void dss_uninit_overlay_managers(void);
	217	int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
	218	void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
54540d41 TV	219	int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
54540d41 TV	220	const struct omap_overlay_manager_info *info);
b917fa39 AT	221	int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
b917fa39 AT	222	const struct omap_video_timings *timings);
6ac48d1e	223	int dss_mgr_check(struct omap_overlay_manager *mgr,
6ac48d1e	224	struct omap_overlay_manager_info *info,
228b2134	225	const struct omap_video_timings *mgr_timings,
6e543595	226	const struct dss_lcd_mgr_config *config,
6ac48d1e	227	struct omap_overlay_info **overlay_infos);
559d6701	228
f476ae9d AT	229	static inline bool dss_mgr_is_lcd(enum omap_channel id)
	230	{
	231	if (id == OMAP_DSS_CHANNEL_LCD \|\| id == OMAP_DSS_CHANNEL_LCD2 \|\|
	232	id == OMAP_DSS_CHANNEL_LCD3)
	233	return true;
	234	else
	235	return false;
	236	}
	237
f6a0492e TV	238	int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
	239	struct platform_device *pdev);
	240	void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
	241
559d6701 TV	242	/* overlay */
	243	void dss_init_overlays(struct platform_device *pdev);
	244	void dss_uninit_overlays(struct platform_device *pdev);
559d6701	245	void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
54540d41 TV	246	int dss_ovl_simple_check(struct omap_overlay *ovl,
54540d41 TV	247	const struct omap_overlay_info *info);
228b2134 AT	248	int dss_ovl_check(struct omap_overlay ovl, struct omap_overlay_info info,
228b2134 AT	249	const struct omap_video_timings *mgr_timings);
6c6f510a AT	250	bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
6c6f510a AT	251	enum omap_color_mode mode);
91691516 TV	252	int dss_overlay_kobj_init(struct omap_overlay *ovl,
	253	struct platform_device *pdev);
	254	void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
559d6701 TV	255
559d6701 TV	256	/* DSS */
6e7e8f06	257	int dss_init_platform_driver(void) __init;
96c401bc	258	void dss_uninit_platform_driver(void);
559d6701	259
99767548 TV	260	int dss_runtime_get(void);
	261	void dss_runtime_put(void);
	262
5aaee69d	263	unsigned long dss_get_dispc_clk_rate(void);
064c2a47	264	int dss_dpi_select_source(int port, enum omap_channel channel);
7ed024aa	265	void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
4a61e267	266	enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
89a35e51	267	const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
8b9cb3a8	268	void dss_dump_clocks(struct seq_file *s);
559d6701	269
99767548 TV	270	/* DSS VIDEO PLL */
	271	struct dss_pll dss_video_pll_init(struct platform_device pdev, int id,
	272	struct regulator *regulator);
	273	void dss_video_pll_uninit(struct dss_pll *pll);
	274
ef691ff4 AT	275	/* dss-of */
	276	struct device_node dss_of_port_get_parent_device(struct device_node port);
	277	u32 dss_of_port_get_port_number(struct device_node *port);
	278
1b3bcb33	279	#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
8b9cb3a8 SG	280	void dss_debug_dump_clocks(struct seq_file *s);
8b9cb3a8 SG	281	#endif
559d6701	282
be40eecf TV	283	void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
	284	void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
	285	enum omap_channel channel);
	286
889b4fd7	287	void dss_sdi_init(int datapairs);
559d6701 TV	288	int dss_sdi_enable(void);
	289	void dss_sdi_disable(void);
	290
5a8b572d AT	291	void dss_select_dsi_clk_source(int dsi_module,
5a8b572d AT	292	enum omap_dss_clk_source clk_src);
ea75159e	293	void dss_select_lcd_clk_source(enum omap_channel channel,
89a35e51 AT	294	enum omap_dss_clk_source clk_src);
89a35e51 AT	295	enum omap_dss_clk_source dss_get_dispc_clk_source(void);
5a8b572d	296	enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
89a35e51	297	enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
2f18c4d8	298
559d6701 TV	299	void dss_set_venc_output(enum omap_dss_venc_type type);
	300	void dss_set_dac_pwrdn_bgz(bool enable);
	301
d0f58bd3	302	int dss_set_fck_rate(unsigned long rate);
559d6701	303
d0f58bd3	304	typedef bool (dss_div_calc_func)(unsigned long fck, void data);
688af02d TV	305	bool dss_div_calc(unsigned long pck, unsigned long fck_min,
688af02d TV	306	dss_div_calc_func func, void *data);
43417823	307
559d6701	308	/* SDI */
6e7e8f06	309	int sdi_init_platform_driver(void) __init;
ede92695	310	void sdi_uninit_platform_driver(void);
559d6701	311
387ce9f2	312	#ifdef CONFIG_OMAP2_DSS_SDI
ede92695 TV	313	int sdi_init_port(struct platform_device pdev, struct device_node port);
ede92695 TV	314	void sdi_uninit_port(struct device_node *port);
387ce9f2	315	#else
ede92695	316	static inline int sdi_init_port(struct platform_device *pdev,
387ce9f2 AT	317	struct device_node *port)
	318	{
	319	return 0;
	320	}
ede92695	321	static inline void sdi_uninit_port(struct device_node *port)
387ce9f2 AT	322	{
	323	}
	324	#endif
2ecef246	325
559d6701	326	/* DSI */
989c79a8	327
368a148e	328	#ifdef CONFIG_OMAP2_DSS_DSI
5a8b572d AT	329
	330	struct dentry;
	331	struct file_operations;
	332
6e7e8f06	333	int dsi_init_platform_driver(void) __init;
ede92695	334	void dsi_uninit_platform_driver(void);
559d6701 TV	335
559d6701 TV	336	void dsi_dump_clocks(struct seq_file *s);
559d6701	337
559d6701	338	void dsi_irq_handler(void);
a3b3cc2b AT	339	u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
a3b3cc2b AT	340
368a148e	341	#else
a3b3cc2b AT	342	static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
a3b3cc2b AT	343	{
85d90b12 DC	344	WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
85d90b12 DC	345	__func__);
a3b3cc2b AT	346	return 0;
a3b3cc2b AT	347	}
368a148e	348	#endif
559d6701 TV	349
559d6701 TV	350	/* DPI */
6e7e8f06	351	int dpi_init_platform_driver(void) __init;
ede92695	352	void dpi_uninit_platform_driver(void);
559d6701	353
387ce9f2	354	#ifdef CONFIG_OMAP2_DSS_DPI
ede92695 TV	355	int dpi_init_port(struct platform_device pdev, struct device_node port);
ede92695 TV	356	void dpi_uninit_port(struct device_node *port);
387ce9f2	357	#else
ede92695	358	static inline int dpi_init_port(struct platform_device *pdev,
387ce9f2 AT	359	struct device_node *port)
	360	{
	361	return 0;
	362	}
ede92695	363	static inline void dpi_uninit_port(struct device_node *port)
387ce9f2 AT	364	{
	365	}
	366	#endif
2ecef246	367
559d6701	368	/* DISPC */
6e7e8f06	369	int dispc_init_platform_driver(void) __init;
ede92695	370	void dispc_uninit_platform_driver(void);
559d6701	371	void dispc_dump_clocks(struct seq_file *s);
559d6701 TV	372
	373	void dispc_enable_sidle(void);
	374	void dispc_disable_sidle(void);
	375
559d6701 TV	376	void dispc_lcd_enable_signal(bool enable);
559d6701 TV	377	void dispc_pck_free_enable(bool enable);
cd295aeb TV	378	void dispc_enable_fifomerge(bool enable);
cd295aeb TV	379	void dispc_enable_gamma_table(bool enable);
cd295aeb	380
7c284e6e TV	381	typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
	382	unsigned long pck, void *data);
	383	bool dispc_div_calc(unsigned long dispc,
	384	unsigned long pck_min, unsigned long pck_max,
	385	dispc_div_calc_func func, void *data);
	386
8f366162	387	bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39	388	const struct omap_video_timings *timings);
cd295aeb TV	389	int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
	390	struct dispc_clock_info *cinfo);
	391
	392
6f04e1bf	393	void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
83fa2f2e	394	void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4 TV	395	u32 fifo_low, u32 fifo_high, bool use_fifomerge,
3568f2a4 TV	396	bool manual_update);
348be69d	397
f0d08f89	398	void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1	399	const struct dispc_clock_info *cinfo);
26d9dd0d	400	int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde	401	struct dispc_clock_info *cinfo);
5391e87d	402	void dispc_set_tv_pclk(unsigned long pclk);
559d6701	403
0b23e5b8 AT	404	u32 dispc_wb_get_framedone_irq(void);
	405	bool dispc_wb_go_busy(void);
	406	void dispc_wb_go(void);
	407	void dispc_wb_enable(bool enable);
	408	bool dispc_wb_is_enabled(void);
d9ac773c	409	void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
749feffa	410	int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7	411	bool mem_to_mem, const struct omap_video_timings *timings);
d9ac773c	412
559d6701	413	/* VENC */
6e7e8f06	414	int venc_init_platform_driver(void) __init;
ede92695	415	void venc_uninit_platform_driver(void);
559d6701	416
c3198a5e	417	/* HDMI */
ef26958a	418	int hdmi4_init_platform_driver(void) __init;
ede92695	419	void hdmi4_uninit_platform_driver(void);
c3198a5e	420
f5bab222	421	int hdmi5_init_platform_driver(void) __init;
ede92695	422	void hdmi5_uninit_platform_driver(void);
f5bab222	423
559d6701	424	/* RFBI */
6e7e8f06	425	int rfbi_init_platform_driver(void) __init;
ede92695	426	void rfbi_uninit_platform_driver(void);
559d6701	427
dfc0fd8d TV	428
	429	#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
	430	static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
	431	{
	432	int b;
	433	for (b = 0; b < 32; ++b) {
	434	if (irqstatus & (1 << b))
	435	irq_arr[b]++;
	436	}
	437	}
	438	#endif
	439
0a20170a TV	440	/* PLL */
	441	typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
	442	unsigned long clkdco, void *data);
	443	typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
	444	void *data);
	445
	446	int dss_pll_register(struct dss_pll *pll);
	447	void dss_pll_unregister(struct dss_pll *pll);
	448	struct dss_pll dss_pll_find(const char name);
	449	int dss_pll_enable(struct dss_pll *pll);
	450	void dss_pll_disable(struct dss_pll *pll);
	451	int dss_pll_set_config(struct dss_pll *pll,
	452	const struct dss_pll_clock_info *cinfo);
	453
	454	bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
	455	unsigned long out_min, unsigned long out_max,
	456	dss_hsdiv_calc_func func, void *data);
	457	bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
	458	unsigned long pll_min, unsigned long pll_max,
	459	dss_pll_calc_func func, void *data);
	460	int dss_pll_write_config_type_a(struct dss_pll *pll,
	461	const struct dss_pll_clock_info *cinfo);
	462	int dss_pll_write_config_type_b(struct dss_pll *pll,
	463	const struct dss_pll_clock_info *cinfo);
eb30199b	464	int dss_pll_wait_reset_done(struct dss_pll *pll);
0a20170a	465
559d6701	466	#endif