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Merge tag 'fbdev-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux
[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / dss_features.c
CommitLineData
e1ef4d23
AT		 1/*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/kernel.h>
eda34273 21#include <linux/module.h>
e1ef4d23
AT		 22#include <linux/types.h>
23#include <linux/err.h>
24#include <linux/slab.h>
25
a0b38cc4 26#include <video/omapdss.h>
e1ef4d23 27
067a57e4 28#include "dss.h"
e1ef4d23
AT		 29#include "dss_features.h"
30
31/* Defines a generic omap register field */
32struct dss_reg_field {
e1ef4d23
AT		 33 u8 start, end;
34};
35
31ef8237
TA		 36struct dss_param_range {
37 int min, max;
38};
39
e1ef4d23
AT		 40struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
c124f23d
AT		 44 const enum dss_feat_id *features;
45 const int num_features;
e1ef4d23
AT		 46
47 const int num_mgrs;
48 const int num_ovls;
49 const enum omap_display_type *supported_displays;
97f01b3a 50 const enum omap_dss_output_id *supported_outputs;
e1ef4d23 51 const enum omap_color_mode *supported_color_modes;
67019db8 52 const enum omap_overlay_caps *overlay_caps;
235e7dba 53 const char * const *clksrc_names;
31ef8237 54 const struct dss_param_range *dss_params;
5ed8cf5b 55
65e006ff
CM		 56 const enum omap_dss_rotation_type supported_rotation_types;
57
5ed8cf5b
TV		 58 const u32 buffer_size_unit;
59 const u32 burst_size_unit;
e1ef4d23
AT		 60};
61
62/* This struct is assigned to one of the below during initialization */
ea290333 63static const struct omap_dss_features *omap_current_dss_features;
e1ef4d23
AT		 64
65static const struct dss_reg_field omap2_dss_reg_fields[] = {
49641116
TA		 66 [FEAT_REG_FIRHINC] = { 11, 0 },
67 [FEAT_REG_FIRVINC] = { 27, 16 },
68 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
69 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
70 [FEAT_REG_FIFOSIZE] = { 8, 0 },
71 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
72 [FEAT_REG_VERTICALACCU] = { 25, 16 },
73 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
e1ef4d23
AT		 74};
75
76static const struct dss_reg_field omap3_dss_reg_fields[] = {
49641116
TA		 77 [FEAT_REG_FIRHINC] = { 12, 0 },
78 [FEAT_REG_FIRVINC] = { 28, 16 },
79 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
80 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
81 [FEAT_REG_FIFOSIZE] = { 10, 0 },
82 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
83 [FEAT_REG_VERTICALACCU] = { 25, 16 },
84 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
87a7484b
AT		 85};
86
d6279d4a
SP		 87static const struct dss_reg_field am43xx_dss_reg_fields[] = {
88 [FEAT_REG_FIRHINC] = { 12, 0 },
89 [FEAT_REG_FIRVINC] = { 28, 16 },
90 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
91 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
92 [FEAT_REG_FIFOSIZE] = { 10, 0 },
93 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
94 [FEAT_REG_VERTICALACCU] = { 25, 16 },
95 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
96};
97
87a7484b 98static const struct dss_reg_field omap4_dss_reg_fields[] = {
49641116
TA		 99 [FEAT_REG_FIRHINC] = { 12, 0 },
100 [FEAT_REG_FIRVINC] = { 28, 16 },
101 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
102 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
103 [FEAT_REG_FIFOSIZE] = { 15, 0 },
104 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
105 [FEAT_REG_VERTICALACCU] = { 26, 16 },
106 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
e1ef4d23
AT		 107};
108
23362832
AT		 109static const struct dss_reg_field omap5_dss_reg_fields[] = {
110 [FEAT_REG_FIRHINC] = { 12, 0 },
111 [FEAT_REG_FIRVINC] = { 28, 16 },
112 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
113 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
114 [FEAT_REG_FIFOSIZE] = { 15, 0 },
115 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
116 [FEAT_REG_VERTICALACCU] = { 26, 16 },
117 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
23362832
AT		 118};
119
e1ef4d23
AT		 120static const enum omap_display_type omap2_dss_supported_displays[] = {
121 /* OMAP_DSS_CHANNEL_LCD */
f8df01f1 122 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
e1ef4d23
AT		 123
124 /* OMAP_DSS_CHANNEL_DIGIT */
125 OMAP_DISPLAY_TYPE_VENC,
126};
127
4e777dd7 128static const enum omap_display_type omap3430_dss_supported_displays[] = {
e1ef4d23
AT		 129 /* OMAP_DSS_CHANNEL_LCD */
130 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
131 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
132
133 /* OMAP_DSS_CHANNEL_DIGIT */
134 OMAP_DISPLAY_TYPE_VENC,
135};
136
4e777dd7
TV		 137static const enum omap_display_type omap3630_dss_supported_displays[] = {
138 /* OMAP_DSS_CHANNEL_LCD */
139 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
140 OMAP_DISPLAY_TYPE_DSI,
141
142 /* OMAP_DSS_CHANNEL_DIGIT */
143 OMAP_DISPLAY_TYPE_VENC,
144};
145
d6279d4a
SP		 146static const enum omap_display_type am43xx_dss_supported_displays[] = {
147 /* OMAP_DSS_CHANNEL_LCD */
148 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
149};
150
d50cd037
AT		 151static const enum omap_display_type omap4_dss_supported_displays[] = {
152 /* OMAP_DSS_CHANNEL_LCD */
153 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
154
155 /* OMAP_DSS_CHANNEL_DIGIT */
b119601d 156 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
d50cd037
AT		 157
158 /* OMAP_DSS_CHANNEL_LCD2 */
159 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
160 OMAP_DISPLAY_TYPE_DSI,
161};
162
23362832
AT		 163static const enum omap_display_type omap5_dss_supported_displays[] = {
164 /* OMAP_DSS_CHANNEL_LCD */
165 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
166 OMAP_DISPLAY_TYPE_DSI,
167
168 /* OMAP_DSS_CHANNEL_DIGIT */
169 OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
170
171 /* OMAP_DSS_CHANNEL_LCD2 */
172 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
173 OMAP_DISPLAY_TYPE_DSI,
174};
175
97f01b3a
AT		 176static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
177 /* OMAP_DSS_CHANNEL_LCD */
178 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
179
180 /* OMAP_DSS_CHANNEL_DIGIT */
181 OMAP_DSS_OUTPUT_VENC,
182};
183
184static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
185 /* OMAP_DSS_CHANNEL_LCD */
186 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
187 OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
188
189 /* OMAP_DSS_CHANNEL_DIGIT */
190 OMAP_DSS_OUTPUT_VENC,
191};
192
193static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
194 /* OMAP_DSS_CHANNEL_LCD */
195 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
196 OMAP_DSS_OUTPUT_DSI1,
197
198 /* OMAP_DSS_CHANNEL_DIGIT */
199 OMAP_DSS_OUTPUT_VENC,
200};
201
d6279d4a
SP		 202static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
203 /* OMAP_DSS_CHANNEL_LCD */
204 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
205};
206
97f01b3a
AT		 207static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
208 /* OMAP_DSS_CHANNEL_LCD */
ff588d83 209 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
97f01b3a
AT		 210
211 /* OMAP_DSS_CHANNEL_DIGIT */
ff588d83 212 OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
97f01b3a
AT		 213
214 /* OMAP_DSS_CHANNEL_LCD2 */
215 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
216 OMAP_DSS_OUTPUT_DSI2,
217};
218
219static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
220 /* OMAP_DSS_CHANNEL_LCD */
221 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
222 OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
223
224 /* OMAP_DSS_CHANNEL_DIGIT */
fa0c52ab 225 OMAP_DSS_OUTPUT_HDMI,
97f01b3a
AT		 226
227 /* OMAP_DSS_CHANNEL_LCD2 */
228 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
229 OMAP_DSS_OUTPUT_DSI1,
230
231 /* OMAP_DSS_CHANNEL_LCD3 */
232 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
233 OMAP_DSS_OUTPUT_DSI2,
234};
235
e1ef4d23
AT		 236static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
237 /* OMAP_DSS_GFX */
238 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
239 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
240 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
241 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
242
243 /* OMAP_DSS_VIDEO1 */
244 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
245 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
246 OMAP_DSS_COLOR_UYVY,
247
248 /* OMAP_DSS_VIDEO2 */
249 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
250 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
251 OMAP_DSS_COLOR_UYVY,
252};
253
254static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
255 /* OMAP_DSS_GFX */
256 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
257 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
258 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
259 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
260 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
261 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
262
263 /* OMAP_DSS_VIDEO1 */
264 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
265 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
266 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
267
268 /* OMAP_DSS_VIDEO2 */
269 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
270 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
271 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
272 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
273 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
274};
275
f20e4220
AJ		 276static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
277 /* OMAP_DSS_GFX */
278 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
279 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
280 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
281 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
282 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
283 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
08f3267e
LM		 284 OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
285 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
f20e4220
AJ		 286
287 /* OMAP_DSS_VIDEO1 */
288 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
289 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
290 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
291 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
292 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
293 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
294 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
295 OMAP_DSS_COLOR_RGBX32,
296
297 /* OMAP_DSS_VIDEO2 */
298 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
299 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
300 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
301 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
302 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
303 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
304 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
305 OMAP_DSS_COLOR_RGBX32,
b8c095b4
AT		 306
307 /* OMAP_DSS_VIDEO3 */
308 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
309 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
310 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
311 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
312 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
313 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
314 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
315 OMAP_DSS_COLOR_RGBX32,
7a155be3
AT		 316
317 /* OMAP_DSS_WB */
318 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
319 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
320 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
321 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
322 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
323 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
324 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
325 OMAP_DSS_COLOR_RGBX32,
f20e4220
AJ		 326};
327
67019db8
TV		 328static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
329 /* OMAP_DSS_GFX */
d79db853 330 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 331
332 /* OMAP_DSS_VIDEO1 */
d79db853
AT		 333 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
334 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 335
336 /* OMAP_DSS_VIDEO2 */
d79db853
AT		 337 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
338 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 339};
340
341static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
342 /* OMAP_DSS_GFX */
d79db853
AT		 343 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
344 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 345
346 /* OMAP_DSS_VIDEO1 */
d79db853
AT		 347 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
348 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 349
350 /* OMAP_DSS_VIDEO2 */
d79db853
AT		 351 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
352 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 353};
354
355static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
356 /* OMAP_DSS_GFX */
d79db853
AT		 357 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
358 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 359
360 /* OMAP_DSS_VIDEO1 */
d79db853
AT		 361 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
362 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 363
364 /* OMAP_DSS_VIDEO2 */
f6dc8150 365 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 366 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
367 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 368};
369
370static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
371 /* OMAP_DSS_GFX */
11354dd5 372 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
d79db853
AT		 373 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
374 OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 375
376 /* OMAP_DSS_VIDEO1 */
f6dc8150 377 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 378 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
379 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 380
381 /* OMAP_DSS_VIDEO2 */
f6dc8150 382 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 383 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
384 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
b8c095b4
AT		 385
386 /* OMAP_DSS_VIDEO3 */
387 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
d79db853
AT		 388 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
389 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
67019db8
TV		 390};
391
235e7dba 392static const char * const omap2_dss_clk_source_names[] = {
89a35e51
AT		 393 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
394 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
395 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
067a57e4
AT		 396};
397
235e7dba 398static const char * const omap3_dss_clk_source_names[] = {
89a35e51
AT		 399 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
400 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
401 [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
067a57e4
AT		 402};
403
235e7dba 404static const char * const omap4_dss_clk_source_names[] = {
89a35e51
AT		 405 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
406 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
407 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
5a8b572d
AT		 408 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
409 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
ea75159e
TA		 410};
411
23362832
AT		 412static const char * const omap5_dss_clk_source_names[] = {
413 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1",
414 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2",
415 [OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK",
416 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
417 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2",
418};
419
31ef8237 420static const struct dss_param_range omap2_dss_param_range[] = {
3729a70b 421 [FEAT_PARAM_DSS_FCK] = { 0, 133000000 },
9eaaf207 422 [FEAT_PARAM_DSS_PCD] = { 2, 255 },
0373cac6 423 [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
7282f1b7
CM		 424 /*
425 * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
426 * scaler cannot scale a image with width more than 768.
427 */
428 [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
31ef8237
TA		 429};
430
431static const struct dss_param_range omap3_dss_param_range[] = {
49641116 432 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
9eaaf207 433 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
49641116 434 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
bc63f304 435 [FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
0373cac6 436 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
7282f1b7 437 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
31ef8237
TA		 438};
439
d6279d4a
SP		 440static const struct dss_param_range am43xx_dss_param_range[] = {
441 [FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
1511c75b 442 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
d6279d4a
SP		 443 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
444 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
445};
446
31ef8237 447static const struct dss_param_range omap4_dss_param_range[] = {
49641116 448 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
9eaaf207 449 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
49641116 450 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
bc63f304 451 [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
0373cac6 452 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
7282f1b7 453 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
31ef8237
TA		 454};
455
23362832 456static const struct dss_param_range omap5_dss_param_range[] = {
3729a70b 457 [FEAT_PARAM_DSS_FCK] = { 0, 209250000 },
23362832 458 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
23362832 459 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
3729a70b 460 [FEAT_PARAM_DSI_FCK] = { 0, 209250000 },
23362832
AT		 461 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
462 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
23362832
AT		 463};
464
c124f23d
AT		 465static const enum dss_feat_id omap2_dss_feat_list[] = {
466 FEAT_LCDENABLEPOL,
467 FEAT_LCDENABLESIGNAL,
468 FEAT_PCKFREEENABLE,
469 FEAT_FUNCGATED,
470 FEAT_ROWREPEATENABLE,
471 FEAT_RESIZECONF,
472};
473
474static const enum dss_feat_id omap3430_dss_feat_list[] = {
475 FEAT_LCDENABLEPOL,
476 FEAT_LCDENABLESIGNAL,
477 FEAT_PCKFREEENABLE,
478 FEAT_FUNCGATED,
479 FEAT_LINEBUFFERSPLIT,
480 FEAT_ROWREPEATENABLE,
481 FEAT_RESIZECONF,
c124f23d
AT		 482 FEAT_DSI_REVERSE_TXCLKESC,
483 FEAT_VENC_REQUIRES_TV_DAC_CLK,
484 FEAT_CPR,
485 FEAT_PRELOAD,
486 FEAT_FIR_COEF_V,
487 FEAT_ALPHA_FIXED_ZORDER,
488 FEAT_FIFO_MERGE,
489 FEAT_OMAP3_DSI_FIFO_BUG,
195e672a 490 FEAT_DPI_USES_VDDS_DSI,
c124f23d
AT		 491};
492
524d9f48
RA		 493static const enum dss_feat_id am35xx_dss_feat_list[] = {
494 FEAT_LCDENABLEPOL,
495 FEAT_LCDENABLESIGNAL,
496 FEAT_PCKFREEENABLE,
497 FEAT_FUNCGATED,
498 FEAT_LINEBUFFERSPLIT,
499 FEAT_ROWREPEATENABLE,
500 FEAT_RESIZECONF,
524d9f48
RA		 501 FEAT_DSI_REVERSE_TXCLKESC,
502 FEAT_VENC_REQUIRES_TV_DAC_CLK,
503 FEAT_CPR,
504 FEAT_PRELOAD,
505 FEAT_FIR_COEF_V,
506 FEAT_ALPHA_FIXED_ZORDER,
507 FEAT_FIFO_MERGE,
508 FEAT_OMAP3_DSI_FIFO_BUG,
509};
510
d6279d4a
SP		 511static const enum dss_feat_id am43xx_dss_feat_list[] = {
512 FEAT_LCDENABLEPOL,
513 FEAT_LCDENABLESIGNAL,
514 FEAT_PCKFREEENABLE,
515 FEAT_FUNCGATED,
516 FEAT_LINEBUFFERSPLIT,
517 FEAT_ROWREPEATENABLE,
518 FEAT_RESIZECONF,
519 FEAT_CPR,
520 FEAT_PRELOAD,
521 FEAT_FIR_COEF_V,
522 FEAT_ALPHA_FIXED_ZORDER,
523 FEAT_FIFO_MERGE,
524};
525
c124f23d
AT		 526static const enum dss_feat_id omap3630_dss_feat_list[] = {
527 FEAT_LCDENABLEPOL,
528 FEAT_LCDENABLESIGNAL,
529 FEAT_PCKFREEENABLE,
530 FEAT_FUNCGATED,
531 FEAT_LINEBUFFERSPLIT,
532 FEAT_ROWREPEATENABLE,
533 FEAT_RESIZECONF,
534 FEAT_DSI_PLL_PWR_BUG,
c124f23d
AT		 535 FEAT_CPR,
536 FEAT_PRELOAD,
537 FEAT_FIR_COEF_V,
538 FEAT_ALPHA_FIXED_ZORDER,
539 FEAT_FIFO_MERGE,
540 FEAT_OMAP3_DSI_FIFO_BUG,
eb91e79b 541 FEAT_DPI_USES_VDDS_DSI,
c124f23d
AT		 542};
543
544static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
545 FEAT_MGR_LCD2,
546 FEAT_CORE_CLK_DIV,
547 FEAT_LCD_CLK_SRC,
548 FEAT_DSI_DCS_CMD_CONFIG_VC,
549 FEAT_DSI_VC_OCP_WIDTH,
550 FEAT_DSI_GNQ,
551 FEAT_HANDLE_UV_SEPARATE,
552 FEAT_ATTR2,
553 FEAT_CPR,
554 FEAT_PRELOAD,
555 FEAT_FIR_COEF_V,
556 FEAT_ALPHA_FREE_ZORDER,
557 FEAT_FIFO_MERGE,
65e006ff 558 FEAT_BURST_2D,
c124f23d
AT		 559};
560
70988194
RN		 561static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
562 FEAT_MGR_LCD2,
563 FEAT_CORE_CLK_DIV,
564 FEAT_LCD_CLK_SRC,
565 FEAT_DSI_DCS_CMD_CONFIG_VC,
566 FEAT_DSI_VC_OCP_WIDTH,
567 FEAT_DSI_GNQ,
568 FEAT_HDMI_CTS_SWMODE,
569 FEAT_HANDLE_UV_SEPARATE,
570 FEAT_ATTR2,
571 FEAT_CPR,
572 FEAT_PRELOAD,
573 FEAT_FIR_COEF_V,
574 FEAT_ALPHA_FREE_ZORDER,
575 FEAT_FIFO_MERGE,
65e006ff 576 FEAT_BURST_2D,
70988194
RN		 577};
578
c124f23d
AT		 579static const enum dss_feat_id omap4_dss_feat_list[] = {
580 FEAT_MGR_LCD2,
581 FEAT_CORE_CLK_DIV,
582 FEAT_LCD_CLK_SRC,
583 FEAT_DSI_DCS_CMD_CONFIG_VC,
584 FEAT_DSI_VC_OCP_WIDTH,
585 FEAT_DSI_GNQ,
586 FEAT_HDMI_CTS_SWMODE,
70988194 587 FEAT_HDMI_AUDIO_USE_MCLK,
c124f23d
AT		 588 FEAT_HANDLE_UV_SEPARATE,
589 FEAT_ATTR2,
590 FEAT_CPR,
591 FEAT_PRELOAD,
592 FEAT_FIR_COEF_V,
593 FEAT_ALPHA_FREE_ZORDER,
594 FEAT_FIFO_MERGE,
65e006ff 595 FEAT_BURST_2D,
c124f23d
AT		 596};
597
23362832
AT		 598static const enum dss_feat_id omap5_dss_feat_list[] = {
599 FEAT_MGR_LCD2,
5b3075ce 600 FEAT_MGR_LCD3,
23362832
AT		 601 FEAT_CORE_CLK_DIV,
602 FEAT_LCD_CLK_SRC,
603 FEAT_DSI_DCS_CMD_CONFIG_VC,
604 FEAT_DSI_VC_OCP_WIDTH,
605 FEAT_DSI_GNQ,
606 FEAT_HDMI_CTS_SWMODE,
607 FEAT_HDMI_AUDIO_USE_MCLK,
608 FEAT_HANDLE_UV_SEPARATE,
609 FEAT_ATTR2,
610 FEAT_CPR,
611 FEAT_PRELOAD,
612 FEAT_FIR_COEF_V,
613 FEAT_ALPHA_FREE_ZORDER,
614 FEAT_FIFO_MERGE,
615 FEAT_BURST_2D,
77ccbfbb 616 FEAT_DSI_PHY_DCC,
29fceeeb 617 FEAT_MFLAG,
23362832
AT		 618};
619
e1ef4d23 620/* OMAP2 DSS Features */
ea290333 621static const struct omap_dss_features omap2_dss_features = {
e1ef4d23
AT		 622 .reg_fields = omap2_dss_reg_fields,
623 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
624
c124f23d
AT		 625 .features = omap2_dss_feat_list,
626 .num_features = ARRAY_SIZE(omap2_dss_feat_list),
d50cd037 627
e1ef4d23
AT		 628 .num_mgrs = 2,
629 .num_ovls = 3,
630 .supported_displays = omap2_dss_supported_displays,
97f01b3a 631 .supported_outputs = omap2_dss_supported_outputs,
e1ef4d23 632 .supported_color_modes = omap2_dss_supported_color_modes,
67019db8 633 .overlay_caps = omap2_dss_overlay_caps,
067a57e4 634 .clksrc_names = omap2_dss_clk_source_names,
31ef8237 635 .dss_params = omap2_dss_param_range,
65e006ff 636 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
5ed8cf5b
TV		 637 .buffer_size_unit = 1,
638 .burst_size_unit = 8,
e1ef4d23
AT		 639};
640
641/* OMAP3 DSS Features */
ea290333 642static const struct omap_dss_features omap3430_dss_features = {
e1ef4d23
AT		 643 .reg_fields = omap3_dss_reg_fields,
644 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
645
c124f23d
AT		 646 .features = omap3430_dss_feat_list,
647 .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
e1ef4d23
AT		 648
649 .num_mgrs = 2,
650 .num_ovls = 3,
4e777dd7 651 .supported_displays = omap3430_dss_supported_displays,
97f01b3a 652 .supported_outputs = omap3430_dss_supported_outputs,
e1ef4d23 653 .supported_color_modes = omap3_dss_supported_color_modes,
67019db8 654 .overlay_caps = omap3430_dss_overlay_caps,
067a57e4 655 .clksrc_names = omap3_dss_clk_source_names,
31ef8237 656 .dss_params = omap3_dss_param_range,
65e006ff 657 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
5ed8cf5b
TV		 658 .buffer_size_unit = 1,
659 .burst_size_unit = 8,
e1ef4d23
AT		 660};
661
524d9f48
RA		 662/*
663 * AM35xx DSS Features. This is basically OMAP3 DSS Features without the
664 * vdds_dsi regulator.
665 */
666static const struct omap_dss_features am35xx_dss_features = {
667 .reg_fields = omap3_dss_reg_fields,
668 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
669
670 .features = am35xx_dss_feat_list,
671 .num_features = ARRAY_SIZE(am35xx_dss_feat_list),
672
673 .num_mgrs = 2,
674 .num_ovls = 3,
675 .supported_displays = omap3430_dss_supported_displays,
97f01b3a 676 .supported_outputs = omap3430_dss_supported_outputs,
524d9f48
RA		 677 .supported_color_modes = omap3_dss_supported_color_modes,
678 .overlay_caps = omap3430_dss_overlay_caps,
679 .clksrc_names = omap3_dss_clk_source_names,
680 .dss_params = omap3_dss_param_range,
681 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
682 .buffer_size_unit = 1,
683 .burst_size_unit = 8,
684};
685
d6279d4a
SP		 686static const struct omap_dss_features am43xx_dss_features = {
687 .reg_fields = am43xx_dss_reg_fields,
688 .num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields),
689
690 .features = am43xx_dss_feat_list,
691 .num_features = ARRAY_SIZE(am43xx_dss_feat_list),
692
693 .num_mgrs = 1,
694 .num_ovls = 3,
695 .supported_displays = am43xx_dss_supported_displays,
696 .supported_outputs = am43xx_dss_supported_outputs,
697 .supported_color_modes = omap3_dss_supported_color_modes,
698 .overlay_caps = omap3430_dss_overlay_caps,
699 .clksrc_names = omap2_dss_clk_source_names,
700 .dss_params = am43xx_dss_param_range,
701 .supported_rotation_types = OMAP_DSS_ROT_DMA,
702 .buffer_size_unit = 1,
703 .burst_size_unit = 8,
704};
705
ea290333 706static const struct omap_dss_features omap3630_dss_features = {
8fbde10a
S		 707 .reg_fields = omap3_dss_reg_fields,
708 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
709
c124f23d
AT		 710 .features = omap3630_dss_feat_list,
711 .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
8fbde10a
S		 712
713 .num_mgrs = 2,
714 .num_ovls = 3,
4e777dd7 715 .supported_displays = omap3630_dss_supported_displays,
97f01b3a 716 .supported_outputs = omap3630_dss_supported_outputs,
8fbde10a 717 .supported_color_modes = omap3_dss_supported_color_modes,
67019db8 718 .overlay_caps = omap3630_dss_overlay_caps,
067a57e4 719 .clksrc_names = omap3_dss_clk_source_names,
31ef8237 720 .dss_params = omap3_dss_param_range,
65e006ff 721 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
5ed8cf5b
TV		 722 .buffer_size_unit = 1,
723 .burst_size_unit = 8,
8fbde10a
S		 724};
725
d50cd037 726/* OMAP4 DSS Features */
6ff7084e
RN		 727/* For OMAP4430 ES 1.0 revision */
728static const struct omap_dss_features omap4430_es1_0_dss_features = {
729 .reg_fields = omap4_dss_reg_fields,
730 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
731
c124f23d
AT		 732 .features = omap4430_es1_0_dss_feat_list,
733 .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
6ff7084e
RN		 734
735 .num_mgrs = 3,
b8c095b4 736 .num_ovls = 4,
6ff7084e 737 .supported_displays = omap4_dss_supported_displays,
97f01b3a 738 .supported_outputs = omap4_dss_supported_outputs,
f20e4220 739 .supported_color_modes = omap4_dss_supported_color_modes,
67019db8 740 .overlay_caps = omap4_dss_overlay_caps,
6ff7084e
RN		 741 .clksrc_names = omap4_dss_clk_source_names,
742 .dss_params = omap4_dss_param_range,
65e006ff 743 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
5ed8cf5b
TV		 744 .buffer_size_unit = 16,
745 .burst_size_unit = 16,
6ff7084e
RN		 746};
747
70988194
RN		 748/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
749static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
750 .reg_fields = omap4_dss_reg_fields,
751 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
752
753 .features = omap4430_es2_0_1_2_dss_feat_list,
754 .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
755
756 .num_mgrs = 3,
757 .num_ovls = 4,
758 .supported_displays = omap4_dss_supported_displays,
97f01b3a 759 .supported_outputs = omap4_dss_supported_outputs,
70988194
RN		 760 .supported_color_modes = omap4_dss_supported_color_modes,
761 .overlay_caps = omap4_dss_overlay_caps,
762 .clksrc_names = omap4_dss_clk_source_names,
763 .dss_params = omap4_dss_param_range,
65e006ff 764 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
70988194
RN		 765 .buffer_size_unit = 16,
766 .burst_size_unit = 16,
767};
768
6ff7084e 769/* For all the other OMAP4 versions */
ea290333 770static const struct omap_dss_features omap4_dss_features = {
87a7484b
AT		 771 .reg_fields = omap4_dss_reg_fields,
772 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
d50cd037 773
c124f23d
AT		 774 .features = omap4_dss_feat_list,
775 .num_features = ARRAY_SIZE(omap4_dss_feat_list),
d50cd037
AT		 776
777 .num_mgrs = 3,
b8c095b4 778 .num_ovls = 4,
d50cd037 779 .supported_displays = omap4_dss_supported_displays,
97f01b3a 780 .supported_outputs = omap4_dss_supported_outputs,
f20e4220 781 .supported_color_modes = omap4_dss_supported_color_modes,
67019db8 782 .overlay_caps = omap4_dss_overlay_caps,
ea75159e 783 .clksrc_names = omap4_dss_clk_source_names,
31ef8237 784 .dss_params = omap4_dss_param_range,
65e006ff 785 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
5ed8cf5b
TV		 786 .buffer_size_unit = 16,
787 .burst_size_unit = 16,
d50cd037
AT		 788};
789
23362832
AT		 790/* OMAP5 DSS Features */
791static const struct omap_dss_features omap5_dss_features = {
792 .reg_fields = omap5_dss_reg_fields,
793 .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
794
795 .features = omap5_dss_feat_list,
796 .num_features = ARRAY_SIZE(omap5_dss_feat_list),
797
5b3075ce 798 .num_mgrs = 4,
23362832
AT		 799 .num_ovls = 4,
800 .supported_displays = omap5_dss_supported_displays,
97f01b3a 801 .supported_outputs = omap5_dss_supported_outputs,
23362832
AT		 802 .supported_color_modes = omap4_dss_supported_color_modes,
803 .overlay_caps = omap4_dss_overlay_caps,
804 .clksrc_names = omap5_dss_clk_source_names,
805 .dss_params = omap5_dss_param_range,
806 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
807 .buffer_size_unit = 16,
808 .burst_size_unit = 16,
809};
810
e1ef4d23
AT		 811/* Functions returning values related to a DSS feature */
812int dss_feat_get_num_mgrs(void)
813{
814 return omap_current_dss_features->num_mgrs;
815}
eda34273 816EXPORT_SYMBOL(dss_feat_get_num_mgrs);
e1ef4d23
AT		 817
818int dss_feat_get_num_ovls(void)
819{
820 return omap_current_dss_features->num_ovls;
821}
eda34273 822EXPORT_SYMBOL(dss_feat_get_num_ovls);
e1ef4d23 823
31ef8237
TA		 824unsigned long dss_feat_get_param_min(enum dss_range_param param)
825{
826 return omap_current_dss_features->dss_params[param].min;
827}
828
829unsigned long dss_feat_get_param_max(enum dss_range_param param)
819d807c 830{
31ef8237 831 return omap_current_dss_features->dss_params[param].max;
819d807c
AT		 832}
833
e1ef4d23
AT		 834enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
835{
836 return omap_current_dss_features->supported_displays[channel];
837}
838
97f01b3a
AT		 839enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel)
840{
841 return omap_current_dss_features->supported_outputs[channel];
842}
843
e1ef4d23
AT		 844enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
845{
846 return omap_current_dss_features->supported_color_modes[plane];
847}
eda34273 848EXPORT_SYMBOL(dss_feat_get_supported_color_modes);
e1ef4d23 849
67019db8
TV		 850enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
851{
852 return omap_current_dss_features->overlay_caps[plane];
853}
854
8dad2ab6
AT		 855bool dss_feat_color_mode_supported(enum omap_plane plane,
856 enum omap_color_mode color_mode)
857{
858 return omap_current_dss_features->supported_color_modes[plane] &
859 color_mode;
860}
861
89a35e51 862const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
067a57e4 863{
235e7dba 864 return omap_current_dss_features->clksrc_names[id];
067a57e4
AT		 865}
866
5ed8cf5b
TV		 867u32 dss_feat_get_buffer_size_unit(void)
868{
869 return omap_current_dss_features->buffer_size_unit;
870}
871
872u32 dss_feat_get_burst_size_unit(void)
873{
874 return omap_current_dss_features->burst_size_unit;
875}
876
e1ef4d23
AT		 877/* DSS has_feature check */
878bool dss_has_feature(enum dss_feat_id id)
879{
c124f23d
AT		 880 int i;
881 const enum dss_feat_id *features = omap_current_dss_features->features;
882 const int num_features = omap_current_dss_features->num_features;
883
884 for (i = 0; i < num_features; i++) {
885 if (features[i] == id)
886 return true;
887 }
888
889 return false;
e1ef4d23
AT		 890}
891
892void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
893{
894 if (id >= omap_current_dss_features->num_reg_fields)
895 BUG();
896
897 *start = omap_current_dss_features->reg_fields[id].start;
898 *end = omap_current_dss_features->reg_fields[id].end;
899}
900
65e006ff
CM		 901bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
902{
903 return omap_current_dss_features->supported_rotation_types & rot_type;
904}
905
649514c6 906void dss_features_init(enum omapdss_version version)
e1ef4d23 907{
649514c6
TV		 908 switch (version) {
909 case OMAPDSS_VER_OMAP24xx:
e1ef4d23 910 omap_current_dss_features = &omap2_dss_features;
649514c6
TV		 911 break;
912
913 case OMAPDSS_VER_OMAP34xx_ES1:
914 case OMAPDSS_VER_OMAP34xx_ES3:
915 omap_current_dss_features = &omap3430_dss_features;
916 break;
917
918 case OMAPDSS_VER_OMAP3630:
8fbde10a 919 omap_current_dss_features = &omap3630_dss_features;
649514c6
TV		 920 break;
921
922 case OMAPDSS_VER_OMAP4430_ES1:
6ff7084e 923 omap_current_dss_features = &omap4430_es1_0_dss_features;
649514c6
TV		 924 break;
925
926 case OMAPDSS_VER_OMAP4430_ES2:
70988194 927 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
649514c6
TV		 928 break;
929
930 case OMAPDSS_VER_OMAP4:
d50cd037 931 omap_current_dss_features = &omap4_dss_features;
649514c6
TV		 932 break;
933
934 case OMAPDSS_VER_OMAP5:
6d817880 935 case OMAPDSS_VER_DRA7xx:
23362832 936 omap_current_dss_features = &omap5_dss_features;
649514c6
TV		 937 break;
938
939 case OMAPDSS_VER_AM35xx:
940 omap_current_dss_features = &am35xx_dss_features;
941 break;
942
d6279d4a
SP		 943 case OMAPDSS_VER_AM43xx:
944 omap_current_dss_features = &am43xx_dss_features;
945 break;
946
649514c6 947 default:
6ff7084e 948 DSSWARN("Unsupported OMAP version");
649514c6
TV		 949 break;
950 }
e1ef4d23 951}
Linux kernel - Deliverables
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