[deliverable/linux.git] / drivers / gpu / drm / omapdrm / dss / hdmi.h

/*
 * HDMI driver definition for TI OMAP4 Processor.
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _HDMI_H
#define _HDMI_H

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/hdmi.h>
#include <video/omapdss.h>

#include "dss.h"

/* HDMI Wrapper */

#define HDMI_WP_REVISION			0x0
#define HDMI_WP_SYSCONFIG			0x10
#define HDMI_WP_IRQSTATUS_RAW			0x24
#define HDMI_WP_IRQSTATUS			0x28
#define HDMI_WP_IRQENABLE_SET			0x2C
#define HDMI_WP_IRQENABLE_CLR			0x30
#define HDMI_WP_IRQWAKEEN			0x34
#define HDMI_WP_PWR_CTRL			0x40
#define HDMI_WP_DEBOUNCE			0x44
#define HDMI_WP_VIDEO_CFG			0x50
#define HDMI_WP_VIDEO_SIZE			0x60
#define HDMI_WP_VIDEO_TIMING_H			0x68
#define HDMI_WP_VIDEO_TIMING_V			0x6C
#define HDMI_WP_CLK				0x70
#define HDMI_WP_AUDIO_CFG			0x80
#define HDMI_WP_AUDIO_CFG2			0x84
#define HDMI_WP_AUDIO_CTRL			0x88
#define HDMI_WP_AUDIO_DATA			0x8C

/* HDMI WP IRQ flags */
#define HDMI_IRQ_CORE				(1 << 0)
#define HDMI_IRQ_OCP_TIMEOUT			(1 << 4)
#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW		(1 << 8)
#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW		(1 << 9)
#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ		(1 << 10)
#define HDMI_IRQ_VIDEO_VSYNC			(1 << 16)
#define HDMI_IRQ_VIDEO_FRAME_DONE		(1 << 17)
#define HDMI_IRQ_PHY_LINE5V_ASSERT		(1 << 24)
#define HDMI_IRQ_LINK_CONNECT			(1 << 25)
#define HDMI_IRQ_LINK_DISCONNECT		(1 << 26)
#define HDMI_IRQ_PLL_LOCK			(1 << 29)
#define HDMI_IRQ_PLL_UNLOCK			(1 << 30)
#define HDMI_IRQ_PLL_RECAL			(1 << 31)

/* HDMI PLL */

#define PLLCTRL_PLL_CONTROL			0x0
#define PLLCTRL_PLL_STATUS			0x4
#define PLLCTRL_PLL_GO				0x8
#define PLLCTRL_CFG1				0xC
#define PLLCTRL_CFG2				0x10
#define PLLCTRL_CFG3				0x14
#define PLLCTRL_SSC_CFG1			0x18
#define PLLCTRL_SSC_CFG2			0x1C
#define PLLCTRL_CFG4				0x20

/* HDMI PHY */

#define HDMI_TXPHY_TX_CTRL			0x0
#define HDMI_TXPHY_DIGITAL_CTRL			0x4
#define HDMI_TXPHY_POWER_CTRL			0x8
#define HDMI_TXPHY_PAD_CFG_CTRL			0xC
#define HDMI_TXPHY_BIST_CONTROL			0x1C

enum hdmi_pll_pwr {
	HDMI_PLLPWRCMD_ALLOFF = 0,
	HDMI_PLLPWRCMD_PLLONLY = 1,
	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
};

enum hdmi_phy_pwr {
	HDMI_PHYPWRCMD_OFF = 0,
	HDMI_PHYPWRCMD_LDOON = 1,
	HDMI_PHYPWRCMD_TXON = 2
};

enum hdmi_core_hdmi_dvi {
	HDMI_DVI = 0,
	HDMI_HDMI = 1
};

enum hdmi_packing_mode {
	HDMI_PACK_10b_RGB_YUV444 = 0,
	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
	HDMI_PACK_20b_YUV422 = 2,
	HDMI_PACK_ALREADYPACKED = 7
};

enum hdmi_stereo_channels {
	HDMI_AUDIO_STEREO_NOCHANNELS = 0,
	HDMI_AUDIO_STEREO_ONECHANNEL = 1,
	HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
	HDMI_AUDIO_STEREO_THREECHANNELS = 3,
	HDMI_AUDIO_STEREO_FOURCHANNELS = 4
};

enum hdmi_audio_type {
	HDMI_AUDIO_TYPE_LPCM = 0,
	HDMI_AUDIO_TYPE_IEC = 1
};

enum hdmi_audio_justify {
	HDMI_AUDIO_JUSTIFY_LEFT = 0,
	HDMI_AUDIO_JUSTIFY_RIGHT = 1
};

enum hdmi_audio_sample_order {
	HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
	HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
};

enum hdmi_audio_samples_perword {
	HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
	HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
};

enum hdmi_audio_sample_size_omap {
	HDMI_AUDIO_SAMPLE_16BITS = 0,
	HDMI_AUDIO_SAMPLE_24BITS = 1
};

enum hdmi_audio_transf_mode {
	HDMI_AUDIO_TRANSF_DMA = 0,
	HDMI_AUDIO_TRANSF_IRQ = 1
};

enum hdmi_audio_blk_strt_end_sig {
	HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
};

enum hdmi_core_audio_layout {
	HDMI_AUDIO_LAYOUT_2CH = 0,
	HDMI_AUDIO_LAYOUT_8CH = 1,
	HDMI_AUDIO_LAYOUT_6CH = 2
};

enum hdmi_core_cts_mode {
	HDMI_AUDIO_CTS_MODE_HW = 0,
	HDMI_AUDIO_CTS_MODE_SW = 1
};

enum hdmi_audio_mclk_mode {
	HDMI_AUDIO_MCLK_128FS = 0,
	HDMI_AUDIO_MCLK_256FS = 1,
	HDMI_AUDIO_MCLK_384FS = 2,
	HDMI_AUDIO_MCLK_512FS = 3,
	HDMI_AUDIO_MCLK_768FS = 4,
	HDMI_AUDIO_MCLK_1024FS = 5,
	HDMI_AUDIO_MCLK_1152FS = 6,
	HDMI_AUDIO_MCLK_192FS = 7
};

struct hdmi_video_format {
	enum hdmi_packing_mode	packing_mode;
	u32			y_res;	/* Line per panel */
	u32			x_res;	/* pixel per line */
};

struct hdmi_config {
	struct omap_video_timings timings;
	struct hdmi_avi_infoframe infoframe;
	enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
};

struct hdmi_audio_format {
	enum hdmi_stereo_channels		stereo_channels;
	u8					active_chnnls_msk;
	enum hdmi_audio_type			type;
	enum hdmi_audio_justify			justification;
	enum hdmi_audio_sample_order		sample_order;
	enum hdmi_audio_samples_perword		samples_per_word;
	enum hdmi_audio_sample_size_omap	sample_size;
	enum hdmi_audio_blk_strt_end_sig	en_sig_blk_strt_end;
};

struct hdmi_audio_dma {
	u8				transfer_size;
	u8				block_size;
	enum hdmi_audio_transf_mode	mode;
	u16				fifo_threshold;
};

struct hdmi_core_audio_i2s_config {
	u8 in_length_bits;
	u8 justification;
	u8 sck_edge_mode;
	u8 vbit;
	u8 direction;
	u8 shift;
	u8 active_sds;
};

struct hdmi_core_audio_config {
	struct hdmi_core_audio_i2s_config	i2s_cfg;
	struct snd_aes_iec958			*iec60958_cfg;
	bool					fs_override;
	u32					n;
	u32					cts;
	u32					aud_par_busclk;
	enum hdmi_core_audio_layout		layout;
	enum hdmi_core_cts_mode			cts_mode;
	bool					use_mclk;
	enum hdmi_audio_mclk_mode		mclk_mode;
	bool					en_acr_pkt;
	bool					en_dsd_audio;
	bool					en_parallel_aud_input;
	bool					en_spdif;
};

struct hdmi_wp_data {
	void __iomem *base;
	phys_addr_t phys_base;
};

struct hdmi_pll_data {
	struct dss_pll pll;

	void __iomem *base;

	struct hdmi_wp_data *wp;
};

struct hdmi_phy_data {
	void __iomem *base;

	u8 lane_function[4];
	u8 lane_polarity[4];
};

struct hdmi_core_data {
	void __iomem *base;
};

static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
		u32 val)
{
	__raw_writel(val, base_addr + idx);
}

static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
{
	return __raw_readl(base_addr + idx);
}

#define REG_FLD_MOD(base, idx, val, start, end) \
	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
							val, start, end))
#define REG_GET(base, idx, start, end) \
	FLD_GET(hdmi_read_reg(base, idx), start, end)

static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
		const u32 idx, int b2, int b1, u32 val)
{
	u32 t = 0, v;
	while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
		if (t++ > 10000)
			return v;
		udelay(1);
	}
	return v;
}

/* HDMI wrapper funcs */
int hdmi_wp_video_start(struct hdmi_wp_data *wp);
void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
		struct hdmi_video_format *video_fmt);
void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
		struct omap_video_timings *timings);
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
		struct omap_video_timings *timings);
void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
		struct omap_video_timings *timings, struct hdmi_config *param);
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);

/* HDMI PLL funcs */
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
void hdmi_pll_compute(struct hdmi_pll_data *pll,
	unsigned long target_tmds, struct dss_pll_clock_info *pi);
int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
	struct hdmi_wp_data *wp);
void hdmi_pll_uninit(struct hdmi_pll_data *hpll);

/* HDMI PHY funcs */
int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
	unsigned long lfbitclk);
void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);

/* HDMI common funcs */
int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
	struct hdmi_phy_data *phy);

/* Audio funcs */
int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
		struct hdmi_audio_format *aud_fmt);
void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
		struct hdmi_audio_dma *aud_dma);
static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
{
	return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
}

/* HDMI DRV data */
struct omap_hdmi {
	struct mutex lock;
	struct platform_device *pdev;

	struct hdmi_wp_data	wp;
	struct hdmi_pll_data	pll;
	struct hdmi_phy_data	phy;
	struct hdmi_core_data	core;

	struct hdmi_config cfg;

	struct regulator *vdda_reg;

	bool core_enabled;

	struct omap_dss_device output;

	struct platform_device *audio_pdev;
	void (*audio_abort_cb)(struct device *dev);
	int wp_idlemode;

	bool audio_configured;
	struct omap_dss_audio audio_config;

	/* This lock should be taken when booleans bellow are touched. */
	spinlock_t audio_playing_lock;
	bool audio_playing;
	bool display_enabled;
};

#endif
Commit	Line	Data
94c52987	1	/*
ef26958a	2	* HDMI driver definition for TI OMAP4 Processor.
94c52987 M	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
ef26958a AT	19	#ifndef _HDMI_H
ef26958a AT	20	#define _HDMI_H
94c52987	21
bdb8bfc6 AT	22	#include <linux/delay.h>
bdb8bfc6 AT	23	#include <linux/io.h>
f382d9eb	24	#include <linux/platform_device.h>
db85ca7c	25	#include <linux/hdmi.h>
bdb8bfc6 AT	26	#include <video/omapdss.h>
	27
	28	#include "dss.h"
	29
	30	/* HDMI Wrapper */
	31
	32	#define HDMI_WP_REVISION 0x0
	33	#define HDMI_WP_SYSCONFIG 0x10
	34	#define HDMI_WP_IRQSTATUS_RAW 0x24
	35	#define HDMI_WP_IRQSTATUS 0x28
	36	#define HDMI_WP_IRQENABLE_SET 0x2C
	37	#define HDMI_WP_IRQENABLE_CLR 0x30
	38	#define HDMI_WP_IRQWAKEEN 0x34
	39	#define HDMI_WP_PWR_CTRL 0x40
	40	#define HDMI_WP_DEBOUNCE 0x44
	41	#define HDMI_WP_VIDEO_CFG 0x50
	42	#define HDMI_WP_VIDEO_SIZE 0x60
	43	#define HDMI_WP_VIDEO_TIMING_H 0x68
	44	#define HDMI_WP_VIDEO_TIMING_V 0x6C
42116517	45	#define HDMI_WP_CLK 0x70
bdb8bfc6 AT	46	#define HDMI_WP_AUDIO_CFG 0x80
	47	#define HDMI_WP_AUDIO_CFG2 0x84
	48	#define HDMI_WP_AUDIO_CTRL 0x88
	49	#define HDMI_WP_AUDIO_DATA 0x8C
	50
8696131f	51	/* HDMI WP IRQ flags */
6873efe1	52	#define HDMI_IRQ_CORE (1 << 0)
8696131f AT	53	#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
	54	#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
	55	#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
	56	#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
	57	#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
	58	#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
	59	#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
	60	#define HDMI_IRQ_LINK_CONNECT (1 << 25)
	61	#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
	62	#define HDMI_IRQ_PLL_LOCK (1 << 29)
	63	#define HDMI_IRQ_PLL_UNLOCK (1 << 30)
	64	#define HDMI_IRQ_PLL_RECAL (1 << 31)
	65
bdb8bfc6 AT	66	/* HDMI PLL */
	67
	68	#define PLLCTRL_PLL_CONTROL 0x0
	69	#define PLLCTRL_PLL_STATUS 0x4
	70	#define PLLCTRL_PLL_GO 0x8
	71	#define PLLCTRL_CFG1 0xC
	72	#define PLLCTRL_CFG2 0x10
	73	#define PLLCTRL_CFG3 0x14
	74	#define PLLCTRL_SSC_CFG1 0x18
	75	#define PLLCTRL_SSC_CFG2 0x1C
	76	#define PLLCTRL_CFG4 0x20
	77
	78	/* HDMI PHY */
	79
	80	#define HDMI_TXPHY_TX_CTRL 0x0
	81	#define HDMI_TXPHY_DIGITAL_CTRL 0x4
	82	#define HDMI_TXPHY_POWER_CTRL 0x8
	83	#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
19289fdc	84	#define HDMI_TXPHY_BIST_CONTROL 0x1C
f382d9eb	85
94c52987 M	86	enum hdmi_pll_pwr {
	87	HDMI_PLLPWRCMD_ALLOFF = 0,
	88	HDMI_PLLPWRCMD_PLLONLY = 1,
	89	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
	90	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
	91	};
	92
f382d9eb AT	93	enum hdmi_phy_pwr {
	94	HDMI_PHYPWRCMD_OFF = 0,
	95	HDMI_PHYPWRCMD_LDOON = 1,
	96	HDMI_PHYPWRCMD_TXON = 2
	97	};
	98
94c52987 M	99	enum hdmi_core_hdmi_dvi {
	100	HDMI_DVI = 0,
	101	HDMI_HDMI = 1
	102	};
	103
f382d9eb AT	104	enum hdmi_packing_mode {
	105	HDMI_PACK_10b_RGB_YUV444 = 0,
	106	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
	107	HDMI_PACK_20b_YUV422 = 2,
	108	HDMI_PACK_ALREADYPACKED = 7
	109	};
	110
	111	enum hdmi_stereo_channels {
	112	HDMI_AUDIO_STEREO_NOCHANNELS = 0,
	113	HDMI_AUDIO_STEREO_ONECHANNEL = 1,
	114	HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
	115	HDMI_AUDIO_STEREO_THREECHANNELS = 3,
	116	HDMI_AUDIO_STEREO_FOURCHANNELS = 4
	117	};
	118
	119	enum hdmi_audio_type {
	120	HDMI_AUDIO_TYPE_LPCM = 0,
	121	HDMI_AUDIO_TYPE_IEC = 1
	122	};
	123
	124	enum hdmi_audio_justify {
	125	HDMI_AUDIO_JUSTIFY_LEFT = 0,
	126	HDMI_AUDIO_JUSTIFY_RIGHT = 1
	127	};
	128
	129	enum hdmi_audio_sample_order {
	130	HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
	131	HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
	132	};
	133
	134	enum hdmi_audio_samples_perword {
	135	HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
	136	HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
	137	};
	138
d27d20c8	139	enum hdmi_audio_sample_size_omap {
f382d9eb AT	140	HDMI_AUDIO_SAMPLE_16BITS = 0,
	141	HDMI_AUDIO_SAMPLE_24BITS = 1
	142	};
	143
	144	enum hdmi_audio_transf_mode {
	145	HDMI_AUDIO_TRANSF_DMA = 0,
	146	HDMI_AUDIO_TRANSF_IRQ = 1
	147	};
	148
	149	enum hdmi_audio_blk_strt_end_sig {
	150	HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
	151	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
	152	};
	153
bdb8bfc6 AT	154	enum hdmi_core_audio_layout {
bdb8bfc6 AT	155	HDMI_AUDIO_LAYOUT_2CH = 0,
652ce043 JS	156	HDMI_AUDIO_LAYOUT_8CH = 1,
652ce043 JS	157	HDMI_AUDIO_LAYOUT_6CH = 2
bdb8bfc6 AT	158	};
	159
	160	enum hdmi_core_cts_mode {
	161	HDMI_AUDIO_CTS_MODE_HW = 0,
	162	HDMI_AUDIO_CTS_MODE_SW = 1
	163	};
	164
	165	enum hdmi_audio_mclk_mode {
	166	HDMI_AUDIO_MCLK_128FS = 0,
	167	HDMI_AUDIO_MCLK_256FS = 1,
	168	HDMI_AUDIO_MCLK_384FS = 2,
	169	HDMI_AUDIO_MCLK_512FS = 3,
	170	HDMI_AUDIO_MCLK_768FS = 4,
	171	HDMI_AUDIO_MCLK_1024FS = 5,
	172	HDMI_AUDIO_MCLK_1152FS = 6,
	173	HDMI_AUDIO_MCLK_192FS = 7
	174	};
	175
f382d9eb AT	176	struct hdmi_video_format {
	177	enum hdmi_packing_mode packing_mode;
	178	u32 y_res; /* Line per panel */
	179	u32 x_res; /* pixel per line */
	180	};
	181
94c52987	182	struct hdmi_config {
cc937e5e	183	struct omap_video_timings timings;
c9d2c799 TV	184	struct hdmi_avi_infoframe infoframe;
c9d2c799 TV	185	enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
94c52987 M	186	};
94c52987 M	187
f382d9eb AT	188	struct hdmi_audio_format {
	189	enum hdmi_stereo_channels stereo_channels;
	190	u8 active_chnnls_msk;
	191	enum hdmi_audio_type type;
	192	enum hdmi_audio_justify justification;
	193	enum hdmi_audio_sample_order sample_order;
	194	enum hdmi_audio_samples_perword samples_per_word;
d27d20c8	195	enum hdmi_audio_sample_size_omap sample_size;
f382d9eb AT	196	enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
	197	};
	198
	199	struct hdmi_audio_dma {
	200	u8 transfer_size;
	201	u8 block_size;
	202	enum hdmi_audio_transf_mode mode;
	203	u16 fifo_threshold;
	204	};
	205
bdb8bfc6 AT	206	struct hdmi_core_audio_i2s_config {
	207	u8 in_length_bits;
	208	u8 justification;
	209	u8 sck_edge_mode;
	210	u8 vbit;
	211	u8 direction;
	212	u8 shift;
	213	u8 active_sds;
	214	};
	215
	216	struct hdmi_core_audio_config {
	217	struct hdmi_core_audio_i2s_config i2s_cfg;
	218	struct snd_aes_iec958 *iec60958_cfg;
	219	bool fs_override;
	220	u32 n;
	221	u32 cts;
	222	u32 aud_par_busclk;
	223	enum hdmi_core_audio_layout layout;
	224	enum hdmi_core_cts_mode cts_mode;
	225	bool use_mclk;
	226	enum hdmi_audio_mclk_mode mclk_mode;
	227	bool en_acr_pkt;
	228	bool en_dsd_audio;
	229	bool en_parallel_aud_input;
	230	bool en_spdif;
	231	};
	232
f382d9eb AT	233	struct hdmi_wp_data {
f382d9eb AT	234	void __iomem *base;
58652163	235	phys_addr_t phys_base;
f382d9eb AT	236	};
f382d9eb AT	237
c1577c1e	238	struct hdmi_pll_data {
c84c3a5b TV	239	struct dss_pll pll;
c84c3a5b TV	240
c1577c1e AT	241	void __iomem *base;
c1577c1e AT	242
03aafa2c	243	struct hdmi_wp_data *wp;
c1577c1e AT	244	};
c1577c1e AT	245
5cac5aee AT	246	struct hdmi_phy_data {
	247	void __iomem *base;
	248
2f5dc676 TV	249	u8 lane_function[4];
2f5dc676 TV	250	u8 lane_polarity[4];
5cac5aee AT	251	};
5cac5aee AT	252
425f02fd AT	253	struct hdmi_core_data {
425f02fd AT	254	void __iomem *base;
425f02fd AT	255	};
425f02fd AT	256
8955b727	257	static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
bdb8bfc6 AT	258	u32 val)
	259	{
	260	__raw_writel(val, base_addr + idx);
	261	}
	262
8955b727	263	static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
bdb8bfc6 AT	264	{
	265	return __raw_readl(base_addr + idx);
	266	}
	267
	268	#define REG_FLD_MOD(base, idx, val, start, end) \
	269	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
	270	val, start, end))
	271	#define REG_GET(base, idx, start, end) \
	272	FLD_GET(hdmi_read_reg(base, idx), start, end)
	273
	274	static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
91b53e6a	275	const u32 idx, int b2, int b1, u32 val)
bdb8bfc6	276	{
91b53e6a TV	277	u32 t = 0, v;
91b53e6a TV	278	while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
bdb8bfc6	279	if (t++ > 10000)
91b53e6a TV	280	return v;
91b53e6a TV	281	udelay(1);
bdb8bfc6	282	}
91b53e6a	283	return v;
bdb8bfc6 AT	284	}
bdb8bfc6 AT	285
f382d9eb AT	286	/* HDMI wrapper funcs */
	287	int hdmi_wp_video_start(struct hdmi_wp_data *wp);
	288	void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
	289	void hdmi_wp_dump(struct hdmi_wp_data wp, struct seq_file s);
	290	u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
	291	void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
	292	void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
	293	void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
	294	int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
	295	int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
	296	void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
	297	struct hdmi_video_format *video_fmt);
	298	void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
	299	struct omap_video_timings *timings);
	300	void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
	301	struct omap_video_timings *timings);
	302	void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
	303	struct omap_video_timings timings, struct hdmi_config param);
	304	int hdmi_wp_init(struct platform_device pdev, struct hdmi_wp_data wp);
58652163	305	phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
f382d9eb	306
c1577c1e	307	/* HDMI PLL funcs */
c1577c1e	308	void hdmi_pll_dump(struct hdmi_pll_data pll, struct seq_file s);
c84c3a5b TV	309	void hdmi_pll_compute(struct hdmi_pll_data *pll,
c84c3a5b TV	310	unsigned long target_tmds, struct dss_pll_clock_info *pi);
03aafa2c TV	311	int hdmi_pll_init(struct platform_device pdev, struct hdmi_pll_data pll,
03aafa2c TV	312	struct hdmi_wp_data *wp);
c84c3a5b	313	void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
c1577c1e	314
5cac5aee	315	/* HDMI PHY funcs */
33f13120 TV	316	int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
33f13120 TV	317	unsigned long lfbitclk);
5cac5aee AT	318	void hdmi_phy_dump(struct hdmi_phy_data phy, struct seq_file s);
5cac5aee AT	319	int hdmi_phy_init(struct platform_device pdev, struct hdmi_phy_data phy);
2f5dc676	320	int hdmi_phy_parse_lanes(struct hdmi_phy_data phy, const u32 lanes);
5cac5aee	321
08d83e4e	322	/* HDMI common funcs */
2f5dc676 TV	323	int hdmi_parse_lanes_of(struct platform_device pdev, struct device_node ep,
2f5dc676 TV	324	struct hdmi_phy_data *phy);
08d83e4e	325
12d3ea9a	326	/* Audio funcs */
08d83e4e	327	int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 n, u32 cts);
f382d9eb AT	328	int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
	329	int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
	330	void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
	331	struct hdmi_audio_format *aud_fmt);
	332	void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
	333	struct hdmi_audio_dma *aud_dma);
5a8bf632	334	static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
08d83e4e	335	{
5a8bf632	336	return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
08d83e4e	337	}
945514b5 JS	338
	339	/* HDMI DRV data */
	340	struct omap_hdmi {
	341	struct mutex lock;
	342	struct platform_device *pdev;
	343
	344	struct hdmi_wp_data wp;
	345	struct hdmi_pll_data pll;
	346	struct hdmi_phy_data phy;
	347	struct hdmi_core_data core;
	348
	349	struct hdmi_config cfg;
	350
	351	struct regulator *vdda_reg;
	352
	353	bool core_enabled;
	354
	355	struct omap_dss_device output;
29c047b7 JS	356
29c047b7 JS	357	struct platform_device *audio_pdev;
5872b35a	358	void (audio_abort_cb)(struct device dev);
2d7639bc	359	int wp_idlemode;
8a9d4626 JS	360
	361	bool audio_configured;
	362	struct omap_dss_audio audio_config;
	363
	364	/* This lock should be taken when booleans bellow are touched. */
	365	spinlock_t audio_playing_lock;
	366	bool audio_playing;
	367	bool display_enabled;
945514b5 JS	368	};
945514b5 JS	369
80a48596	370	#endif