Commit | Line | Data |
---|---|---|
c3198a5e | 1 | /* |
ef26958a | 2 | * HDMI interface DSS driver for TI's OMAP4 family of SoCs. |
c3198a5e M |
3 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
4 | * Authors: Yong Zhi | |
5 | * Mythri pk <mythripk@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "HDMI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/mutex.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/string.h> | |
24e6289c | 30 | #include <linux/platform_device.h> |
4fbafaf3 TV |
31 | #include <linux/pm_runtime.h> |
32 | #include <linux/clk.h> | |
cca35017 | 33 | #include <linux/gpio.h> |
17486943 | 34 | #include <linux/regulator/consumer.h> |
736e60dd | 35 | #include <linux/component.h> |
d9e32ecd | 36 | #include <linux/of.h> |
4d594dff | 37 | #include <sound/omap-hdmi-audio.h> |
c3198a5e | 38 | |
32043da7 | 39 | #include "omapdss.h" |
ef26958a | 40 | #include "hdmi4_core.h" |
c3198a5e | 41 | #include "dss.h" |
ad44cc32 | 42 | #include "dss_features.h" |
945514b5 | 43 | #include "hdmi.h" |
c3198a5e | 44 | |
945514b5 | 45 | static struct omap_hdmi hdmi; |
c3198a5e | 46 | |
4fbafaf3 TV |
47 | static int hdmi_runtime_get(void) |
48 | { | |
49 | int r; | |
50 | ||
51 | DSSDBG("hdmi_runtime_get\n"); | |
52 | ||
53 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
54 | WARN_ON(r < 0); | |
a247ce78 | 55 | if (r < 0) |
852f0838 | 56 | return r; |
a247ce78 AT |
57 | |
58 | return 0; | |
4fbafaf3 TV |
59 | } |
60 | ||
61 | static void hdmi_runtime_put(void) | |
62 | { | |
63 | int r; | |
64 | ||
65 | DSSDBG("hdmi_runtime_put\n"); | |
66 | ||
0eaf9f52 | 67 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
5be3aebd | 68 | WARN_ON(r < 0 && r != -ENOSYS); |
4fbafaf3 TV |
69 | } |
70 | ||
dcf5f729 TV |
71 | static irqreturn_t hdmi_irq_handler(int irq, void *data) |
72 | { | |
73 | struct hdmi_wp_data *wp = data; | |
74 | u32 irqstatus; | |
75 | ||
76 | irqstatus = hdmi_wp_get_irqstatus(wp); | |
77 | hdmi_wp_set_irqstatus(wp, irqstatus); | |
78 | ||
79 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && | |
80 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
81 | /* | |
82 | * If we get both connect and disconnect interrupts at the same | |
83 | * time, turn off the PHY, clear interrupts, and restart, which | |
84 | * raises connect interrupt if a cable is connected, or nothing | |
85 | * if cable is not connected. | |
86 | */ | |
87 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | |
88 | ||
89 | hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | | |
90 | HDMI_IRQ_LINK_DISCONNECT); | |
91 | ||
92 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
93 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { | |
94 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); | |
95 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
96 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
97 | } | |
98 | ||
99 | return IRQ_HANDLED; | |
100 | } | |
101 | ||
e25001d8 TV |
102 | static int hdmi_init_regulator(void) |
103 | { | |
104 | struct regulator *reg; | |
105 | ||
945514b5 | 106 | if (hdmi.vdda_reg != NULL) |
e25001d8 TV |
107 | return 0; |
108 | ||
931d4bd6 | 109 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); |
e25001d8 TV |
110 | |
111 | if (IS_ERR(reg)) { | |
40359a9b | 112 | if (PTR_ERR(reg) != -EPROBE_DEFER) |
931d4bd6 | 113 | DSSERR("can't get VDDA regulator\n"); |
e25001d8 TV |
114 | return PTR_ERR(reg); |
115 | } | |
116 | ||
945514b5 | 117 | hdmi.vdda_reg = reg; |
e25001d8 TV |
118 | |
119 | return 0; | |
120 | } | |
121 | ||
bb426fc9 | 122 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) |
c3198a5e | 123 | { |
46095b2d | 124 | int r; |
c3198a5e | 125 | |
945514b5 | 126 | r = regulator_enable(hdmi.vdda_reg); |
17486943 | 127 | if (r) |
164ebdd1 | 128 | return r; |
17486943 | 129 | |
4fbafaf3 TV |
130 | r = hdmi_runtime_get(); |
131 | if (r) | |
cca35017 | 132 | goto err_runtime_get; |
c3198a5e | 133 | |
bb426fc9 TV |
134 | /* Make selection of HDMI in DSS */ |
135 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
136 | ||
0b450c31 TV |
137 | hdmi.core_enabled = true; |
138 | ||
bb426fc9 TV |
139 | return 0; |
140 | ||
141 | err_runtime_get: | |
945514b5 | 142 | regulator_disable(hdmi.vdda_reg); |
164ebdd1 | 143 | |
bb426fc9 TV |
144 | return r; |
145 | } | |
146 | ||
147 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | |
148 | { | |
0b450c31 TV |
149 | hdmi.core_enabled = false; |
150 | ||
bb426fc9 | 151 | hdmi_runtime_put(); |
945514b5 | 152 | regulator_disable(hdmi.vdda_reg); |
bb426fc9 TV |
153 | } |
154 | ||
155 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |
156 | { | |
157 | int r; | |
158 | struct omap_video_timings *p; | |
46e1ef3b | 159 | enum omap_channel channel = dssdev->dispc_channel; |
dcf5f729 | 160 | struct hdmi_wp_data *wp = &hdmi.wp; |
c84c3a5b | 161 | struct dss_pll_clock_info hdmi_cinfo = { 0 }; |
67d8ffdd | 162 | unsigned pc; |
bb426fc9 TV |
163 | |
164 | r = hdmi_power_on_core(dssdev); | |
165 | if (r) | |
166 | return r; | |
167 | ||
dcf5f729 TV |
168 | /* disable and clear irqs */ |
169 | hdmi_wp_clear_irqenable(wp, 0xffffffff); | |
170 | hdmi_wp_set_irqstatus(wp, 0xffffffff); | |
171 | ||
275cfa1a | 172 | p = &hdmi.cfg.timings; |
c3198a5e | 173 | |
7849398f | 174 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); |
c3198a5e | 175 | |
67d8ffdd TV |
176 | pc = p->pixelclock; |
177 | if (p->double_pixel) | |
178 | pc *= 2; | |
179 | ||
c107751d TV |
180 | /* DSS_HDMI_TCLK is bitclk / 10 */ |
181 | pc *= 10; | |
182 | ||
c17dc0e3 TV |
183 | dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin), |
184 | pc, &hdmi_cinfo); | |
c3198a5e | 185 | |
c84c3a5b | 186 | r = dss_pll_enable(&hdmi.pll.pll); |
c3198a5e | 187 | if (r) { |
c2fbd061 | 188 | DSSERR("Failed to enable PLL\n"); |
cca35017 | 189 | goto err_pll_enable; |
c3198a5e M |
190 | } |
191 | ||
c84c3a5b | 192 | r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); |
c2fbd061 TV |
193 | if (r) { |
194 | DSSERR("Failed to configure PLL\n"); | |
195 | goto err_pll_cfg; | |
196 | } | |
197 | ||
c84c3a5b TV |
198 | r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco, |
199 | hdmi_cinfo.clkout[0]); | |
c3198a5e | 200 | if (r) { |
dcf5f729 TV |
201 | DSSDBG("Failed to configure PHY\n"); |
202 | goto err_phy_cfg; | |
c3198a5e M |
203 | } |
204 | ||
dcf5f729 TV |
205 | r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); |
206 | if (r) | |
207 | goto err_phy_pwr; | |
208 | ||
275cfa1a | 209 | hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); |
c3198a5e | 210 | |
c3198a5e | 211 | /* tv size */ |
46e1ef3b | 212 | dss_mgr_set_timings(channel, p); |
c3198a5e | 213 | |
46e1ef3b | 214 | r = dss_mgr_enable(channel); |
33ca237f TV |
215 | if (r) |
216 | goto err_mgr_enable; | |
3870c909 | 217 | |
4e4b53ce TV |
218 | r = hdmi_wp_video_start(&hdmi.wp); |
219 | if (r) | |
220 | goto err_vid_enable; | |
221 | ||
dcf5f729 TV |
222 | hdmi_wp_set_irqenable(wp, |
223 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | |
224 | ||
c3198a5e | 225 | return 0; |
33ca237f | 226 | |
c0456be3 | 227 | err_vid_enable: |
46e1ef3b | 228 | dss_mgr_disable(channel); |
4e4b53ce | 229 | err_mgr_enable: |
dcf5f729 TV |
230 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); |
231 | err_phy_pwr: | |
9bba13f0 | 232 | err_phy_cfg: |
c2fbd061 | 233 | err_pll_cfg: |
c84c3a5b | 234 | dss_pll_disable(&hdmi.pll.pll); |
cca35017 | 235 | err_pll_enable: |
bb426fc9 | 236 | hdmi_power_off_core(dssdev); |
c3198a5e M |
237 | return -EIO; |
238 | } | |
239 | ||
bb426fc9 | 240 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) |
c3198a5e | 241 | { |
46e1ef3b | 242 | enum omap_channel channel = dssdev->dispc_channel; |
cea87b92 | 243 | |
dcf5f729 TV |
244 | hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); |
245 | ||
275cfa1a | 246 | hdmi_wp_video_stop(&hdmi.wp); |
dcf5f729 | 247 | |
46e1ef3b | 248 | dss_mgr_disable(channel); |
4e4b53ce | 249 | |
dcf5f729 TV |
250 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); |
251 | ||
c84c3a5b | 252 | dss_pll_disable(&hdmi.pll.pll); |
17486943 | 253 | |
bb426fc9 | 254 | hdmi_power_off_core(dssdev); |
c3198a5e M |
255 | } |
256 | ||
164ebdd1 | 257 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, |
c3198a5e M |
258 | struct omap_video_timings *timings) |
259 | { | |
46e1ef3b | 260 | if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings)) |
c3198a5e | 261 | return -EINVAL; |
c3198a5e M |
262 | |
263 | return 0; | |
c3198a5e M |
264 | } |
265 | ||
164ebdd1 | 266 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, |
7849398f | 267 | struct omap_video_timings *timings) |
c3198a5e | 268 | { |
ed1aa900 AT |
269 | mutex_lock(&hdmi.lock); |
270 | ||
ab0aee95 | 271 | hdmi.cfg.timings = *timings; |
5391e87d | 272 | |
ab0aee95 | 273 | dispc_set_tv_pclk(timings->pixelclock); |
1e676248 | 274 | |
ed1aa900 | 275 | mutex_unlock(&hdmi.lock); |
c3198a5e M |
276 | } |
277 | ||
164ebdd1 | 278 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, |
0b450c31 TV |
279 | struct omap_video_timings *timings) |
280 | { | |
ab0aee95 | 281 | *timings = hdmi.cfg.timings; |
0b450c31 TV |
282 | } |
283 | ||
e40402cf | 284 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
285 | { |
286 | mutex_lock(&hdmi.lock); | |
287 | ||
f8fb7d7b WY |
288 | if (hdmi_runtime_get()) { |
289 | mutex_unlock(&hdmi.lock); | |
162874d5 | 290 | return; |
f8fb7d7b | 291 | } |
162874d5 | 292 | |
275cfa1a AT |
293 | hdmi_wp_dump(&hdmi.wp, s); |
294 | hdmi_pll_dump(&hdmi.pll, s); | |
295 | hdmi_phy_dump(&hdmi.phy, s); | |
296 | hdmi4_core_dump(&hdmi.core, s); | |
162874d5 M |
297 | |
298 | hdmi_runtime_put(); | |
299 | mutex_unlock(&hdmi.lock); | |
300 | } | |
301 | ||
164ebdd1 | 302 | static int read_edid(u8 *buf, int len) |
47024565 TV |
303 | { |
304 | int r; | |
305 | ||
306 | mutex_lock(&hdmi.lock); | |
307 | ||
308 | r = hdmi_runtime_get(); | |
309 | BUG_ON(r); | |
310 | ||
275cfa1a | 311 | r = hdmi4_read_edid(&hdmi.core, buf, len); |
47024565 TV |
312 | |
313 | hdmi_runtime_put(); | |
314 | mutex_unlock(&hdmi.lock); | |
315 | ||
316 | return r; | |
317 | } | |
318 | ||
8a9d4626 JS |
319 | static void hdmi_start_audio_stream(struct omap_hdmi *hd) |
320 | { | |
321 | hdmi_wp_audio_enable(&hd->wp, true); | |
322 | hdmi4_audio_start(&hd->core, &hd->wp); | |
323 | } | |
324 | ||
325 | static void hdmi_stop_audio_stream(struct omap_hdmi *hd) | |
326 | { | |
327 | hdmi4_audio_stop(&hd->core, &hd->wp); | |
328 | hdmi_wp_audio_enable(&hd->wp, false); | |
329 | } | |
330 | ||
164ebdd1 | 331 | static int hdmi_display_enable(struct omap_dss_device *dssdev) |
c3198a5e | 332 | { |
1f68d9c4 | 333 | struct omap_dss_device *out = &hdmi.output; |
8a9d4626 | 334 | unsigned long flags; |
c3198a5e M |
335 | int r = 0; |
336 | ||
337 | DSSDBG("ENTER hdmi_display_enable\n"); | |
338 | ||
339 | mutex_lock(&hdmi.lock); | |
340 | ||
f1504ad0 | 341 | if (!out->dispc_channel_connected) { |
cea87b92 | 342 | DSSERR("failed to enable display: no output/manager\n"); |
05e1d606 TV |
343 | r = -ENODEV; |
344 | goto err0; | |
345 | } | |
346 | ||
bb426fc9 | 347 | r = hdmi_power_on_full(dssdev); |
c3198a5e M |
348 | if (r) { |
349 | DSSERR("failed to power on device\n"); | |
d3923933 | 350 | goto err0; |
c3198a5e M |
351 | } |
352 | ||
8a9d4626 JS |
353 | if (hdmi.audio_configured) { |
354 | r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, | |
355 | hdmi.cfg.timings.pixelclock); | |
356 | if (r) { | |
357 | DSSERR("Error restoring audio configuration: %d", r); | |
358 | hdmi.audio_abort_cb(&hdmi.pdev->dev); | |
359 | hdmi.audio_configured = false; | |
360 | } | |
361 | } | |
362 | ||
363 | spin_lock_irqsave(&hdmi.audio_playing_lock, flags); | |
364 | if (hdmi.audio_configured && hdmi.audio_playing) | |
365 | hdmi_start_audio_stream(&hdmi); | |
4d594dff | 366 | hdmi.display_enabled = true; |
8a9d4626 | 367 | spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); |
4d594dff | 368 | |
c3198a5e M |
369 | mutex_unlock(&hdmi.lock); |
370 | return 0; | |
371 | ||
c3198a5e M |
372 | err0: |
373 | mutex_unlock(&hdmi.lock); | |
374 | return r; | |
375 | } | |
376 | ||
164ebdd1 | 377 | static void hdmi_display_disable(struct omap_dss_device *dssdev) |
c3198a5e | 378 | { |
8a9d4626 JS |
379 | unsigned long flags; |
380 | ||
c3198a5e M |
381 | DSSDBG("Enter hdmi_display_disable\n"); |
382 | ||
383 | mutex_lock(&hdmi.lock); | |
384 | ||
8a9d4626 JS |
385 | spin_lock_irqsave(&hdmi.audio_playing_lock, flags); |
386 | hdmi_stop_audio_stream(&hdmi); | |
387 | hdmi.display_enabled = false; | |
388 | spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); | |
4d594dff | 389 | |
bb426fc9 | 390 | hdmi_power_off_full(dssdev); |
c3198a5e | 391 | |
c3198a5e M |
392 | mutex_unlock(&hdmi.lock); |
393 | } | |
394 | ||
164ebdd1 | 395 | static int hdmi_core_enable(struct omap_dss_device *dssdev) |
4489823c TV |
396 | { |
397 | int r = 0; | |
398 | ||
399 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | |
400 | ||
401 | mutex_lock(&hdmi.lock); | |
402 | ||
4489823c TV |
403 | r = hdmi_power_on_core(dssdev); |
404 | if (r) { | |
405 | DSSERR("failed to power on device\n"); | |
406 | goto err0; | |
407 | } | |
408 | ||
409 | mutex_unlock(&hdmi.lock); | |
410 | return 0; | |
411 | ||
412 | err0: | |
413 | mutex_unlock(&hdmi.lock); | |
414 | return r; | |
415 | } | |
416 | ||
164ebdd1 | 417 | static void hdmi_core_disable(struct omap_dss_device *dssdev) |
4489823c TV |
418 | { |
419 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | |
420 | ||
421 | mutex_lock(&hdmi.lock); | |
422 | ||
423 | hdmi_power_off_core(dssdev); | |
424 | ||
425 | mutex_unlock(&hdmi.lock); | |
426 | } | |
427 | ||
0b450c31 TV |
428 | static int hdmi_connect(struct omap_dss_device *dssdev, |
429 | struct omap_dss_device *dst) | |
430 | { | |
46e1ef3b | 431 | enum omap_channel channel = dssdev->dispc_channel; |
0b450c31 TV |
432 | int r; |
433 | ||
0b450c31 TV |
434 | r = hdmi_init_regulator(); |
435 | if (r) | |
436 | return r; | |
437 | ||
46e1ef3b | 438 | r = dss_mgr_connect(channel, dssdev); |
0b450c31 TV |
439 | if (r) |
440 | return r; | |
441 | ||
442 | r = omapdss_output_set_device(dssdev, dst); | |
443 | if (r) { | |
444 | DSSERR("failed to connect output to new device: %s\n", | |
445 | dst->name); | |
46e1ef3b | 446 | dss_mgr_disconnect(channel, dssdev); |
0b450c31 TV |
447 | return r; |
448 | } | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | |
454 | struct omap_dss_device *dst) | |
455 | { | |
46e1ef3b TV |
456 | enum omap_channel channel = dssdev->dispc_channel; |
457 | ||
9560dc10 | 458 | WARN_ON(dst != dssdev->dst); |
0b450c31 | 459 | |
9560dc10 | 460 | if (dst != dssdev->dst) |
0b450c31 TV |
461 | return; |
462 | ||
463 | omapdss_output_unset_device(dssdev); | |
464 | ||
46e1ef3b | 465 | dss_mgr_disconnect(channel, dssdev); |
0b450c31 TV |
466 | } |
467 | ||
468 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | |
469 | u8 *edid, int len) | |
470 | { | |
471 | bool need_enable; | |
472 | int r; | |
473 | ||
474 | need_enable = hdmi.core_enabled == false; | |
475 | ||
476 | if (need_enable) { | |
164ebdd1 | 477 | r = hdmi_core_enable(dssdev); |
0b450c31 TV |
478 | if (r) |
479 | return r; | |
480 | } | |
481 | ||
164ebdd1 | 482 | r = read_edid(edid, len); |
0b450c31 TV |
483 | |
484 | if (need_enable) | |
164ebdd1 | 485 | hdmi_core_disable(dssdev); |
0b450c31 TV |
486 | |
487 | return r; | |
488 | } | |
489 | ||
ab0aee95 TV |
490 | static int hdmi_set_infoframe(struct omap_dss_device *dssdev, |
491 | const struct hdmi_avi_infoframe *avi) | |
492 | { | |
493 | hdmi.cfg.infoframe = *avi; | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, | |
498 | bool hdmi_mode) | |
499 | { | |
500 | hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; | |
501 | return 0; | |
502 | } | |
503 | ||
0b450c31 TV |
504 | static const struct omapdss_hdmi_ops hdmi_ops = { |
505 | .connect = hdmi_connect, | |
506 | .disconnect = hdmi_disconnect, | |
507 | ||
164ebdd1 TV |
508 | .enable = hdmi_display_enable, |
509 | .disable = hdmi_display_disable, | |
0b450c31 | 510 | |
164ebdd1 TV |
511 | .check_timings = hdmi_display_check_timing, |
512 | .set_timings = hdmi_display_set_timing, | |
513 | .get_timings = hdmi_display_get_timings, | |
0b450c31 TV |
514 | |
515 | .read_edid = hdmi_read_edid, | |
ab0aee95 TV |
516 | .set_infoframe = hdmi_set_infoframe, |
517 | .set_hdmi_mode = hdmi_set_hdmi_mode, | |
0b450c31 TV |
518 | }; |
519 | ||
17ae4e8c | 520 | static void hdmi_init_output(struct platform_device *pdev) |
81b87f51 | 521 | { |
1f68d9c4 | 522 | struct omap_dss_device *out = &hdmi.output; |
81b87f51 | 523 | |
1f68d9c4 | 524 | out->dev = &pdev->dev; |
81b87f51 | 525 | out->id = OMAP_DSS_OUTPUT_HDMI; |
1f68d9c4 | 526 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; |
7286a08f | 527 | out->name = "hdmi.0"; |
2eea5ae6 | 528 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; |
0b450c31 | 529 | out->ops.hdmi = &hdmi_ops; |
b7328e14 | 530 | out->owner = THIS_MODULE; |
81b87f51 | 531 | |
5d47dbc8 | 532 | omapdss_register_output(out); |
81b87f51 AT |
533 | } |
534 | ||
39c1b7bf | 535 | static void hdmi_uninit_output(struct platform_device *pdev) |
81b87f51 | 536 | { |
1f68d9c4 | 537 | struct omap_dss_device *out = &hdmi.output; |
81b87f51 | 538 | |
5d47dbc8 | 539 | omapdss_unregister_output(out); |
81b87f51 AT |
540 | } |
541 | ||
2f5dc676 TV |
542 | static int hdmi_probe_of(struct platform_device *pdev) |
543 | { | |
544 | struct device_node *node = pdev->dev.of_node; | |
545 | struct device_node *ep; | |
546 | int r; | |
547 | ||
548 | ep = omapdss_of_get_first_endpoint(node); | |
549 | if (!ep) | |
550 | return 0; | |
551 | ||
552 | r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); | |
553 | if (r) | |
554 | goto err; | |
555 | ||
556 | of_node_put(ep); | |
557 | return 0; | |
558 | ||
559 | err: | |
560 | of_node_put(ep); | |
561 | return r; | |
562 | } | |
563 | ||
4d594dff JS |
564 | /* Audio callbacks */ |
565 | static int hdmi_audio_startup(struct device *dev, | |
566 | void (*abort_cb)(struct device *dev)) | |
567 | { | |
568 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
569 | int ret = 0; | |
570 | ||
571 | mutex_lock(&hd->lock); | |
572 | ||
573 | if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { | |
574 | ret = -EPERM; | |
575 | goto out; | |
576 | } | |
577 | ||
578 | hd->audio_abort_cb = abort_cb; | |
579 | ||
580 | out: | |
581 | mutex_unlock(&hd->lock); | |
582 | ||
583 | return ret; | |
584 | } | |
585 | ||
586 | static int hdmi_audio_shutdown(struct device *dev) | |
587 | { | |
588 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
589 | ||
590 | mutex_lock(&hd->lock); | |
591 | hd->audio_abort_cb = NULL; | |
8a9d4626 JS |
592 | hd->audio_configured = false; |
593 | hd->audio_playing = false; | |
4d594dff JS |
594 | mutex_unlock(&hd->lock); |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int hdmi_audio_start(struct device *dev) | |
600 | { | |
601 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
8a9d4626 | 602 | unsigned long flags; |
4d594dff JS |
603 | |
604 | WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); | |
4d594dff | 605 | |
8a9d4626 JS |
606 | spin_lock_irqsave(&hd->audio_playing_lock, flags); |
607 | ||
608 | if (hd->display_enabled) | |
609 | hdmi_start_audio_stream(hd); | |
610 | hd->audio_playing = true; | |
4d594dff | 611 | |
8a9d4626 | 612 | spin_unlock_irqrestore(&hd->audio_playing_lock, flags); |
4d594dff JS |
613 | return 0; |
614 | } | |
615 | ||
616 | static void hdmi_audio_stop(struct device *dev) | |
617 | { | |
618 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
8a9d4626 | 619 | unsigned long flags; |
4d594dff JS |
620 | |
621 | WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); | |
4d594dff | 622 | |
8a9d4626 JS |
623 | spin_lock_irqsave(&hd->audio_playing_lock, flags); |
624 | ||
625 | if (hd->display_enabled) | |
626 | hdmi_stop_audio_stream(hd); | |
627 | hd->audio_playing = false; | |
628 | ||
629 | spin_unlock_irqrestore(&hd->audio_playing_lock, flags); | |
4d594dff JS |
630 | } |
631 | ||
632 | static int hdmi_audio_config(struct device *dev, | |
633 | struct omap_dss_audio *dss_audio) | |
634 | { | |
635 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
636 | int ret; | |
637 | ||
638 | mutex_lock(&hd->lock); | |
639 | ||
640 | if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { | |
641 | ret = -EPERM; | |
642 | goto out; | |
643 | } | |
644 | ||
645 | ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, | |
646 | hd->cfg.timings.pixelclock); | |
8a9d4626 JS |
647 | if (!ret) { |
648 | hd->audio_configured = true; | |
649 | hd->audio_config = *dss_audio; | |
650 | } | |
4d594dff JS |
651 | out: |
652 | mutex_unlock(&hd->lock); | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
657 | static const struct omap_hdmi_audio_ops hdmi_audio_ops = { | |
658 | .audio_startup = hdmi_audio_startup, | |
659 | .audio_shutdown = hdmi_audio_shutdown, | |
660 | .audio_start = hdmi_audio_start, | |
661 | .audio_stop = hdmi_audio_stop, | |
662 | .audio_config = hdmi_audio_config, | |
663 | }; | |
664 | ||
665 | static int hdmi_audio_register(struct device *dev) | |
666 | { | |
667 | struct omap_hdmi_audio_pdata pdata = { | |
668 | .dev = dev, | |
669 | .dss_version = omapdss_get_version(), | |
670 | .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), | |
671 | .ops = &hdmi_audio_ops, | |
672 | }; | |
673 | ||
674 | hdmi.audio_pdev = platform_device_register_data( | |
675 | dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO, | |
676 | &pdata, sizeof(pdata)); | |
677 | ||
678 | if (IS_ERR(hdmi.audio_pdev)) | |
679 | return PTR_ERR(hdmi.audio_pdev); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
c3198a5e | 684 | /* HDMI HW IP initialisation */ |
736e60dd | 685 | static int hdmi4_bind(struct device *dev, struct device *master, void *data) |
c3198a5e | 686 | { |
736e60dd | 687 | struct platform_device *pdev = to_platform_device(dev); |
38f3daf6 | 688 | int r; |
dcf5f729 | 689 | int irq; |
c3198a5e | 690 | |
c3198a5e | 691 | hdmi.pdev = pdev; |
945514b5 | 692 | dev_set_drvdata(&pdev->dev, &hdmi); |
c3198a5e M |
693 | |
694 | mutex_init(&hdmi.lock); | |
8a9d4626 | 695 | spin_lock_init(&hdmi.audio_playing_lock); |
c3198a5e | 696 | |
2f5dc676 TV |
697 | if (pdev->dev.of_node) { |
698 | r = hdmi_probe_of(pdev); | |
699 | if (r) | |
700 | return r; | |
701 | } | |
702 | ||
275cfa1a | 703 | r = hdmi_wp_init(pdev, &hdmi.wp); |
f382d9eb AT |
704 | if (r) |
705 | return r; | |
c3198a5e | 706 | |
03aafa2c | 707 | r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); |
c1577c1e AT |
708 | if (r) |
709 | return r; | |
710 | ||
275cfa1a | 711 | r = hdmi_phy_init(pdev, &hdmi.phy); |
5cac5aee | 712 | if (r) |
c84c3a5b | 713 | goto err; |
ddb1d5ca | 714 | |
275cfa1a | 715 | r = hdmi4_core_init(pdev, &hdmi.core); |
425f02fd | 716 | if (r) |
c84c3a5b | 717 | goto err; |
4fbafaf3 | 718 | |
dcf5f729 TV |
719 | irq = platform_get_irq(pdev, 0); |
720 | if (irq < 0) { | |
721 | DSSERR("platform_get_irq failed\n"); | |
c84c3a5b TV |
722 | r = -ENODEV; |
723 | goto err; | |
dcf5f729 TV |
724 | } |
725 | ||
726 | r = devm_request_threaded_irq(&pdev->dev, irq, | |
727 | NULL, hdmi_irq_handler, | |
728 | IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); | |
729 | if (r) { | |
730 | DSSERR("HDMI IRQ request failed\n"); | |
c84c3a5b | 731 | goto err; |
dcf5f729 TV |
732 | } |
733 | ||
4fbafaf3 TV |
734 | pm_runtime_enable(&pdev->dev); |
735 | ||
002d368d TV |
736 | hdmi_init_output(pdev); |
737 | ||
4d594dff JS |
738 | r = hdmi_audio_register(&pdev->dev); |
739 | if (r) { | |
740 | DSSERR("Registering HDMI audio failed\n"); | |
741 | hdmi_uninit_output(pdev); | |
742 | pm_runtime_disable(&pdev->dev); | |
743 | return r; | |
744 | } | |
745 | ||
e40402cf TV |
746 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
747 | ||
cca35017 | 748 | return 0; |
c84c3a5b TV |
749 | err: |
750 | hdmi_pll_uninit(&hdmi.pll); | |
751 | return r; | |
cca35017 TV |
752 | } |
753 | ||
736e60dd | 754 | static void hdmi4_unbind(struct device *dev, struct device *master, void *data) |
c3198a5e | 755 | { |
736e60dd TV |
756 | struct platform_device *pdev = to_platform_device(dev); |
757 | ||
4d594dff JS |
758 | if (hdmi.audio_pdev) |
759 | platform_device_unregister(hdmi.audio_pdev); | |
760 | ||
81b87f51 AT |
761 | hdmi_uninit_output(pdev); |
762 | ||
c84c3a5b TV |
763 | hdmi_pll_uninit(&hdmi.pll); |
764 | ||
4fbafaf3 | 765 | pm_runtime_disable(&pdev->dev); |
736e60dd TV |
766 | } |
767 | ||
768 | static const struct component_ops hdmi4_component_ops = { | |
769 | .bind = hdmi4_bind, | |
770 | .unbind = hdmi4_unbind, | |
771 | }; | |
4fbafaf3 | 772 | |
736e60dd TV |
773 | static int hdmi4_probe(struct platform_device *pdev) |
774 | { | |
775 | return component_add(&pdev->dev, &hdmi4_component_ops); | |
776 | } | |
777 | ||
778 | static int hdmi4_remove(struct platform_device *pdev) | |
779 | { | |
780 | component_del(&pdev->dev, &hdmi4_component_ops); | |
c3198a5e M |
781 | return 0; |
782 | } | |
783 | ||
4fbafaf3 TV |
784 | static int hdmi_runtime_suspend(struct device *dev) |
785 | { | |
4fbafaf3 | 786 | dispc_runtime_put(); |
4fbafaf3 TV |
787 | |
788 | return 0; | |
789 | } | |
790 | ||
791 | static int hdmi_runtime_resume(struct device *dev) | |
792 | { | |
793 | int r; | |
794 | ||
4fbafaf3 TV |
795 | r = dispc_runtime_get(); |
796 | if (r < 0) | |
852f0838 | 797 | return r; |
4fbafaf3 | 798 | |
4fbafaf3 | 799 | return 0; |
4fbafaf3 TV |
800 | } |
801 | ||
802 | static const struct dev_pm_ops hdmi_pm_ops = { | |
803 | .runtime_suspend = hdmi_runtime_suspend, | |
804 | .runtime_resume = hdmi_runtime_resume, | |
805 | }; | |
806 | ||
0465616d TV |
807 | static const struct of_device_id hdmi_of_match[] = { |
808 | { .compatible = "ti,omap4-hdmi", }, | |
809 | {}, | |
810 | }; | |
811 | ||
c3198a5e | 812 | static struct platform_driver omapdss_hdmihw_driver = { |
736e60dd TV |
813 | .probe = hdmi4_probe, |
814 | .remove = hdmi4_remove, | |
c3198a5e M |
815 | .driver = { |
816 | .name = "omapdss_hdmi", | |
4fbafaf3 | 817 | .pm = &hdmi_pm_ops, |
0465616d | 818 | .of_match_table = hdmi_of_match, |
422ccbd5 | 819 | .suppress_bind_attrs = true, |
c3198a5e M |
820 | }, |
821 | }; | |
822 | ||
ef26958a | 823 | int __init hdmi4_init_platform_driver(void) |
c3198a5e | 824 | { |
17ae4e8c | 825 | return platform_driver_register(&omapdss_hdmihw_driver); |
c3198a5e M |
826 | } |
827 | ||
ede92695 | 828 | void hdmi4_uninit_platform_driver(void) |
c3198a5e | 829 | { |
04c742c3 | 830 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 831 | } |