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99767548 TV |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Ltd | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License version 2 as published by | |
6 | * the Free Software Foundation. | |
7 | * | |
8 | * You should have received a copy of the GNU General Public License along with | |
9 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/sched.h> | |
19 | ||
32043da7 | 20 | #include "omapdss.h" |
99767548 TV |
21 | #include "dss.h" |
22 | #include "dss_features.h" | |
23 | ||
24 | struct dss_video_pll { | |
25 | struct dss_pll pll; | |
26 | ||
27 | struct device *dev; | |
28 | ||
29 | void __iomem *clkctrl_base; | |
30 | }; | |
31 | ||
32 | #define REG_MOD(reg, val, start, end) \ | |
33 | writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg) | |
34 | ||
35 | static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll) | |
36 | { | |
37 | REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ | |
38 | } | |
39 | ||
40 | static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) | |
41 | { | |
42 | REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ | |
43 | } | |
44 | ||
45 | static void dss_dpll_power_enable(struct dss_video_pll *vpll) | |
46 | { | |
47 | REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ | |
48 | ||
49 | /* | |
50 | * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, | |
51 | * so we have to use fixed delay here. | |
52 | */ | |
53 | msleep(1); | |
54 | } | |
55 | ||
56 | static void dss_dpll_power_disable(struct dss_video_pll *vpll) | |
57 | { | |
58 | REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ | |
59 | } | |
60 | ||
61 | static int dss_video_pll_enable(struct dss_pll *pll) | |
62 | { | |
63 | struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); | |
64 | int r; | |
65 | ||
66 | r = dss_runtime_get(); | |
67 | if (r) | |
68 | return r; | |
69 | ||
70 | dss_ctrl_pll_enable(pll->id, true); | |
71 | ||
72 | dss_dpll_enable_scp_clk(vpll); | |
73 | ||
74 | r = dss_pll_wait_reset_done(pll); | |
75 | if (r) | |
76 | goto err_reset; | |
77 | ||
78 | dss_dpll_power_enable(vpll); | |
79 | ||
80 | return 0; | |
81 | ||
82 | err_reset: | |
83 | dss_dpll_disable_scp_clk(vpll); | |
84 | dss_ctrl_pll_enable(pll->id, false); | |
85 | dss_runtime_put(); | |
86 | ||
87 | return r; | |
88 | } | |
89 | ||
90 | static void dss_video_pll_disable(struct dss_pll *pll) | |
91 | { | |
92 | struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); | |
93 | ||
94 | dss_dpll_power_disable(vpll); | |
95 | ||
96 | dss_dpll_disable_scp_clk(vpll); | |
97 | ||
98 | dss_ctrl_pll_enable(pll->id, false); | |
99 | ||
100 | dss_runtime_put(); | |
101 | } | |
102 | ||
103 | static const struct dss_pll_ops dss_pll_ops = { | |
104 | .enable = dss_video_pll_enable, | |
105 | .disable = dss_video_pll_disable, | |
106 | .set_config = dss_pll_write_config_type_a, | |
107 | }; | |
108 | ||
109 | static const struct dss_pll_hw dss_dra7_video_pll_hw = { | |
06ede3dd TV |
110 | .type = DSS_PLL_TYPE_A, |
111 | ||
99767548 TV |
112 | .n_max = (1 << 8) - 1, |
113 | .m_max = (1 << 12) - 1, | |
114 | .mX_max = (1 << 5) - 1, | |
115 | .fint_min = 500000, | |
116 | .fint_max = 2500000, | |
117 | .clkdco_max = 1800000000, | |
118 | ||
119 | .n_msb = 8, | |
120 | .n_lsb = 1, | |
121 | .m_msb = 20, | |
122 | .m_lsb = 9, | |
123 | ||
124 | .mX_msb[0] = 25, | |
125 | .mX_lsb[0] = 21, | |
126 | .mX_msb[1] = 30, | |
127 | .mX_lsb[1] = 26, | |
50c0164a TV |
128 | .mX_msb[2] = 4, |
129 | .mX_lsb[2] = 0, | |
130 | .mX_msb[3] = 9, | |
131 | .mX_lsb[3] = 5, | |
99767548 TV |
132 | |
133 | .has_refsel = true, | |
134 | }; | |
135 | ||
136 | struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, | |
137 | struct regulator *regulator) | |
138 | { | |
139 | const char * const reg_name[] = { "pll1", "pll2" }; | |
140 | const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" }; | |
141 | const char * const clkin_name[] = { "video1_clk", "video2_clk" }; | |
142 | ||
143 | struct resource *res; | |
144 | struct dss_video_pll *vpll; | |
145 | void __iomem *pll_base, *clkctrl_base; | |
146 | struct clk *clk; | |
147 | struct dss_pll *pll; | |
148 | int r; | |
149 | ||
150 | /* PLL CONTROL */ | |
151 | ||
152 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]); | |
153 | if (!res) { | |
154 | dev_err(&pdev->dev, | |
155 | "missing platform resource data for pll%d\n", id); | |
156 | return ERR_PTR(-ENODEV); | |
157 | } | |
158 | ||
159 | pll_base = devm_ioremap_resource(&pdev->dev, res); | |
160 | if (IS_ERR(pll_base)) { | |
161 | dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id); | |
162 | return ERR_CAST(pll_base); | |
163 | } | |
164 | ||
165 | /* CLOCK CONTROL */ | |
166 | ||
167 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
168 | clkctrl_name[id]); | |
169 | if (!res) { | |
170 | dev_err(&pdev->dev, | |
171 | "missing platform resource data for pll%d\n", id); | |
172 | return ERR_PTR(-ENODEV); | |
173 | } | |
174 | ||
175 | clkctrl_base = devm_ioremap_resource(&pdev->dev, res); | |
176 | if (IS_ERR(clkctrl_base)) { | |
177 | dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id); | |
178 | return ERR_CAST(clkctrl_base); | |
179 | } | |
180 | ||
181 | /* CLKIN */ | |
182 | ||
183 | clk = devm_clk_get(&pdev->dev, clkin_name[id]); | |
184 | if (IS_ERR(clk)) { | |
185 | DSSERR("can't get video pll clkin\n"); | |
186 | return ERR_CAST(clk); | |
187 | } | |
188 | ||
189 | vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL); | |
190 | if (!vpll) | |
191 | return ERR_PTR(-ENOMEM); | |
192 | ||
193 | vpll->dev = &pdev->dev; | |
194 | vpll->clkctrl_base = clkctrl_base; | |
195 | ||
196 | pll = &vpll->pll; | |
197 | ||
198 | pll->name = id == 0 ? "video0" : "video1"; | |
199 | pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2; | |
200 | pll->clkin = clk; | |
201 | pll->regulator = regulator; | |
202 | pll->base = pll_base; | |
203 | pll->hw = &dss_dra7_video_pll_hw; | |
204 | pll->ops = &dss_pll_ops; | |
205 | ||
206 | r = dss_pll_register(pll); | |
207 | if (r) | |
208 | return ERR_PTR(r); | |
209 | ||
210 | return pll; | |
211 | } | |
212 | ||
213 | void dss_video_pll_uninit(struct dss_pll *pll) | |
214 | { | |
215 | dss_pll_unregister(pll); | |
216 | } |