drm: omapdrm: Replace encoder mode_fixup with atomic_check
[deliverable/linux.git] / drivers / gpu / drm / omapdrm / omap_drv.c
CommitLineData
cd5351f4 1/*
8bb0daff 2 * drivers/gpu/drm/omapdrm/omap_drv.c
cd5351f4
RC
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Rob Clark <rob@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
cef77d40 20#include <drm/drm_atomic_helper.h>
2d278f54
LP
21#include <drm/drm_crtc_helper.h>
22#include <drm/drm_fb_helper.h>
cd5351f4 23
5c137797 24#include "omap_dmm_tiler.h"
2d278f54 25#include "omap_drv.h"
cd5351f4
RC
26
27#define DRIVER_NAME MODULE_NAME
28#define DRIVER_DESC "OMAP DRM"
29#define DRIVER_DATE "20110917"
30#define DRIVER_MAJOR 1
31#define DRIVER_MINOR 0
32#define DRIVER_PATCHLEVEL 0
33
cd5351f4
RC
34static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
35
36MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
37module_param(num_crtc, int, 0600);
38
39/*
40 * mode config funcs
41 */
42
43/* Notes about mapping DSS and DRM entities:
44 * CRTC: overlay
45 * encoder: manager.. with some extension to allow one primary CRTC
46 * and zero or more video CRTC's to be mapped to one encoder?
47 * connector: dssdev.. manager can be attached/detached from different
48 * devices
49 */
50
51static void omap_fb_output_poll_changed(struct drm_device *dev)
52{
53 struct omap_drm_private *priv = dev->dev_private;
54 DBG("dev=%p", dev);
c7f904b3 55 if (priv->fbdev)
cd5351f4 56 drm_fb_helper_hotplug_event(priv->fbdev);
cd5351f4
RC
57}
58
e6ecefaa 59static const struct drm_mode_config_funcs omap_mode_config_funcs = {
cd5351f4
RC
60 .fb_create = omap_framebuffer_create,
61 .output_poll_changed = omap_fb_output_poll_changed,
cef77d40
LP
62 .atomic_check = drm_atomic_helper_check,
63 .atomic_commit = drm_atomic_helper_commit,
cd5351f4
RC
64};
65
66static int get_connector_type(struct omap_dss_device *dssdev)
67{
68 switch (dssdev->type) {
69 case OMAP_DISPLAY_TYPE_HDMI:
70 return DRM_MODE_CONNECTOR_HDMIA;
4635c17d
TV
71 case OMAP_DISPLAY_TYPE_DVI:
72 return DRM_MODE_CONNECTOR_DVID;
cd5351f4
RC
73 default:
74 return DRM_MODE_CONNECTOR_Unknown;
75 }
76}
77
0d8f371f
AT
78static bool channel_used(struct drm_device *dev, enum omap_channel channel)
79{
80 struct omap_drm_private *priv = dev->dev_private;
81 int i;
82
83 for (i = 0; i < priv->num_crtcs; i++) {
84 struct drm_crtc *crtc = priv->crtcs[i];
85
86 if (omap_crtc_channel(crtc) == channel)
87 return true;
88 }
89
90 return false;
91}
cc823bdc
AT
92static void omap_disconnect_dssdevs(void)
93{
94 struct omap_dss_device *dssdev = NULL;
95
96 for_each_dss_dev(dssdev)
97 dssdev->driver->disconnect(dssdev);
98}
0d8f371f 99
3a01ab25
AT
100static int omap_connect_dssdevs(void)
101{
102 int r;
103 struct omap_dss_device *dssdev = NULL;
104 bool no_displays = true;
105
106 for_each_dss_dev(dssdev) {
107 r = dssdev->driver->connect(dssdev);
108 if (r == -EPROBE_DEFER) {
109 omap_dss_put_device(dssdev);
110 goto cleanup;
111 } else if (r) {
112 dev_warn(dssdev->dev, "could not connect display: %s\n",
113 dssdev->name);
114 } else {
115 no_displays = false;
116 }
117 }
118
119 if (no_displays)
120 return -EPROBE_DEFER;
121
122 return 0;
123
124cleanup:
125 /*
126 * if we are deferring probe, we disconnect the devices we previously
127 * connected
128 */
cc823bdc 129 omap_disconnect_dssdevs();
3a01ab25
AT
130
131 return r;
132}
0d8f371f 133
fb9a35f8
LP
134static int omap_modeset_create_crtc(struct drm_device *dev, int id,
135 enum omap_channel channel)
136{
137 struct omap_drm_private *priv = dev->dev_private;
138 struct drm_plane *plane;
139 struct drm_crtc *crtc;
140
ef6b0e02 141 plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY);
fb9a35f8
LP
142 if (IS_ERR(plane))
143 return PTR_ERR(plane);
144
145 crtc = omap_crtc_init(dev, plane, channel, id);
146
147 BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
148 priv->crtcs[id] = crtc;
149 priv->num_crtcs++;
150
151 priv->planes[id] = plane;
152 priv->num_planes++;
153
154 return 0;
155}
156
e2cd09b2
LP
157static int omap_modeset_init_properties(struct drm_device *dev)
158{
159 struct omap_drm_private *priv = dev->dev_private;
160
161 if (priv->has_dmm) {
162 dev->mode_config.rotation_property =
163 drm_mode_create_rotation_property(dev,
164 BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) |
165 BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270) |
166 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y));
167 if (!dev->mode_config.rotation_property)
168 return -ENOMEM;
169 }
170
171 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
172 if (!priv->zorder_prop)
173 return -ENOMEM;
174
175 return 0;
176}
177
f5f9454c 178static int omap_modeset_init(struct drm_device *dev)
cd5351f4
RC
179{
180 struct omap_drm_private *priv = dev->dev_private;
f5f9454c
RC
181 struct omap_dss_device *dssdev = NULL;
182 int num_ovls = dss_feat_get_num_ovls();
0d8f371f
AT
183 int num_mgrs = dss_feat_get_num_mgrs();
184 int num_crtcs;
185 int i, id = 0;
fb9a35f8 186 int ret;
04b1fc02 187
f5f9454c 188 drm_mode_config_init(dev);
cd5351f4 189
f5f9454c 190 omap_drm_irq_install(dev);
cd5351f4 191
e2cd09b2
LP
192 ret = omap_modeset_init_properties(dev);
193 if (ret < 0)
194 return ret;
195
f5f9454c 196 /*
0d8f371f
AT
197 * We usually don't want to create a CRTC for each manager, at least
198 * not until we have a way to expose private planes to userspace.
199 * Otherwise there would not be enough video pipes left for drm planes.
200 * We use the num_crtc argument to limit the number of crtcs we create.
f5f9454c 201 */
0d8f371f 202 num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
cd5351f4 203
0d8f371f 204 dssdev = NULL;
cd5351f4 205
f5f9454c
RC
206 for_each_dss_dev(dssdev) {
207 struct drm_connector *connector;
208 struct drm_encoder *encoder;
0d8f371f 209 enum omap_channel channel;
a7e71e7f 210 struct omap_overlay_manager *mgr;
c7f904b3 211
3a01ab25 212 if (!omapdss_device_is_connected(dssdev))
581382e3 213 continue;
a7e71e7f 214
f5f9454c 215 encoder = omap_encoder_init(dev, dssdev);
cd5351f4 216
f5f9454c
RC
217 if (!encoder) {
218 dev_err(dev->dev, "could not create encoder: %s\n",
219 dssdev->name);
220 return -ENOMEM;
cd5351f4
RC
221 }
222
f5f9454c
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223 connector = omap_connector_init(dev,
224 get_connector_type(dssdev), dssdev, encoder);
cd5351f4 225
f5f9454c
RC
226 if (!connector) {
227 dev_err(dev->dev, "could not create connector: %s\n",
228 dssdev->name);
229 return -ENOMEM;
cd5351f4 230 }
bb5c2d9a 231
f5f9454c
RC
232 BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
233 BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
cd5351f4 234
f5f9454c
RC
235 priv->encoders[priv->num_encoders++] = encoder;
236 priv->connectors[priv->num_connectors++] = connector;
cd5351f4 237
f5f9454c 238 drm_mode_connector_attach_encoder(connector, encoder);
cd5351f4 239
0d8f371f
AT
240 /*
241 * if we have reached the limit of the crtcs we are allowed to
242 * create, let's not try to look for a crtc for this
243 * panel/encoder and onwards, we will, of course, populate the
244 * the possible_crtcs field for all the encoders with the final
245 * set of crtcs we create
246 */
247 if (id == num_crtcs)
248 continue;
249
250 /*
251 * get the recommended DISPC channel for this encoder. For now,
252 * we only try to get create a crtc out of the recommended, the
253 * other possible channels to which the encoder can connect are
254 * not considered.
255 */
0d8f371f 256
a7e71e7f
TV
257 mgr = omapdss_find_mgr_from_display(dssdev);
258 channel = mgr->id;
0d8f371f
AT
259 /*
260 * if this channel hasn't already been taken by a previously
261 * allocated crtc, we create a new crtc for it
262 */
263 if (!channel_used(dev, channel)) {
fb9a35f8
LP
264 ret = omap_modeset_create_crtc(dev, id, channel);
265 if (ret < 0) {
266 dev_err(dev->dev,
267 "could not create CRTC (channel %u)\n",
268 channel);
269 return ret;
270 }
0d8f371f
AT
271
272 id++;
273 }
274 }
275
276 /*
277 * we have allocated crtcs according to the need of the panels/encoders,
278 * adding more crtcs here if needed
279 */
280 for (; id < num_crtcs; id++) {
281
282 /* find a free manager for this crtc */
283 for (i = 0; i < num_mgrs; i++) {
fb9a35f8 284 if (!channel_used(dev, i))
0d8f371f 285 break;
0d8f371f
AT
286 }
287
288 if (i == num_mgrs) {
289 /* this shouldn't really happen */
290 dev_err(dev->dev, "no managers left for crtc\n");
291 return -ENOMEM;
292 }
fb9a35f8
LP
293
294 ret = omap_modeset_create_crtc(dev, id, i);
295 if (ret < 0) {
296 dev_err(dev->dev,
297 "could not create CRTC (channel %u)\n", i);
298 return ret;
299 }
0d8f371f
AT
300 }
301
302 /*
303 * Create normal planes for the remaining overlays:
304 */
305 for (; id < num_ovls; id++) {
fb9a35f8
LP
306 struct drm_plane *plane;
307
ef6b0e02 308 plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY);
fb9a35f8
LP
309 if (IS_ERR(plane))
310 return PTR_ERR(plane);
0d8f371f
AT
311
312 BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
313 priv->planes[priv->num_planes++] = plane;
314 }
315
316 for (i = 0; i < priv->num_encoders; i++) {
317 struct drm_encoder *encoder = priv->encoders[i];
318 struct omap_dss_device *dssdev =
319 omap_encoder_get_dssdev(encoder);
1f68d9c4 320 struct omap_dss_device *output;
be8e8e1c
TV
321
322 output = omapdss_find_output_from_display(dssdev);
0d8f371f 323
f5f9454c
RC
324 /* figure out which crtc's we can connect the encoder to: */
325 encoder->possible_crtcs = 0;
326 for (id = 0; id < priv->num_crtcs; id++) {
0d8f371f
AT
327 struct drm_crtc *crtc = priv->crtcs[id];
328 enum omap_channel crtc_channel;
0d8f371f
AT
329
330 crtc_channel = omap_crtc_channel(crtc);
0d8f371f 331
17337297 332 if (output->dispc_channel == crtc_channel) {
f5f9454c 333 encoder->possible_crtcs |= (1 << id);
17337297
TV
334 break;
335 }
bb5c2d9a 336 }
820caabf
TV
337
338 omap_dss_put_device(output);
cd5351f4
RC
339 }
340
0d8f371f
AT
341 DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
342 priv->num_planes, priv->num_crtcs, priv->num_encoders,
343 priv->num_connectors);
344
6b8ca4cf
RC
345 dev->mode_config.min_width = 32;
346 dev->mode_config.min_height = 32;
cd5351f4
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347
348 /* note: eventually will need some cpu_is_omapXYZ() type stuff here
349 * to fill in these limits properly on different OMAP generations..
350 */
351 dev->mode_config.max_width = 2048;
352 dev->mode_config.max_height = 2048;
353
354 dev->mode_config.funcs = &omap_mode_config_funcs;
355
69a12263
LP
356 drm_mode_config_reset(dev);
357
cd5351f4
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358 return 0;
359}
360
361static void omap_modeset_free(struct drm_device *dev)
362{
363 drm_mode_config_cleanup(dev);
364}
365
366/*
367 * drm ioctl funcs
368 */
369
370
371static int ioctl_get_param(struct drm_device *dev, void *data,
372 struct drm_file *file_priv)
373{
5e3b0874 374 struct omap_drm_private *priv = dev->dev_private;
cd5351f4
RC
375 struct drm_omap_param *args = data;
376
377 DBG("%p: param=%llu", dev, args->param);
378
379 switch (args->param) {
380 case OMAP_PARAM_CHIPSET_ID:
5e3b0874 381 args->value = priv->omaprev;
cd5351f4
RC
382 break;
383 default:
384 DBG("unknown parameter %lld", args->param);
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
391static int ioctl_set_param(struct drm_device *dev, void *data,
392 struct drm_file *file_priv)
393{
394 struct drm_omap_param *args = data;
395
396 switch (args->param) {
397 default:
398 DBG("unknown parameter %lld", args->param);
399 return -EINVAL;
400 }
401
402 return 0;
403}
404
405static int ioctl_gem_new(struct drm_device *dev, void *data,
406 struct drm_file *file_priv)
407{
408 struct drm_omap_gem_new *args = data;
f5f9454c 409 VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
cd5351f4
RC
410 args->size.bytes, args->flags);
411 return omap_gem_new_handle(dev, file_priv, args->size,
412 args->flags, &args->handle);
413}
414
415static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
416 struct drm_file *file_priv)
417{
418 struct drm_omap_gem_cpu_prep *args = data;
419 struct drm_gem_object *obj;
420 int ret;
421
422 VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
423
424 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
c7f904b3 425 if (!obj)
cd5351f4 426 return -ENOENT;
cd5351f4
RC
427
428 ret = omap_gem_op_sync(obj, args->op);
429
c7f904b3 430 if (!ret)
cd5351f4 431 ret = omap_gem_op_start(obj, args->op);
cd5351f4
RC
432
433 drm_gem_object_unreference_unlocked(obj);
434
435 return ret;
436}
437
438static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
439 struct drm_file *file_priv)
440{
441 struct drm_omap_gem_cpu_fini *args = data;
442 struct drm_gem_object *obj;
443 int ret;
444
445 VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
446
447 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
c7f904b3 448 if (!obj)
cd5351f4 449 return -ENOENT;
cd5351f4
RC
450
451 /* XXX flushy, flushy */
452 ret = 0;
453
c7f904b3 454 if (!ret)
cd5351f4 455 ret = omap_gem_op_finish(obj, args->op);
cd5351f4
RC
456
457 drm_gem_object_unreference_unlocked(obj);
458
459 return ret;
460}
461
462static int ioctl_gem_info(struct drm_device *dev, void *data,
463 struct drm_file *file_priv)
464{
465 struct drm_omap_gem_info *args = data;
466 struct drm_gem_object *obj;
467 int ret = 0;
468
f5f9454c 469 VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
cd5351f4
RC
470
471 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
c7f904b3 472 if (!obj)
cd5351f4 473 return -ENOENT;
cd5351f4 474
f7f9f453 475 args->size = omap_gem_mmap_size(obj);
cd5351f4
RC
476 args->offset = omap_gem_mmap_offset(obj);
477
478 drm_gem_object_unreference_unlocked(obj);
479
480 return ret;
481}
482
baa70943 483static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
cd5351f4
RC
484 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH),
485 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
486 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
488 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH),
490};
491
492/*
493 * drm driver funcs
494 */
495
496/**
497 * load - setup chip and create an initial config
498 * @dev: DRM device
499 * @flags: startup flags
500 *
501 * The driver load routine has to do several things:
502 * - initialize the memory manager
503 * - allocate initial config memory
504 * - setup the DRM framebuffer with the allocated memory
505 */
506static int dev_load(struct drm_device *dev, unsigned long flags)
507{
5e3b0874 508 struct omap_drm_platform_data *pdata = dev->dev->platform_data;
cd5351f4 509 struct omap_drm_private *priv;
c397cfd4 510 unsigned int i;
cd5351f4
RC
511 int ret;
512
513 DBG("load: dev=%p", dev);
514
cd5351f4 515 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
78110bb8 516 if (!priv)
cd5351f4 517 return -ENOMEM;
cd5351f4 518
5e3b0874
RC
519 priv->omaprev = pdata->omaprev;
520
cd5351f4
RC
521 dev->dev_private = priv;
522
4619cdbc 523 priv->wq = alloc_ordered_workqueue("omapdrm", 0);
5609f7fe 524
76c4055f 525 spin_lock_init(&priv->list_lock);
f6b6036e
RC
526 INIT_LIST_HEAD(&priv->obj_list);
527
f7f9f453
RC
528 omap_gem_init(dev);
529
cd5351f4
RC
530 ret = omap_modeset_init(dev);
531 if (ret) {
532 dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret);
533 dev->dev_private = NULL;
534 kfree(priv);
535 return ret;
536 }
537
c397cfd4 538 /* Initialize vblank handling, start with all CRTCs disabled. */
f5f9454c
RC
539 ret = drm_vblank_init(dev, priv->num_crtcs);
540 if (ret)
541 dev_warn(dev->dev, "could not init vblank\n");
542
c397cfd4
LP
543 for (i = 0; i < priv->num_crtcs; i++)
544 drm_crtc_vblank_off(priv->crtcs[i]);
545
cd5351f4
RC
546 priv->fbdev = omap_fbdev_init(dev);
547 if (!priv->fbdev) {
548 dev_warn(dev->dev, "omap_fbdev_init failed\n");
549 /* well, limp along without an fbdev.. maybe X11 will work? */
550 }
551
e78edba1
AG
552 /* store off drm_device for use in pm ops */
553 dev_set_drvdata(dev->dev, dev);
554
cd5351f4
RC
555 drm_kms_helper_poll_init(dev);
556
cd5351f4
RC
557 return 0;
558}
559
560static int dev_unload(struct drm_device *dev)
561{
5609f7fe
RC
562 struct omap_drm_private *priv = dev->dev_private;
563
cd5351f4
RC
564 DBG("unload: dev=%p", dev);
565
cd5351f4
RC
566 drm_kms_helper_poll_fini(dev);
567
c7c1aecd
TV
568 if (priv->fbdev)
569 omap_fbdev_free(dev);
e2f8fd74 570
cd5351f4 571 omap_modeset_free(dev);
f7f9f453 572 omap_gem_deinit(dev);
cd5351f4 573
5609f7fe
RC
574 destroy_workqueue(priv->wq);
575
80e4ed54
AT
576 drm_vblank_cleanup(dev);
577 omap_drm_irq_uninstall(dev);
578
cd5351f4
RC
579 kfree(dev->dev_private);
580 dev->dev_private = NULL;
581
e78edba1
AG
582 dev_set_drvdata(dev->dev, NULL);
583
cd5351f4
RC
584 return 0;
585}
586
587static int dev_open(struct drm_device *dev, struct drm_file *file)
588{
589 file->driver_priv = NULL;
590
591 DBG("open: dev=%p, file=%p", dev, file);
592
593 return 0;
594}
595
cd5351f4
RC
596/**
597 * lastclose - clean up after all DRM clients have exited
598 * @dev: DRM device
599 *
600 * Take care of cleaning up after all DRM clients have exited. In the
601 * mode setting case, we want to restore the kernel's initial mode (just
602 * in case the last client left us in a bad state).
603 */
604static void dev_lastclose(struct drm_device *dev)
605{
3c810c61
RC
606 int i;
607
cd5351f4
RC
608 /* we don't support vga-switcheroo.. so just make sure the fbdev
609 * mode is active
610 */
611 struct omap_drm_private *priv = dev->dev_private;
612 int ret;
613
614 DBG("lastclose: dev=%p", dev);
615
e2cd09b2 616 if (dev->mode_config.rotation_property) {
c2a6a552
RC
617 /* need to restore default rotation state.. not sure
618 * if there is a cleaner way to restore properties to
619 * default state? Maybe a flag that properties should
620 * automatically be restored to default state on
621 * lastclose?
622 */
623 for (i = 0; i < priv->num_crtcs; i++) {
624 drm_object_property_set_value(&priv->crtcs[i]->base,
e2cd09b2 625 dev->mode_config.rotation_property, 0);
c2a6a552 626 }
3c810c61 627
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RC
628 for (i = 0; i < priv->num_planes; i++) {
629 drm_object_property_set_value(&priv->planes[i]->base,
e2cd09b2 630 dev->mode_config.rotation_property, 0);
c2a6a552 631 }
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632 }
633
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634 if (priv->fbdev) {
635 ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
636 if (ret)
637 DBG("failed to restore crtc mode");
638 }
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639}
640
641static void dev_preclose(struct drm_device *dev, struct drm_file *file)
642{
1d5e5ea1
LP
643 struct omap_drm_private *priv = dev->dev_private;
644 unsigned int i;
645
cd5351f4 646 DBG("preclose: dev=%p", dev);
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647
648 for (i = 0; i < priv->num_crtcs; ++i)
649 omap_crtc_cancel_page_flip(priv->crtcs[i], file);
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650}
651
652static void dev_postclose(struct drm_device *dev, struct drm_file *file)
653{
654 DBG("postclose: dev=%p, file=%p", dev, file);
655}
656
78b68556 657static const struct vm_operations_struct omap_gem_vm_ops = {
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658 .fault = omap_gem_fault,
659 .open = drm_gem_vm_open,
660 .close = drm_gem_vm_close,
661};
662
ff4f3876 663static const struct file_operations omapdriver_fops = {
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LP
664 .owner = THIS_MODULE,
665 .open = drm_open,
666 .unlocked_ioctl = drm_ioctl,
667 .release = drm_release,
668 .mmap = omap_gem_mmap,
669 .poll = drm_poll,
670 .read = drm_read,
671 .llseek = noop_llseek,
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672};
673
cd5351f4 674static struct drm_driver omap_drm_driver = {
f13ab005 675 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
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LP
676 .load = dev_load,
677 .unload = dev_unload,
678 .open = dev_open,
679 .lastclose = dev_lastclose,
680 .preclose = dev_preclose,
681 .postclose = dev_postclose,
682 .set_busid = drm_platform_set_busid,
683 .get_vblank_counter = drm_vblank_count,
684 .enable_vblank = omap_irq_enable_vblank,
685 .disable_vblank = omap_irq_disable_vblank,
6169a148 686#ifdef CONFIG_DEBUG_FS
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687 .debugfs_init = omap_debugfs_init,
688 .debugfs_cleanup = omap_debugfs_cleanup,
6169a148 689#endif
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690 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
691 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
692 .gem_prime_export = omap_gem_prime_export,
693 .gem_prime_import = omap_gem_prime_import,
694 .gem_free_object = omap_gem_free_object,
695 .gem_vm_ops = &omap_gem_vm_ops,
696 .dumb_create = omap_gem_dumb_create,
697 .dumb_map_offset = omap_gem_dumb_map_offset,
698 .dumb_destroy = drm_gem_dumb_destroy,
699 .ioctls = ioctls,
700 .num_ioctls = DRM_OMAP_NUM_IOCTLS,
701 .fops = &omapdriver_fops,
702 .name = DRIVER_NAME,
703 .desc = DRIVER_DESC,
704 .date = DRIVER_DATE,
705 .major = DRIVER_MAJOR,
706 .minor = DRIVER_MINOR,
707 .patchlevel = DRIVER_PATCHLEVEL,
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708};
709
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710static int pdev_probe(struct platform_device *device)
711{
3a01ab25
AT
712 int r;
713
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714 if (omapdss_is_initialized() == false)
715 return -EPROBE_DEFER;
716
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AT
717 omap_crtc_pre_init();
718
719 r = omap_connect_dssdevs();
720 if (r) {
721 omap_crtc_pre_uninit();
722 return r;
723 }
724
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725 DBG("%s", device->name);
726 return drm_platform_init(&omap_drm_driver, device);
727}
728
729static int pdev_remove(struct platform_device *device)
730{
731 DBG("");
5c137797 732
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733 drm_put_dev(platform_get_drvdata(device));
734
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AT
735 omap_disconnect_dssdevs();
736 omap_crtc_pre_uninit();
fd3c0253 737
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738 return 0;
739}
740
8450c8d0 741#ifdef CONFIG_PM_SLEEP
ccd7b5ed
TV
742static int omap_drm_suspend(struct device *dev)
743{
744 struct drm_device *drm_dev = dev_get_drvdata(dev);
745
746 drm_kms_helper_poll_disable(drm_dev);
747
748 return 0;
749}
750
751static int omap_drm_resume(struct device *dev)
752{
753 struct drm_device *drm_dev = dev_get_drvdata(dev);
754
755 drm_kms_helper_poll_enable(drm_dev);
756
757 return omap_gem_resume(dev);
758}
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759#endif
760
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761static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
762
6717cd29 763static struct platform_driver pdev = {
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LP
764 .driver = {
765 .name = DRIVER_NAME,
222025e4 766 .pm = &omapdrm_pm_ops,
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LP
767 },
768 .probe = pdev_probe,
769 .remove = pdev_remove,
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770};
771
772static int __init omap_drm_init(void)
773{
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TV
774 int r;
775
cd5351f4 776 DBG("init");
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777
778 r = platform_driver_register(&omap_dmm_driver);
779 if (r) {
780 pr_err("DMM driver registration failed\n");
781 return r;
be0775ac 782 }
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783
784 r = platform_driver_register(&pdev);
785 if (r) {
786 pr_err("omapdrm driver registration failed\n");
787 platform_driver_unregister(&omap_dmm_driver);
788 return r;
789 }
790
791 return 0;
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792}
793
794static void __exit omap_drm_fini(void)
795{
796 DBG("fini");
ea7e3a66 797
cd5351f4 798 platform_driver_unregister(&pdev);
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799
800 platform_driver_unregister(&omap_dmm_driver);
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801}
802
803/* need late_initcall() so we load after dss_driver's are loaded */
804late_initcall(omap_drm_init);
805module_exit(omap_drm_fini);
806
807MODULE_AUTHOR("Rob Clark <rob@ti.com>");
808MODULE_DESCRIPTION("OMAP DRM Display Driver");
809MODULE_ALIAS("platform:" DRIVER_NAME);
810MODULE_LICENSE("GPL v2");
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