Commit | Line | Data |
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746c1aa4 DA |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
8d1c702a | 25 | * Jerome Glisse |
746c1aa4 | 26 | */ |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
746c1aa4 DA |
29 | #include "radeon.h" |
30 | ||
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
760285e7 | 33 | #include <drm/drm_dp_helper.h> |
746c1aa4 | 34 | |
f92a8b67 | 35 | /* move these to drm_dp_helper.c/h */ |
5801ead6 | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
1a644cd4 | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
5801ead6 AD |
38 | |
39 | static char *voltage_names[] = { | |
40 | "0.4V", "0.6V", "0.8V", "1.2V" | |
41 | }; | |
42 | static char *pre_emph_names[] = { | |
43 | "0dB", "3.5dB", "6dB", "9.5dB" | |
44 | }; | |
f92a8b67 | 45 | |
224d94b1 | 46 | /***** radeon AUX functions *****/ |
34be8c9a AD |
47 | |
48 | /* Atom needs data in little endian format | |
49 | * so swap as appropriate when copying data to | |
50 | * or from atom. Note that atom operates on | |
51 | * dw units. | |
52 | */ | |
4543eda5 | 53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
34be8c9a AD |
54 | { |
55 | #ifdef __BIG_ENDIAN | |
56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ | |
57 | u32 *dst32, *src32; | |
58 | int i; | |
59 | ||
60 | memcpy(src_tmp, src, num_bytes); | |
61 | src32 = (u32 *)src_tmp; | |
62 | dst32 = (u32 *)dst_tmp; | |
63 | if (to_le) { | |
64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
65 | dst32[i] = cpu_to_le32(src32[i]); | |
66 | memcpy(dst, dst_tmp, num_bytes); | |
67 | } else { | |
68 | u8 dws = num_bytes & ~3; | |
69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
70 | dst32[i] = le32_to_cpu(src32[i]); | |
71 | memcpy(dst, dst_tmp, dws); | |
72 | if (num_bytes % 4) { | |
73 | for (i = 0; i < (num_bytes % 4); i++) | |
74 | dst[dws+i] = dst_tmp[dws+i]; | |
75 | } | |
76 | } | |
77 | #else | |
78 | memcpy(dst, src, num_bytes); | |
79 | #endif | |
80 | } | |
81 | ||
224d94b1 AD |
82 | union aux_channel_transaction { |
83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; | |
84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; | |
f92a8b67 AD |
85 | }; |
86 | ||
224d94b1 AD |
87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
88 | u8 *send, int send_bytes, | |
89 | u8 *recv, int recv_size, | |
90 | u8 delay, u8 *ack) | |
91 | { | |
92 | struct drm_device *dev = chan->dev; | |
93 | struct radeon_device *rdev = dev->dev_private; | |
94 | union aux_channel_transaction args; | |
95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); | |
96 | unsigned char *base; | |
97 | int recv_bytes; | |
98 | ||
99 | memset(&args, 0, sizeof(args)); | |
f92a8b67 | 100 | |
97412a7a | 101 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
224d94b1 | 102 | |
4543eda5 | 103 | radeon_atom_copy_swap(base, send, send_bytes, true); |
224d94b1 | 104 | |
34be8c9a AD |
105 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
106 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); | |
224d94b1 AD |
107 | args.v1.ucDataOutLen = 0; |
108 | args.v1.ucChannelID = chan->rec.i2c_id; | |
109 | args.v1.ucDelay = delay / 10; | |
110 | if (ASIC_IS_DCE4(rdev)) | |
111 | args.v2.ucHPD_ID = chan->rec.hpd; | |
112 | ||
113 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
114 | ||
115 | *ack = args.v1.ucReplyStatus; | |
116 | ||
117 | /* timeout */ | |
118 | if (args.v1.ucReplyStatus == 1) { | |
119 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); | |
120 | return -ETIMEDOUT; | |
121 | } | |
122 | ||
123 | /* flags not zero */ | |
124 | if (args.v1.ucReplyStatus == 2) { | |
125 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); | |
126 | return -EBUSY; | |
127 | } | |
128 | ||
129 | /* error */ | |
130 | if (args.v1.ucReplyStatus == 3) { | |
131 | DRM_DEBUG_KMS("dp_aux_ch error\n"); | |
132 | return -EIO; | |
133 | } | |
134 | ||
135 | recv_bytes = args.v1.ucDataOutLen; | |
136 | if (recv_bytes > recv_size) | |
137 | recv_bytes = recv_size; | |
138 | ||
139 | if (recv && recv_size) | |
4543eda5 | 140 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
224d94b1 AD |
141 | |
142 | return recv_bytes; | |
143 | } | |
144 | ||
25377b92 AD |
145 | #define BARE_ADDRESS_SIZE 3 |
146 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
5801ead6 | 147 | |
496263bf AD |
148 | static ssize_t |
149 | radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
f92a8b67 | 150 | { |
496263bf AD |
151 | struct radeon_i2c_chan *chan = |
152 | container_of(aux, struct radeon_i2c_chan, aux); | |
224d94b1 | 153 | int ret; |
496263bf AD |
154 | u8 tx_buf[20]; |
155 | size_t tx_size; | |
156 | u8 ack, delay = 0; | |
157 | ||
158 | if (WARN_ON(msg->size > 16)) | |
159 | return -E2BIG; | |
160 | ||
161 | tx_buf[0] = msg->address & 0xff; | |
162 | tx_buf[1] = msg->address >> 8; | |
163 | tx_buf[2] = msg->request << 4; | |
25377b92 | 164 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
496263bf AD |
165 | |
166 | switch (msg->request & ~DP_AUX_I2C_MOT) { | |
167 | case DP_AUX_NATIVE_WRITE: | |
168 | case DP_AUX_I2C_WRITE: | |
25377b92 AD |
169 | /* tx_size needs to be 4 even for bare address packets since the atom |
170 | * table needs the info in tx_buf[3]. | |
171 | */ | |
496263bf | 172 | tx_size = HEADER_SIZE + msg->size; |
25377b92 AD |
173 | if (msg->size == 0) |
174 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; | |
175 | else | |
176 | tx_buf[3] |= tx_size << 4; | |
496263bf AD |
177 | memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); |
178 | ret = radeon_process_aux_ch(chan, | |
179 | tx_buf, tx_size, NULL, 0, delay, &ack); | |
180 | if (ret >= 0) | |
181 | /* Return payload size. */ | |
182 | ret = msg->size; | |
183 | break; | |
184 | case DP_AUX_NATIVE_READ: | |
185 | case DP_AUX_I2C_READ: | |
25377b92 AD |
186 | /* tx_size needs to be 4 even for bare address packets since the atom |
187 | * table needs the info in tx_buf[3]. | |
188 | */ | |
496263bf | 189 | tx_size = HEADER_SIZE; |
25377b92 AD |
190 | if (msg->size == 0) |
191 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; | |
192 | else | |
193 | tx_buf[3] |= tx_size << 4; | |
496263bf AD |
194 | ret = radeon_process_aux_ch(chan, |
195 | tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); | |
196 | break; | |
197 | default: | |
198 | ret = -EINVAL; | |
199 | break; | |
224d94b1 | 200 | } |
6375bda0 | 201 | |
25377b92 | 202 | if (ret >= 0) |
496263bf | 203 | msg->reply = ack >> 4; |
f92a8b67 | 204 | |
496263bf | 205 | return ret; |
224d94b1 AD |
206 | } |
207 | ||
496263bf | 208 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
224d94b1 | 209 | { |
496263bf | 210 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
224d94b1 | 211 | |
496263bf AD |
212 | dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev; |
213 | dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer; | |
224d94b1 AD |
214 | } |
215 | ||
216 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |
217 | u8 write_byte, u8 *read_byte) | |
218 | { | |
219 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
f3381dfc | 220 | struct radeon_i2c_chan *auxch = i2c_get_adapdata(adapter); |
224d94b1 AD |
221 | u16 address = algo_data->address; |
222 | u8 msg[5]; | |
223 | u8 reply[2]; | |
224 | unsigned retry; | |
225 | int msg_bytes; | |
226 | int reply_bytes = 1; | |
227 | int ret; | |
228 | u8 ack; | |
229 | ||
dca0be0d | 230 | /* Set up the address */ |
224d94b1 AD |
231 | msg[0] = address; |
232 | msg[1] = address >> 8; | |
233 | ||
dca0be0d AD |
234 | /* Set up the command byte */ |
235 | if (mode & MODE_I2C_READ) { | |
236 | msg[2] = DP_AUX_I2C_READ << 4; | |
237 | msg_bytes = 4; | |
238 | msg[3] = msg_bytes << 4; | |
239 | } else { | |
240 | msg[2] = DP_AUX_I2C_WRITE << 4; | |
224d94b1 AD |
241 | msg_bytes = 5; |
242 | msg[3] = msg_bytes << 4; | |
243 | msg[4] = write_byte; | |
f92a8b67 AD |
244 | } |
245 | ||
dca0be0d AD |
246 | /* special handling for start/stop */ |
247 | if (mode & (MODE_I2C_START | MODE_I2C_STOP)) | |
248 | msg[3] = 3 << 4; | |
249 | ||
250 | /* Set MOT bit for all but stop */ | |
251 | if ((mode & MODE_I2C_STOP) == 0) | |
252 | msg[2] |= DP_AUX_I2C_MOT << 4; | |
253 | ||
2138681b | 254 | for (retry = 0; retry < 7; retry++) { |
224d94b1 AD |
255 | ret = radeon_process_aux_ch(auxch, |
256 | msg, msg_bytes, reply, reply_bytes, 0, &ack); | |
4f332844 AD |
257 | if (ret == -EBUSY) |
258 | continue; | |
259 | else if (ret < 0) { | |
224d94b1 AD |
260 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
261 | return ret; | |
262 | } | |
f92a8b67 | 263 | |
6b27f7f0 TR |
264 | switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
265 | case DP_AUX_NATIVE_REPLY_ACK: | |
224d94b1 AD |
266 | /* I2C-over-AUX Reply field is only valid |
267 | * when paired with AUX ACK. | |
268 | */ | |
269 | break; | |
6b27f7f0 | 270 | case DP_AUX_NATIVE_REPLY_NACK: |
224d94b1 AD |
271 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
272 | return -EREMOTEIO; | |
6b27f7f0 | 273 | case DP_AUX_NATIVE_REPLY_DEFER: |
224d94b1 | 274 | DRM_DEBUG_KMS("aux_ch native defer\n"); |
ab9f51c0 | 275 | usleep_range(500, 600); |
224d94b1 AD |
276 | continue; |
277 | default: | |
278 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); | |
279 | return -EREMOTEIO; | |
280 | } | |
5801ead6 | 281 | |
6b27f7f0 TR |
282 | switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) { |
283 | case DP_AUX_I2C_REPLY_ACK: | |
224d94b1 AD |
284 | if (mode == MODE_I2C_READ) |
285 | *read_byte = reply[0]; | |
286 | return ret; | |
6b27f7f0 | 287 | case DP_AUX_I2C_REPLY_NACK: |
224d94b1 AD |
288 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
289 | return -EREMOTEIO; | |
6b27f7f0 | 290 | case DP_AUX_I2C_REPLY_DEFER: |
224d94b1 | 291 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab9f51c0 | 292 | usleep_range(400, 500); |
224d94b1 AD |
293 | break; |
294 | default: | |
295 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); | |
296 | return -EREMOTEIO; | |
297 | } | |
298 | } | |
5801ead6 | 299 | |
091264f0 | 300 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
224d94b1 | 301 | return -EREMOTEIO; |
5801ead6 AD |
302 | } |
303 | ||
224d94b1 AD |
304 | /***** general DP utility functions *****/ |
305 | ||
5801ead6 | 306 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
224d94b1 | 307 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
5801ead6 AD |
308 | |
309 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |
310 | int lane_count, | |
311 | u8 train_set[4]) | |
312 | { | |
313 | u8 v = 0; | |
314 | u8 p = 0; | |
315 | int lane; | |
316 | ||
317 | for (lane = 0; lane < lane_count; lane++) { | |
0f037bde DV |
318 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
319 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
5801ead6 | 320 | |
d9fdaafb | 321 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
53c1e09f AD |
322 | lane, |
323 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | |
324 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
325 | |
326 | if (this_v > v) | |
327 | v = this_v; | |
328 | if (this_p > p) | |
329 | p = this_p; | |
330 | } | |
331 | ||
332 | if (v >= DP_VOLTAGE_MAX) | |
224d94b1 | 333 | v |= DP_TRAIN_MAX_SWING_REACHED; |
5801ead6 | 334 | |
224d94b1 AD |
335 | if (p >= DP_PRE_EMPHASIS_MAX) |
336 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
5801ead6 | 337 | |
d9fdaafb | 338 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
53c1e09f AD |
339 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
340 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
341 | |
342 | for (lane = 0; lane < 4; lane++) | |
343 | train_set[lane] = v | p; | |
344 | } | |
345 | ||
224d94b1 AD |
346 | /* convert bits per color to bits per pixel */ |
347 | /* get bpc from the EDID */ | |
348 | static int convert_bpc_to_bpp(int bpc) | |
746c1aa4 | 349 | { |
224d94b1 AD |
350 | if (bpc == 0) |
351 | return 24; | |
352 | else | |
353 | return bpc * 3; | |
354 | } | |
746c1aa4 | 355 | |
224d94b1 AD |
356 | /* get the max pix clock supported by the link rate and lane num */ |
357 | static int dp_get_max_dp_pix_clock(int link_rate, | |
358 | int lane_num, | |
359 | int bpp) | |
360 | { | |
361 | return (link_rate * lane_num * 8) / bpp; | |
362 | } | |
834b2904 | 363 | |
224d94b1 | 364 | /***** radeon specific DP functions *****/ |
746c1aa4 | 365 | |
224d94b1 AD |
366 | /* First get the min lane# when low rate is used according to pixel clock |
367 | * (prefer low rate), second check max lane# supported by DP panel, | |
368 | * if the max lane# < low rate lane# then use max lane# instead. | |
369 | */ | |
370 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, | |
371 | u8 dpcd[DP_DPCD_SIZE], | |
372 | int pix_clock) | |
373 | { | |
eccea792 | 374 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
3b5c662e | 375 | int max_link_rate = drm_dp_max_link_rate(dpcd); |
397fe157 | 376 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
224d94b1 AD |
377 | int lane_num; |
378 | int max_dp_pix_clock; | |
379 | ||
380 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { | |
381 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); | |
382 | if (pix_clock <= max_dp_pix_clock) | |
383 | break; | |
834b2904 | 384 | } |
746c1aa4 | 385 | |
224d94b1 | 386 | return lane_num; |
746c1aa4 DA |
387 | } |
388 | ||
224d94b1 AD |
389 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
390 | u8 dpcd[DP_DPCD_SIZE], | |
391 | int pix_clock) | |
746c1aa4 | 392 | { |
eccea792 | 393 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
224d94b1 AD |
394 | int lane_num, max_pix_clock; |
395 | ||
fdca78c3 AD |
396 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
397 | ENCODER_OBJECT_ID_NUTMEG) | |
224d94b1 AD |
398 | return 270000; |
399 | ||
400 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); | |
401 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); | |
402 | if (pix_clock <= max_pix_clock) | |
403 | return 162000; | |
404 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); | |
405 | if (pix_clock <= max_pix_clock) | |
406 | return 270000; | |
407 | if (radeon_connector_is_dp12_capable(connector)) { | |
408 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); | |
409 | if (pix_clock <= max_pix_clock) | |
410 | return 540000; | |
834b2904 | 411 | } |
224d94b1 | 412 | |
3b5c662e | 413 | return drm_dp_max_link_rate(dpcd); |
746c1aa4 DA |
414 | } |
415 | ||
834b2904 AD |
416 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
417 | int action, int dp_clock, | |
224d94b1 | 418 | u8 ucconfig, u8 lane_num) |
5801ead6 AD |
419 | { |
420 | DP_ENCODER_SERVICE_PARAMETERS args; | |
421 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
422 | ||
423 | memset(&args, 0, sizeof(args)); | |
424 | args.ucLinkClock = dp_clock / 10; | |
425 | args.ucConfig = ucconfig; | |
426 | args.ucAction = action; | |
427 | args.ucLaneNum = lane_num; | |
428 | args.ucStatus = 0; | |
429 | ||
430 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
431 | return args.ucStatus; | |
432 | } | |
433 | ||
434 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) | |
435 | { | |
436 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
437 | struct drm_device *dev = radeon_connector->base.dev; | |
438 | struct radeon_device *rdev = dev->dev_private; | |
439 | ||
440 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, | |
441 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); | |
442 | } | |
443 | ||
40c5d876 AJ |
444 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
445 | { | |
446 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
447 | u8 buf[3]; | |
448 | ||
449 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
450 | return; | |
451 | ||
496263bf | 452 | if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3)) |
40c5d876 AJ |
453 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
454 | buf[0], buf[1], buf[2]); | |
455 | ||
496263bf | 456 | if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3)) |
40c5d876 AJ |
457 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
458 | buf[0], buf[1], buf[2]); | |
459 | } | |
460 | ||
9fa05c98 | 461 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
746c1aa4 | 462 | { |
5801ead6 | 463 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
1a644cd4 | 464 | u8 msg[DP_DPCD_SIZE]; |
224d94b1 | 465 | int ret, i; |
746c1aa4 | 466 | |
496263bf AD |
467 | ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg, |
468 | DP_DPCD_SIZE); | |
834b2904 | 469 | if (ret > 0) { |
1a644cd4 | 470 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
224d94b1 | 471 | DRM_DEBUG_KMS("DPCD: "); |
1a644cd4 | 472 | for (i = 0; i < DP_DPCD_SIZE; i++) |
224d94b1 AD |
473 | DRM_DEBUG_KMS("%02x ", msg[i]); |
474 | DRM_DEBUG_KMS("\n"); | |
40c5d876 AJ |
475 | |
476 | radeon_dp_probe_oui(radeon_connector); | |
477 | ||
9fa05c98 | 478 | return true; |
746c1aa4 | 479 | } |
5801ead6 | 480 | dig_connector->dpcd[0] = 0; |
9fa05c98 | 481 | return false; |
746c1aa4 DA |
482 | } |
483 | ||
386d4d75 AD |
484 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
485 | struct drm_connector *connector) | |
224d94b1 AD |
486 | { |
487 | struct drm_device *dev = encoder->dev; | |
488 | struct radeon_device *rdev = dev->dev_private; | |
00dfb8df | 489 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
496263bf | 490 | struct radeon_connector_atom_dig *dig_connector; |
224d94b1 | 491 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
0ceb996c AD |
492 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
493 | u8 tmp; | |
224d94b1 AD |
494 | |
495 | if (!ASIC_IS_DCE4(rdev)) | |
386d4d75 | 496 | return panel_mode; |
224d94b1 | 497 | |
496263bf AD |
498 | if (!radeon_connector->con_priv) |
499 | return panel_mode; | |
500 | ||
501 | dig_connector = radeon_connector->con_priv; | |
502 | ||
0ceb996c AD |
503 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
504 | /* DP bridge chips */ | |
496263bf AD |
505 | drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, |
506 | DP_EDP_CONFIGURATION_CAP, &tmp); | |
0ceb996c AD |
507 | if (tmp & 1) |
508 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
509 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || | |
510 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) | |
304a4840 AD |
511 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
512 | else | |
0ceb996c | 513 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
304a4840 | 514 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
0ceb996c | 515 | /* eDP */ |
496263bf AD |
516 | drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, |
517 | DP_EDP_CONFIGURATION_CAP, &tmp); | |
00dfb8df AD |
518 | if (tmp & 1) |
519 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
520 | } | |
224d94b1 | 521 | |
386d4d75 | 522 | return panel_mode; |
224d94b1 AD |
523 | } |
524 | ||
5801ead6 | 525 | void radeon_dp_set_link_config(struct drm_connector *connector, |
e811f5ae | 526 | const struct drm_display_mode *mode) |
5801ead6 | 527 | { |
224d94b1 | 528 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5801ead6 AD |
529 | struct radeon_connector_atom_dig *dig_connector; |
530 | ||
5801ead6 AD |
531 | if (!radeon_connector->con_priv) |
532 | return; | |
533 | dig_connector = radeon_connector->con_priv; | |
534 | ||
224d94b1 AD |
535 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
536 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { | |
537 | dig_connector->dp_clock = | |
538 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
539 | dig_connector->dp_lane_count = | |
540 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); | |
541 | } | |
5801ead6 AD |
542 | } |
543 | ||
224d94b1 | 544 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
545 | struct drm_display_mode *mode) |
546 | { | |
224d94b1 AD |
547 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
548 | struct radeon_connector_atom_dig *dig_connector; | |
549 | int dp_clock; | |
5801ead6 | 550 | |
224d94b1 AD |
551 | if (!radeon_connector->con_priv) |
552 | return MODE_CLOCK_HIGH; | |
553 | dig_connector = radeon_connector->con_priv; | |
554 | ||
555 | dp_clock = | |
556 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
557 | ||
558 | if ((dp_clock == 540000) && | |
559 | (!radeon_connector_is_dp12_capable(connector))) | |
560 | return MODE_CLOCK_HIGH; | |
561 | ||
562 | return MODE_OK; | |
5801ead6 AD |
563 | } |
564 | ||
d5811e87 AD |
565 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
566 | { | |
567 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
568 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
569 | ||
ab8f1a2a | 570 | if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0) |
d5811e87 | 571 | return false; |
1ffdff13 | 572 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
d5811e87 AD |
573 | return false; |
574 | return true; | |
575 | } | |
576 | ||
2953da15 AD |
577 | void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
578 | u8 power_state) | |
579 | { | |
580 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
581 | struct radeon_connector_atom_dig *dig_connector; | |
582 | ||
583 | if (!radeon_connector->con_priv) | |
584 | return; | |
585 | ||
586 | dig_connector = radeon_connector->con_priv; | |
587 | ||
588 | /* power up/down the sink */ | |
589 | if (dig_connector->dpcd[0] >= 0x11) { | |
496263bf | 590 | drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux, |
2953da15 AD |
591 | DP_SET_POWER, power_state); |
592 | usleep_range(1000, 2000); | |
593 | } | |
594 | } | |
595 | ||
596 | ||
224d94b1 AD |
597 | struct radeon_dp_link_train_info { |
598 | struct radeon_device *rdev; | |
599 | struct drm_encoder *encoder; | |
600 | struct drm_connector *connector; | |
224d94b1 AD |
601 | int enc_id; |
602 | int dp_clock; | |
603 | int dp_lane_count; | |
224d94b1 | 604 | bool tp3_supported; |
1a644cd4 | 605 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
224d94b1 AD |
606 | u8 train_set[4]; |
607 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
608 | u8 tries; | |
5a96a899 | 609 | bool use_dpencoder; |
496263bf | 610 | struct drm_dp_aux *aux; |
224d94b1 | 611 | }; |
5801ead6 | 612 | |
224d94b1 | 613 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 614 | { |
224d94b1 AD |
615 | /* set the initial vs/emph on the source */ |
616 | atombios_dig_transmitter_setup(dp_info->encoder, | |
617 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, | |
618 | 0, dp_info->train_set[0]); /* sets all lanes at once */ | |
619 | ||
620 | /* set the vs/emph on the sink */ | |
496263bf AD |
621 | drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, |
622 | dp_info->train_set, dp_info->dp_lane_count); | |
5801ead6 AD |
623 | } |
624 | ||
224d94b1 | 625 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
746c1aa4 | 626 | { |
224d94b1 | 627 | int rtp = 0; |
746c1aa4 | 628 | |
224d94b1 | 629 | /* set training pattern on the source */ |
5a96a899 | 630 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
224d94b1 AD |
631 | switch (tp) { |
632 | case DP_TRAINING_PATTERN_1: | |
633 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; | |
634 | break; | |
635 | case DP_TRAINING_PATTERN_2: | |
636 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; | |
637 | break; | |
638 | case DP_TRAINING_PATTERN_3: | |
639 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; | |
640 | break; | |
641 | } | |
642 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); | |
643 | } else { | |
644 | switch (tp) { | |
645 | case DP_TRAINING_PATTERN_1: | |
646 | rtp = 0; | |
647 | break; | |
648 | case DP_TRAINING_PATTERN_2: | |
649 | rtp = 1; | |
650 | break; | |
651 | } | |
652 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, | |
653 | dp_info->dp_clock, dp_info->enc_id, rtp); | |
654 | } | |
746c1aa4 | 655 | |
224d94b1 | 656 | /* enable training pattern on the sink */ |
496263bf | 657 | drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); |
746c1aa4 DA |
658 | } |
659 | ||
224d94b1 | 660 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 661 | { |
386d4d75 AD |
662 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
663 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
224d94b1 | 664 | u8 tmp; |
5801ead6 | 665 | |
224d94b1 | 666 | /* power up the sink */ |
2953da15 | 667 | radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); |
224d94b1 AD |
668 | |
669 | /* possibly enable downspread on the sink */ | |
670 | if (dp_info->dpcd[3] & 0x1) | |
496263bf AD |
671 | drm_dp_dpcd_writeb(dp_info->aux, |
672 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); | |
224d94b1 | 673 | else |
496263bf AD |
674 | drm_dp_dpcd_writeb(dp_info->aux, |
675 | DP_DOWNSPREAD_CTRL, 0); | |
5801ead6 | 676 | |
386d4d75 AD |
677 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
678 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { | |
496263bf | 679 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
386d4d75 | 680 | } |
5801ead6 | 681 | |
224d94b1 AD |
682 | /* set the lane count on the sink */ |
683 | tmp = dp_info->dp_lane_count; | |
27f75dc6 | 684 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
224d94b1 | 685 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
496263bf | 686 | drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); |
5801ead6 | 687 | |
224d94b1 | 688 | /* set the link rate on the sink */ |
3b5c662e | 689 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
496263bf | 690 | drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); |
5801ead6 | 691 | |
224d94b1 | 692 | /* start training on the source */ |
5a96a899 | 693 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
694 | atombios_dig_encoder_setup(dp_info->encoder, |
695 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); | |
5801ead6 | 696 | else |
224d94b1 AD |
697 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
698 | dp_info->dp_clock, dp_info->enc_id, 0); | |
5801ead6 | 699 | |
5801ead6 | 700 | /* disable the training pattern on the sink */ |
496263bf AD |
701 | drm_dp_dpcd_writeb(dp_info->aux, |
702 | DP_TRAINING_PATTERN_SET, | |
703 | DP_TRAINING_PATTERN_DISABLE); | |
224d94b1 AD |
704 | |
705 | return 0; | |
706 | } | |
5801ead6 | 707 | |
224d94b1 AD |
708 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
709 | { | |
5801ead6 | 710 | udelay(400); |
5801ead6 | 711 | |
224d94b1 | 712 | /* disable the training pattern on the sink */ |
496263bf AD |
713 | drm_dp_dpcd_writeb(dp_info->aux, |
714 | DP_TRAINING_PATTERN_SET, | |
715 | DP_TRAINING_PATTERN_DISABLE); | |
224d94b1 AD |
716 | |
717 | /* disable the training pattern on the source */ | |
5a96a899 | 718 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
719 | atombios_dig_encoder_setup(dp_info->encoder, |
720 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); | |
721 | else | |
722 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, | |
723 | dp_info->dp_clock, dp_info->enc_id, 0); | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) | |
729 | { | |
730 | bool clock_recovery; | |
731 | u8 voltage; | |
732 | int i; | |
733 | ||
734 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); | |
735 | memset(dp_info->train_set, 0, 4); | |
736 | radeon_dp_update_vs_emph(dp_info); | |
737 | ||
738 | udelay(400); | |
5fbfce7f | 739 | |
5801ead6 AD |
740 | /* clock recovery loop */ |
741 | clock_recovery = false; | |
224d94b1 | 742 | dp_info->tries = 0; |
5801ead6 | 743 | voltage = 0xff; |
224d94b1 | 744 | while (1) { |
1a644cd4 | 745 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
224d94b1 | 746 | |
ab8f1a2a AD |
747 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
748 | dp_info->link_status) <= 0) { | |
8d1c702a | 749 | DRM_ERROR("displayport link status failed\n"); |
5801ead6 | 750 | break; |
8d1c702a | 751 | } |
5801ead6 | 752 | |
01916270 | 753 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
754 | clock_recovery = true; |
755 | break; | |
756 | } | |
757 | ||
224d94b1 AD |
758 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
759 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
5801ead6 AD |
760 | break; |
761 | } | |
224d94b1 | 762 | if (i == dp_info->dp_lane_count) { |
5801ead6 AD |
763 | DRM_ERROR("clock recovery reached max voltage\n"); |
764 | break; | |
765 | } | |
766 | ||
224d94b1 AD |
767 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
768 | ++dp_info->tries; | |
769 | if (dp_info->tries == 5) { | |
5801ead6 AD |
770 | DRM_ERROR("clock recovery tried 5 times\n"); |
771 | break; | |
772 | } | |
773 | } else | |
224d94b1 | 774 | dp_info->tries = 0; |
5801ead6 | 775 | |
224d94b1 | 776 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
5801ead6 AD |
777 | |
778 | /* Compute new train_set as requested by sink */ | |
224d94b1 AD |
779 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
780 | ||
781 | radeon_dp_update_vs_emph(dp_info); | |
5801ead6 | 782 | } |
224d94b1 | 783 | if (!clock_recovery) { |
5801ead6 | 784 | DRM_ERROR("clock recovery failed\n"); |
224d94b1 AD |
785 | return -1; |
786 | } else { | |
d9fdaafb | 787 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
788 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
789 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
53c1e09f | 790 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
791 | return 0; |
792 | } | |
793 | } | |
5801ead6 | 794 | |
224d94b1 AD |
795 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
796 | { | |
797 | bool channel_eq; | |
5801ead6 | 798 | |
224d94b1 AD |
799 | if (dp_info->tp3_supported) |
800 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); | |
bcc1c2a1 | 801 | else |
224d94b1 | 802 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
5801ead6 AD |
803 | |
804 | /* channel equalization loop */ | |
224d94b1 | 805 | dp_info->tries = 0; |
5801ead6 | 806 | channel_eq = false; |
224d94b1 | 807 | while (1) { |
1a644cd4 | 808 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
224d94b1 | 809 | |
ab8f1a2a AD |
810 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
811 | dp_info->link_status) <= 0) { | |
8d1c702a | 812 | DRM_ERROR("displayport link status failed\n"); |
5801ead6 | 813 | break; |
8d1c702a | 814 | } |
5801ead6 | 815 | |
1ffdff13 | 816 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
817 | channel_eq = true; |
818 | break; | |
819 | } | |
820 | ||
821 | /* Try 5 times */ | |
224d94b1 | 822 | if (dp_info->tries > 5) { |
5801ead6 AD |
823 | DRM_ERROR("channel eq failed: 5 tries\n"); |
824 | break; | |
825 | } | |
826 | ||
827 | /* Compute new train_set as requested by sink */ | |
224d94b1 | 828 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
5801ead6 | 829 | |
224d94b1 AD |
830 | radeon_dp_update_vs_emph(dp_info); |
831 | dp_info->tries++; | |
5801ead6 AD |
832 | } |
833 | ||
224d94b1 | 834 | if (!channel_eq) { |
5801ead6 | 835 | DRM_ERROR("channel eq failed\n"); |
224d94b1 AD |
836 | return -1; |
837 | } else { | |
d9fdaafb | 838 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
839 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
840 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) | |
53c1e09f | 841 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
842 | return 0; |
843 | } | |
5801ead6 AD |
844 | } |
845 | ||
224d94b1 AD |
846 | void radeon_dp_link_train(struct drm_encoder *encoder, |
847 | struct drm_connector *connector) | |
746c1aa4 | 848 | { |
224d94b1 AD |
849 | struct drm_device *dev = encoder->dev; |
850 | struct radeon_device *rdev = dev->dev_private; | |
851 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
852 | struct radeon_encoder_atom_dig *dig; | |
853 | struct radeon_connector *radeon_connector; | |
854 | struct radeon_connector_atom_dig *dig_connector; | |
855 | struct radeon_dp_link_train_info dp_info; | |
5a96a899 JG |
856 | int index; |
857 | u8 tmp, frev, crev; | |
746c1aa4 | 858 | |
224d94b1 AD |
859 | if (!radeon_encoder->enc_priv) |
860 | return; | |
861 | dig = radeon_encoder->enc_priv; | |
746c1aa4 | 862 | |
224d94b1 AD |
863 | radeon_connector = to_radeon_connector(connector); |
864 | if (!radeon_connector->con_priv) | |
865 | return; | |
866 | dig_connector = radeon_connector->con_priv; | |
834b2904 | 867 | |
224d94b1 AD |
868 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
869 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) | |
870 | return; | |
746c1aa4 | 871 | |
5a96a899 JG |
872 | /* DPEncoderService newer than 1.1 can't program properly the |
873 | * training pattern. When facing such version use the | |
874 | * DIGXEncoderControl (X== 1 | 2) | |
875 | */ | |
876 | dp_info.use_dpencoder = true; | |
877 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
878 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { | |
879 | if (crev > 1) { | |
880 | dp_info.use_dpencoder = false; | |
881 | } | |
882 | } | |
883 | ||
224d94b1 AD |
884 | dp_info.enc_id = 0; |
885 | if (dig->dig_encoder) | |
886 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; | |
887 | else | |
888 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; | |
889 | if (dig->linkb) | |
890 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; | |
891 | else | |
892 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; | |
834b2904 | 893 | |
496263bf | 894 | drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp); |
224d94b1 AD |
895 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
896 | dp_info.tp3_supported = true; | |
897 | else | |
898 | dp_info.tp3_supported = false; | |
899 | ||
1a644cd4 | 900 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
224d94b1 AD |
901 | dp_info.rdev = rdev; |
902 | dp_info.encoder = encoder; | |
903 | dp_info.connector = connector; | |
224d94b1 AD |
904 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
905 | dp_info.dp_clock = dig_connector->dp_clock; | |
496263bf | 906 | dp_info.aux = &dig_connector->dp_i2c_bus->aux; |
224d94b1 AD |
907 | |
908 | if (radeon_dp_link_train_init(&dp_info)) | |
909 | goto done; | |
910 | if (radeon_dp_link_train_cr(&dp_info)) | |
911 | goto done; | |
912 | if (radeon_dp_link_train_ce(&dp_info)) | |
913 | goto done; | |
914 | done: | |
915 | if (radeon_dp_link_train_finish(&dp_info)) | |
916 | return; | |
746c1aa4 | 917 | } |