projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: use drm_detect_hdmi_monitor for picking encoder mode
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38
39static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40{
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54 return true;
55 default:
56 return false;
57 }
58}
59
60static struct drm_connector *
61radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
62{
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
67
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
71 return connector;
72 }
73 return NULL;
74}
75
76static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
79{
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct drm_device *dev = encoder->dev;
82 struct radeon_device *rdev = dev->dev_private;
83
84 /* set the active encoder to connector routing */
85 radeon_encoder_set_active_device(encoder);
86 drm_mode_set_crtcinfo(adjusted_mode, 0);
87
88 /* hw bug */
89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
92
93 /* get the native mode for LVDS */
94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95 radeon_panel_mode_fixup(encoder, adjusted_mode);
96
97 /* get the native mode for TV */
98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
100 if (tv_dac) {
101 if (tv_dac->tv_std == TV_STD_NTSC ||
102 tv_dac->tv_std == TV_STD_NTSC_J ||
103 tv_dac->tv_std == TV_STD_PAL_M)
104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
105 else
106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
107 }
108 }
109
110 if (ASIC_IS_DCE3(rdev) &&
111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114 radeon_dp_set_link_config(connector, mode);
115 }
116
117 return true;
118}
119
120static void
121atombios_dac_setup(struct drm_encoder *encoder, int action)
122{
123 struct drm_device *dev = encoder->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
127 int index = 0;
128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
129
130 memset(&args, 0, sizeof(args));
131
132 switch (radeon_encoder->encoder_id) {
133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
136 break;
137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
140 break;
141 }
142
143 args.ucAction = action;
144
145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146 args.ucDacStandard = ATOM_DAC1_PS2;
147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148 args.ucDacStandard = ATOM_DAC1_CV;
149 else {
150 switch (dac_info->tv_std) {
151 case TV_STD_PAL:
152 case TV_STD_PAL_M:
153 case TV_STD_SCART_PAL:
154 case TV_STD_SECAM:
155 case TV_STD_PAL_CN:
156 args.ucDacStandard = ATOM_DAC1_PAL;
157 break;
158 case TV_STD_NTSC:
159 case TV_STD_NTSC_J:
160 case TV_STD_PAL_60:
161 default:
162 args.ucDacStandard = ATOM_DAC1_NTSC;
163 break;
164 }
165 }
166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
167
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
169
170}
171
172static void
173atombios_tv_setup(struct drm_encoder *encoder, int action)
174{
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 TV_ENCODER_CONTROL_PS_ALLOCATION args;
179 int index = 0;
180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
181
182 memset(&args, 0, sizeof(args));
183
184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
185
186 args.sTVEncoder.ucAction = action;
187
188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
190 else {
191 switch (dac_info->tv_std) {
192 case TV_STD_NTSC:
193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
194 break;
195 case TV_STD_PAL:
196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
197 break;
198 case TV_STD_PAL_M:
199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
200 break;
201 case TV_STD_PAL_60:
202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
203 break;
204 case TV_STD_NTSC_J:
205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
206 break;
207 case TV_STD_SCART_PAL:
208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
209 break;
210 case TV_STD_SECAM:
211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
212 break;
213 case TV_STD_PAL_CN:
214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
215 break;
216 default:
217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
218 break;
219 }
220 }
221
222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
223
224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
225
226}
227
228union dvo_encoder_control {
229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
232};
233
234void
235atombios_dvo_setup(struct drm_encoder *encoder, int action)
236{
237 struct drm_device *dev = encoder->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240 union dvo_encoder_control args;
241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 242 uint8_t frev, crev;
3f03ced8
AD		 243
244 memset(&args, 0, sizeof(args));
245
24153dd3
AD		 246 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
247 return;
248
249 switch (frev) {
250 case 1:
251 switch (crev) {
252 case 1:
253 /* R4xx, R5xx */
254 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
255
256 if (radeon_encoder->pixel_clock > 165000)
257 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
258
259 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
260 break;
261 case 2:
262 /* RS600/690/740 */
263 args.dvo.sDVOEncoder.ucAction = action;
264 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
265 /* DFP1, CRT1, TV1 depending on the type of port */
266 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
267
268 if (radeon_encoder->pixel_clock > 165000)
269 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
270 break;
271 case 3:
272 /* R6xx */
273 args.dvo_v3.ucAction = action;
274 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
275 args.dvo_v3.ucDVOConfig = 0; /* XXX */
276 break;
277 default:
278 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
279 break;
280 }
281 break;
282 default:
283 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
284 break;
3f03ced8
AD		 285 }
286
287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
288}
289
290union lvds_encoder_control {
291 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
292 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
293};
294
295void
296atombios_digital_setup(struct drm_encoder *encoder, int action)
297{
298 struct drm_device *dev = encoder->dev;
299 struct radeon_device *rdev = dev->dev_private;
300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
301 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
302 union lvds_encoder_control args;
303 int index = 0;
304 int hdmi_detected = 0;
305 uint8_t frev, crev;
306
307 if (!dig)
308 return;
309
310 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
311 hdmi_detected = 1;
312
313 memset(&args, 0, sizeof(args));
314
315 switch (radeon_encoder->encoder_id) {
316 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
317 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
318 break;
319 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
321 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
322 break;
323 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
324 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
325 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
326 else
327 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
328 break;
329 }
330
331 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
332 return;
333
334 switch (frev) {
335 case 1:
336 case 2:
337 switch (crev) {
338 case 1:
339 args.v1.ucMisc = 0;
340 args.v1.ucAction = action;
341 if (hdmi_detected)
342 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
343 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
344 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
345 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
346 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
347 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
348 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
349 } else {
350 if (dig->linkb)
351 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
352 if (radeon_encoder->pixel_clock > 165000)
353 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
354 /*if (pScrn->rgbBits == 8) */
355 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
356 }
357 break;
358 case 2:
359 case 3:
360 args.v2.ucMisc = 0;
361 args.v2.ucAction = action;
362 if (crev == 3) {
363 if (dig->coherent_mode)
364 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
365 }
366 if (hdmi_detected)
367 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
368 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
369 args.v2.ucTruncate = 0;
370 args.v2.ucSpatial = 0;
371 args.v2.ucTemporal = 0;
372 args.v2.ucFRC = 0;
373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
374 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
376 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
377 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
378 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
379 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
380 }
381 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
382 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
383 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
384 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
385 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
386 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
387 }
388 } else {
389 if (dig->linkb)
390 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
391 if (radeon_encoder->pixel_clock > 165000)
392 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
393 }
394 break;
395 default:
396 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
397 break;
398 }
399 break;
400 default:
401 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
402 break;
403 }
404
405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406}
407
408int
409atombios_get_encoder_mode(struct drm_encoder *encoder)
410{
411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 412 struct drm_connector *connector;
413 struct radeon_connector *radeon_connector;
414 struct radeon_connector_atom_dig *dig_connector;
415
416 /* dp bridges are always DP */
417 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
418 return ATOM_ENCODER_MODE_DP;
419
420 /* DVO is always DVO */
421 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
422 return ATOM_ENCODER_MODE_DVO;
423
424 connector = radeon_get_connector_for_encoder(encoder);
425 /* if we don't have an active device yet, just use one of
426 * the connectors tied to the encoder.
427 */
428 if (!connector)
429 connector = radeon_get_connector_for_encoder_init(encoder);
430 radeon_connector = to_radeon_connector(connector);
431
432 switch (connector->connector_type) {
433 case DRM_MODE_CONNECTOR_DVII:
434 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 435 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 436 radeon_audio)
437 return ATOM_ENCODER_MODE_HDMI;
438 else if (radeon_connector->use_digital)
3f03ced8
AD		 439 return ATOM_ENCODER_MODE_DVI;
440 else
441 return ATOM_ENCODER_MODE_CRT;
442 break;
443 case DRM_MODE_CONNECTOR_DVID:
444 case DRM_MODE_CONNECTOR_HDMIA:
445 default:
27d9cc84 446 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 447 radeon_audio)
448 return ATOM_ENCODER_MODE_HDMI;
449 else
3f03ced8
AD		 450 return ATOM_ENCODER_MODE_DVI;
451 break;
452 case DRM_MODE_CONNECTOR_LVDS:
453 return ATOM_ENCODER_MODE_LVDS;
454 break;
455 case DRM_MODE_CONNECTOR_DisplayPort:
456 dig_connector = radeon_connector->con_priv;
457 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
458 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
459 return ATOM_ENCODER_MODE_DP;
27d9cc84 460 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 461 radeon_audio)
462 return ATOM_ENCODER_MODE_HDMI;
463 else
3f03ced8
AD		 464 return ATOM_ENCODER_MODE_DVI;
465 break;
466 case DRM_MODE_CONNECTOR_eDP:
467 return ATOM_ENCODER_MODE_DP;
468 case DRM_MODE_CONNECTOR_DVIA:
469 case DRM_MODE_CONNECTOR_VGA:
470 return ATOM_ENCODER_MODE_CRT;
471 break;
472 case DRM_MODE_CONNECTOR_Composite:
473 case DRM_MODE_CONNECTOR_SVIDEO:
474 case DRM_MODE_CONNECTOR_9PinDIN:
475 /* fix me */
476 return ATOM_ENCODER_MODE_TV;
477 /*return ATOM_ENCODER_MODE_CV;*/
478 break;
479 }
480}
481
482/*
483 * DIG Encoder/Transmitter Setup
484 *
485 * DCE 3.0/3.1
486 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
487 * Supports up to 3 digital outputs
488 * - 2 DIG encoder blocks.
489 * DIG1 can drive UNIPHY link A or link B
490 * DIG2 can drive UNIPHY link B or LVTMA
491 *
492 * DCE 3.2
493 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
494 * Supports up to 5 digital outputs
495 * - 2 DIG encoder blocks.
496 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
497 *
498 * DCE 4.0/5.0
499 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
500 * Supports up to 6 digital outputs
501 * - 6 DIG encoder blocks.
502 * - DIG to PHY mapping is hardcoded
503 * DIG1 drives UNIPHY0 link A, A+B
504 * DIG2 drives UNIPHY0 link B
505 * DIG3 drives UNIPHY1 link A, A+B
506 * DIG4 drives UNIPHY1 link B
507 * DIG5 drives UNIPHY2 link A, A+B
508 * DIG6 drives UNIPHY2 link B
509 *
510 * DCE 4.1
511 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
512 * Supports up to 6 digital outputs
513 * - 2 DIG encoder blocks.
514 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
515 *
516 * Routing
517 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
518 * Examples:
519 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
520 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
521 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
522 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
523 */
524
525union dig_encoder_control {
526 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
527 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
528 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
529 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
530};
531
532void
533atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
534{
535 struct drm_device *dev = encoder->dev;
536 struct radeon_device *rdev = dev->dev_private;
537 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
538 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
539 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
540 union dig_encoder_control args;
541 int index = 0;
542 uint8_t frev, crev;
543 int dp_clock = 0;
544 int dp_lane_count = 0;
545 int hpd_id = RADEON_HPD_NONE;
546 int bpc = 8;
547
548 if (connector) {
549 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
550 struct radeon_connector_atom_dig *dig_connector =
551 radeon_connector->con_priv;
552
553 dp_clock = dig_connector->dp_clock;
554 dp_lane_count = dig_connector->dp_lane_count;
555 hpd_id = radeon_connector->hpd.hpd;
556 bpc = connector->display_info.bpc;
557 }
558
559 /* no dig encoder assigned */
560 if (dig->dig_encoder == -1)
561 return;
562
563 memset(&args, 0, sizeof(args));
564
565 if (ASIC_IS_DCE4(rdev))
566 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
567 else {
568 if (dig->dig_encoder)
569 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
570 else
571 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
572 }
573
574 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
575 return;
576
58cdcb8b
AD		 577 switch (frev) {
578 case 1:
579 switch (crev) {
580 case 1:
581 args.v1.ucAction = action;
582 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
583 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
584 args.v3.ucPanelMode = panel_mode;
585 else
586 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
587
588 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
589 args.v1.ucLaneNum = dp_lane_count;
590 else if (radeon_encoder->pixel_clock > 165000)
591 args.v1.ucLaneNum = 8;
592 else
593 args.v1.ucLaneNum = 4;
594
595 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
596 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
597 switch (radeon_encoder->encoder_id) {
598 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
599 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
600 break;
601 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
603 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
604 break;
605 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
606 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
607 break;
608 }
609 if (dig->linkb)
610 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
611 else
612 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 613 break;
58cdcb8b
AD		 614 case 2:
615 case 3:
616 args.v3.ucAction = action;
617 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
618 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
619 args.v3.ucPanelMode = panel_mode;
620 else
621 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
622
623 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
624 args.v3.ucLaneNum = dp_lane_count;
625 else if (radeon_encoder->pixel_clock > 165000)
626 args.v3.ucLaneNum = 8;
627 else
628 args.v3.ucLaneNum = 4;
629
630 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
631 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
632 args.v3.acConfig.ucDigSel = dig->dig_encoder;
633 switch (bpc) {
634 case 0:
635 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
636 break;
637 case 6:
638 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
639 break;
640 case 8:
641 default:
642 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
643 break;
644 case 10:
645 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
646 break;
647 case 12:
648 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
649 break;
650 case 16:
651 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
652 break;
653 }
3f03ced8 654 break;
58cdcb8b
AD		 655 case 4:
656 args.v4.ucAction = action;
657 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
658 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
659 args.v4.ucPanelMode = panel_mode;
660 else
661 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
662
663 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
664 args.v4.ucLaneNum = dp_lane_count;
665 else if (radeon_encoder->pixel_clock > 165000)
666 args.v4.ucLaneNum = 8;
667 else
668 args.v4.ucLaneNum = 4;
669
670 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
671 if (dp_clock == 270000)
672 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
673 else if (dp_clock == 540000)
674 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
675 }
676 args.v4.acConfig.ucDigSel = dig->dig_encoder;
677 switch (bpc) {
678 case 0:
679 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
680 break;
681 case 6:
682 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
683 break;
684 case 8:
685 default:
686 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
687 break;
688 case 10:
689 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
690 break;
691 case 12:
692 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
693 break;
694 case 16:
695 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
696 break;
697 }
698 if (hpd_id == RADEON_HPD_NONE)
699 args.v4.ucHPD_ID = 0;
700 else
701 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 702 break;
3f03ced8 703 default:
58cdcb8b 704 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 705 break;
706 }
58cdcb8b
AD		 707 break;
708 default:
709 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
710 break;
3f03ced8
AD		 711 }
712
713 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
714
715}
716
717union dig_transmitter_control {
718 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
719 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
720 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
721 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
722};
723
724void
725atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
726{
727 struct drm_device *dev = encoder->dev;
728 struct radeon_device *rdev = dev->dev_private;
729 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
730 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
731 struct drm_connector *connector;
732 union dig_transmitter_control args;
733 int index = 0;
734 uint8_t frev, crev;
735 bool is_dp = false;
736 int pll_id = 0;
737 int dp_clock = 0;
738 int dp_lane_count = 0;
739 int connector_object_id = 0;
740 int igp_lane_info = 0;
741 int dig_encoder = dig->dig_encoder;
742
743 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
744 connector = radeon_get_connector_for_encoder_init(encoder);
745 /* just needed to avoid bailing in the encoder check. the encoder
746 * isn't used for init
747 */
748 dig_encoder = 0;
749 } else
750 connector = radeon_get_connector_for_encoder(encoder);
751
752 if (connector) {
753 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
754 struct radeon_connector_atom_dig *dig_connector =
755 radeon_connector->con_priv;
756
757 dp_clock = dig_connector->dp_clock;
758 dp_lane_count = dig_connector->dp_lane_count;
759 connector_object_id =
760 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
761 igp_lane_info = dig_connector->igp_lane_info;
762 }
763
a3b08294
AD		 764 if (encoder->crtc) {
765 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
766 pll_id = radeon_crtc->pll_id;
767 }
768
3f03ced8
AD		 769 /* no dig encoder assigned */
770 if (dig_encoder == -1)
771 return;
772
773 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
774 is_dp = true;
775
776 memset(&args, 0, sizeof(args));
777
778 switch (radeon_encoder->encoder_id) {
779 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
780 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
781 break;
782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
783 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
784 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
785 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
786 break;
787 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
788 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
789 break;
790 }
791
792 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
793 return;
794
a3b08294
AD		 795 switch (frev) {
796 case 1:
797 switch (crev) {
798 case 1:
799 args.v1.ucAction = action;
800 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
801 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
802 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
803 args.v1.asMode.ucLaneSel = lane_num;
804 args.v1.asMode.ucLaneSet = lane_set;
805 } else {
806 if (is_dp)
807 args.v1.usPixelClock =
808 cpu_to_le16(dp_clock / 10);
809 else if (radeon_encoder->pixel_clock > 165000)
810 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
811 else
812 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
813 }
3f03ced8 814
a3b08294 815 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 816
a3b08294
AD		 817 if (dig_encoder)
818 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
819 else
820 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
821
822 if ((rdev->flags & RADEON_IS_IGP) &&
823 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
824 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
825 if (igp_lane_info & 0x1)
826 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
827 else if (igp_lane_info & 0x2)
828 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
829 else if (igp_lane_info & 0x4)
830 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
831 else if (igp_lane_info & 0x8)
832 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
833 } else {
834 if (igp_lane_info & 0x3)
835 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
836 else if (igp_lane_info & 0xc)
837 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
838 }
839 }
840
841 if (dig->linkb)
842 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
843 else
844 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
845
846 if (is_dp)
847 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
848 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
849 if (dig->coherent_mode)
850 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
851 if (radeon_encoder->pixel_clock > 165000)
852 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
853 }
854 break;
855 case 2:
856 args.v2.ucAction = action;
857 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
858 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
859 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
860 args.v2.asMode.ucLaneSel = lane_num;
861 args.v2.asMode.ucLaneSet = lane_set;
862 } else {
863 if (is_dp)
864 args.v2.usPixelClock =
865 cpu_to_le16(dp_clock / 10);
866 else if (radeon_encoder->pixel_clock > 165000)
867 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
868 else
869 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
870 }
871
872 args.v2.acConfig.ucEncoderSel = dig_encoder;
873 if (dig->linkb)
874 args.v2.acConfig.ucLinkSel = 1;
875
876 switch (radeon_encoder->encoder_id) {
877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
878 args.v2.acConfig.ucTransmitterSel = 0;
879 break;
880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
881 args.v2.acConfig.ucTransmitterSel = 1;
882 break;
883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
884 args.v2.acConfig.ucTransmitterSel = 2;
885 break;
886 }
3f03ced8 887
3f03ced8 888 if (is_dp) {
a3b08294
AD		 889 args.v2.acConfig.fCoherentMode = 1;
890 args.v2.acConfig.fDPConnector = 1;
891 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
892 if (dig->coherent_mode)
893 args.v2.acConfig.fCoherentMode = 1;
894 if (radeon_encoder->pixel_clock > 165000)
895 args.v2.acConfig.fDualLinkConnector = 1;
896 }
897 break;
898 case 3:
899 args.v3.ucAction = action;
900 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
901 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
902 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
903 args.v3.asMode.ucLaneSel = lane_num;
904 args.v3.asMode.ucLaneSet = lane_set;
905 } else {
906 if (is_dp)
907 args.v3.usPixelClock =
908 cpu_to_le16(dp_clock / 10);
909 else if (radeon_encoder->pixel_clock > 165000)
910 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 911 else
a3b08294
AD		 912 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
913 }
914
915 if (is_dp)
916 args.v3.ucLaneNum = dp_lane_count;
917 else if (radeon_encoder->pixel_clock > 165000)
918 args.v3.ucLaneNum = 8;
919 else
920 args.v3.ucLaneNum = 4;
921
922 if (dig->linkb)
923 args.v3.acConfig.ucLinkSel = 1;
924 if (dig_encoder & 1)
925 args.v3.acConfig.ucEncoderSel = 1;
926
927 /* Select the PLL for the PHY
928 * DP PHY should be clocked from external src if there is
929 * one.
930 */
3f03ced8
AD		 931 /* On DCE4, if there is an external clock, it generates the DP ref clock */
932 if (is_dp && rdev->clock.dp_extclk)
933 args.v3.acConfig.ucRefClkSource = 2; /* external src */
934 else
935 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 936
a3b08294
AD		 937 switch (radeon_encoder->encoder_id) {
938 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
939 args.v3.acConfig.ucTransmitterSel = 0;
940 break;
941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
942 args.v3.acConfig.ucTransmitterSel = 1;
943 break;
944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
945 args.v3.acConfig.ucTransmitterSel = 2;
946 break;
947 }
3f03ced8 948
a3b08294
AD		 949 if (is_dp)
950 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
951 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
952 if (dig->coherent_mode)
953 args.v3.acConfig.fCoherentMode = 1;
954 if (radeon_encoder->pixel_clock > 165000)
955 args.v3.acConfig.fDualLinkConnector = 1;
956 }
3f03ced8 957 break;
a3b08294
AD		 958 case 4:
959 args.v4.ucAction = action;
960 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
961 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
962 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
963 args.v4.asMode.ucLaneSel = lane_num;
964 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 965 } else {
a3b08294
AD		 966 if (is_dp)
967 args.v4.usPixelClock =
968 cpu_to_le16(dp_clock / 10);
969 else if (radeon_encoder->pixel_clock > 165000)
970 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
971 else
972 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 973 }
3f03ced8 974
a3b08294
AD		 975 if (is_dp)
976 args.v4.ucLaneNum = dp_lane_count;
977 else if (radeon_encoder->pixel_clock > 165000)
978 args.v4.ucLaneNum = 8;
979 else
980 args.v4.ucLaneNum = 4;
3f03ced8 981
a3b08294
AD		 982 if (dig->linkb)
983 args.v4.acConfig.ucLinkSel = 1;
984 if (dig_encoder & 1)
985 args.v4.acConfig.ucEncoderSel = 1;
986
987 /* Select the PLL for the PHY
988 * DP PHY should be clocked from external src if there is
989 * one.
990 */
991 /* On DCE5 DCPLL usually generates the DP ref clock */
992 if (is_dp) {
993 if (rdev->clock.dp_extclk)
994 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
995 else
996 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
997 } else
998 args.v4.acConfig.ucRefClkSource = pll_id;
999
1000 switch (radeon_encoder->encoder_id) {
1001 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1002 args.v4.acConfig.ucTransmitterSel = 0;
1003 break;
1004 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1005 args.v4.acConfig.ucTransmitterSel = 1;
1006 break;
1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1008 args.v4.acConfig.ucTransmitterSel = 2;
1009 break;
1010 }
1011
1012 if (is_dp)
1013 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1014 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1015 if (dig->coherent_mode)
1016 args.v4.acConfig.fCoherentMode = 1;
1017 if (radeon_encoder->pixel_clock > 165000)
1018 args.v4.acConfig.fDualLinkConnector = 1;
1019 }
1020 break;
1021 default:
1022 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1023 break;
3f03ced8 1024 }
a3b08294
AD		 1025 break;
1026 default:
1027 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1028 break;
3f03ced8
AD		 1029 }
1030
1031 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1032}
1033
1034bool
1035atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1036{
1037 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1038 struct drm_device *dev = radeon_connector->base.dev;
1039 struct radeon_device *rdev = dev->dev_private;
1040 union dig_transmitter_control args;
1041 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1042 uint8_t frev, crev;
1043
1044 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1045 goto done;
1046
1047 if (!ASIC_IS_DCE4(rdev))
1048 goto done;
1049
1050 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1051 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1052 goto done;
1053
1054 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1055 goto done;
1056
1057 memset(&args, 0, sizeof(args));
1058
1059 args.v1.ucAction = action;
1060
1061 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1062
1063 /* wait for the panel to power up */
1064 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1065 int i;
1066
1067 for (i = 0; i < 300; i++) {
1068 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1069 return true;
1070 mdelay(1);
1071 }
1072 return false;
1073 }
1074done:
1075 return true;
1076}
1077
1078union external_encoder_control {
1079 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1080 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1081};
1082
1083static void
1084atombios_external_encoder_setup(struct drm_encoder *encoder,
1085 struct drm_encoder *ext_encoder,
1086 int action)
1087{
1088 struct drm_device *dev = encoder->dev;
1089 struct radeon_device *rdev = dev->dev_private;
1090 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1091 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1092 union external_encoder_control args;
1093 struct drm_connector *connector;
1094 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1095 u8 frev, crev;
1096 int dp_clock = 0;
1097 int dp_lane_count = 0;
1098 int connector_object_id = 0;
1099 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1100 int bpc = 8;
1101
1102 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1103 connector = radeon_get_connector_for_encoder_init(encoder);
1104 else
1105 connector = radeon_get_connector_for_encoder(encoder);
1106
1107 if (connector) {
1108 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1109 struct radeon_connector_atom_dig *dig_connector =
1110 radeon_connector->con_priv;
1111
1112 dp_clock = dig_connector->dp_clock;
1113 dp_lane_count = dig_connector->dp_lane_count;
1114 connector_object_id =
1115 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1116 bpc = connector->display_info.bpc;
1117 }
1118
1119 memset(&args, 0, sizeof(args));
1120
1121 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1122 return;
1123
1124 switch (frev) {
1125 case 1:
1126 /* no params on frev 1 */
1127 break;
1128 case 2:
1129 switch (crev) {
1130 case 1:
1131 case 2:
1132 args.v1.sDigEncoder.ucAction = action;
1133 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1134 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1135
1136 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1137 if (dp_clock == 270000)
1138 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1139 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1140 } else if (radeon_encoder->pixel_clock > 165000)
1141 args.v1.sDigEncoder.ucLaneNum = 8;
1142 else
1143 args.v1.sDigEncoder.ucLaneNum = 4;
1144 break;
1145 case 3:
1146 args.v3.sExtEncoder.ucAction = action;
1147 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1148 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1149 else
1150 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1151 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1152
1153 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1154 if (dp_clock == 270000)
1155 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1156 else if (dp_clock == 540000)
1157 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1158 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1159 } else if (radeon_encoder->pixel_clock > 165000)
1160 args.v3.sExtEncoder.ucLaneNum = 8;
1161 else
1162 args.v3.sExtEncoder.ucLaneNum = 4;
1163 switch (ext_enum) {
1164 case GRAPH_OBJECT_ENUM_ID1:
1165 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1166 break;
1167 case GRAPH_OBJECT_ENUM_ID2:
1168 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1169 break;
1170 case GRAPH_OBJECT_ENUM_ID3:
1171 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1172 break;
1173 }
1174 switch (bpc) {
1175 case 0:
1176 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1177 break;
1178 case 6:
1179 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1180 break;
1181 case 8:
1182 default:
1183 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1184 break;
1185 case 10:
1186 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1187 break;
1188 case 12:
1189 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1190 break;
1191 case 16:
1192 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1193 break;
1194 }
1195 break;
1196 default:
1197 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1198 return;
1199 }
1200 break;
1201 default:
1202 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1203 return;
1204 }
1205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1206}
1207
1208static void
1209atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1210{
1211 struct drm_device *dev = encoder->dev;
1212 struct radeon_device *rdev = dev->dev_private;
1213 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1215 ENABLE_YUV_PS_ALLOCATION args;
1216 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1217 uint32_t temp, reg;
1218
1219 memset(&args, 0, sizeof(args));
1220
1221 if (rdev->family >= CHIP_R600)
1222 reg = R600_BIOS_3_SCRATCH;
1223 else
1224 reg = RADEON_BIOS_3_SCRATCH;
1225
1226 /* XXX: fix up scratch reg handling */
1227 temp = RREG32(reg);
1228 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1229 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1230 (radeon_crtc->crtc_id << 18)));
1231 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1232 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1233 else
1234 WREG32(reg, 0);
1235
1236 if (enable)
1237 args.ucEnable = ATOM_ENABLE;
1238 args.ucCRTC = radeon_crtc->crtc_id;
1239
1240 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1241
1242 WREG32(reg, temp);
1243}
1244
1245static void
1246radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1247{
1248 struct drm_device *dev = encoder->dev;
1249 struct radeon_device *rdev = dev->dev_private;
1250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1251 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1252 int index = 0;
1253
1254 memset(&args, 0, sizeof(args));
1255
1256 switch (radeon_encoder->encoder_id) {
1257 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1258 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1259 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1260 break;
1261 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1262 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1263 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1264 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1265 break;
1266 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1267 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1268 break;
1269 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1270 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1271 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1272 else
1273 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1274 break;
1275 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1276 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1277 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1278 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1279 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1280 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1281 else
1282 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1283 break;
1284 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1285 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1286 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1287 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1288 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1289 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1290 else
1291 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1292 break;
1293 default:
1294 return;
1295 }
1296
1297 switch (mode) {
1298 case DRM_MODE_DPMS_ON:
1299 args.ucAction = ATOM_ENABLE;
1300 /* workaround for DVOOutputControl on some RS690 systems */
1301 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1302 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1303 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1304 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1305 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1306 } else
1307 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1308 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1309 args.ucAction = ATOM_LCD_BLON;
1310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1311 }
1312 break;
1313 case DRM_MODE_DPMS_STANDBY:
1314 case DRM_MODE_DPMS_SUSPEND:
1315 case DRM_MODE_DPMS_OFF:
1316 args.ucAction = ATOM_DISABLE;
1317 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1318 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1319 args.ucAction = ATOM_LCD_BLOFF;
1320 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1321 }
1322 break;
1323 }
1324}
1325
1326static void
1327radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1328{
1329 struct drm_device *dev = encoder->dev;
1330 struct radeon_device *rdev = dev->dev_private;
1331 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1333 struct radeon_connector *radeon_connector = NULL;
1334 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1335
1336 if (connector) {
1337 radeon_connector = to_radeon_connector(connector);
1338 radeon_dig_connector = radeon_connector->con_priv;
1339 }
1340
1341 switch (mode) {
1342 case DRM_MODE_DPMS_ON:
1343 /* some early dce3.2 boards have a bug in their transmitter control table */
3a47824d
AD		 1344 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
1345 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
3f03ced8
AD		 1346 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1347 else
1348 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1349 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1350 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1351 atombios_set_edp_panel_power(connector,
1352 ATOM_TRANSMITTER_ACTION_POWER_ON);
1353 radeon_dig_connector->edp_on = true;
1354 }
3f03ced8
AD		 1355 radeon_dp_link_train(encoder, connector);
1356 if (ASIC_IS_DCE4(rdev))
1357 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1358 }
1359 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1360 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1361 break;
1362 case DRM_MODE_DPMS_STANDBY:
1363 case DRM_MODE_DPMS_SUSPEND:
1364 case DRM_MODE_DPMS_OFF:
3a47824d
AD		 1365 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1366 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1367 else
1368 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
3f03ced8
AD		 1369 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1370 if (ASIC_IS_DCE4(rdev))
1371 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1372 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1373 atombios_set_edp_panel_power(connector,
1374 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1375 radeon_dig_connector->edp_on = false;
1376 }
1377 }
1378 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1379 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1380 break;
1381 }
1382}
1383
1384static void
1385radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1386 struct drm_encoder *ext_encoder,
1387 int mode)
1388{
1389 struct drm_device *dev = encoder->dev;
1390 struct radeon_device *rdev = dev->dev_private;
1391
1392 switch (mode) {
1393 case DRM_MODE_DPMS_ON:
1394 default:
1395 if (ASIC_IS_DCE41(rdev)) {
1396 atombios_external_encoder_setup(encoder, ext_encoder,
1397 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1398 atombios_external_encoder_setup(encoder, ext_encoder,
1399 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1400 } else
1401 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1402 break;
1403 case DRM_MODE_DPMS_STANDBY:
1404 case DRM_MODE_DPMS_SUSPEND:
1405 case DRM_MODE_DPMS_OFF:
1406 if (ASIC_IS_DCE41(rdev)) {
1407 atombios_external_encoder_setup(encoder, ext_encoder,
1408 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1409 atombios_external_encoder_setup(encoder, ext_encoder,
1410 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1411 } else
1412 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1413 break;
1414 }
1415}
1416
1417static void
1418radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1419{
1420 struct drm_device *dev = encoder->dev;
1421 struct radeon_device *rdev = dev->dev_private;
1422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1423 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1424
1425 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1426 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1427 radeon_encoder->active_device);
1428 switch (radeon_encoder->encoder_id) {
1429 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1431 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1432 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1433 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1434 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1435 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1436 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1437 radeon_atom_encoder_dpms_avivo(encoder, mode);
1438 break;
1439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1440 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1441 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1442 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1443 radeon_atom_encoder_dpms_dig(encoder, mode);
1444 break;
1445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1446 if (ASIC_IS_DCE5(rdev)) {
1447 switch (mode) {
1448 case DRM_MODE_DPMS_ON:
1449 atombios_dvo_setup(encoder, ATOM_ENABLE);
1450 break;
1451 case DRM_MODE_DPMS_STANDBY:
1452 case DRM_MODE_DPMS_SUSPEND:
1453 case DRM_MODE_DPMS_OFF:
1454 atombios_dvo_setup(encoder, ATOM_DISABLE);
1455 break;
1456 }
1457 } else if (ASIC_IS_DCE3(rdev))
1458 radeon_atom_encoder_dpms_dig(encoder, mode);
1459 else
1460 radeon_atom_encoder_dpms_avivo(encoder, mode);
1461 break;
1462 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1463 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1464 if (ASIC_IS_DCE5(rdev)) {
1465 switch (mode) {
1466 case DRM_MODE_DPMS_ON:
1467 atombios_dac_setup(encoder, ATOM_ENABLE);
1468 break;
1469 case DRM_MODE_DPMS_STANDBY:
1470 case DRM_MODE_DPMS_SUSPEND:
1471 case DRM_MODE_DPMS_OFF:
1472 atombios_dac_setup(encoder, ATOM_DISABLE);
1473 break;
1474 }
1475 } else
1476 radeon_atom_encoder_dpms_avivo(encoder, mode);
1477 break;
1478 default:
1479 return;
1480 }
1481
1482 if (ext_encoder)
1483 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1484
1485 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1486
1487}
1488
1489union crtc_source_param {
1490 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1491 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1492};
1493
1494static void
1495atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1496{
1497 struct drm_device *dev = encoder->dev;
1498 struct radeon_device *rdev = dev->dev_private;
1499 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1500 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1501 union crtc_source_param args;
1502 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1503 uint8_t frev, crev;
1504 struct radeon_encoder_atom_dig *dig;
1505
1506 memset(&args, 0, sizeof(args));
1507
1508 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1509 return;
1510
1511 switch (frev) {
1512 case 1:
1513 switch (crev) {
1514 case 1:
1515 default:
1516 if (ASIC_IS_AVIVO(rdev))
1517 args.v1.ucCRTC = radeon_crtc->crtc_id;
1518 else {
1519 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1520 args.v1.ucCRTC = radeon_crtc->crtc_id;
1521 } else {
1522 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1523 }
1524 }
1525 switch (radeon_encoder->encoder_id) {
1526 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1527 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1528 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1529 break;
1530 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1531 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1532 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1533 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1534 else
1535 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1536 break;
1537 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1538 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1540 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1541 break;
1542 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1544 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1545 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1546 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1547 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1548 else
1549 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1550 break;
1551 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1553 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1554 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1555 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1556 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1557 else
1558 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1559 break;
1560 }
1561 break;
1562 case 2:
1563 args.v2.ucCRTC = radeon_crtc->crtc_id;
1564 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1565 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1566
1567 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1568 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1569 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1570 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1571 else
1572 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1573 } else
1574 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1575 switch (radeon_encoder->encoder_id) {
1576 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1577 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1578 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1580 dig = radeon_encoder->enc_priv;
1581 switch (dig->dig_encoder) {
1582 case 0:
1583 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1584 break;
1585 case 1:
1586 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1587 break;
1588 case 2:
1589 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1590 break;
1591 case 3:
1592 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1593 break;
1594 case 4:
1595 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1596 break;
1597 case 5:
1598 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1599 break;
1600 }
1601 break;
1602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1603 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1604 break;
1605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1606 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1607 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1608 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1609 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1610 else
1611 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1612 break;
1613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1614 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1615 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1616 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1617 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1618 else
1619 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1620 break;
1621 }
1622 break;
1623 }
1624 break;
1625 default:
1626 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1627 return;
1628 }
1629
1630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1631
1632 /* update scratch regs with new routing */
1633 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1634}
1635
1636static void
1637atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1638 struct drm_display_mode *mode)
1639{
1640 struct drm_device *dev = encoder->dev;
1641 struct radeon_device *rdev = dev->dev_private;
1642 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1643 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1644
1645 /* Funky macbooks */
1646 if ((dev->pdev->device == 0x71C5) &&
1647 (dev->pdev->subsystem_vendor == 0x106b) &&
1648 (dev->pdev->subsystem_device == 0x0080)) {
1649 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1650 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1651
1652 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1653 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1654
1655 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1656 }
1657 }
1658
1659 /* set scaler clears this on some chips */
1660 if (ASIC_IS_AVIVO(rdev) &&
1661 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1662 if (ASIC_IS_DCE4(rdev)) {
1663 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1664 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1665 EVERGREEN_INTERLEAVE_EN);
1666 else
1667 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1668 } else {
1669 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1670 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1671 AVIVO_D1MODE_INTERLEAVE_EN);
1672 else
1673 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1674 }
1675 }
1676}
1677
1678static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1679{
1680 struct drm_device *dev = encoder->dev;
1681 struct radeon_device *rdev = dev->dev_private;
1682 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1683 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1684 struct drm_encoder *test_encoder;
1685 struct radeon_encoder_atom_dig *dig;
1686 uint32_t dig_enc_in_use = 0;
1687
1688 /* DCE4/5 */
1689 if (ASIC_IS_DCE4(rdev)) {
1690 dig = radeon_encoder->enc_priv;
1691 if (ASIC_IS_DCE41(rdev)) {
1692 /* ontario follows DCE4 */
1693 if (rdev->family == CHIP_PALM) {
1694 if (dig->linkb)
1695 return 1;
1696 else
1697 return 0;
1698 } else
1699 /* llano follows DCE3.2 */
1700 return radeon_crtc->crtc_id;
1701 } else {
1702 switch (radeon_encoder->encoder_id) {
1703 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1704 if (dig->linkb)
1705 return 1;
1706 else
1707 return 0;
1708 break;
1709 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1710 if (dig->linkb)
1711 return 3;
1712 else
1713 return 2;
1714 break;
1715 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1716 if (dig->linkb)
1717 return 5;
1718 else
1719 return 4;
1720 break;
1721 }
1722 }
1723 }
1724
1725 /* on DCE32 and encoder can driver any block so just crtc id */
1726 if (ASIC_IS_DCE32(rdev)) {
1727 return radeon_crtc->crtc_id;
1728 }
1729
1730 /* on DCE3 - LVTMA can only be driven by DIGB */
1731 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1732 struct radeon_encoder *radeon_test_encoder;
1733
1734 if (encoder == test_encoder)
1735 continue;
1736
1737 if (!radeon_encoder_is_digital(test_encoder))
1738 continue;
1739
1740 radeon_test_encoder = to_radeon_encoder(test_encoder);
1741 dig = radeon_test_encoder->enc_priv;
1742
1743 if (dig->dig_encoder >= 0)
1744 dig_enc_in_use |= (1 << dig->dig_encoder);
1745 }
1746
1747 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1748 if (dig_enc_in_use & 0x2)
1749 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1750 return 1;
1751 }
1752 if (!(dig_enc_in_use & 1))
1753 return 0;
1754 return 1;
1755}
1756
1757/* This only needs to be called once at startup */
1758void
1759radeon_atom_encoder_init(struct radeon_device *rdev)
1760{
1761 struct drm_device *dev = rdev->ddev;
1762 struct drm_encoder *encoder;
1763
1764 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1765 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1766 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1767
1768 switch (radeon_encoder->encoder_id) {
1769 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1770 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1771 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1772 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1773 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1774 break;
1775 default:
1776 break;
1777 }
1778
1779 if (ext_encoder && ASIC_IS_DCE41(rdev))
1780 atombios_external_encoder_setup(encoder, ext_encoder,
1781 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1782 }
1783}
1784
1785static void
1786radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1787 struct drm_display_mode *mode,
1788 struct drm_display_mode *adjusted_mode)
1789{
1790 struct drm_device *dev = encoder->dev;
1791 struct radeon_device *rdev = dev->dev_private;
1792 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1793 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1794
1795 radeon_encoder->pixel_clock = adjusted_mode->clock;
1796
1797 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1798 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1799 atombios_yuv_setup(encoder, true);
1800 else
1801 atombios_yuv_setup(encoder, false);
1802 }
1803
1804 switch (radeon_encoder->encoder_id) {
1805 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1806 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1807 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1808 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1809 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1810 break;
1811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1814 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
3a47824d 1815 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
386d4d75
AD		 1816 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1817 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1818
1819 if (!connector)
1820 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1821 else
1822 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1823
3f03ced8
AD		 1824 /* setup and enable the encoder */
1825 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
386d4d75
AD		 1826 atombios_dig_encoder_setup(encoder,
1827 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1828 dig->panel_mode);
3a47824d
AD		 1829 } else if (ASIC_IS_DCE4(rdev)) {
1830 /* disable the transmitter */
1831 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1832 /* setup and enable the encoder */
1833 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
3f03ced8
AD		 1834
1835 /* enable the transmitter */
1836 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1837 } else {
1838 /* disable the encoder and transmitter */
1839 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1840 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1841
1842 /* setup and enable the encoder and transmitter */
1843 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1844 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1845 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1846 }
1847 break;
1848 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1849 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1850 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1851 atombios_dvo_setup(encoder, ATOM_ENABLE);
1852 break;
1853 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1855 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1856 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1857 atombios_dac_setup(encoder, ATOM_ENABLE);
1858 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1859 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1860 atombios_tv_setup(encoder, ATOM_ENABLE);
1861 else
1862 atombios_tv_setup(encoder, ATOM_DISABLE);
1863 }
1864 break;
1865 }
1866
1867 if (ext_encoder) {
1868 if (ASIC_IS_DCE41(rdev))
1869 atombios_external_encoder_setup(encoder, ext_encoder,
1870 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1871 else
1872 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1873 }
1874
1875 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1876
1877 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1878 r600_hdmi_enable(encoder);
1879 r600_hdmi_setmode(encoder, adjusted_mode);
1880 }
1881}
1882
1883static bool
1884atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1885{
1886 struct drm_device *dev = encoder->dev;
1887 struct radeon_device *rdev = dev->dev_private;
1888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1889 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1890
1891 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1892 ATOM_DEVICE_CV_SUPPORT |
1893 ATOM_DEVICE_CRT_SUPPORT)) {
1894 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1895 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1896 uint8_t frev, crev;
1897
1898 memset(&args, 0, sizeof(args));
1899
1900 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1901 return false;
1902
1903 args.sDacload.ucMisc = 0;
1904
1905 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1906 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1907 args.sDacload.ucDacType = ATOM_DAC_A;
1908 else
1909 args.sDacload.ucDacType = ATOM_DAC_B;
1910
1911 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1912 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1913 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1914 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1915 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1916 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1917 if (crev >= 3)
1918 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1919 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1920 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1921 if (crev >= 3)
1922 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1923 }
1924
1925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1926
1927 return true;
1928 } else
1929 return false;
1930}
1931
1932static enum drm_connector_status
1933radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1934{
1935 struct drm_device *dev = encoder->dev;
1936 struct radeon_device *rdev = dev->dev_private;
1937 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1938 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1939 uint32_t bios_0_scratch;
1940
1941 if (!atombios_dac_load_detect(encoder, connector)) {
1942 DRM_DEBUG_KMS("detect returned false \n");
1943 return connector_status_unknown;
1944 }
1945
1946 if (rdev->family >= CHIP_R600)
1947 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1948 else
1949 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1950
1951 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1952 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1953 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1954 return connector_status_connected;
1955 }
1956 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1957 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1958 return connector_status_connected;
1959 }
1960 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1961 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1962 return connector_status_connected;
1963 }
1964 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1965 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1966 return connector_status_connected; /* CTV */
1967 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1968 return connector_status_connected; /* STV */
1969 }
1970 return connector_status_disconnected;
1971}
1972
1973static enum drm_connector_status
1974radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1975{
1976 struct drm_device *dev = encoder->dev;
1977 struct radeon_device *rdev = dev->dev_private;
1978 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1979 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1980 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1981 u32 bios_0_scratch;
1982
1983 if (!ASIC_IS_DCE4(rdev))
1984 return connector_status_unknown;
1985
1986 if (!ext_encoder)
1987 return connector_status_unknown;
1988
1989 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1990 return connector_status_unknown;
1991
1992 /* load detect on the dp bridge */
1993 atombios_external_encoder_setup(encoder, ext_encoder,
1994 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1995
1996 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1997
1998 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1999 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2000 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2001 return connector_status_connected;
2002 }
2003 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2004 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2005 return connector_status_connected;
2006 }
2007 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2008 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2009 return connector_status_connected;
2010 }
2011 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2012 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2013 return connector_status_connected; /* CTV */
2014 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2015 return connector_status_connected; /* STV */
2016 }
2017 return connector_status_disconnected;
2018}
2019
2020void
2021radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2022{
2023 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2024
2025 if (ext_encoder)
2026 /* ddc_setup on the dp bridge */
2027 atombios_external_encoder_setup(encoder, ext_encoder,
2028 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2029
2030}
2031
2032static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2033{
2034 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2035 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2036
2037 if ((radeon_encoder->active_device &
2038 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2039 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2040 ENCODER_OBJECT_ID_NONE)) {
2041 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2042 if (dig)
2043 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2044 }
2045
2046 radeon_atom_output_lock(encoder, true);
2047 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2048
2049 if (connector) {
2050 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2051
2052 /* select the clock/data port if it uses a router */
2053 if (radeon_connector->router.cd_valid)
2054 radeon_router_select_cd_port(radeon_connector);
2055
2056 /* turn eDP panel on for mode set */
2057 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2058 atombios_set_edp_panel_power(connector,
2059 ATOM_TRANSMITTER_ACTION_POWER_ON);
2060 }
2061
2062 /* this is needed for the pll/ss setup to work correctly in some cases */
2063 atombios_set_encoder_crtc_source(encoder);
2064}
2065
2066static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2067{
2068 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2069 radeon_atom_output_lock(encoder, false);
2070}
2071
2072static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2073{
2074 struct drm_device *dev = encoder->dev;
2075 struct radeon_device *rdev = dev->dev_private;
2076 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2077 struct radeon_encoder_atom_dig *dig;
2078
2079 /* check for pre-DCE3 cards with shared encoders;
2080 * can't really use the links individually, so don't disable
2081 * the encoder if it's in use by another connector
2082 */
2083 if (!ASIC_IS_DCE3(rdev)) {
2084 struct drm_encoder *other_encoder;
2085 struct radeon_encoder *other_radeon_encoder;
2086
2087 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2088 other_radeon_encoder = to_radeon_encoder(other_encoder);
2089 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2090 drm_helper_encoder_in_use(other_encoder))
2091 goto disable_done;
2092 }
2093 }
2094
2095 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2096
2097 switch (radeon_encoder->encoder_id) {
2098 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2099 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2100 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2101 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2102 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2103 break;
2104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2107 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2108 if (ASIC_IS_DCE4(rdev))
2109 /* disable the transmitter */
2110 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2111 else {
2112 /* disable the encoder and transmitter */
2113 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2114 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2115 }
2116 break;
2117 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2118 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2120 atombios_dvo_setup(encoder, ATOM_DISABLE);
2121 break;
2122 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2123 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2124 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2126 atombios_dac_setup(encoder, ATOM_DISABLE);
2127 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2128 atombios_tv_setup(encoder, ATOM_DISABLE);
2129 break;
2130 }
2131
2132disable_done:
2133 if (radeon_encoder_is_digital(encoder)) {
2134 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2135 r600_hdmi_disable(encoder);
2136 dig = radeon_encoder->enc_priv;
2137 dig->dig_encoder = -1;
2138 }
2139 radeon_encoder->active_device = 0;
2140}
2141
2142/* these are handled by the primary encoders */
2143static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2144{
2145
2146}
2147
2148static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2149{
2150
2151}
2152
2153static void
2154radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2155 struct drm_display_mode *mode,
2156 struct drm_display_mode *adjusted_mode)
2157{
2158
2159}
2160
2161static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2162{
2163
2164}
2165
2166static void
2167radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2168{
2169
2170}
2171
2172static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2173 struct drm_display_mode *mode,
2174 struct drm_display_mode *adjusted_mode)
2175{
2176 return true;
2177}
2178
2179static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2180 .dpms = radeon_atom_ext_dpms,
2181 .mode_fixup = radeon_atom_ext_mode_fixup,
2182 .prepare = radeon_atom_ext_prepare,
2183 .mode_set = radeon_atom_ext_mode_set,
2184 .commit = radeon_atom_ext_commit,
2185 .disable = radeon_atom_ext_disable,
2186 /* no detect for TMDS/LVDS yet */
2187};
2188
2189static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2190 .dpms = radeon_atom_encoder_dpms,
2191 .mode_fixup = radeon_atom_mode_fixup,
2192 .prepare = radeon_atom_encoder_prepare,
2193 .mode_set = radeon_atom_encoder_mode_set,
2194 .commit = radeon_atom_encoder_commit,
2195 .disable = radeon_atom_encoder_disable,
2196 .detect = radeon_atom_dig_detect,
2197};
2198
2199static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2200 .dpms = radeon_atom_encoder_dpms,
2201 .mode_fixup = radeon_atom_mode_fixup,
2202 .prepare = radeon_atom_encoder_prepare,
2203 .mode_set = radeon_atom_encoder_mode_set,
2204 .commit = radeon_atom_encoder_commit,
2205 .detect = radeon_atom_dac_detect,
2206};
2207
2208void radeon_enc_destroy(struct drm_encoder *encoder)
2209{
2210 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2211 kfree(radeon_encoder->enc_priv);
2212 drm_encoder_cleanup(encoder);
2213 kfree(radeon_encoder);
2214}
2215
2216static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2217 .destroy = radeon_enc_destroy,
2218};
2219
2220struct radeon_encoder_atom_dac *
2221radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2222{
2223 struct drm_device *dev = radeon_encoder->base.dev;
2224 struct radeon_device *rdev = dev->dev_private;
2225 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2226
2227 if (!dac)
2228 return NULL;
2229
2230 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2231 return dac;
2232}
2233
2234struct radeon_encoder_atom_dig *
2235radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2236{
2237 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2238 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2239
2240 if (!dig)
2241 return NULL;
2242
2243 /* coherent mode by default */
2244 dig->coherent_mode = true;
2245 dig->dig_encoder = -1;
2246
2247 if (encoder_enum == 2)
2248 dig->linkb = true;
2249 else
2250 dig->linkb = false;
2251
2252 return dig;
2253}
2254
2255void
2256radeon_add_atom_encoder(struct drm_device *dev,
2257 uint32_t encoder_enum,
2258 uint32_t supported_device,
2259 u16 caps)
2260{
2261 struct radeon_device *rdev = dev->dev_private;
2262 struct drm_encoder *encoder;
2263 struct radeon_encoder *radeon_encoder;
2264
2265 /* see if we already added it */
2266 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2267 radeon_encoder = to_radeon_encoder(encoder);
2268 if (radeon_encoder->encoder_enum == encoder_enum) {
2269 radeon_encoder->devices |= supported_device;
2270 return;
2271 }
2272
2273 }
2274
2275 /* add a new one */
2276 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2277 if (!radeon_encoder)
2278 return;
2279
2280 encoder = &radeon_encoder->base;
2281 switch (rdev->num_crtc) {
2282 case 1:
2283 encoder->possible_crtcs = 0x1;
2284 break;
2285 case 2:
2286 default:
2287 encoder->possible_crtcs = 0x3;
2288 break;
2289 case 4:
2290 encoder->possible_crtcs = 0xf;
2291 break;
2292 case 6:
2293 encoder->possible_crtcs = 0x3f;
2294 break;
2295 }
2296
2297 radeon_encoder->enc_priv = NULL;
2298
2299 radeon_encoder->encoder_enum = encoder_enum;
2300 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2301 radeon_encoder->devices = supported_device;
2302 radeon_encoder->rmx_type = RMX_OFF;
2303 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2304 radeon_encoder->is_ext_encoder = false;
2305 radeon_encoder->caps = caps;
2306
2307 switch (radeon_encoder->encoder_id) {
2308 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2309 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2310 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2311 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2312 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2313 radeon_encoder->rmx_type = RMX_FULL;
2314 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2315 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2316 } else {
2317 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2318 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2319 }
2320 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2321 break;
2322 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2323 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2324 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2325 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2326 break;
2327 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2328 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2329 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2330 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2331 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2332 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2333 break;
2334 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2336 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2337 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2338 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2339 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2340 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2341 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2342 radeon_encoder->rmx_type = RMX_FULL;
2343 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2344 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2345 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2346 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2347 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2348 } else {
2349 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2350 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2351 }
2352 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2353 break;
2354 case ENCODER_OBJECT_ID_SI170B:
2355 case ENCODER_OBJECT_ID_CH7303:
2356 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2357 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2358 case ENCODER_OBJECT_ID_TITFP513:
2359 case ENCODER_OBJECT_ID_VT1623:
2360 case ENCODER_OBJECT_ID_HDMI_SI1930:
2361 case ENCODER_OBJECT_ID_TRAVIS:
2362 case ENCODER_OBJECT_ID_NUTMEG:
2363 /* these are handled by the primary encoders */
2364 radeon_encoder->is_ext_encoder = true;
2365 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2366 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2367 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2368 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2369 else
2370 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2371 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2372 break;
2373 }
2374}
Linux kernel - Deliverables
This page took 0.141469 seconds and 5 git commands to generate.