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3f03ced8 AD |
1 | /* |
2 | * Copyright 2007-11 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "drm_crtc_helper.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon.h" | |
30 | #include "atom.h" | |
f3728734 | 31 | #include <linux/backlight.h> |
3f03ced8 AD |
32 | |
33 | extern int atom_debug; | |
34 | ||
f3728734 AD |
35 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
36 | ||
37 | static u8 | |
38 | radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) | |
39 | { | |
40 | u8 backlight_level; | |
41 | u32 bios_2_scratch; | |
42 | ||
43 | if (rdev->family >= CHIP_R600) | |
44 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
45 | else | |
46 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
47 | ||
48 | backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> | |
49 | ATOM_S2_CURRENT_BL_LEVEL_SHIFT); | |
50 | ||
51 | return backlight_level; | |
52 | } | |
53 | ||
54 | static void | |
55 | radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, | |
56 | u8 backlight_level) | |
57 | { | |
58 | u32 bios_2_scratch; | |
59 | ||
60 | if (rdev->family >= CHIP_R600) | |
61 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
62 | else | |
63 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
64 | ||
65 | bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; | |
66 | bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & | |
67 | ATOM_S2_CURRENT_BL_LEVEL_MASK); | |
68 | ||
69 | if (rdev->family >= CHIP_R600) | |
70 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
71 | else | |
72 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
73 | } | |
74 | ||
fda4b25c | 75 | void |
37e9b6a6 | 76 | atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
f3728734 AD |
77 | { |
78 | struct drm_encoder *encoder = &radeon_encoder->base; | |
79 | struct drm_device *dev = radeon_encoder->base.dev; | |
80 | struct radeon_device *rdev = dev->dev_private; | |
81 | struct radeon_encoder_atom_dig *dig; | |
82 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
83 | int index; | |
84 | ||
37e9b6a6 AD |
85 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
86 | return; | |
87 | ||
88 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && | |
89 | radeon_encoder->enc_priv) { | |
f3728734 | 90 | dig = radeon_encoder->enc_priv; |
37e9b6a6 | 91 | dig->backlight_level = level; |
f3728734 AD |
92 | radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); |
93 | ||
94 | switch (radeon_encoder->encoder_id) { | |
95 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
96 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
97 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
98 | if (dig->backlight_level == 0) { | |
99 | args.ucAction = ATOM_LCD_BLOFF; | |
100 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
101 | } else { | |
102 | args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; | |
103 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
104 | args.ucAction = ATOM_LCD_BLON; | |
105 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
106 | } | |
107 | break; | |
108 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
109 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
110 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
111 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
112 | if (dig->backlight_level == 0) | |
113 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); | |
114 | else { | |
115 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); | |
116 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); | |
117 | } | |
118 | break; | |
119 | default: | |
120 | break; | |
121 | } | |
122 | } | |
123 | } | |
124 | ||
125 | static u8 radeon_atom_bl_level(struct backlight_device *bd) | |
126 | { | |
127 | u8 level; | |
128 | ||
129 | /* Convert brightness to hardware level */ | |
130 | if (bd->props.brightness < 0) | |
131 | level = 0; | |
132 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) | |
133 | level = RADEON_MAX_BL_LEVEL; | |
134 | else | |
135 | level = bd->props.brightness; | |
136 | ||
137 | return level; | |
138 | } | |
139 | ||
140 | static int radeon_atom_backlight_update_status(struct backlight_device *bd) | |
141 | { | |
142 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); | |
143 | struct radeon_encoder *radeon_encoder = pdata->encoder; | |
144 | ||
37e9b6a6 | 145 | atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); |
f3728734 AD |
146 | |
147 | return 0; | |
148 | } | |
149 | ||
150 | static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) | |
151 | { | |
152 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); | |
153 | struct radeon_encoder *radeon_encoder = pdata->encoder; | |
154 | struct drm_device *dev = radeon_encoder->base.dev; | |
155 | struct radeon_device *rdev = dev->dev_private; | |
156 | ||
157 | return radeon_atom_get_backlight_level_from_reg(rdev); | |
158 | } | |
159 | ||
160 | static const struct backlight_ops radeon_atom_backlight_ops = { | |
161 | .get_brightness = radeon_atom_backlight_get_brightness, | |
162 | .update_status = radeon_atom_backlight_update_status, | |
163 | }; | |
164 | ||
165 | void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, | |
166 | struct drm_connector *drm_connector) | |
167 | { | |
168 | struct drm_device *dev = radeon_encoder->base.dev; | |
169 | struct radeon_device *rdev = dev->dev_private; | |
170 | struct backlight_device *bd; | |
171 | struct backlight_properties props; | |
172 | struct radeon_backlight_privdata *pdata; | |
173 | struct radeon_encoder_atom_dig *dig; | |
174 | u8 backlight_level; | |
175 | ||
176 | if (!radeon_encoder->enc_priv) | |
177 | return; | |
178 | ||
179 | if (!rdev->is_atom_bios) | |
180 | return; | |
181 | ||
182 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) | |
183 | return; | |
184 | ||
185 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); | |
186 | if (!pdata) { | |
187 | DRM_ERROR("Memory allocation failed\n"); | |
188 | goto error; | |
189 | } | |
190 | ||
191 | memset(&props, 0, sizeof(props)); | |
192 | props.max_brightness = RADEON_MAX_BL_LEVEL; | |
193 | props.type = BACKLIGHT_RAW; | |
194 | bd = backlight_device_register("radeon_bl", &drm_connector->kdev, | |
195 | pdata, &radeon_atom_backlight_ops, &props); | |
196 | if (IS_ERR(bd)) { | |
197 | DRM_ERROR("Backlight registration failed\n"); | |
198 | goto error; | |
199 | } | |
200 | ||
201 | pdata->encoder = radeon_encoder; | |
202 | ||
203 | backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); | |
204 | ||
205 | dig = radeon_encoder->enc_priv; | |
206 | dig->bl_dev = bd; | |
207 | ||
208 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); | |
209 | bd->props.power = FB_BLANK_UNBLANK; | |
210 | backlight_update_status(bd); | |
211 | ||
212 | DRM_INFO("radeon atom DIG backlight initialized\n"); | |
213 | ||
214 | return; | |
215 | ||
216 | error: | |
217 | kfree(pdata); | |
218 | return; | |
219 | } | |
220 | ||
221 | static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) | |
222 | { | |
223 | struct drm_device *dev = radeon_encoder->base.dev; | |
224 | struct radeon_device *rdev = dev->dev_private; | |
225 | struct backlight_device *bd = NULL; | |
226 | struct radeon_encoder_atom_dig *dig; | |
227 | ||
228 | if (!radeon_encoder->enc_priv) | |
229 | return; | |
230 | ||
231 | if (!rdev->is_atom_bios) | |
232 | return; | |
233 | ||
234 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) | |
235 | return; | |
236 | ||
237 | dig = radeon_encoder->enc_priv; | |
238 | bd = dig->bl_dev; | |
239 | dig->bl_dev = NULL; | |
240 | ||
241 | if (bd) { | |
242 | struct radeon_legacy_backlight_privdata *pdata; | |
243 | ||
244 | pdata = bl_get_data(bd); | |
245 | backlight_device_unregister(bd); | |
246 | kfree(pdata); | |
247 | ||
248 | DRM_INFO("radeon atom LVDS backlight unloaded\n"); | |
249 | } | |
250 | } | |
251 | ||
252 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
253 | ||
254 | void radeon_atom_backlight_init(struct radeon_encoder *encoder) | |
255 | { | |
256 | } | |
257 | ||
258 | static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) | |
259 | { | |
260 | } | |
261 | ||
262 | #endif | |
263 | ||
3f03ced8 AD |
264 | /* evil but including atombios.h is much worse */ |
265 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | |
266 | struct drm_display_mode *mode); | |
267 | ||
268 | ||
269 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) | |
270 | { | |
271 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
272 | switch (radeon_encoder->encoder_id) { | |
273 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
274 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
275 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
276 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
277 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
278 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
279 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
280 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
281 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
282 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
283 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
284 | return true; | |
285 | default: | |
286 | return false; | |
287 | } | |
288 | } | |
289 | ||
3f03ced8 | 290 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 291 | const struct drm_display_mode *mode, |
3f03ced8 AD |
292 | struct drm_display_mode *adjusted_mode) |
293 | { | |
294 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
295 | struct drm_device *dev = encoder->dev; | |
296 | struct radeon_device *rdev = dev->dev_private; | |
297 | ||
298 | /* set the active encoder to connector routing */ | |
299 | radeon_encoder_set_active_device(encoder); | |
300 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
301 | ||
302 | /* hw bug */ | |
303 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) | |
304 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | |
305 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | |
306 | ||
307 | /* get the native mode for LVDS */ | |
308 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) | |
309 | radeon_panel_mode_fixup(encoder, adjusted_mode); | |
310 | ||
311 | /* get the native mode for TV */ | |
312 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { | |
313 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; | |
314 | if (tv_dac) { | |
315 | if (tv_dac->tv_std == TV_STD_NTSC || | |
316 | tv_dac->tv_std == TV_STD_NTSC_J || | |
317 | tv_dac->tv_std == TV_STD_PAL_M) | |
318 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | |
319 | else | |
320 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | |
321 | } | |
322 | } | |
323 | ||
324 | if (ASIC_IS_DCE3(rdev) && | |
325 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || | |
326 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { | |
327 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
328 | radeon_dp_set_link_config(connector, mode); | |
329 | } | |
330 | ||
331 | return true; | |
332 | } | |
333 | ||
334 | static void | |
335 | atombios_dac_setup(struct drm_encoder *encoder, int action) | |
336 | { | |
337 | struct drm_device *dev = encoder->dev; | |
338 | struct radeon_device *rdev = dev->dev_private; | |
339 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
340 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; | |
341 | int index = 0; | |
342 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; | |
343 | ||
344 | memset(&args, 0, sizeof(args)); | |
345 | ||
346 | switch (radeon_encoder->encoder_id) { | |
347 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
348 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
349 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); | |
350 | break; | |
351 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
352 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
353 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); | |
354 | break; | |
355 | } | |
356 | ||
357 | args.ucAction = action; | |
358 | ||
359 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) | |
360 | args.ucDacStandard = ATOM_DAC1_PS2; | |
361 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
362 | args.ucDacStandard = ATOM_DAC1_CV; | |
363 | else { | |
364 | switch (dac_info->tv_std) { | |
365 | case TV_STD_PAL: | |
366 | case TV_STD_PAL_M: | |
367 | case TV_STD_SCART_PAL: | |
368 | case TV_STD_SECAM: | |
369 | case TV_STD_PAL_CN: | |
370 | args.ucDacStandard = ATOM_DAC1_PAL; | |
371 | break; | |
372 | case TV_STD_NTSC: | |
373 | case TV_STD_NTSC_J: | |
374 | case TV_STD_PAL_60: | |
375 | default: | |
376 | args.ucDacStandard = ATOM_DAC1_NTSC; | |
377 | break; | |
378 | } | |
379 | } | |
380 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
381 | ||
382 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
383 | ||
384 | } | |
385 | ||
386 | static void | |
387 | atombios_tv_setup(struct drm_encoder *encoder, int action) | |
388 | { | |
389 | struct drm_device *dev = encoder->dev; | |
390 | struct radeon_device *rdev = dev->dev_private; | |
391 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
392 | TV_ENCODER_CONTROL_PS_ALLOCATION args; | |
393 | int index = 0; | |
394 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; | |
395 | ||
396 | memset(&args, 0, sizeof(args)); | |
397 | ||
398 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); | |
399 | ||
400 | args.sTVEncoder.ucAction = action; | |
401 | ||
402 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
403 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; | |
404 | else { | |
405 | switch (dac_info->tv_std) { | |
406 | case TV_STD_NTSC: | |
407 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
408 | break; | |
409 | case TV_STD_PAL: | |
410 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; | |
411 | break; | |
412 | case TV_STD_PAL_M: | |
413 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; | |
414 | break; | |
415 | case TV_STD_PAL_60: | |
416 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; | |
417 | break; | |
418 | case TV_STD_NTSC_J: | |
419 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; | |
420 | break; | |
421 | case TV_STD_SCART_PAL: | |
422 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ | |
423 | break; | |
424 | case TV_STD_SECAM: | |
425 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; | |
426 | break; | |
427 | case TV_STD_PAL_CN: | |
428 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; | |
429 | break; | |
430 | default: | |
431 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
432 | break; | |
433 | } | |
434 | } | |
435 | ||
436 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
437 | ||
438 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
439 | ||
440 | } | |
441 | ||
442 | union dvo_encoder_control { | |
443 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; | |
444 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; | |
445 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; | |
446 | }; | |
447 | ||
448 | void | |
449 | atombios_dvo_setup(struct drm_encoder *encoder, int action) | |
450 | { | |
451 | struct drm_device *dev = encoder->dev; | |
452 | struct radeon_device *rdev = dev->dev_private; | |
453 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
454 | union dvo_encoder_control args; | |
455 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
24153dd3 | 456 | uint8_t frev, crev; |
3f03ced8 AD |
457 | |
458 | memset(&args, 0, sizeof(args)); | |
459 | ||
24153dd3 AD |
460 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
461 | return; | |
462 | ||
afceb931 AD |
463 | /* some R4xx chips have the wrong frev */ |
464 | if (rdev->family <= CHIP_RV410) | |
465 | frev = 1; | |
466 | ||
24153dd3 AD |
467 | switch (frev) { |
468 | case 1: | |
469 | switch (crev) { | |
470 | case 1: | |
471 | /* R4xx, R5xx */ | |
472 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; | |
473 | ||
9aa59993 | 474 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
24153dd3 AD |
475 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
476 | ||
477 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
478 | break; | |
479 | case 2: | |
480 | /* RS600/690/740 */ | |
481 | args.dvo.sDVOEncoder.ucAction = action; | |
482 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
483 | /* DFP1, CRT1, TV1 depending on the type of port */ | |
484 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; | |
485 | ||
9aa59993 | 486 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
24153dd3 AD |
487 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
488 | break; | |
489 | case 3: | |
490 | /* R6xx */ | |
491 | args.dvo_v3.ucAction = action; | |
492 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
493 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ | |
494 | break; | |
495 | default: | |
496 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
497 | break; | |
498 | } | |
499 | break; | |
500 | default: | |
501 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
502 | break; | |
3f03ced8 AD |
503 | } |
504 | ||
505 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
506 | } | |
507 | ||
508 | union lvds_encoder_control { | |
509 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; | |
510 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; | |
511 | }; | |
512 | ||
513 | void | |
514 | atombios_digital_setup(struct drm_encoder *encoder, int action) | |
515 | { | |
516 | struct drm_device *dev = encoder->dev; | |
517 | struct radeon_device *rdev = dev->dev_private; | |
518 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
519 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
520 | union lvds_encoder_control args; | |
521 | int index = 0; | |
522 | int hdmi_detected = 0; | |
523 | uint8_t frev, crev; | |
524 | ||
525 | if (!dig) | |
526 | return; | |
527 | ||
528 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) | |
529 | hdmi_detected = 1; | |
530 | ||
531 | memset(&args, 0, sizeof(args)); | |
532 | ||
533 | switch (radeon_encoder->encoder_id) { | |
534 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
535 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
536 | break; | |
537 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
538 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
539 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); | |
540 | break; | |
541 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
542 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
543 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
544 | else | |
545 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); | |
546 | break; | |
547 | } | |
548 | ||
549 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
550 | return; | |
551 | ||
552 | switch (frev) { | |
553 | case 1: | |
554 | case 2: | |
555 | switch (crev) { | |
556 | case 1: | |
557 | args.v1.ucMisc = 0; | |
558 | args.v1.ucAction = action; | |
559 | if (hdmi_detected) | |
560 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; | |
561 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
562 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
563 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) | |
564 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
565 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) | |
566 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
567 | } else { | |
568 | if (dig->linkb) | |
569 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
9aa59993 | 570 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
571 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
572 | /*if (pScrn->rgbBits == 8) */ | |
573 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
574 | } | |
575 | break; | |
576 | case 2: | |
577 | case 3: | |
578 | args.v2.ucMisc = 0; | |
579 | args.v2.ucAction = action; | |
580 | if (crev == 3) { | |
581 | if (dig->coherent_mode) | |
582 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | |
583 | } | |
584 | if (hdmi_detected) | |
585 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; | |
586 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
587 | args.v2.ucTruncate = 0; | |
588 | args.v2.ucSpatial = 0; | |
589 | args.v2.ucTemporal = 0; | |
590 | args.v2.ucFRC = 0; | |
591 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
592 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) | |
593 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
594 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { | |
595 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; | |
596 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) | |
597 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; | |
598 | } | |
599 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { | |
600 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; | |
601 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) | |
602 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; | |
603 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) | |
604 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; | |
605 | } | |
606 | } else { | |
607 | if (dig->linkb) | |
608 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | |
9aa59993 | 609 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
610 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
611 | } | |
612 | break; | |
613 | default: | |
614 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
615 | break; | |
616 | } | |
617 | break; | |
618 | default: | |
619 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
620 | break; | |
621 | } | |
622 | ||
623 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
624 | } | |
625 | ||
626 | int | |
627 | atombios_get_encoder_mode(struct drm_encoder *encoder) | |
628 | { | |
629 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3f03ced8 AD |
630 | struct drm_connector *connector; |
631 | struct radeon_connector *radeon_connector; | |
632 | struct radeon_connector_atom_dig *dig_connector; | |
633 | ||
634 | /* dp bridges are always DP */ | |
635 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) | |
636 | return ATOM_ENCODER_MODE_DP; | |
637 | ||
638 | /* DVO is always DVO */ | |
639 | if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) | |
640 | return ATOM_ENCODER_MODE_DVO; | |
641 | ||
642 | connector = radeon_get_connector_for_encoder(encoder); | |
643 | /* if we don't have an active device yet, just use one of | |
644 | * the connectors tied to the encoder. | |
645 | */ | |
646 | if (!connector) | |
647 | connector = radeon_get_connector_for_encoder_init(encoder); | |
648 | radeon_connector = to_radeon_connector(connector); | |
649 | ||
650 | switch (connector->connector_type) { | |
651 | case DRM_MODE_CONNECTOR_DVII: | |
652 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ | |
27d9cc84 | 653 | if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
f92e70ca RM |
654 | radeon_audio) |
655 | return ATOM_ENCODER_MODE_HDMI; | |
656 | else if (radeon_connector->use_digital) | |
3f03ced8 AD |
657 | return ATOM_ENCODER_MODE_DVI; |
658 | else | |
659 | return ATOM_ENCODER_MODE_CRT; | |
660 | break; | |
661 | case DRM_MODE_CONNECTOR_DVID: | |
662 | case DRM_MODE_CONNECTOR_HDMIA: | |
663 | default: | |
27d9cc84 | 664 | if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
f92e70ca RM |
665 | radeon_audio) |
666 | return ATOM_ENCODER_MODE_HDMI; | |
667 | else | |
3f03ced8 AD |
668 | return ATOM_ENCODER_MODE_DVI; |
669 | break; | |
670 | case DRM_MODE_CONNECTOR_LVDS: | |
671 | return ATOM_ENCODER_MODE_LVDS; | |
672 | break; | |
673 | case DRM_MODE_CONNECTOR_DisplayPort: | |
674 | dig_connector = radeon_connector->con_priv; | |
675 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
676 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | |
677 | return ATOM_ENCODER_MODE_DP; | |
27d9cc84 | 678 | else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
f92e70ca RM |
679 | radeon_audio) |
680 | return ATOM_ENCODER_MODE_HDMI; | |
681 | else | |
3f03ced8 AD |
682 | return ATOM_ENCODER_MODE_DVI; |
683 | break; | |
684 | case DRM_MODE_CONNECTOR_eDP: | |
685 | return ATOM_ENCODER_MODE_DP; | |
686 | case DRM_MODE_CONNECTOR_DVIA: | |
687 | case DRM_MODE_CONNECTOR_VGA: | |
688 | return ATOM_ENCODER_MODE_CRT; | |
689 | break; | |
690 | case DRM_MODE_CONNECTOR_Composite: | |
691 | case DRM_MODE_CONNECTOR_SVIDEO: | |
692 | case DRM_MODE_CONNECTOR_9PinDIN: | |
693 | /* fix me */ | |
694 | return ATOM_ENCODER_MODE_TV; | |
695 | /*return ATOM_ENCODER_MODE_CV;*/ | |
696 | break; | |
697 | } | |
698 | } | |
699 | ||
700 | /* | |
701 | * DIG Encoder/Transmitter Setup | |
702 | * | |
703 | * DCE 3.0/3.1 | |
704 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. | |
705 | * Supports up to 3 digital outputs | |
706 | * - 2 DIG encoder blocks. | |
707 | * DIG1 can drive UNIPHY link A or link B | |
708 | * DIG2 can drive UNIPHY link B or LVTMA | |
709 | * | |
710 | * DCE 3.2 | |
711 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). | |
712 | * Supports up to 5 digital outputs | |
713 | * - 2 DIG encoder blocks. | |
714 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
715 | * | |
2d415869 | 716 | * DCE 4.0/5.0/6.0 |
3f03ced8 AD |
717 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
718 | * Supports up to 6 digital outputs | |
719 | * - 6 DIG encoder blocks. | |
720 | * - DIG to PHY mapping is hardcoded | |
721 | * DIG1 drives UNIPHY0 link A, A+B | |
722 | * DIG2 drives UNIPHY0 link B | |
723 | * DIG3 drives UNIPHY1 link A, A+B | |
724 | * DIG4 drives UNIPHY1 link B | |
725 | * DIG5 drives UNIPHY2 link A, A+B | |
726 | * DIG6 drives UNIPHY2 link B | |
727 | * | |
728 | * DCE 4.1 | |
729 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). | |
730 | * Supports up to 6 digital outputs | |
731 | * - 2 DIG encoder blocks. | |
2d415869 | 732 | * llano |
3f03ced8 | 733 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
2d415869 AD |
734 | * ontario |
735 | * DIG1 drives UNIPHY0/1/2 link A | |
736 | * DIG2 drives UNIPHY0/1/2 link B | |
3f03ced8 AD |
737 | * |
738 | * Routing | |
739 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) | |
740 | * Examples: | |
741 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI | |
742 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP | |
743 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS | |
744 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI | |
745 | */ | |
746 | ||
747 | union dig_encoder_control { | |
748 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; | |
749 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; | |
750 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; | |
751 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; | |
752 | }; | |
753 | ||
754 | void | |
755 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) | |
756 | { | |
757 | struct drm_device *dev = encoder->dev; | |
758 | struct radeon_device *rdev = dev->dev_private; | |
759 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
760 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
761 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
762 | union dig_encoder_control args; | |
763 | int index = 0; | |
764 | uint8_t frev, crev; | |
765 | int dp_clock = 0; | |
766 | int dp_lane_count = 0; | |
767 | int hpd_id = RADEON_HPD_NONE; | |
768 | int bpc = 8; | |
769 | ||
770 | if (connector) { | |
771 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
772 | struct radeon_connector_atom_dig *dig_connector = | |
773 | radeon_connector->con_priv; | |
774 | ||
775 | dp_clock = dig_connector->dp_clock; | |
776 | dp_lane_count = dig_connector->dp_lane_count; | |
777 | hpd_id = radeon_connector->hpd.hpd; | |
eccea792 | 778 | bpc = radeon_get_monitor_bpc(connector); |
3f03ced8 AD |
779 | } |
780 | ||
781 | /* no dig encoder assigned */ | |
782 | if (dig->dig_encoder == -1) | |
783 | return; | |
784 | ||
785 | memset(&args, 0, sizeof(args)); | |
786 | ||
787 | if (ASIC_IS_DCE4(rdev)) | |
788 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); | |
789 | else { | |
790 | if (dig->dig_encoder) | |
791 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
792 | else | |
793 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
794 | } | |
795 | ||
796 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
797 | return; | |
798 | ||
58cdcb8b AD |
799 | switch (frev) { |
800 | case 1: | |
801 | switch (crev) { | |
802 | case 1: | |
803 | args.v1.ucAction = action; | |
804 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
805 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) | |
806 | args.v3.ucPanelMode = panel_mode; | |
807 | else | |
808 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
809 | ||
810 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | |
811 | args.v1.ucLaneNum = dp_lane_count; | |
9aa59993 | 812 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
58cdcb8b AD |
813 | args.v1.ucLaneNum = 8; |
814 | else | |
815 | args.v1.ucLaneNum = 4; | |
816 | ||
817 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) | |
818 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
819 | switch (radeon_encoder->encoder_id) { | |
820 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
821 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; | |
822 | break; | |
823 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
824 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
825 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; | |
826 | break; | |
827 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
828 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; | |
829 | break; | |
830 | } | |
831 | if (dig->linkb) | |
832 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; | |
833 | else | |
834 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | |
3f03ced8 | 835 | break; |
58cdcb8b AD |
836 | case 2: |
837 | case 3: | |
838 | args.v3.ucAction = action; | |
839 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
840 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) | |
841 | args.v3.ucPanelMode = panel_mode; | |
842 | else | |
843 | args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
844 | ||
845 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | |
846 | args.v3.ucLaneNum = dp_lane_count; | |
9aa59993 | 847 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
58cdcb8b AD |
848 | args.v3.ucLaneNum = 8; |
849 | else | |
850 | args.v3.ucLaneNum = 4; | |
851 | ||
852 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) | |
853 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | |
854 | args.v3.acConfig.ucDigSel = dig->dig_encoder; | |
855 | switch (bpc) { | |
856 | case 0: | |
857 | args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; | |
858 | break; | |
859 | case 6: | |
860 | args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; | |
861 | break; | |
862 | case 8: | |
863 | default: | |
864 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
865 | break; | |
866 | case 10: | |
867 | args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; | |
868 | break; | |
869 | case 12: | |
870 | args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; | |
871 | break; | |
872 | case 16: | |
873 | args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; | |
874 | break; | |
875 | } | |
3f03ced8 | 876 | break; |
58cdcb8b AD |
877 | case 4: |
878 | args.v4.ucAction = action; | |
879 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
880 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) | |
881 | args.v4.ucPanelMode = panel_mode; | |
882 | else | |
883 | args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
884 | ||
885 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) | |
886 | args.v4.ucLaneNum = dp_lane_count; | |
9aa59993 | 887 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
58cdcb8b AD |
888 | args.v4.ucLaneNum = 8; |
889 | else | |
890 | args.v4.ucLaneNum = 4; | |
891 | ||
892 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { | |
893 | if (dp_clock == 270000) | |
894 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; | |
895 | else if (dp_clock == 540000) | |
896 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; | |
897 | } | |
898 | args.v4.acConfig.ucDigSel = dig->dig_encoder; | |
899 | switch (bpc) { | |
900 | case 0: | |
901 | args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; | |
902 | break; | |
903 | case 6: | |
904 | args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; | |
905 | break; | |
906 | case 8: | |
907 | default: | |
908 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
909 | break; | |
910 | case 10: | |
911 | args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; | |
912 | break; | |
913 | case 12: | |
914 | args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; | |
915 | break; | |
916 | case 16: | |
917 | args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; | |
918 | break; | |
919 | } | |
920 | if (hpd_id == RADEON_HPD_NONE) | |
921 | args.v4.ucHPD_ID = 0; | |
922 | else | |
923 | args.v4.ucHPD_ID = hpd_id + 1; | |
3f03ced8 | 924 | break; |
3f03ced8 | 925 | default: |
58cdcb8b | 926 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
3f03ced8 AD |
927 | break; |
928 | } | |
58cdcb8b AD |
929 | break; |
930 | default: | |
931 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
932 | break; | |
3f03ced8 AD |
933 | } |
934 | ||
935 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
936 | ||
937 | } | |
938 | ||
939 | union dig_transmitter_control { | |
940 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | |
941 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | |
942 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; | |
943 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; | |
47aef7a8 | 944 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; |
3f03ced8 AD |
945 | }; |
946 | ||
947 | void | |
948 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) | |
949 | { | |
950 | struct drm_device *dev = encoder->dev; | |
951 | struct radeon_device *rdev = dev->dev_private; | |
952 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
953 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
954 | struct drm_connector *connector; | |
955 | union dig_transmitter_control args; | |
956 | int index = 0; | |
957 | uint8_t frev, crev; | |
958 | bool is_dp = false; | |
959 | int pll_id = 0; | |
960 | int dp_clock = 0; | |
961 | int dp_lane_count = 0; | |
962 | int connector_object_id = 0; | |
963 | int igp_lane_info = 0; | |
964 | int dig_encoder = dig->dig_encoder; | |
47aef7a8 | 965 | int hpd_id = RADEON_HPD_NONE; |
3f03ced8 AD |
966 | |
967 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
968 | connector = radeon_get_connector_for_encoder_init(encoder); | |
969 | /* just needed to avoid bailing in the encoder check. the encoder | |
970 | * isn't used for init | |
971 | */ | |
972 | dig_encoder = 0; | |
973 | } else | |
974 | connector = radeon_get_connector_for_encoder(encoder); | |
975 | ||
976 | if (connector) { | |
977 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
978 | struct radeon_connector_atom_dig *dig_connector = | |
979 | radeon_connector->con_priv; | |
980 | ||
47aef7a8 | 981 | hpd_id = radeon_connector->hpd.hpd; |
3f03ced8 AD |
982 | dp_clock = dig_connector->dp_clock; |
983 | dp_lane_count = dig_connector->dp_lane_count; | |
984 | connector_object_id = | |
985 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
986 | igp_lane_info = dig_connector->igp_lane_info; | |
987 | } | |
988 | ||
a3b08294 AD |
989 | if (encoder->crtc) { |
990 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
991 | pll_id = radeon_crtc->pll_id; | |
992 | } | |
993 | ||
3f03ced8 AD |
994 | /* no dig encoder assigned */ |
995 | if (dig_encoder == -1) | |
996 | return; | |
997 | ||
998 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) | |
999 | is_dp = true; | |
1000 | ||
1001 | memset(&args, 0, sizeof(args)); | |
1002 | ||
1003 | switch (radeon_encoder->encoder_id) { | |
1004 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1005 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1006 | break; | |
1007 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1008 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1009 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1010 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); | |
1011 | break; | |
1012 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1013 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); | |
1014 | break; | |
1015 | } | |
1016 | ||
1017 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1018 | return; | |
1019 | ||
a3b08294 AD |
1020 | switch (frev) { |
1021 | case 1: | |
1022 | switch (crev) { | |
1023 | case 1: | |
1024 | args.v1.ucAction = action; | |
1025 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1026 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); | |
1027 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1028 | args.v1.asMode.ucLaneSel = lane_num; | |
1029 | args.v1.asMode.ucLaneSet = lane_set; | |
1030 | } else { | |
1031 | if (is_dp) | |
1032 | args.v1.usPixelClock = | |
1033 | cpu_to_le16(dp_clock / 10); | |
9aa59993 | 1034 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1035 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1036 | else | |
1037 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1038 | } | |
3f03ced8 | 1039 | |
a3b08294 | 1040 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
3f03ced8 | 1041 | |
a3b08294 AD |
1042 | if (dig_encoder) |
1043 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; | |
1044 | else | |
1045 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; | |
1046 | ||
1047 | if ((rdev->flags & RADEON_IS_IGP) && | |
1048 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | |
9aa59993 AD |
1049 | if (is_dp || |
1050 | !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { | |
a3b08294 AD |
1051 | if (igp_lane_info & 0x1) |
1052 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | |
1053 | else if (igp_lane_info & 0x2) | |
1054 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; | |
1055 | else if (igp_lane_info & 0x4) | |
1056 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; | |
1057 | else if (igp_lane_info & 0x8) | |
1058 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; | |
1059 | } else { | |
1060 | if (igp_lane_info & 0x3) | |
1061 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; | |
1062 | else if (igp_lane_info & 0xc) | |
1063 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | if (dig->linkb) | |
1068 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; | |
1069 | else | |
1070 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | |
1071 | ||
1072 | if (is_dp) | |
1073 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
1074 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1075 | if (dig->coherent_mode) | |
1076 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
9aa59993 | 1077 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1078 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
1079 | } | |
1080 | break; | |
1081 | case 2: | |
1082 | args.v2.ucAction = action; | |
1083 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1084 | args.v2.usInitInfo = cpu_to_le16(connector_object_id); | |
1085 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1086 | args.v2.asMode.ucLaneSel = lane_num; | |
1087 | args.v2.asMode.ucLaneSet = lane_set; | |
1088 | } else { | |
1089 | if (is_dp) | |
1090 | args.v2.usPixelClock = | |
1091 | cpu_to_le16(dp_clock / 10); | |
9aa59993 | 1092 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1093 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1094 | else | |
1095 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1096 | } | |
1097 | ||
1098 | args.v2.acConfig.ucEncoderSel = dig_encoder; | |
1099 | if (dig->linkb) | |
1100 | args.v2.acConfig.ucLinkSel = 1; | |
1101 | ||
1102 | switch (radeon_encoder->encoder_id) { | |
1103 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1104 | args.v2.acConfig.ucTransmitterSel = 0; | |
1105 | break; | |
1106 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1107 | args.v2.acConfig.ucTransmitterSel = 1; | |
1108 | break; | |
1109 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1110 | args.v2.acConfig.ucTransmitterSel = 2; | |
1111 | break; | |
1112 | } | |
3f03ced8 | 1113 | |
3f03ced8 | 1114 | if (is_dp) { |
a3b08294 AD |
1115 | args.v2.acConfig.fCoherentMode = 1; |
1116 | args.v2.acConfig.fDPConnector = 1; | |
1117 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1118 | if (dig->coherent_mode) | |
1119 | args.v2.acConfig.fCoherentMode = 1; | |
9aa59993 | 1120 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1121 | args.v2.acConfig.fDualLinkConnector = 1; |
1122 | } | |
1123 | break; | |
1124 | case 3: | |
1125 | args.v3.ucAction = action; | |
1126 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1127 | args.v3.usInitInfo = cpu_to_le16(connector_object_id); | |
1128 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1129 | args.v3.asMode.ucLaneSel = lane_num; | |
1130 | args.v3.asMode.ucLaneSet = lane_set; | |
1131 | } else { | |
1132 | if (is_dp) | |
1133 | args.v3.usPixelClock = | |
1134 | cpu_to_le16(dp_clock / 10); | |
9aa59993 | 1135 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 | 1136 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
3f03ced8 | 1137 | else |
a3b08294 AD |
1138 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1139 | } | |
1140 | ||
1141 | if (is_dp) | |
1142 | args.v3.ucLaneNum = dp_lane_count; | |
9aa59993 | 1143 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1144 | args.v3.ucLaneNum = 8; |
1145 | else | |
1146 | args.v3.ucLaneNum = 4; | |
1147 | ||
1148 | if (dig->linkb) | |
1149 | args.v3.acConfig.ucLinkSel = 1; | |
1150 | if (dig_encoder & 1) | |
1151 | args.v3.acConfig.ucEncoderSel = 1; | |
1152 | ||
1153 | /* Select the PLL for the PHY | |
1154 | * DP PHY should be clocked from external src if there is | |
1155 | * one. | |
1156 | */ | |
3f03ced8 AD |
1157 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
1158 | if (is_dp && rdev->clock.dp_extclk) | |
1159 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | |
1160 | else | |
1161 | args.v3.acConfig.ucRefClkSource = pll_id; | |
3f03ced8 | 1162 | |
a3b08294 AD |
1163 | switch (radeon_encoder->encoder_id) { |
1164 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1165 | args.v3.acConfig.ucTransmitterSel = 0; | |
1166 | break; | |
1167 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1168 | args.v3.acConfig.ucTransmitterSel = 1; | |
1169 | break; | |
1170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1171 | args.v3.acConfig.ucTransmitterSel = 2; | |
1172 | break; | |
1173 | } | |
3f03ced8 | 1174 | |
a3b08294 AD |
1175 | if (is_dp) |
1176 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
1177 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1178 | if (dig->coherent_mode) | |
1179 | args.v3.acConfig.fCoherentMode = 1; | |
9aa59993 | 1180 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1181 | args.v3.acConfig.fDualLinkConnector = 1; |
1182 | } | |
3f03ced8 | 1183 | break; |
a3b08294 AD |
1184 | case 4: |
1185 | args.v4.ucAction = action; | |
1186 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
1187 | args.v4.usInitInfo = cpu_to_le16(connector_object_id); | |
1188 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | |
1189 | args.v4.asMode.ucLaneSel = lane_num; | |
1190 | args.v4.asMode.ucLaneSet = lane_set; | |
3f03ced8 | 1191 | } else { |
a3b08294 AD |
1192 | if (is_dp) |
1193 | args.v4.usPixelClock = | |
1194 | cpu_to_le16(dp_clock / 10); | |
9aa59993 | 1195 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1196 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
1197 | else | |
1198 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
3f03ced8 | 1199 | } |
3f03ced8 | 1200 | |
a3b08294 AD |
1201 | if (is_dp) |
1202 | args.v4.ucLaneNum = dp_lane_count; | |
9aa59993 | 1203 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1204 | args.v4.ucLaneNum = 8; |
1205 | else | |
1206 | args.v4.ucLaneNum = 4; | |
3f03ced8 | 1207 | |
a3b08294 AD |
1208 | if (dig->linkb) |
1209 | args.v4.acConfig.ucLinkSel = 1; | |
1210 | if (dig_encoder & 1) | |
1211 | args.v4.acConfig.ucEncoderSel = 1; | |
1212 | ||
1213 | /* Select the PLL for the PHY | |
1214 | * DP PHY should be clocked from external src if there is | |
1215 | * one. | |
1216 | */ | |
1217 | /* On DCE5 DCPLL usually generates the DP ref clock */ | |
1218 | if (is_dp) { | |
1219 | if (rdev->clock.dp_extclk) | |
1220 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; | |
1221 | else | |
1222 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; | |
1223 | } else | |
1224 | args.v4.acConfig.ucRefClkSource = pll_id; | |
1225 | ||
1226 | switch (radeon_encoder->encoder_id) { | |
1227 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1228 | args.v4.acConfig.ucTransmitterSel = 0; | |
1229 | break; | |
1230 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1231 | args.v4.acConfig.ucTransmitterSel = 1; | |
1232 | break; | |
1233 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1234 | args.v4.acConfig.ucTransmitterSel = 2; | |
1235 | break; | |
1236 | } | |
1237 | ||
1238 | if (is_dp) | |
1239 | args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
1240 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1241 | if (dig->coherent_mode) | |
1242 | args.v4.acConfig.fCoherentMode = 1; | |
9aa59993 | 1243 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
a3b08294 AD |
1244 | args.v4.acConfig.fDualLinkConnector = 1; |
1245 | } | |
1246 | break; | |
47aef7a8 AD |
1247 | case 5: |
1248 | args.v5.ucAction = action; | |
1249 | if (is_dp) | |
1250 | args.v5.usSymClock = cpu_to_le16(dp_clock / 10); | |
1251 | else | |
1252 | args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1253 | ||
1254 | switch (radeon_encoder->encoder_id) { | |
1255 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1256 | if (dig->linkb) | |
1257 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; | |
1258 | else | |
1259 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; | |
1260 | break; | |
1261 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1262 | if (dig->linkb) | |
1263 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; | |
1264 | else | |
1265 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; | |
1266 | break; | |
1267 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1268 | if (dig->linkb) | |
1269 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; | |
1270 | else | |
1271 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; | |
1272 | break; | |
1273 | } | |
1274 | if (is_dp) | |
1275 | args.v5.ucLaneNum = dp_lane_count; | |
1276 | else if (radeon_encoder->pixel_clock > 165000) | |
1277 | args.v5.ucLaneNum = 8; | |
1278 | else | |
1279 | args.v5.ucLaneNum = 4; | |
1280 | args.v5.ucConnObjId = connector_object_id; | |
1281 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); | |
1282 | ||
1283 | if (is_dp && rdev->clock.dp_extclk) | |
1284 | args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; | |
1285 | else | |
1286 | args.v5.asConfig.ucPhyClkSrcId = pll_id; | |
1287 | ||
1288 | if (is_dp) | |
1289 | args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ | |
1290 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
1291 | if (dig->coherent_mode) | |
1292 | args.v5.asConfig.ucCoherentMode = 1; | |
1293 | } | |
1294 | if (hpd_id == RADEON_HPD_NONE) | |
1295 | args.v5.asConfig.ucHPDSel = 0; | |
1296 | else | |
1297 | args.v5.asConfig.ucHPDSel = hpd_id + 1; | |
1298 | args.v5.ucDigEncoderSel = 1 << dig_encoder; | |
1299 | args.v5.ucDPLaneSet = lane_set; | |
1300 | break; | |
a3b08294 AD |
1301 | default: |
1302 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1303 | break; | |
3f03ced8 | 1304 | } |
a3b08294 AD |
1305 | break; |
1306 | default: | |
1307 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1308 | break; | |
3f03ced8 AD |
1309 | } |
1310 | ||
1311 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1312 | } | |
1313 | ||
1314 | bool | |
1315 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) | |
1316 | { | |
1317 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1318 | struct drm_device *dev = radeon_connector->base.dev; | |
1319 | struct radeon_device *rdev = dev->dev_private; | |
1320 | union dig_transmitter_control args; | |
1321 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); | |
1322 | uint8_t frev, crev; | |
1323 | ||
1324 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
1325 | goto done; | |
1326 | ||
1327 | if (!ASIC_IS_DCE4(rdev)) | |
1328 | goto done; | |
1329 | ||
1330 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && | |
1331 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) | |
1332 | goto done; | |
1333 | ||
1334 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1335 | goto done; | |
1336 | ||
1337 | memset(&args, 0, sizeof(args)); | |
1338 | ||
1339 | args.v1.ucAction = action; | |
1340 | ||
1341 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1342 | ||
1343 | /* wait for the panel to power up */ | |
1344 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { | |
1345 | int i; | |
1346 | ||
1347 | for (i = 0; i < 300; i++) { | |
1348 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) | |
1349 | return true; | |
1350 | mdelay(1); | |
1351 | } | |
1352 | return false; | |
1353 | } | |
1354 | done: | |
1355 | return true; | |
1356 | } | |
1357 | ||
1358 | union external_encoder_control { | |
1359 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; | |
1360 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; | |
1361 | }; | |
1362 | ||
1363 | static void | |
1364 | atombios_external_encoder_setup(struct drm_encoder *encoder, | |
1365 | struct drm_encoder *ext_encoder, | |
1366 | int action) | |
1367 | { | |
1368 | struct drm_device *dev = encoder->dev; | |
1369 | struct radeon_device *rdev = dev->dev_private; | |
1370 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1371 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); | |
1372 | union external_encoder_control args; | |
1373 | struct drm_connector *connector; | |
1374 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); | |
1375 | u8 frev, crev; | |
1376 | int dp_clock = 0; | |
1377 | int dp_lane_count = 0; | |
1378 | int connector_object_id = 0; | |
1379 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
1380 | int bpc = 8; | |
1381 | ||
1382 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) | |
1383 | connector = radeon_get_connector_for_encoder_init(encoder); | |
1384 | else | |
1385 | connector = radeon_get_connector_for_encoder(encoder); | |
1386 | ||
1387 | if (connector) { | |
1388 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1389 | struct radeon_connector_atom_dig *dig_connector = | |
1390 | radeon_connector->con_priv; | |
1391 | ||
1392 | dp_clock = dig_connector->dp_clock; | |
1393 | dp_lane_count = dig_connector->dp_lane_count; | |
1394 | connector_object_id = | |
1395 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
eccea792 | 1396 | bpc = radeon_get_monitor_bpc(connector); |
3f03ced8 AD |
1397 | } |
1398 | ||
1399 | memset(&args, 0, sizeof(args)); | |
1400 | ||
1401 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1402 | return; | |
1403 | ||
1404 | switch (frev) { | |
1405 | case 1: | |
1406 | /* no params on frev 1 */ | |
1407 | break; | |
1408 | case 2: | |
1409 | switch (crev) { | |
1410 | case 1: | |
1411 | case 2: | |
1412 | args.v1.sDigEncoder.ucAction = action; | |
1413 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1414 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
1415 | ||
1416 | if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { | |
1417 | if (dp_clock == 270000) | |
1418 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
1419 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; | |
9aa59993 | 1420 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
1421 | args.v1.sDigEncoder.ucLaneNum = 8; |
1422 | else | |
1423 | args.v1.sDigEncoder.ucLaneNum = 4; | |
1424 | break; | |
1425 | case 3: | |
1426 | args.v3.sExtEncoder.ucAction = action; | |
1427 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) | |
1428 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); | |
1429 | else | |
1430 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1431 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
1432 | ||
1433 | if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { | |
1434 | if (dp_clock == 270000) | |
1435 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | |
1436 | else if (dp_clock == 540000) | |
1437 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; | |
1438 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; | |
9aa59993 | 1439 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
3f03ced8 AD |
1440 | args.v3.sExtEncoder.ucLaneNum = 8; |
1441 | else | |
1442 | args.v3.sExtEncoder.ucLaneNum = 4; | |
1443 | switch (ext_enum) { | |
1444 | case GRAPH_OBJECT_ENUM_ID1: | |
1445 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; | |
1446 | break; | |
1447 | case GRAPH_OBJECT_ENUM_ID2: | |
1448 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; | |
1449 | break; | |
1450 | case GRAPH_OBJECT_ENUM_ID3: | |
1451 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; | |
1452 | break; | |
1453 | } | |
1454 | switch (bpc) { | |
1455 | case 0: | |
1456 | args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; | |
1457 | break; | |
1458 | case 6: | |
1459 | args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; | |
1460 | break; | |
1461 | case 8: | |
1462 | default: | |
1463 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
1464 | break; | |
1465 | case 10: | |
1466 | args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; | |
1467 | break; | |
1468 | case 12: | |
1469 | args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; | |
1470 | break; | |
1471 | case 16: | |
1472 | args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; | |
1473 | break; | |
1474 | } | |
1475 | break; | |
1476 | default: | |
1477 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1478 | return; | |
1479 | } | |
1480 | break; | |
1481 | default: | |
1482 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1483 | return; | |
1484 | } | |
1485 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1486 | } | |
1487 | ||
1488 | static void | |
1489 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |
1490 | { | |
1491 | struct drm_device *dev = encoder->dev; | |
1492 | struct radeon_device *rdev = dev->dev_private; | |
1493 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1494 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1495 | ENABLE_YUV_PS_ALLOCATION args; | |
1496 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); | |
1497 | uint32_t temp, reg; | |
1498 | ||
1499 | memset(&args, 0, sizeof(args)); | |
1500 | ||
1501 | if (rdev->family >= CHIP_R600) | |
1502 | reg = R600_BIOS_3_SCRATCH; | |
1503 | else | |
1504 | reg = RADEON_BIOS_3_SCRATCH; | |
1505 | ||
1506 | /* XXX: fix up scratch reg handling */ | |
1507 | temp = RREG32(reg); | |
1508 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1509 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | | |
1510 | (radeon_crtc->crtc_id << 18))); | |
1511 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1512 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); | |
1513 | else | |
1514 | WREG32(reg, 0); | |
1515 | ||
1516 | if (enable) | |
1517 | args.ucEnable = ATOM_ENABLE; | |
1518 | args.ucCRTC = radeon_crtc->crtc_id; | |
1519 | ||
1520 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1521 | ||
1522 | WREG32(reg, temp); | |
1523 | } | |
1524 | ||
1525 | static void | |
1526 | radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) | |
1527 | { | |
1528 | struct drm_device *dev = encoder->dev; | |
1529 | struct radeon_device *rdev = dev->dev_private; | |
1530 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1531 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | |
1532 | int index = 0; | |
1533 | ||
1534 | memset(&args, 0, sizeof(args)); | |
1535 | ||
1536 | switch (radeon_encoder->encoder_id) { | |
1537 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1538 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1539 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); | |
1540 | break; | |
1541 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1542 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1543 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1544 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1545 | break; | |
1546 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1547 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1548 | break; | |
1549 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1550 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1551 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1552 | else | |
1553 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); | |
1554 | break; | |
1555 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1556 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1557 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1558 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | |
1559 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1560 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | |
1561 | else | |
1562 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | |
1563 | break; | |
1564 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1565 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1566 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1567 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | |
1568 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1569 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | |
1570 | else | |
1571 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | |
1572 | break; | |
1573 | default: | |
1574 | return; | |
1575 | } | |
1576 | ||
1577 | switch (mode) { | |
1578 | case DRM_MODE_DPMS_ON: | |
1579 | args.ucAction = ATOM_ENABLE; | |
1580 | /* workaround for DVOOutputControl on some RS690 systems */ | |
1581 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { | |
1582 | u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); | |
1583 | WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); | |
1584 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1585 | WREG32(RADEON_BIOS_3_SCRATCH, reg); | |
1586 | } else | |
1587 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1588 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1589 | args.ucAction = ATOM_LCD_BLON; | |
1590 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1591 | } | |
1592 | break; | |
1593 | case DRM_MODE_DPMS_STANDBY: | |
1594 | case DRM_MODE_DPMS_SUSPEND: | |
1595 | case DRM_MODE_DPMS_OFF: | |
1596 | args.ucAction = ATOM_DISABLE; | |
1597 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1598 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1599 | args.ucAction = ATOM_LCD_BLOFF; | |
1600 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1601 | } | |
1602 | break; | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | static void | |
1607 | radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |
1608 | { | |
1609 | struct drm_device *dev = encoder->dev; | |
1610 | struct radeon_device *rdev = dev->dev_private; | |
1611 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
8d1af57a AD |
1612 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
1613 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
3f03ced8 AD |
1614 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1615 | struct radeon_connector *radeon_connector = NULL; | |
1616 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; | |
1617 | ||
1618 | if (connector) { | |
1619 | radeon_connector = to_radeon_connector(connector); | |
1620 | radeon_dig_connector = radeon_connector->con_priv; | |
1621 | } | |
1622 | ||
1623 | switch (mode) { | |
1624 | case DRM_MODE_DPMS_ON: | |
8d1af57a AD |
1625 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1626 | if (!connector) | |
1627 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; | |
1628 | else | |
1629 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); | |
1630 | ||
1631 | /* setup and enable the encoder */ | |
1632 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | |
1633 | atombios_dig_encoder_setup(encoder, | |
1634 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, | |
1635 | dig->panel_mode); | |
1636 | if (ext_encoder) { | |
1637 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) | |
1638 | atombios_external_encoder_setup(encoder, ext_encoder, | |
1639 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); | |
fcedac67 | 1640 | } |
3f03ced8 | 1641 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
8d1af57a AD |
1642 | } else if (ASIC_IS_DCE4(rdev)) { |
1643 | /* setup and enable the encoder */ | |
1644 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); | |
1645 | /* enable the transmitter */ | |
1646 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
3f03ced8 | 1647 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
8d1af57a AD |
1648 | } else { |
1649 | /* setup and enable the encoder and transmitter */ | |
1650 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); | |
1651 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | |
1652 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1653 | /* some early dce3.2 boards have a bug in their transmitter control table */ | |
1654 | if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730)) | |
1655 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | |
fcedac67 | 1656 | } |
3f03ced8 AD |
1657 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1658 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | |
1659 | atombios_set_edp_panel_power(connector, | |
1660 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
1661 | radeon_dig_connector->edp_on = true; | |
1662 | } | |
3f03ced8 AD |
1663 | radeon_dp_link_train(encoder, connector); |
1664 | if (ASIC_IS_DCE4(rdev)) | |
1665 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); | |
1666 | } | |
1667 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1668 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); | |
1669 | break; | |
1670 | case DRM_MODE_DPMS_STANDBY: | |
1671 | case DRM_MODE_DPMS_SUSPEND: | |
1672 | case DRM_MODE_DPMS_OFF: | |
8d1af57a AD |
1673 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
1674 | /* disable the transmitter */ | |
3a47824d | 1675 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
8d1af57a AD |
1676 | } else if (ASIC_IS_DCE4(rdev)) { |
1677 | /* disable the transmitter */ | |
1678 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | |
1679 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1680 | } else { | |
1681 | /* disable the encoder and transmitter */ | |
3a47824d | 1682 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
8d1af57a AD |
1683 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
1684 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); | |
1685 | } | |
3f03ced8 AD |
1686 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
1687 | if (ASIC_IS_DCE4(rdev)) | |
1688 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); | |
1689 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | |
1690 | atombios_set_edp_panel_power(connector, | |
1691 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1692 | radeon_dig_connector->edp_on = false; | |
1693 | } | |
1694 | } | |
1695 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1696 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); | |
1697 | break; | |
1698 | } | |
1699 | } | |
1700 | ||
1701 | static void | |
1702 | radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, | |
1703 | struct drm_encoder *ext_encoder, | |
1704 | int mode) | |
1705 | { | |
1706 | struct drm_device *dev = encoder->dev; | |
1707 | struct radeon_device *rdev = dev->dev_private; | |
1708 | ||
1709 | switch (mode) { | |
1710 | case DRM_MODE_DPMS_ON: | |
1711 | default: | |
1d3949c4 | 1712 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { |
3f03ced8 AD |
1713 | atombios_external_encoder_setup(encoder, ext_encoder, |
1714 | EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); | |
1715 | atombios_external_encoder_setup(encoder, ext_encoder, | |
1716 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); | |
1717 | } else | |
1718 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); | |
1719 | break; | |
1720 | case DRM_MODE_DPMS_STANDBY: | |
1721 | case DRM_MODE_DPMS_SUSPEND: | |
1722 | case DRM_MODE_DPMS_OFF: | |
1d3949c4 | 1723 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { |
3f03ced8 AD |
1724 | atombios_external_encoder_setup(encoder, ext_encoder, |
1725 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); | |
1726 | atombios_external_encoder_setup(encoder, ext_encoder, | |
1727 | EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); | |
1728 | } else | |
1729 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); | |
1730 | break; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | static void | |
1735 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |
1736 | { | |
1737 | struct drm_device *dev = encoder->dev; | |
1738 | struct radeon_device *rdev = dev->dev_private; | |
1739 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1740 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
1741 | ||
1742 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", | |
1743 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | |
1744 | radeon_encoder->active_device); | |
1745 | switch (radeon_encoder->encoder_id) { | |
1746 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1747 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1748 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1749 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1750 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1751 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1752 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1753 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1754 | radeon_atom_encoder_dpms_avivo(encoder, mode); | |
1755 | break; | |
1756 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1757 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1758 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1759 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1760 | radeon_atom_encoder_dpms_dig(encoder, mode); | |
1761 | break; | |
1762 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1763 | if (ASIC_IS_DCE5(rdev)) { | |
1764 | switch (mode) { | |
1765 | case DRM_MODE_DPMS_ON: | |
1766 | atombios_dvo_setup(encoder, ATOM_ENABLE); | |
1767 | break; | |
1768 | case DRM_MODE_DPMS_STANDBY: | |
1769 | case DRM_MODE_DPMS_SUSPEND: | |
1770 | case DRM_MODE_DPMS_OFF: | |
1771 | atombios_dvo_setup(encoder, ATOM_DISABLE); | |
1772 | break; | |
1773 | } | |
1774 | } else if (ASIC_IS_DCE3(rdev)) | |
1775 | radeon_atom_encoder_dpms_dig(encoder, mode); | |
1776 | else | |
1777 | radeon_atom_encoder_dpms_avivo(encoder, mode); | |
1778 | break; | |
1779 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1780 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1781 | if (ASIC_IS_DCE5(rdev)) { | |
1782 | switch (mode) { | |
1783 | case DRM_MODE_DPMS_ON: | |
1784 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
1785 | break; | |
1786 | case DRM_MODE_DPMS_STANDBY: | |
1787 | case DRM_MODE_DPMS_SUSPEND: | |
1788 | case DRM_MODE_DPMS_OFF: | |
1789 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
1790 | break; | |
1791 | } | |
1792 | } else | |
1793 | radeon_atom_encoder_dpms_avivo(encoder, mode); | |
1794 | break; | |
1795 | default: | |
1796 | return; | |
1797 | } | |
1798 | ||
1799 | if (ext_encoder) | |
1800 | radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); | |
1801 | ||
1802 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); | |
1803 | ||
1804 | } | |
1805 | ||
1806 | union crtc_source_param { | |
1807 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; | |
1808 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; | |
1809 | }; | |
1810 | ||
1811 | static void | |
1812 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) | |
1813 | { | |
1814 | struct drm_device *dev = encoder->dev; | |
1815 | struct radeon_device *rdev = dev->dev_private; | |
1816 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1817 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1818 | union crtc_source_param args; | |
1819 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); | |
1820 | uint8_t frev, crev; | |
1821 | struct radeon_encoder_atom_dig *dig; | |
1822 | ||
1823 | memset(&args, 0, sizeof(args)); | |
1824 | ||
1825 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1826 | return; | |
1827 | ||
1828 | switch (frev) { | |
1829 | case 1: | |
1830 | switch (crev) { | |
1831 | case 1: | |
1832 | default: | |
1833 | if (ASIC_IS_AVIVO(rdev)) | |
1834 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1835 | else { | |
1836 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { | |
1837 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1838 | } else { | |
1839 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; | |
1840 | } | |
1841 | } | |
1842 | switch (radeon_encoder->encoder_id) { | |
1843 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1844 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1845 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; | |
1846 | break; | |
1847 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1848 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1849 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) | |
1850 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; | |
1851 | else | |
1852 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; | |
1853 | break; | |
1854 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1855 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1856 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1857 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; | |
1858 | break; | |
1859 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1860 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1861 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1862 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; | |
1863 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1864 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; | |
1865 | else | |
1866 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; | |
1867 | break; | |
1868 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1869 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1870 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1871 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; | |
1872 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1873 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; | |
1874 | else | |
1875 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; | |
1876 | break; | |
1877 | } | |
1878 | break; | |
1879 | case 2: | |
1880 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
1881 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { | |
1882 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
1883 | ||
1884 | if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) | |
1885 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; | |
1886 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) | |
1887 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; | |
1888 | else | |
1889 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
1890 | } else | |
1891 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
1892 | switch (radeon_encoder->encoder_id) { | |
1893 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1894 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1895 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1896 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1897 | dig = radeon_encoder->enc_priv; | |
1898 | switch (dig->dig_encoder) { | |
1899 | case 0: | |
1900 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; | |
1901 | break; | |
1902 | case 1: | |
1903 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1904 | break; | |
1905 | case 2: | |
1906 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; | |
1907 | break; | |
1908 | case 3: | |
1909 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; | |
1910 | break; | |
1911 | case 4: | |
1912 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; | |
1913 | break; | |
1914 | case 5: | |
1915 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; | |
1916 | break; | |
1917 | } | |
1918 | break; | |
1919 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1920 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; | |
1921 | break; | |
1922 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1923 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1924 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1925 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1926 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1927 | else | |
1928 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; | |
1929 | break; | |
1930 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1931 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1932 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1933 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1934 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; | |
1935 | else | |
1936 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; | |
1937 | break; | |
1938 | } | |
1939 | break; | |
1940 | } | |
1941 | break; | |
1942 | default: | |
1943 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1944 | return; | |
1945 | } | |
1946 | ||
1947 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1948 | ||
1949 | /* update scratch regs with new routing */ | |
1950 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | |
1951 | } | |
1952 | ||
1953 | static void | |
1954 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |
1955 | struct drm_display_mode *mode) | |
1956 | { | |
1957 | struct drm_device *dev = encoder->dev; | |
1958 | struct radeon_device *rdev = dev->dev_private; | |
1959 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1960 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1961 | ||
1962 | /* Funky macbooks */ | |
1963 | if ((dev->pdev->device == 0x71C5) && | |
1964 | (dev->pdev->subsystem_vendor == 0x106b) && | |
1965 | (dev->pdev->subsystem_device == 0x0080)) { | |
1966 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
1967 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); | |
1968 | ||
1969 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
1970 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
1971 | ||
1972 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); | |
1973 | } | |
1974 | } | |
1975 | ||
1976 | /* set scaler clears this on some chips */ | |
1977 | if (ASIC_IS_AVIVO(rdev) && | |
1978 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { | |
1979 | if (ASIC_IS_DCE4(rdev)) { | |
1980 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1981 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1982 | EVERGREEN_INTERLEAVE_EN); | |
1983 | else | |
1984 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
1985 | } else { | |
1986 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1987 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1988 | AVIVO_D1MODE_INTERLEAVE_EN); | |
1989 | else | |
1990 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
1991 | } | |
1992 | } | |
1993 | } | |
1994 | ||
1995 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) | |
1996 | { | |
1997 | struct drm_device *dev = encoder->dev; | |
1998 | struct radeon_device *rdev = dev->dev_private; | |
1999 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
2000 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2001 | struct drm_encoder *test_encoder; | |
41fa5437 | 2002 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
3f03ced8 AD |
2003 | uint32_t dig_enc_in_use = 0; |
2004 | ||
41fa5437 AD |
2005 | if (ASIC_IS_DCE6(rdev)) { |
2006 | /* DCE6 */ | |
2007 | switch (radeon_encoder->encoder_id) { | |
2008 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2009 | if (dig->linkb) | |
2010 | return 1; | |
2011 | else | |
2012 | return 0; | |
2013 | break; | |
2014 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2015 | if (dig->linkb) | |
2016 | return 3; | |
2017 | else | |
2018 | return 2; | |
2019 | break; | |
2020 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2021 | if (dig->linkb) | |
2022 | return 5; | |
2023 | else | |
2024 | return 4; | |
2025 | break; | |
2026 | } | |
2027 | } else if (ASIC_IS_DCE4(rdev)) { | |
2028 | /* DCE4/5 */ | |
2029 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { | |
3f03ced8 AD |
2030 | /* ontario follows DCE4 */ |
2031 | if (rdev->family == CHIP_PALM) { | |
2032 | if (dig->linkb) | |
2033 | return 1; | |
2034 | else | |
2035 | return 0; | |
2036 | } else | |
2037 | /* llano follows DCE3.2 */ | |
2038 | return radeon_crtc->crtc_id; | |
2039 | } else { | |
2040 | switch (radeon_encoder->encoder_id) { | |
2041 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2042 | if (dig->linkb) | |
2043 | return 1; | |
2044 | else | |
2045 | return 0; | |
2046 | break; | |
2047 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2048 | if (dig->linkb) | |
2049 | return 3; | |
2050 | else | |
2051 | return 2; | |
2052 | break; | |
2053 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2054 | if (dig->linkb) | |
2055 | return 5; | |
2056 | else | |
2057 | return 4; | |
2058 | break; | |
2059 | } | |
2060 | } | |
2061 | } | |
2062 | ||
2063 | /* on DCE32 and encoder can driver any block so just crtc id */ | |
2064 | if (ASIC_IS_DCE32(rdev)) { | |
2065 | return radeon_crtc->crtc_id; | |
2066 | } | |
2067 | ||
2068 | /* on DCE3 - LVTMA can only be driven by DIGB */ | |
2069 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
2070 | struct radeon_encoder *radeon_test_encoder; | |
2071 | ||
2072 | if (encoder == test_encoder) | |
2073 | continue; | |
2074 | ||
2075 | if (!radeon_encoder_is_digital(test_encoder)) | |
2076 | continue; | |
2077 | ||
2078 | radeon_test_encoder = to_radeon_encoder(test_encoder); | |
2079 | dig = radeon_test_encoder->enc_priv; | |
2080 | ||
2081 | if (dig->dig_encoder >= 0) | |
2082 | dig_enc_in_use |= (1 << dig->dig_encoder); | |
2083 | } | |
2084 | ||
2085 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { | |
2086 | if (dig_enc_in_use & 0x2) | |
2087 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); | |
2088 | return 1; | |
2089 | } | |
2090 | if (!(dig_enc_in_use & 1)) | |
2091 | return 0; | |
2092 | return 1; | |
2093 | } | |
2094 | ||
2095 | /* This only needs to be called once at startup */ | |
2096 | void | |
2097 | radeon_atom_encoder_init(struct radeon_device *rdev) | |
2098 | { | |
2099 | struct drm_device *dev = rdev->ddev; | |
2100 | struct drm_encoder *encoder; | |
2101 | ||
2102 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2103 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2104 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
2105 | ||
2106 | switch (radeon_encoder->encoder_id) { | |
2107 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2108 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2109 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2110 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
2111 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
2112 | break; | |
2113 | default: | |
2114 | break; | |
2115 | } | |
2116 | ||
1d3949c4 | 2117 | if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) |
3f03ced8 AD |
2118 | atombios_external_encoder_setup(encoder, ext_encoder, |
2119 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); | |
2120 | } | |
2121 | } | |
2122 | ||
2123 | static void | |
2124 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |
2125 | struct drm_display_mode *mode, | |
2126 | struct drm_display_mode *adjusted_mode) | |
2127 | { | |
2128 | struct drm_device *dev = encoder->dev; | |
2129 | struct radeon_device *rdev = dev->dev_private; | |
2130 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3f03ced8 AD |
2131 | |
2132 | radeon_encoder->pixel_clock = adjusted_mode->clock; | |
2133 | ||
8d1af57a AD |
2134 | /* need to call this here rather than in prepare() since we need some crtc info */ |
2135 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
2136 | ||
3f03ced8 AD |
2137 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
2138 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) | |
2139 | atombios_yuv_setup(encoder, true); | |
2140 | else | |
2141 | atombios_yuv_setup(encoder, false); | |
2142 | } | |
2143 | ||
2144 | switch (radeon_encoder->encoder_id) { | |
2145 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2146 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2147 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2148 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2149 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); | |
2150 | break; | |
2151 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2152 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2153 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2154 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
8d1af57a | 2155 | /* handled in dpms */ |
3f03ced8 AD |
2156 | break; |
2157 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2158 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2159 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2160 | atombios_dvo_setup(encoder, ATOM_ENABLE); | |
2161 | break; | |
2162 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
2163 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2164 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
2166 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
2167 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { | |
2168 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
2169 | atombios_tv_setup(encoder, ATOM_ENABLE); | |
2170 | else | |
2171 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
2172 | } | |
2173 | break; | |
2174 | } | |
2175 | ||
3f03ced8 AD |
2176 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
2177 | ||
2178 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { | |
2179 | r600_hdmi_enable(encoder); | |
6b53a050 RM |
2180 | if (ASIC_IS_DCE6(rdev)) |
2181 | ; /* TODO (use pointers instead of if-s?) */ | |
2182 | else if (ASIC_IS_DCE4(rdev)) | |
e55d3e6c RM |
2183 | evergreen_hdmi_setmode(encoder, adjusted_mode); |
2184 | else | |
2185 | r600_hdmi_setmode(encoder, adjusted_mode); | |
3f03ced8 AD |
2186 | } |
2187 | } | |
2188 | ||
2189 | static bool | |
2190 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
2191 | { | |
2192 | struct drm_device *dev = encoder->dev; | |
2193 | struct radeon_device *rdev = dev->dev_private; | |
2194 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2195 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2196 | ||
2197 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | | |
2198 | ATOM_DEVICE_CV_SUPPORT | | |
2199 | ATOM_DEVICE_CRT_SUPPORT)) { | |
2200 | DAC_LOAD_DETECTION_PS_ALLOCATION args; | |
2201 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); | |
2202 | uint8_t frev, crev; | |
2203 | ||
2204 | memset(&args, 0, sizeof(args)); | |
2205 | ||
2206 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
2207 | return false; | |
2208 | ||
2209 | args.sDacload.ucMisc = 0; | |
2210 | ||
2211 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || | |
2212 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) | |
2213 | args.sDacload.ucDacType = ATOM_DAC_A; | |
2214 | else | |
2215 | args.sDacload.ucDacType = ATOM_DAC_B; | |
2216 | ||
2217 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) | |
2218 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); | |
2219 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) | |
2220 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); | |
2221 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2222 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); | |
2223 | if (crev >= 3) | |
2224 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
2225 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2226 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); | |
2227 | if (crev >= 3) | |
2228 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
2229 | } | |
2230 | ||
2231 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2232 | ||
2233 | return true; | |
2234 | } else | |
2235 | return false; | |
2236 | } | |
2237 | ||
2238 | static enum drm_connector_status | |
2239 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
2240 | { | |
2241 | struct drm_device *dev = encoder->dev; | |
2242 | struct radeon_device *rdev = dev->dev_private; | |
2243 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2244 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2245 | uint32_t bios_0_scratch; | |
2246 | ||
2247 | if (!atombios_dac_load_detect(encoder, connector)) { | |
2248 | DRM_DEBUG_KMS("detect returned false \n"); | |
2249 | return connector_status_unknown; | |
2250 | } | |
2251 | ||
2252 | if (rdev->family >= CHIP_R600) | |
2253 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
2254 | else | |
2255 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
2256 | ||
2257 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); | |
2258 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2259 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) | |
2260 | return connector_status_connected; | |
2261 | } | |
2262 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2263 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) | |
2264 | return connector_status_connected; | |
2265 | } | |
2266 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2267 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) | |
2268 | return connector_status_connected; | |
2269 | } | |
2270 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2271 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) | |
2272 | return connector_status_connected; /* CTV */ | |
2273 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
2274 | return connector_status_connected; /* STV */ | |
2275 | } | |
2276 | return connector_status_disconnected; | |
2277 | } | |
2278 | ||
2279 | static enum drm_connector_status | |
2280 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
2281 | { | |
2282 | struct drm_device *dev = encoder->dev; | |
2283 | struct radeon_device *rdev = dev->dev_private; | |
2284 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2285 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2286 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
2287 | u32 bios_0_scratch; | |
2288 | ||
2289 | if (!ASIC_IS_DCE4(rdev)) | |
2290 | return connector_status_unknown; | |
2291 | ||
2292 | if (!ext_encoder) | |
2293 | return connector_status_unknown; | |
2294 | ||
2295 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) | |
2296 | return connector_status_unknown; | |
2297 | ||
2298 | /* load detect on the dp bridge */ | |
2299 | atombios_external_encoder_setup(encoder, ext_encoder, | |
2300 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); | |
2301 | ||
2302 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
2303 | ||
2304 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); | |
2305 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2306 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) | |
2307 | return connector_status_connected; | |
2308 | } | |
2309 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2310 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) | |
2311 | return connector_status_connected; | |
2312 | } | |
2313 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2314 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) | |
2315 | return connector_status_connected; | |
2316 | } | |
2317 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2318 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) | |
2319 | return connector_status_connected; /* CTV */ | |
2320 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
2321 | return connector_status_connected; /* STV */ | |
2322 | } | |
2323 | return connector_status_disconnected; | |
2324 | } | |
2325 | ||
2326 | void | |
2327 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) | |
2328 | { | |
2329 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); | |
2330 | ||
2331 | if (ext_encoder) | |
2332 | /* ddc_setup on the dp bridge */ | |
2333 | atombios_external_encoder_setup(encoder, ext_encoder, | |
2334 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); | |
2335 | ||
2336 | } | |
2337 | ||
2338 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |
2339 | { | |
cfcbd6d3 | 2340 | struct radeon_device *rdev = encoder->dev->dev_private; |
3f03ced8 AD |
2341 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2342 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
2343 | ||
2344 | if ((radeon_encoder->active_device & | |
2345 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || | |
2346 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != | |
2347 | ENCODER_OBJECT_ID_NONE)) { | |
2348 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
cfcbd6d3 | 2349 | if (dig) { |
3f03ced8 | 2350 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
cfcbd6d3 RM |
2351 | if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { |
2352 | if (rdev->family >= CHIP_R600) | |
2353 | dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; | |
2354 | else | |
2355 | /* RS600/690/740 have only 1 afmt block */ | |
2356 | dig->afmt = rdev->mode_info.afmt[0]; | |
2357 | } | |
2358 | } | |
3f03ced8 AD |
2359 | } |
2360 | ||
2361 | radeon_atom_output_lock(encoder, true); | |
3f03ced8 AD |
2362 | |
2363 | if (connector) { | |
2364 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
2365 | ||
2366 | /* select the clock/data port if it uses a router */ | |
2367 | if (radeon_connector->router.cd_valid) | |
2368 | radeon_router_select_cd_port(radeon_connector); | |
2369 | ||
2370 | /* turn eDP panel on for mode set */ | |
2371 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
2372 | atombios_set_edp_panel_power(connector, | |
2373 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
2374 | } | |
2375 | ||
2376 | /* this is needed for the pll/ss setup to work correctly in some cases */ | |
2377 | atombios_set_encoder_crtc_source(encoder); | |
2378 | } | |
2379 | ||
2380 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | |
2381 | { | |
8d1af57a | 2382 | /* need to call this here as we need the crtc set up */ |
3f03ced8 AD |
2383 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
2384 | radeon_atom_output_lock(encoder, false); | |
2385 | } | |
2386 | ||
2387 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) | |
2388 | { | |
2389 | struct drm_device *dev = encoder->dev; | |
2390 | struct radeon_device *rdev = dev->dev_private; | |
2391 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2392 | struct radeon_encoder_atom_dig *dig; | |
2393 | ||
2394 | /* check for pre-DCE3 cards with shared encoders; | |
2395 | * can't really use the links individually, so don't disable | |
2396 | * the encoder if it's in use by another connector | |
2397 | */ | |
2398 | if (!ASIC_IS_DCE3(rdev)) { | |
2399 | struct drm_encoder *other_encoder; | |
2400 | struct radeon_encoder *other_radeon_encoder; | |
2401 | ||
2402 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { | |
2403 | other_radeon_encoder = to_radeon_encoder(other_encoder); | |
2404 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && | |
2405 | drm_helper_encoder_in_use(other_encoder)) | |
2406 | goto disable_done; | |
2407 | } | |
2408 | } | |
2409 | ||
2410 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
2411 | ||
2412 | switch (radeon_encoder->encoder_id) { | |
2413 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2414 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2415 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2416 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2417 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); | |
2418 | break; | |
2419 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2420 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2421 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2422 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
8d1af57a | 2423 | /* handled in dpms */ |
3f03ced8 AD |
2424 | break; |
2425 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2426 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2427 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2428 | atombios_dvo_setup(encoder, ATOM_DISABLE); | |
2429 | break; | |
2430 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
2431 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2432 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2433 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
2434 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
2435 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
2436 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
2437 | break; | |
2438 | } | |
2439 | ||
2440 | disable_done: | |
2441 | if (radeon_encoder_is_digital(encoder)) { | |
2442 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) | |
2443 | r600_hdmi_disable(encoder); | |
2444 | dig = radeon_encoder->enc_priv; | |
2445 | dig->dig_encoder = -1; | |
2446 | } | |
2447 | radeon_encoder->active_device = 0; | |
2448 | } | |
2449 | ||
2450 | /* these are handled by the primary encoders */ | |
2451 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) | |
2452 | { | |
2453 | ||
2454 | } | |
2455 | ||
2456 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) | |
2457 | { | |
2458 | ||
2459 | } | |
2460 | ||
2461 | static void | |
2462 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, | |
2463 | struct drm_display_mode *mode, | |
2464 | struct drm_display_mode *adjusted_mode) | |
2465 | { | |
2466 | ||
2467 | } | |
2468 | ||
2469 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) | |
2470 | { | |
2471 | ||
2472 | } | |
2473 | ||
2474 | static void | |
2475 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) | |
2476 | { | |
2477 | ||
2478 | } | |
2479 | ||
2480 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 2481 | const struct drm_display_mode *mode, |
3f03ced8 AD |
2482 | struct drm_display_mode *adjusted_mode) |
2483 | { | |
2484 | return true; | |
2485 | } | |
2486 | ||
2487 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { | |
2488 | .dpms = radeon_atom_ext_dpms, | |
2489 | .mode_fixup = radeon_atom_ext_mode_fixup, | |
2490 | .prepare = radeon_atom_ext_prepare, | |
2491 | .mode_set = radeon_atom_ext_mode_set, | |
2492 | .commit = radeon_atom_ext_commit, | |
2493 | .disable = radeon_atom_ext_disable, | |
2494 | /* no detect for TMDS/LVDS yet */ | |
2495 | }; | |
2496 | ||
2497 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { | |
2498 | .dpms = radeon_atom_encoder_dpms, | |
2499 | .mode_fixup = radeon_atom_mode_fixup, | |
2500 | .prepare = radeon_atom_encoder_prepare, | |
2501 | .mode_set = radeon_atom_encoder_mode_set, | |
2502 | .commit = radeon_atom_encoder_commit, | |
2503 | .disable = radeon_atom_encoder_disable, | |
2504 | .detect = radeon_atom_dig_detect, | |
2505 | }; | |
2506 | ||
2507 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | |
2508 | .dpms = radeon_atom_encoder_dpms, | |
2509 | .mode_fixup = radeon_atom_mode_fixup, | |
2510 | .prepare = radeon_atom_encoder_prepare, | |
2511 | .mode_set = radeon_atom_encoder_mode_set, | |
2512 | .commit = radeon_atom_encoder_commit, | |
2513 | .detect = radeon_atom_dac_detect, | |
2514 | }; | |
2515 | ||
2516 | void radeon_enc_destroy(struct drm_encoder *encoder) | |
2517 | { | |
2518 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
f3728734 AD |
2519 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2520 | radeon_atom_backlight_exit(radeon_encoder); | |
3f03ced8 AD |
2521 | kfree(radeon_encoder->enc_priv); |
2522 | drm_encoder_cleanup(encoder); | |
2523 | kfree(radeon_encoder); | |
2524 | } | |
2525 | ||
2526 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { | |
2527 | .destroy = radeon_enc_destroy, | |
2528 | }; | |
2529 | ||
2530 | struct radeon_encoder_atom_dac * | |
2531 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) | |
2532 | { | |
2533 | struct drm_device *dev = radeon_encoder->base.dev; | |
2534 | struct radeon_device *rdev = dev->dev_private; | |
2535 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); | |
2536 | ||
2537 | if (!dac) | |
2538 | return NULL; | |
2539 | ||
2540 | dac->tv_std = radeon_atombios_get_tv_info(rdev); | |
2541 | return dac; | |
2542 | } | |
2543 | ||
2544 | struct radeon_encoder_atom_dig * | |
2545 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | |
2546 | { | |
2547 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
2548 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
2549 | ||
2550 | if (!dig) | |
2551 | return NULL; | |
2552 | ||
2553 | /* coherent mode by default */ | |
2554 | dig->coherent_mode = true; | |
2555 | dig->dig_encoder = -1; | |
2556 | ||
2557 | if (encoder_enum == 2) | |
2558 | dig->linkb = true; | |
2559 | else | |
2560 | dig->linkb = false; | |
2561 | ||
2562 | return dig; | |
2563 | } | |
2564 | ||
2565 | void | |
2566 | radeon_add_atom_encoder(struct drm_device *dev, | |
2567 | uint32_t encoder_enum, | |
2568 | uint32_t supported_device, | |
2569 | u16 caps) | |
2570 | { | |
2571 | struct radeon_device *rdev = dev->dev_private; | |
2572 | struct drm_encoder *encoder; | |
2573 | struct radeon_encoder *radeon_encoder; | |
2574 | ||
2575 | /* see if we already added it */ | |
2576 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2577 | radeon_encoder = to_radeon_encoder(encoder); | |
2578 | if (radeon_encoder->encoder_enum == encoder_enum) { | |
2579 | radeon_encoder->devices |= supported_device; | |
2580 | return; | |
2581 | } | |
2582 | ||
2583 | } | |
2584 | ||
2585 | /* add a new one */ | |
2586 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); | |
2587 | if (!radeon_encoder) | |
2588 | return; | |
2589 | ||
2590 | encoder = &radeon_encoder->base; | |
2591 | switch (rdev->num_crtc) { | |
2592 | case 1: | |
2593 | encoder->possible_crtcs = 0x1; | |
2594 | break; | |
2595 | case 2: | |
2596 | default: | |
2597 | encoder->possible_crtcs = 0x3; | |
2598 | break; | |
2599 | case 4: | |
2600 | encoder->possible_crtcs = 0xf; | |
2601 | break; | |
2602 | case 6: | |
2603 | encoder->possible_crtcs = 0x3f; | |
2604 | break; | |
2605 | } | |
2606 | ||
2607 | radeon_encoder->enc_priv = NULL; | |
2608 | ||
2609 | radeon_encoder->encoder_enum = encoder_enum; | |
2610 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
2611 | radeon_encoder->devices = supported_device; | |
2612 | radeon_encoder->rmx_type = RMX_OFF; | |
2613 | radeon_encoder->underscan_type = UNDERSCAN_OFF; | |
2614 | radeon_encoder->is_ext_encoder = false; | |
2615 | radeon_encoder->caps = caps; | |
2616 | ||
2617 | switch (radeon_encoder->encoder_id) { | |
2618 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2619 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2620 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2621 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2622 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
2623 | radeon_encoder->rmx_type = RMX_FULL; | |
2624 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
2625 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
2626 | } else { | |
2627 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
2628 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
2629 | } | |
2630 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
2631 | break; | |
2632 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
2633 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
2634 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); | |
2635 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); | |
2636 | break; | |
2637 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2638 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2639 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
2640 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); | |
2641 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); | |
2642 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); | |
2643 | break; | |
2644 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2645 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2646 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2647 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2648 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
2649 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2650 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2651 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
2652 | radeon_encoder->rmx_type = RMX_FULL; | |
2653 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
2654 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
2655 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { | |
2656 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
2657 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
2658 | } else { | |
2659 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
2660 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
2661 | } | |
2662 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
2663 | break; | |
2664 | case ENCODER_OBJECT_ID_SI170B: | |
2665 | case ENCODER_OBJECT_ID_CH7303: | |
2666 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: | |
2667 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: | |
2668 | case ENCODER_OBJECT_ID_TITFP513: | |
2669 | case ENCODER_OBJECT_ID_VT1623: | |
2670 | case ENCODER_OBJECT_ID_HDMI_SI1930: | |
2671 | case ENCODER_OBJECT_ID_TRAVIS: | |
2672 | case ENCODER_OBJECT_ID_NUTMEG: | |
2673 | /* these are handled by the primary encoders */ | |
2674 | radeon_encoder->is_ext_encoder = true; | |
2675 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
2676 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
2677 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) | |
2678 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
2679 | else | |
2680 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
2681 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); | |
2682 | break; | |
2683 | } | |
2684 | } |