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drm/radeon/dce8: crtc_set_base updates
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8
AD		 29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35static u8
36radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37{
38 u8 backlight_level;
39 u32 bios_2_scratch;
40
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 else
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48
49 return backlight_level;
50}
51
52static void
53radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 u8 backlight_level)
55{
56 u32 bios_2_scratch;
57
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 else
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
66
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 else
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71}
72
6d92f81d
AD		 73u8
74atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75{
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
78
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 return 0;
81
82 return radeon_atom_get_backlight_level_from_reg(rdev);
83}
84
fda4b25c 85void
37e9b6a6 86atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 87{
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 int index;
94
37e9b6a6
AD		 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 return;
97
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
f3728734 100 dig = radeon_encoder->enc_priv;
37e9b6a6 101 dig->backlight_level = level;
f3728734
AD		 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 } else {
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 }
117 break;
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
124 else {
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
127 }
128 break;
129 default:
130 break;
131 }
132 }
133}
134
bced76f2
AD		 135#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
136
f3728734
AD		 137static u8 radeon_atom_bl_level(struct backlight_device *bd)
138{
139 u8 level;
140
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
143 level = 0;
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
146 else
147 level = bd->props.brightness;
148
149 return level;
150}
151
152static int radeon_atom_backlight_update_status(struct backlight_device *bd)
153{
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
156
37e9b6a6 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 158
159 return 0;
160}
161
162static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
163{
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168
169 return radeon_atom_get_backlight_level_from_reg(rdev);
170}
171
172static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
175};
176
177void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
179{
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
186 u8 backlight_level;
614499b4 187 char bl_name[16];
f3728734 188
80101790
AD		 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
f3728734
AD		 196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
614499b4
AD		 214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, &drm_connector->kdev,
f3728734
AD		 217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
226
227 dig = radeon_encoder->enc_priv;
228 dig->bl_dev = bd;
229
230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
231 bd->props.power = FB_BLANK_UNBLANK;
232 backlight_update_status(bd);
233
234 DRM_INFO("radeon atom DIG backlight initialized\n");
235
236 return;
237
238error:
239 kfree(pdata);
240 return;
241}
242
243static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
244{
245 struct drm_device *dev = radeon_encoder->base.dev;
246 struct radeon_device *rdev = dev->dev_private;
247 struct backlight_device *bd = NULL;
248 struct radeon_encoder_atom_dig *dig;
249
250 if (!radeon_encoder->enc_priv)
251 return;
252
253 if (!rdev->is_atom_bios)
254 return;
255
256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
257 return;
258
259 dig = radeon_encoder->enc_priv;
260 bd = dig->bl_dev;
261 dig->bl_dev = NULL;
262
263 if (bd) {
264 struct radeon_legacy_backlight_privdata *pdata;
265
266 pdata = bl_get_data(bd);
267 backlight_device_unregister(bd);
268 kfree(pdata);
269
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
271 }
272}
273
274#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
275
276void radeon_atom_backlight_init(struct radeon_encoder *encoder)
277{
278}
279
280static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
281{
282}
283
284#endif
285
3f03ced8
AD		 286/* evil but including atombios.h is much worse */
287bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
288 struct drm_display_mode *mode);
289
290
291static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
292{
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 switch (radeon_encoder->encoder_id) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
306 return true;
307 default:
308 return false;
309 }
310}
311
3f03ced8 312static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 313 const struct drm_display_mode *mode,
3f03ced8
AD		 314 struct drm_display_mode *adjusted_mode)
315{
316 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
317 struct drm_device *dev = encoder->dev;
318 struct radeon_device *rdev = dev->dev_private;
319
320 /* set the active encoder to connector routing */
321 radeon_encoder_set_active_device(encoder);
322 drm_mode_set_crtcinfo(adjusted_mode, 0);
323
324 /* hw bug */
325 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
326 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
327 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
328
329 /* get the native mode for LVDS */
330 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
331 radeon_panel_mode_fixup(encoder, adjusted_mode);
332
333 /* get the native mode for TV */
334 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
335 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
336 if (tv_dac) {
337 if (tv_dac->tv_std == TV_STD_NTSC ||
338 tv_dac->tv_std == TV_STD_NTSC_J ||
339 tv_dac->tv_std == TV_STD_PAL_M)
340 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
341 else
342 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
343 }
344 }
345
346 if (ASIC_IS_DCE3(rdev) &&
347 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
348 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
349 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 350 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 351 }
352
353 return true;
354}
355
356static void
357atombios_dac_setup(struct drm_encoder *encoder, int action)
358{
359 struct drm_device *dev = encoder->dev;
360 struct radeon_device *rdev = dev->dev_private;
361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
362 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
363 int index = 0;
364 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
365
366 memset(&args, 0, sizeof(args));
367
368 switch (radeon_encoder->encoder_id) {
369 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
370 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
371 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
372 break;
373 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
374 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
375 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
376 break;
377 }
378
379 args.ucAction = action;
380
381 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
382 args.ucDacStandard = ATOM_DAC1_PS2;
383 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
384 args.ucDacStandard = ATOM_DAC1_CV;
385 else {
386 switch (dac_info->tv_std) {
387 case TV_STD_PAL:
388 case TV_STD_PAL_M:
389 case TV_STD_SCART_PAL:
390 case TV_STD_SECAM:
391 case TV_STD_PAL_CN:
392 args.ucDacStandard = ATOM_DAC1_PAL;
393 break;
394 case TV_STD_NTSC:
395 case TV_STD_NTSC_J:
396 case TV_STD_PAL_60:
397 default:
398 args.ucDacStandard = ATOM_DAC1_NTSC;
399 break;
400 }
401 }
402 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
403
404 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
405
406}
407
408static void
409atombios_tv_setup(struct drm_encoder *encoder, int action)
410{
411 struct drm_device *dev = encoder->dev;
412 struct radeon_device *rdev = dev->dev_private;
413 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
414 TV_ENCODER_CONTROL_PS_ALLOCATION args;
415 int index = 0;
416 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
417
418 memset(&args, 0, sizeof(args));
419
420 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
421
422 args.sTVEncoder.ucAction = action;
423
424 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
425 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
426 else {
427 switch (dac_info->tv_std) {
428 case TV_STD_NTSC:
429 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
430 break;
431 case TV_STD_PAL:
432 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
433 break;
434 case TV_STD_PAL_M:
435 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
436 break;
437 case TV_STD_PAL_60:
438 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
439 break;
440 case TV_STD_NTSC_J:
441 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
442 break;
443 case TV_STD_SCART_PAL:
444 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
445 break;
446 case TV_STD_SECAM:
447 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
448 break;
449 case TV_STD_PAL_CN:
450 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
451 break;
452 default:
453 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
454 break;
455 }
456 }
457
458 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
459
460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
461
462}
463
1f0e2943
AD		 464static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
465{
466 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
467 int bpc = 8;
468
469 if (connector)
470 bpc = radeon_get_monitor_bpc(connector);
471
472 switch (bpc) {
473 case 0:
474 return PANEL_BPC_UNDEFINE;
475 case 6:
476 return PANEL_6BIT_PER_COLOR;
477 case 8:
478 default:
479 return PANEL_8BIT_PER_COLOR;
480 case 10:
481 return PANEL_10BIT_PER_COLOR;
482 case 12:
483 return PANEL_12BIT_PER_COLOR;
484 case 16:
485 return PANEL_16BIT_PER_COLOR;
486 }
487}
488
489
3f03ced8
AD		 490union dvo_encoder_control {
491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
494};
495
496void
497atombios_dvo_setup(struct drm_encoder *encoder, int action)
498{
499 struct drm_device *dev = encoder->dev;
500 struct radeon_device *rdev = dev->dev_private;
501 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
502 union dvo_encoder_control args;
503 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 504 uint8_t frev, crev;
3f03ced8
AD		 505
506 memset(&args, 0, sizeof(args));
507
24153dd3
AD		 508 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
509 return;
510
afceb931
AD		 511 /* some R4xx chips have the wrong frev */
512 if (rdev->family <= CHIP_RV410)
513 frev = 1;
514
24153dd3
AD		 515 switch (frev) {
516 case 1:
517 switch (crev) {
518 case 1:
519 /* R4xx, R5xx */
520 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
521
9aa59993 522 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 523 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
524
525 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
526 break;
527 case 2:
528 /* RS600/690/740 */
529 args.dvo.sDVOEncoder.ucAction = action;
530 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 /* DFP1, CRT1, TV1 depending on the type of port */
532 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
533
9aa59993 534 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 535 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
536 break;
537 case 3:
538 /* R6xx */
539 args.dvo_v3.ucAction = action;
540 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
541 args.dvo_v3.ucDVOConfig = 0; /* XXX */
542 break;
543 default:
544 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
545 break;
546 }
547 break;
548 default:
549 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
550 break;
3f03ced8
AD		 551 }
552
553 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
554}
555
556union lvds_encoder_control {
557 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
558 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
559};
560
561void
562atombios_digital_setup(struct drm_encoder *encoder, int action)
563{
564 struct drm_device *dev = encoder->dev;
565 struct radeon_device *rdev = dev->dev_private;
566 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
567 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
568 union lvds_encoder_control args;
569 int index = 0;
570 int hdmi_detected = 0;
571 uint8_t frev, crev;
572
573 if (!dig)
574 return;
575
576 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
577 hdmi_detected = 1;
578
579 memset(&args, 0, sizeof(args));
580
581 switch (radeon_encoder->encoder_id) {
582 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
583 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
584 break;
585 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
586 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
587 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
588 break;
589 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
590 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
592 else
593 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
594 break;
595 }
596
597 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
598 return;
599
600 switch (frev) {
601 case 1:
602 case 2:
603 switch (crev) {
604 case 1:
605 args.v1.ucMisc = 0;
606 args.v1.ucAction = action;
607 if (hdmi_detected)
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
609 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
611 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
613 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
614 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
615 } else {
616 if (dig->linkb)
617 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 618 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 619 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
620 /*if (pScrn->rgbBits == 8) */
621 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
622 }
623 break;
624 case 2:
625 case 3:
626 args.v2.ucMisc = 0;
627 args.v2.ucAction = action;
628 if (crev == 3) {
629 if (dig->coherent_mode)
630 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
631 }
632 if (hdmi_detected)
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
634 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
635 args.v2.ucTruncate = 0;
636 args.v2.ucSpatial = 0;
637 args.v2.ucTemporal = 0;
638 args.v2.ucFRC = 0;
639 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
640 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
641 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
642 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
643 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
644 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
645 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
646 }
647 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
648 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
649 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
650 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
651 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
652 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
653 }
654 } else {
655 if (dig->linkb)
656 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 657 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 658 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
659 }
660 break;
661 default:
662 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
663 break;
664 }
665 break;
666 default:
667 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
668 break;
669 }
670
671 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
672}
673
674int
675atombios_get_encoder_mode(struct drm_encoder *encoder)
676{
1cbcca30
AD		 677 struct drm_device *dev = encoder->dev;
678 struct radeon_device *rdev = dev->dev_private;
3f03ced8 679 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 680 struct drm_connector *connector;
681 struct radeon_connector *radeon_connector;
682 struct radeon_connector_atom_dig *dig_connector;
683
684 /* dp bridges are always DP */
685 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
686 return ATOM_ENCODER_MODE_DP;
687
688 /* DVO is always DVO */
a59fbb8e
AD		 689 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
690 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 691 return ATOM_ENCODER_MODE_DVO;
692
693 connector = radeon_get_connector_for_encoder(encoder);
694 /* if we don't have an active device yet, just use one of
695 * the connectors tied to the encoder.
696 */
697 if (!connector)
698 connector = radeon_get_connector_for_encoder_init(encoder);
699 radeon_connector = to_radeon_connector(connector);
700
701 switch (connector->connector_type) {
702 case DRM_MODE_CONNECTOR_DVII:
703 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 704 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 705 radeon_audio &&
706 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 707 return ATOM_ENCODER_MODE_HDMI;
708 else if (radeon_connector->use_digital)
3f03ced8
AD		 709 return ATOM_ENCODER_MODE_DVI;
710 else
711 return ATOM_ENCODER_MODE_CRT;
712 break;
713 case DRM_MODE_CONNECTOR_DVID:
714 case DRM_MODE_CONNECTOR_HDMIA:
715 default:
27d9cc84 716 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 717 radeon_audio &&
718 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 719 return ATOM_ENCODER_MODE_HDMI;
720 else
3f03ced8
AD		 721 return ATOM_ENCODER_MODE_DVI;
722 break;
723 case DRM_MODE_CONNECTOR_LVDS:
724 return ATOM_ENCODER_MODE_LVDS;
725 break;
726 case DRM_MODE_CONNECTOR_DisplayPort:
727 dig_connector = radeon_connector->con_priv;
728 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
729 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
730 return ATOM_ENCODER_MODE_DP;
27d9cc84 731 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
1cbcca30
AD		 732 radeon_audio &&
733 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
f92e70ca
RM		 734 return ATOM_ENCODER_MODE_HDMI;
735 else
3f03ced8
AD		 736 return ATOM_ENCODER_MODE_DVI;
737 break;
738 case DRM_MODE_CONNECTOR_eDP:
739 return ATOM_ENCODER_MODE_DP;
740 case DRM_MODE_CONNECTOR_DVIA:
741 case DRM_MODE_CONNECTOR_VGA:
742 return ATOM_ENCODER_MODE_CRT;
743 break;
744 case DRM_MODE_CONNECTOR_Composite:
745 case DRM_MODE_CONNECTOR_SVIDEO:
746 case DRM_MODE_CONNECTOR_9PinDIN:
747 /* fix me */
748 return ATOM_ENCODER_MODE_TV;
749 /*return ATOM_ENCODER_MODE_CV;*/
750 break;
751 }
752}
753
754/*
755 * DIG Encoder/Transmitter Setup
756 *
757 * DCE 3.0/3.1
758 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
759 * Supports up to 3 digital outputs
760 * - 2 DIG encoder blocks.
761 * DIG1 can drive UNIPHY link A or link B
762 * DIG2 can drive UNIPHY link B or LVTMA
763 *
764 * DCE 3.2
765 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
766 * Supports up to 5 digital outputs
767 * - 2 DIG encoder blocks.
768 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
769 *
2d415869 770 * DCE 4.0/5.0/6.0
3f03ced8
AD		 771 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
772 * Supports up to 6 digital outputs
773 * - 6 DIG encoder blocks.
774 * - DIG to PHY mapping is hardcoded
775 * DIG1 drives UNIPHY0 link A, A+B
776 * DIG2 drives UNIPHY0 link B
777 * DIG3 drives UNIPHY1 link A, A+B
778 * DIG4 drives UNIPHY1 link B
779 * DIG5 drives UNIPHY2 link A, A+B
780 * DIG6 drives UNIPHY2 link B
781 *
782 * DCE 4.1
783 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
784 * Supports up to 6 digital outputs
785 * - 2 DIG encoder blocks.
2d415869 786 * llano
3f03ced8 787 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 788 * ontario
789 * DIG1 drives UNIPHY0/1/2 link A
790 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 791 *
792 * Routing
793 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
794 * Examples:
795 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
796 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
797 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
798 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
799 */
800
801union dig_encoder_control {
802 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
803 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
804 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
805 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
806};
807
808void
809atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
810{
811 struct drm_device *dev = encoder->dev;
812 struct radeon_device *rdev = dev->dev_private;
813 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
814 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
815 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
816 union dig_encoder_control args;
817 int index = 0;
818 uint8_t frev, crev;
819 int dp_clock = 0;
820 int dp_lane_count = 0;
821 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 822
823 if (connector) {
824 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
825 struct radeon_connector_atom_dig *dig_connector =
826 radeon_connector->con_priv;
827
828 dp_clock = dig_connector->dp_clock;
829 dp_lane_count = dig_connector->dp_lane_count;
830 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 831 }
832
833 /* no dig encoder assigned */
834 if (dig->dig_encoder == -1)
835 return;
836
837 memset(&args, 0, sizeof(args));
838
839 if (ASIC_IS_DCE4(rdev))
840 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
841 else {
842 if (dig->dig_encoder)
843 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
844 else
845 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
846 }
847
848 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
849 return;
850
58cdcb8b
AD		 851 switch (frev) {
852 case 1:
853 switch (crev) {
854 case 1:
855 args.v1.ucAction = action;
856 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
857 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
858 args.v3.ucPanelMode = panel_mode;
859 else
860 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
861
862 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
863 args.v1.ucLaneNum = dp_lane_count;
9aa59993 864 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 865 args.v1.ucLaneNum = 8;
866 else
867 args.v1.ucLaneNum = 4;
868
869 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
870 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
871 switch (radeon_encoder->encoder_id) {
872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
873 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
874 break;
875 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
876 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
877 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
878 break;
879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
880 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
881 break;
882 }
883 if (dig->linkb)
884 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
885 else
886 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 887 break;
58cdcb8b
AD		 888 case 2:
889 case 3:
890 args.v3.ucAction = action;
891 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
892 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
893 args.v3.ucPanelMode = panel_mode;
894 else
895 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
896
2f6fa79a 897 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 898 args.v3.ucLaneNum = dp_lane_count;
9aa59993 899 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 900 args.v3.ucLaneNum = 8;
901 else
902 args.v3.ucLaneNum = 4;
903
2f6fa79a 904 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 905 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
906 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 907 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 908 break;
58cdcb8b
AD		 909 case 4:
910 args.v4.ucAction = action;
911 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
912 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
913 args.v4.ucPanelMode = panel_mode;
914 else
915 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
916
2f6fa79a 917 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 918 args.v4.ucLaneNum = dp_lane_count;
9aa59993 919 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 920 args.v4.ucLaneNum = 8;
921 else
922 args.v4.ucLaneNum = 4;
923
2f6fa79a 924 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
58cdcb8b
AD		 925 if (dp_clock == 270000)
926 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
927 else if (dp_clock == 540000)
928 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
929 }
930 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 931 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 932 if (hpd_id == RADEON_HPD_NONE)
933 args.v4.ucHPD_ID = 0;
934 else
935 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 936 break;
3f03ced8 937 default:
58cdcb8b 938 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 939 break;
940 }
58cdcb8b
AD		 941 break;
942 default:
943 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
944 break;
3f03ced8
AD		 945 }
946
947 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
948
949}
950
951union dig_transmitter_control {
952 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
953 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
954 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
955 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 956 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 957};
958
959void
960atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
961{
962 struct drm_device *dev = encoder->dev;
963 struct radeon_device *rdev = dev->dev_private;
964 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
965 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
966 struct drm_connector *connector;
967 union dig_transmitter_control args;
968 int index = 0;
969 uint8_t frev, crev;
970 bool is_dp = false;
971 int pll_id = 0;
972 int dp_clock = 0;
973 int dp_lane_count = 0;
974 int connector_object_id = 0;
975 int igp_lane_info = 0;
976 int dig_encoder = dig->dig_encoder;
47aef7a8 977 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 978
979 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
980 connector = radeon_get_connector_for_encoder_init(encoder);
981 /* just needed to avoid bailing in the encoder check. the encoder
982 * isn't used for init
983 */
984 dig_encoder = 0;
985 } else
986 connector = radeon_get_connector_for_encoder(encoder);
987
988 if (connector) {
989 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
990 struct radeon_connector_atom_dig *dig_connector =
991 radeon_connector->con_priv;
992
47aef7a8 993 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 994 dp_clock = dig_connector->dp_clock;
995 dp_lane_count = dig_connector->dp_lane_count;
996 connector_object_id =
997 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
998 igp_lane_info = dig_connector->igp_lane_info;
999 }
1000
a3b08294
AD		 1001 if (encoder->crtc) {
1002 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1003 pll_id = radeon_crtc->pll_id;
1004 }
1005
3f03ced8
AD		 1006 /* no dig encoder assigned */
1007 if (dig_encoder == -1)
1008 return;
1009
1010 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1011 is_dp = true;
1012
1013 memset(&args, 0, sizeof(args));
1014
1015 switch (radeon_encoder->encoder_id) {
1016 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1017 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1018 break;
1019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1021 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1022 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1023 break;
1024 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1025 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1026 break;
1027 }
1028
1029 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1030 return;
1031
a3b08294
AD		 1032 switch (frev) {
1033 case 1:
1034 switch (crev) {
1035 case 1:
1036 args.v1.ucAction = action;
1037 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1038 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1039 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1040 args.v1.asMode.ucLaneSel = lane_num;
1041 args.v1.asMode.ucLaneSet = lane_set;
1042 } else {
1043 if (is_dp)
6e76a2df 1044 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1045 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1046 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1047 else
1048 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1049 }
3f03ced8 1050
a3b08294 1051 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1052
a3b08294
AD		 1053 if (dig_encoder)
1054 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1055 else
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1057
1058 if ((rdev->flags & RADEON_IS_IGP) &&
1059 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1060 if (is_dp ||
1061 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1062 if (igp_lane_info & 0x1)
1063 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1064 else if (igp_lane_info & 0x2)
1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1066 else if (igp_lane_info & 0x4)
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1068 else if (igp_lane_info & 0x8)
1069 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1070 } else {
1071 if (igp_lane_info & 0x3)
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1073 else if (igp_lane_info & 0xc)
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1075 }
1076 }
1077
1078 if (dig->linkb)
1079 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1080 else
1081 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1082
1083 if (is_dp)
1084 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1085 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1086 if (dig->coherent_mode)
1087 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1088 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1089 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1090 }
1091 break;
1092 case 2:
1093 args.v2.ucAction = action;
1094 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1095 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1096 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1097 args.v2.asMode.ucLaneSel = lane_num;
1098 args.v2.asMode.ucLaneSet = lane_set;
1099 } else {
1100 if (is_dp)
6e76a2df 1101 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1102 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1103 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1104 else
1105 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1106 }
1107
1108 args.v2.acConfig.ucEncoderSel = dig_encoder;
1109 if (dig->linkb)
1110 args.v2.acConfig.ucLinkSel = 1;
1111
1112 switch (radeon_encoder->encoder_id) {
1113 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1114 args.v2.acConfig.ucTransmitterSel = 0;
1115 break;
1116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1117 args.v2.acConfig.ucTransmitterSel = 1;
1118 break;
1119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1120 args.v2.acConfig.ucTransmitterSel = 2;
1121 break;
1122 }
3f03ced8 1123
3f03ced8 1124 if (is_dp) {
a3b08294
AD		 1125 args.v2.acConfig.fCoherentMode = 1;
1126 args.v2.acConfig.fDPConnector = 1;
1127 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1128 if (dig->coherent_mode)
1129 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1130 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1131 args.v2.acConfig.fDualLinkConnector = 1;
1132 }
1133 break;
1134 case 3:
1135 args.v3.ucAction = action;
1136 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1137 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1138 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1139 args.v3.asMode.ucLaneSel = lane_num;
1140 args.v3.asMode.ucLaneSet = lane_set;
1141 } else {
1142 if (is_dp)
6e76a2df 1143 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1144 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1145 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1146 else
a3b08294
AD		 1147 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1148 }
1149
1150 if (is_dp)
1151 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1152 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1153 args.v3.ucLaneNum = 8;
1154 else
1155 args.v3.ucLaneNum = 4;
1156
1157 if (dig->linkb)
1158 args.v3.acConfig.ucLinkSel = 1;
1159 if (dig_encoder & 1)
1160 args.v3.acConfig.ucEncoderSel = 1;
1161
1162 /* Select the PLL for the PHY
1163 * DP PHY should be clocked from external src if there is
1164 * one.
1165 */
3f03ced8
AD		 1166 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1167 if (is_dp && rdev->clock.dp_extclk)
1168 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1169 else
1170 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1171
a3b08294
AD		 1172 switch (radeon_encoder->encoder_id) {
1173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1174 args.v3.acConfig.ucTransmitterSel = 0;
1175 break;
1176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1177 args.v3.acConfig.ucTransmitterSel = 1;
1178 break;
1179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1180 args.v3.acConfig.ucTransmitterSel = 2;
1181 break;
1182 }
3f03ced8 1183
a3b08294
AD		 1184 if (is_dp)
1185 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1186 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1187 if (dig->coherent_mode)
1188 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1189 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1190 args.v3.acConfig.fDualLinkConnector = 1;
1191 }
3f03ced8 1192 break;
a3b08294
AD		 1193 case 4:
1194 args.v4.ucAction = action;
1195 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1196 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1197 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1198 args.v4.asMode.ucLaneSel = lane_num;
1199 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1200 } else {
a3b08294 1201 if (is_dp)
6e76a2df 1202 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1203 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1204 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1205 else
1206 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1207 }
3f03ced8 1208
a3b08294
AD		 1209 if (is_dp)
1210 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1211 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1212 args.v4.ucLaneNum = 8;
1213 else
1214 args.v4.ucLaneNum = 4;
3f03ced8 1215
a3b08294
AD		 1216 if (dig->linkb)
1217 args.v4.acConfig.ucLinkSel = 1;
1218 if (dig_encoder & 1)
1219 args.v4.acConfig.ucEncoderSel = 1;
1220
1221 /* Select the PLL for the PHY
1222 * DP PHY should be clocked from external src if there is
1223 * one.
1224 */
1225 /* On DCE5 DCPLL usually generates the DP ref clock */
1226 if (is_dp) {
1227 if (rdev->clock.dp_extclk)
1228 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1229 else
1230 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1231 } else
1232 args.v4.acConfig.ucRefClkSource = pll_id;
1233
1234 switch (radeon_encoder->encoder_id) {
1235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1236 args.v4.acConfig.ucTransmitterSel = 0;
1237 break;
1238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1239 args.v4.acConfig.ucTransmitterSel = 1;
1240 break;
1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1242 args.v4.acConfig.ucTransmitterSel = 2;
1243 break;
1244 }
1245
1246 if (is_dp)
1247 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1248 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1249 if (dig->coherent_mode)
1250 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1251 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1252 args.v4.acConfig.fDualLinkConnector = 1;
1253 }
1254 break;
47aef7a8
AD		 1255 case 5:
1256 args.v5.ucAction = action;
1257 if (is_dp)
1258 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1259 else
1260 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1261
1262 switch (radeon_encoder->encoder_id) {
1263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1264 if (dig->linkb)
1265 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1266 else
1267 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1268 break;
1269 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1270 if (dig->linkb)
1271 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1272 else
1273 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1274 break;
1275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1276 if (dig->linkb)
1277 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1278 else
1279 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1280 break;
1281 }
1282 if (is_dp)
1283 args.v5.ucLaneNum = dp_lane_count;
1284 else if (radeon_encoder->pixel_clock > 165000)
1285 args.v5.ucLaneNum = 8;
1286 else
1287 args.v5.ucLaneNum = 4;
1288 args.v5.ucConnObjId = connector_object_id;
1289 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1290
1291 if (is_dp && rdev->clock.dp_extclk)
1292 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1293 else
1294 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1295
1296 if (is_dp)
1297 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1298 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1299 if (dig->coherent_mode)
1300 args.v5.asConfig.ucCoherentMode = 1;
1301 }
1302 if (hpd_id == RADEON_HPD_NONE)
1303 args.v5.asConfig.ucHPDSel = 0;
1304 else
1305 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1306 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1307 args.v5.ucDPLaneSet = lane_set;
1308 break;
a3b08294
AD		 1309 default:
1310 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1311 break;
3f03ced8 1312 }
a3b08294
AD		 1313 break;
1314 default:
1315 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1316 break;
3f03ced8
AD		 1317 }
1318
1319 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1320}
1321
1322bool
1323atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1324{
1325 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1326 struct drm_device *dev = radeon_connector->base.dev;
1327 struct radeon_device *rdev = dev->dev_private;
1328 union dig_transmitter_control args;
1329 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1330 uint8_t frev, crev;
1331
1332 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1333 goto done;
1334
1335 if (!ASIC_IS_DCE4(rdev))
1336 goto done;
1337
1338 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1339 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1340 goto done;
1341
1342 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1343 goto done;
1344
1345 memset(&args, 0, sizeof(args));
1346
1347 args.v1.ucAction = action;
1348
1349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1350
1351 /* wait for the panel to power up */
1352 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1353 int i;
1354
1355 for (i = 0; i < 300; i++) {
1356 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1357 return true;
1358 mdelay(1);
1359 }
1360 return false;
1361 }
1362done:
1363 return true;
1364}
1365
1366union external_encoder_control {
1367 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1368 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1369};
1370
1371static void
1372atombios_external_encoder_setup(struct drm_encoder *encoder,
1373 struct drm_encoder *ext_encoder,
1374 int action)
1375{
1376 struct drm_device *dev = encoder->dev;
1377 struct radeon_device *rdev = dev->dev_private;
1378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1379 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1380 union external_encoder_control args;
1381 struct drm_connector *connector;
1382 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1383 u8 frev, crev;
1384 int dp_clock = 0;
1385 int dp_lane_count = 0;
1386 int connector_object_id = 0;
1387 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1388
1389 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1390 connector = radeon_get_connector_for_encoder_init(encoder);
1391 else
1392 connector = radeon_get_connector_for_encoder(encoder);
1393
1394 if (connector) {
1395 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1396 struct radeon_connector_atom_dig *dig_connector =
1397 radeon_connector->con_priv;
1398
1399 dp_clock = dig_connector->dp_clock;
1400 dp_lane_count = dig_connector->dp_lane_count;
1401 connector_object_id =
1402 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1403 }
1404
1405 memset(&args, 0, sizeof(args));
1406
1407 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1408 return;
1409
1410 switch (frev) {
1411 case 1:
1412 /* no params on frev 1 */
1413 break;
1414 case 2:
1415 switch (crev) {
1416 case 1:
1417 case 2:
1418 args.v1.sDigEncoder.ucAction = action;
1419 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1420 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1421
1422 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1423 if (dp_clock == 270000)
1424 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1425 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1426 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1427 args.v1.sDigEncoder.ucLaneNum = 8;
1428 else
1429 args.v1.sDigEncoder.ucLaneNum = 4;
1430 break;
1431 case 3:
1432 args.v3.sExtEncoder.ucAction = action;
1433 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1434 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1435 else
1436 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1437 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1438
1439 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1440 if (dp_clock == 270000)
1441 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1442 else if (dp_clock == 540000)
1443 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1444 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1445 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1446 args.v3.sExtEncoder.ucLaneNum = 8;
1447 else
1448 args.v3.sExtEncoder.ucLaneNum = 4;
1449 switch (ext_enum) {
1450 case GRAPH_OBJECT_ENUM_ID1:
1451 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1452 break;
1453 case GRAPH_OBJECT_ENUM_ID2:
1454 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1455 break;
1456 case GRAPH_OBJECT_ENUM_ID3:
1457 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1458 break;
1459 }
1f0e2943 1460 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1461 break;
1462 default:
1463 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1464 return;
1465 }
1466 break;
1467 default:
1468 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1469 return;
1470 }
1471 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1472}
1473
1474static void
1475atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1476{
1477 struct drm_device *dev = encoder->dev;
1478 struct radeon_device *rdev = dev->dev_private;
1479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1480 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1481 ENABLE_YUV_PS_ALLOCATION args;
1482 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1483 uint32_t temp, reg;
1484
1485 memset(&args, 0, sizeof(args));
1486
1487 if (rdev->family >= CHIP_R600)
1488 reg = R600_BIOS_3_SCRATCH;
1489 else
1490 reg = RADEON_BIOS_3_SCRATCH;
1491
1492 /* XXX: fix up scratch reg handling */
1493 temp = RREG32(reg);
1494 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1495 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1496 (radeon_crtc->crtc_id << 18)));
1497 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1498 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1499 else
1500 WREG32(reg, 0);
1501
1502 if (enable)
1503 args.ucEnable = ATOM_ENABLE;
1504 args.ucCRTC = radeon_crtc->crtc_id;
1505
1506 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1507
1508 WREG32(reg, temp);
1509}
1510
1511static void
1512radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1513{
1514 struct drm_device *dev = encoder->dev;
1515 struct radeon_device *rdev = dev->dev_private;
1516 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1517 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1518 int index = 0;
1519
1520 memset(&args, 0, sizeof(args));
1521
1522 switch (radeon_encoder->encoder_id) {
1523 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1524 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1525 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1526 break;
1527 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1528 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1529 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1530 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1531 break;
1532 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1533 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1534 break;
1535 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1536 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1537 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1538 else
1539 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1540 break;
1541 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1542 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1543 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1544 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1545 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1546 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1547 else
1548 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1549 break;
1550 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1551 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1552 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1553 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1554 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1555 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1556 else
1557 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1558 break;
1559 default:
1560 return;
1561 }
1562
1563 switch (mode) {
1564 case DRM_MODE_DPMS_ON:
1565 args.ucAction = ATOM_ENABLE;
1566 /* workaround for DVOOutputControl on some RS690 systems */
1567 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1568 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1569 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1571 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1572 } else
1573 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1574 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1575 args.ucAction = ATOM_LCD_BLON;
1576 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1577 }
1578 break;
1579 case DRM_MODE_DPMS_STANDBY:
1580 case DRM_MODE_DPMS_SUSPEND:
1581 case DRM_MODE_DPMS_OFF:
1582 args.ucAction = ATOM_DISABLE;
1583 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1584 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1585 args.ucAction = ATOM_LCD_BLOFF;
1586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1587 }
1588 break;
1589 }
1590}
1591
1592static void
1593radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1594{
1595 struct drm_device *dev = encoder->dev;
1596 struct radeon_device *rdev = dev->dev_private;
1597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1598 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1599 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1600 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1601 struct radeon_connector *radeon_connector = NULL;
1602 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1603
1604 if (connector) {
1605 radeon_connector = to_radeon_connector(connector);
1606 radeon_dig_connector = radeon_connector->con_priv;
1607 }
1608
1609 switch (mode) {
1610 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1611 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1612 if (!connector)
1613 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1614 else
1615 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1616
1617 /* setup and enable the encoder */
1618 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1619 atombios_dig_encoder_setup(encoder,
1620 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1621 dig->panel_mode);
1622 if (ext_encoder) {
1623 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1624 atombios_external_encoder_setup(encoder, ext_encoder,
1625 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1626 }
3f03ced8 1627 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1628 } else if (ASIC_IS_DCE4(rdev)) {
1629 /* setup and enable the encoder */
1630 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1631 /* enable the transmitter */
1632 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1633 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1634 } else {
1635 /* setup and enable the encoder and transmitter */
1636 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1637 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1638 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1639 /* some early dce3.2 boards have a bug in their transmitter control table */
b9196395 1640 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
8d1af57a 1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1642 }
3f03ced8
AD		 1643 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1644 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1645 atombios_set_edp_panel_power(connector,
1646 ATOM_TRANSMITTER_ACTION_POWER_ON);
1647 radeon_dig_connector->edp_on = true;
1648 }
3f03ced8
AD		 1649 radeon_dp_link_train(encoder, connector);
1650 if (ASIC_IS_DCE4(rdev))
1651 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1652 }
1653 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1654 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1655 break;
1656 case DRM_MODE_DPMS_STANDBY:
1657 case DRM_MODE_DPMS_SUSPEND:
1658 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1659 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1660 /* disable the transmitter */
3a47824d 1661 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1662 } else if (ASIC_IS_DCE4(rdev)) {
1663 /* disable the transmitter */
1664 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1666 } else {
1667 /* disable the encoder and transmitter */
3a47824d 1668 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1670 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1671 }
3f03ced8
AD		 1672 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1673 if (ASIC_IS_DCE4(rdev))
1674 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1675 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1676 atombios_set_edp_panel_power(connector,
1677 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1678 radeon_dig_connector->edp_on = false;
1679 }
1680 }
1681 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1682 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1683 break;
1684 }
1685}
1686
1687static void
1688radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1689 struct drm_encoder *ext_encoder,
1690 int mode)
1691{
1692 struct drm_device *dev = encoder->dev;
1693 struct radeon_device *rdev = dev->dev_private;
1694
1695 switch (mode) {
1696 case DRM_MODE_DPMS_ON:
1697 default:
1d3949c4 1698 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1699 atombios_external_encoder_setup(encoder, ext_encoder,
1700 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1701 atombios_external_encoder_setup(encoder, ext_encoder,
1702 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1703 } else
1704 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1705 break;
1706 case DRM_MODE_DPMS_STANDBY:
1707 case DRM_MODE_DPMS_SUSPEND:
1708 case DRM_MODE_DPMS_OFF:
1d3949c4 1709 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1710 atombios_external_encoder_setup(encoder, ext_encoder,
1711 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1712 atombios_external_encoder_setup(encoder, ext_encoder,
1713 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1714 } else
1715 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1716 break;
1717 }
1718}
1719
1720static void
1721radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1722{
1723 struct drm_device *dev = encoder->dev;
1724 struct radeon_device *rdev = dev->dev_private;
1725 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1726 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1727
1728 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1729 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1730 radeon_encoder->active_device);
1731 switch (radeon_encoder->encoder_id) {
1732 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1734 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1735 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1736 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1737 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1738 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1739 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1740 radeon_atom_encoder_dpms_avivo(encoder, mode);
1741 break;
1742 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1744 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1745 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1746 radeon_atom_encoder_dpms_dig(encoder, mode);
1747 break;
1748 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1749 if (ASIC_IS_DCE5(rdev)) {
1750 switch (mode) {
1751 case DRM_MODE_DPMS_ON:
1752 atombios_dvo_setup(encoder, ATOM_ENABLE);
1753 break;
1754 case DRM_MODE_DPMS_STANDBY:
1755 case DRM_MODE_DPMS_SUSPEND:
1756 case DRM_MODE_DPMS_OFF:
1757 atombios_dvo_setup(encoder, ATOM_DISABLE);
1758 break;
1759 }
1760 } else if (ASIC_IS_DCE3(rdev))
1761 radeon_atom_encoder_dpms_dig(encoder, mode);
1762 else
1763 radeon_atom_encoder_dpms_avivo(encoder, mode);
1764 break;
1765 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1767 if (ASIC_IS_DCE5(rdev)) {
1768 switch (mode) {
1769 case DRM_MODE_DPMS_ON:
1770 atombios_dac_setup(encoder, ATOM_ENABLE);
1771 break;
1772 case DRM_MODE_DPMS_STANDBY:
1773 case DRM_MODE_DPMS_SUSPEND:
1774 case DRM_MODE_DPMS_OFF:
1775 atombios_dac_setup(encoder, ATOM_DISABLE);
1776 break;
1777 }
1778 } else
1779 radeon_atom_encoder_dpms_avivo(encoder, mode);
1780 break;
1781 default:
1782 return;
1783 }
1784
1785 if (ext_encoder)
1786 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1787
1788 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1789
1790}
1791
1792union crtc_source_param {
1793 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1794 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1795};
1796
1797static void
1798atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1799{
1800 struct drm_device *dev = encoder->dev;
1801 struct radeon_device *rdev = dev->dev_private;
1802 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1803 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1804 union crtc_source_param args;
1805 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1806 uint8_t frev, crev;
1807 struct radeon_encoder_atom_dig *dig;
1808
1809 memset(&args, 0, sizeof(args));
1810
1811 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1812 return;
1813
1814 switch (frev) {
1815 case 1:
1816 switch (crev) {
1817 case 1:
1818 default:
1819 if (ASIC_IS_AVIVO(rdev))
1820 args.v1.ucCRTC = radeon_crtc->crtc_id;
1821 else {
1822 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1823 args.v1.ucCRTC = radeon_crtc->crtc_id;
1824 } else {
1825 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1826 }
1827 }
1828 switch (radeon_encoder->encoder_id) {
1829 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1830 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1831 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1832 break;
1833 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1834 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1835 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1836 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1837 else
1838 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1839 break;
1840 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1841 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1843 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1844 break;
1845 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1846 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1847 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1848 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1849 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1850 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1851 else
1852 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1853 break;
1854 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1855 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1856 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1857 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1858 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1859 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1860 else
1861 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1862 break;
1863 }
1864 break;
1865 case 2:
1866 args.v2.ucCRTC = radeon_crtc->crtc_id;
1867 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1868 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1869
1870 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1871 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1872 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1873 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1874 else
1875 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1876 } else
1877 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1878 switch (radeon_encoder->encoder_id) {
1879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1882 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1883 dig = radeon_encoder->enc_priv;
1884 switch (dig->dig_encoder) {
1885 case 0:
1886 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1887 break;
1888 case 1:
1889 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1890 break;
1891 case 2:
1892 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1893 break;
1894 case 3:
1895 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1896 break;
1897 case 4:
1898 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1899 break;
1900 case 5:
1901 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1902 break;
1903 }
1904 break;
1905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1906 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1907 break;
1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1910 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1911 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1912 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1913 else
1914 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1915 break;
1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1917 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1918 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1919 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1920 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1921 else
1922 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1923 break;
1924 }
1925 break;
1926 }
1927 break;
1928 default:
1929 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1930 return;
1931 }
1932
1933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1934
1935 /* update scratch regs with new routing */
1936 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1937}
1938
1939static void
1940atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1941 struct drm_display_mode *mode)
1942{
1943 struct drm_device *dev = encoder->dev;
1944 struct radeon_device *rdev = dev->dev_private;
1945 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1946 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1947
1948 /* Funky macbooks */
1949 if ((dev->pdev->device == 0x71C5) &&
1950 (dev->pdev->subsystem_vendor == 0x106b) &&
1951 (dev->pdev->subsystem_device == 0x0080)) {
1952 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1953 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1954
1955 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1956 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1957
1958 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1959 }
1960 }
1961
1962 /* set scaler clears this on some chips */
1963 if (ASIC_IS_AVIVO(rdev) &&
1964 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
d798f2f2
AD		 1965 if (ASIC_IS_DCE8(rdev)) {
1966 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1967 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1968 CIK_INTERLEAVE_EN);
1969 else
1970 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1971 } else if (ASIC_IS_DCE4(rdev)) {
3f03ced8
AD		 1972 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1973 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1974 EVERGREEN_INTERLEAVE_EN);
1975 else
1976 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1977 } else {
1978 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1979 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1980 AVIVO_D1MODE_INTERLEAVE_EN);
1981 else
1982 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1983 }
1984 }
1985}
1986
1987static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1988{
1989 struct drm_device *dev = encoder->dev;
1990 struct radeon_device *rdev = dev->dev_private;
1991 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1992 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1993 struct drm_encoder *test_encoder;
41fa5437 1994 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1995 uint32_t dig_enc_in_use = 0;
1996
41fa5437
AD		 1997 if (ASIC_IS_DCE6(rdev)) {
1998 /* DCE6 */
1999 switch (radeon_encoder->encoder_id) {
2000 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2001 if (dig->linkb)
2002 return 1;
2003 else
2004 return 0;
2005 break;
2006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2007 if (dig->linkb)
2008 return 3;
2009 else
2010 return 2;
2011 break;
2012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2013 if (dig->linkb)
2014 return 5;
2015 else
2016 return 4;
2017 break;
2018 }
2019 } else if (ASIC_IS_DCE4(rdev)) {
2020 /* DCE4/5 */
2021 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2022 /* ontario follows DCE4 */
2023 if (rdev->family == CHIP_PALM) {
2024 if (dig->linkb)
2025 return 1;
2026 else
2027 return 0;
2028 } else
2029 /* llano follows DCE3.2 */
2030 return radeon_crtc->crtc_id;
2031 } else {
2032 switch (radeon_encoder->encoder_id) {
2033 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2034 if (dig->linkb)
2035 return 1;
2036 else
2037 return 0;
2038 break;
2039 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2040 if (dig->linkb)
2041 return 3;
2042 else
2043 return 2;
2044 break;
2045 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2046 if (dig->linkb)
2047 return 5;
2048 else
2049 return 4;
2050 break;
2051 }
2052 }
2053 }
2054
2055 /* on DCE32 and encoder can driver any block so just crtc id */
2056 if (ASIC_IS_DCE32(rdev)) {
2057 return radeon_crtc->crtc_id;
2058 }
2059
2060 /* on DCE3 - LVTMA can only be driven by DIGB */
2061 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2062 struct radeon_encoder *radeon_test_encoder;
2063
2064 if (encoder == test_encoder)
2065 continue;
2066
2067 if (!radeon_encoder_is_digital(test_encoder))
2068 continue;
2069
2070 radeon_test_encoder = to_radeon_encoder(test_encoder);
2071 dig = radeon_test_encoder->enc_priv;
2072
2073 if (dig->dig_encoder >= 0)
2074 dig_enc_in_use |= (1 << dig->dig_encoder);
2075 }
2076
2077 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2078 if (dig_enc_in_use & 0x2)
2079 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2080 return 1;
2081 }
2082 if (!(dig_enc_in_use & 1))
2083 return 0;
2084 return 1;
2085}
2086
2087/* This only needs to be called once at startup */
2088void
2089radeon_atom_encoder_init(struct radeon_device *rdev)
2090{
2091 struct drm_device *dev = rdev->ddev;
2092 struct drm_encoder *encoder;
2093
2094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2095 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2096 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2097
2098 switch (radeon_encoder->encoder_id) {
2099 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2102 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2103 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2104 break;
2105 default:
2106 break;
2107 }
2108
1d3949c4 2109 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2110 atombios_external_encoder_setup(encoder, ext_encoder,
2111 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2112 }
2113}
2114
2115static void
2116radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2117 struct drm_display_mode *mode,
2118 struct drm_display_mode *adjusted_mode)
2119{
2120 struct drm_device *dev = encoder->dev;
2121 struct radeon_device *rdev = dev->dev_private;
2122 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2123
2124 radeon_encoder->pixel_clock = adjusted_mode->clock;
2125
8d1af57a
AD		 2126 /* need to call this here rather than in prepare() since we need some crtc info */
2127 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2128
3f03ced8
AD		 2129 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2130 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2131 atombios_yuv_setup(encoder, true);
2132 else
2133 atombios_yuv_setup(encoder, false);
2134 }
2135
2136 switch (radeon_encoder->encoder_id) {
2137 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2139 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2140 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2141 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2142 break;
2143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2144 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2146 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2147 /* handled in dpms */
3f03ced8
AD		 2148 break;
2149 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2150 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2151 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2152 atombios_dvo_setup(encoder, ATOM_ENABLE);
2153 break;
2154 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2155 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2156 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2158 atombios_dac_setup(encoder, ATOM_ENABLE);
2159 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2160 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2161 atombios_tv_setup(encoder, ATOM_ENABLE);
2162 else
2163 atombios_tv_setup(encoder, ATOM_DISABLE);
2164 }
2165 break;
2166 }
2167
3f03ced8
AD		 2168 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2169
2170 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
a973bea1
AD		 2171 if (rdev->asic->display.hdmi_enable)
2172 radeon_hdmi_enable(rdev, encoder, true);
2173 if (rdev->asic->display.hdmi_setmode)
2174 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
3f03ced8
AD		 2175 }
2176}
2177
2178static bool
2179atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2180{
2181 struct drm_device *dev = encoder->dev;
2182 struct radeon_device *rdev = dev->dev_private;
2183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2184 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2185
2186 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2187 ATOM_DEVICE_CV_SUPPORT |
2188 ATOM_DEVICE_CRT_SUPPORT)) {
2189 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2190 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2191 uint8_t frev, crev;
2192
2193 memset(&args, 0, sizeof(args));
2194
2195 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2196 return false;
2197
2198 args.sDacload.ucMisc = 0;
2199
2200 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2201 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2202 args.sDacload.ucDacType = ATOM_DAC_A;
2203 else
2204 args.sDacload.ucDacType = ATOM_DAC_B;
2205
2206 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2207 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2208 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2209 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2210 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2211 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2212 if (crev >= 3)
2213 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2214 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2215 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2216 if (crev >= 3)
2217 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2218 }
2219
2220 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2221
2222 return true;
2223 } else
2224 return false;
2225}
2226
2227static enum drm_connector_status
2228radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2229{
2230 struct drm_device *dev = encoder->dev;
2231 struct radeon_device *rdev = dev->dev_private;
2232 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2233 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2234 uint32_t bios_0_scratch;
2235
2236 if (!atombios_dac_load_detect(encoder, connector)) {
2237 DRM_DEBUG_KMS("detect returned false \n");
2238 return connector_status_unknown;
2239 }
2240
2241 if (rdev->family >= CHIP_R600)
2242 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2243 else
2244 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2245
2246 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2247 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2248 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2249 return connector_status_connected;
2250 }
2251 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2252 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2253 return connector_status_connected;
2254 }
2255 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2256 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2257 return connector_status_connected;
2258 }
2259 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2260 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2261 return connector_status_connected; /* CTV */
2262 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2263 return connector_status_connected; /* STV */
2264 }
2265 return connector_status_disconnected;
2266}
2267
2268static enum drm_connector_status
2269radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2270{
2271 struct drm_device *dev = encoder->dev;
2272 struct radeon_device *rdev = dev->dev_private;
2273 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2274 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2275 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2276 u32 bios_0_scratch;
2277
2278 if (!ASIC_IS_DCE4(rdev))
2279 return connector_status_unknown;
2280
2281 if (!ext_encoder)
2282 return connector_status_unknown;
2283
2284 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2285 return connector_status_unknown;
2286
2287 /* load detect on the dp bridge */
2288 atombios_external_encoder_setup(encoder, ext_encoder,
2289 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2290
2291 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2292
2293 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2294 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2295 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2296 return connector_status_connected;
2297 }
2298 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2299 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2300 return connector_status_connected;
2301 }
2302 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2303 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2304 return connector_status_connected;
2305 }
2306 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2307 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2308 return connector_status_connected; /* CTV */
2309 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2310 return connector_status_connected; /* STV */
2311 }
2312 return connector_status_disconnected;
2313}
2314
2315void
2316radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2317{
2318 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2319
2320 if (ext_encoder)
2321 /* ddc_setup on the dp bridge */
2322 atombios_external_encoder_setup(encoder, ext_encoder,
2323 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2324
2325}
2326
2327static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2328{
cfcbd6d3 2329 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2330 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2331 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2332
2333 if ((radeon_encoder->active_device &
2334 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2335 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2336 ENCODER_OBJECT_ID_NONE)) {
2337 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2338 if (dig) {
3f03ced8 2339 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2340 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2341 if (rdev->family >= CHIP_R600)
2342 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2343 else
2344 /* RS600/690/740 have only 1 afmt block */
2345 dig->afmt = rdev->mode_info.afmt[0];
2346 }
2347 }
3f03ced8
AD		 2348 }
2349
2350 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2351
2352 if (connector) {
2353 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2354
2355 /* select the clock/data port if it uses a router */
2356 if (radeon_connector->router.cd_valid)
2357 radeon_router_select_cd_port(radeon_connector);
2358
2359 /* turn eDP panel on for mode set */
2360 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2361 atombios_set_edp_panel_power(connector,
2362 ATOM_TRANSMITTER_ACTION_POWER_ON);
2363 }
2364
2365 /* this is needed for the pll/ss setup to work correctly in some cases */
2366 atombios_set_encoder_crtc_source(encoder);
2367}
2368
2369static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2370{
8d1af57a 2371 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2372 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2373 radeon_atom_output_lock(encoder, false);
2374}
2375
2376static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2377{
2378 struct drm_device *dev = encoder->dev;
2379 struct radeon_device *rdev = dev->dev_private;
2380 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2381 struct radeon_encoder_atom_dig *dig;
2382
2383 /* check for pre-DCE3 cards with shared encoders;
2384 * can't really use the links individually, so don't disable
2385 * the encoder if it's in use by another connector
2386 */
2387 if (!ASIC_IS_DCE3(rdev)) {
2388 struct drm_encoder *other_encoder;
2389 struct radeon_encoder *other_radeon_encoder;
2390
2391 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2392 other_radeon_encoder = to_radeon_encoder(other_encoder);
2393 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2394 drm_helper_encoder_in_use(other_encoder))
2395 goto disable_done;
2396 }
2397 }
2398
2399 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2400
2401 switch (radeon_encoder->encoder_id) {
2402 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2403 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2404 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2405 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2406 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2407 break;
2408 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2409 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2411 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2412 /* handled in dpms */
3f03ced8
AD		 2413 break;
2414 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2415 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2416 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2417 atombios_dvo_setup(encoder, ATOM_DISABLE);
2418 break;
2419 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2420 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2421 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2423 atombios_dac_setup(encoder, ATOM_DISABLE);
2424 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2425 atombios_tv_setup(encoder, ATOM_DISABLE);
2426 break;
2427 }
2428
2429disable_done:
2430 if (radeon_encoder_is_digital(encoder)) {
a973bea1
AD		 2431 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2432 if (rdev->asic->display.hdmi_enable)
2433 radeon_hdmi_enable(rdev, encoder, false);
2434 }
3f03ced8
AD		 2435 dig = radeon_encoder->enc_priv;
2436 dig->dig_encoder = -1;
2437 }
2438 radeon_encoder->active_device = 0;
2439}
2440
2441/* these are handled by the primary encoders */
2442static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2443{
2444
2445}
2446
2447static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2448{
2449
2450}
2451
2452static void
2453radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2454 struct drm_display_mode *mode,
2455 struct drm_display_mode *adjusted_mode)
2456{
2457
2458}
2459
2460static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2461{
2462
2463}
2464
2465static void
2466radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2467{
2468
2469}
2470
2471static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2472 const struct drm_display_mode *mode,
3f03ced8
AD		 2473 struct drm_display_mode *adjusted_mode)
2474{
2475 return true;
2476}
2477
2478static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2479 .dpms = radeon_atom_ext_dpms,
2480 .mode_fixup = radeon_atom_ext_mode_fixup,
2481 .prepare = radeon_atom_ext_prepare,
2482 .mode_set = radeon_atom_ext_mode_set,
2483 .commit = radeon_atom_ext_commit,
2484 .disable = radeon_atom_ext_disable,
2485 /* no detect for TMDS/LVDS yet */
2486};
2487
2488static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2489 .dpms = radeon_atom_encoder_dpms,
2490 .mode_fixup = radeon_atom_mode_fixup,
2491 .prepare = radeon_atom_encoder_prepare,
2492 .mode_set = radeon_atom_encoder_mode_set,
2493 .commit = radeon_atom_encoder_commit,
2494 .disable = radeon_atom_encoder_disable,
2495 .detect = radeon_atom_dig_detect,
2496};
2497
2498static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2499 .dpms = radeon_atom_encoder_dpms,
2500 .mode_fixup = radeon_atom_mode_fixup,
2501 .prepare = radeon_atom_encoder_prepare,
2502 .mode_set = radeon_atom_encoder_mode_set,
2503 .commit = radeon_atom_encoder_commit,
2504 .detect = radeon_atom_dac_detect,
2505};
2506
2507void radeon_enc_destroy(struct drm_encoder *encoder)
2508{
2509 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2510 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2511 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2512 kfree(radeon_encoder->enc_priv);
2513 drm_encoder_cleanup(encoder);
2514 kfree(radeon_encoder);
2515}
2516
2517static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2518 .destroy = radeon_enc_destroy,
2519};
2520
1109ca09 2521static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2522radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2523{
2524 struct drm_device *dev = radeon_encoder->base.dev;
2525 struct radeon_device *rdev = dev->dev_private;
2526 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2527
2528 if (!dac)
2529 return NULL;
2530
2531 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2532 return dac;
2533}
2534
1109ca09 2535static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2536radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2537{
2538 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2539 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2540
2541 if (!dig)
2542 return NULL;
2543
2544 /* coherent mode by default */
2545 dig->coherent_mode = true;
2546 dig->dig_encoder = -1;
2547
2548 if (encoder_enum == 2)
2549 dig->linkb = true;
2550 else
2551 dig->linkb = false;
2552
2553 return dig;
2554}
2555
2556void
2557radeon_add_atom_encoder(struct drm_device *dev,
2558 uint32_t encoder_enum,
2559 uint32_t supported_device,
2560 u16 caps)
2561{
2562 struct radeon_device *rdev = dev->dev_private;
2563 struct drm_encoder *encoder;
2564 struct radeon_encoder *radeon_encoder;
2565
2566 /* see if we already added it */
2567 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2568 radeon_encoder = to_radeon_encoder(encoder);
2569 if (radeon_encoder->encoder_enum == encoder_enum) {
2570 radeon_encoder->devices |= supported_device;
2571 return;
2572 }
2573
2574 }
2575
2576 /* add a new one */
2577 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2578 if (!radeon_encoder)
2579 return;
2580
2581 encoder = &radeon_encoder->base;
2582 switch (rdev->num_crtc) {
2583 case 1:
2584 encoder->possible_crtcs = 0x1;
2585 break;
2586 case 2:
2587 default:
2588 encoder->possible_crtcs = 0x3;
2589 break;
2590 case 4:
2591 encoder->possible_crtcs = 0xf;
2592 break;
2593 case 6:
2594 encoder->possible_crtcs = 0x3f;
2595 break;
2596 }
2597
2598 radeon_encoder->enc_priv = NULL;
2599
2600 radeon_encoder->encoder_enum = encoder_enum;
2601 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2602 radeon_encoder->devices = supported_device;
2603 radeon_encoder->rmx_type = RMX_OFF;
2604 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2605 radeon_encoder->is_ext_encoder = false;
2606 radeon_encoder->caps = caps;
2607
2608 switch (radeon_encoder->encoder_id) {
2609 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2610 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2611 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2612 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2613 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2614 radeon_encoder->rmx_type = RMX_FULL;
2615 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2616 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2617 } else {
2618 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2619 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2620 }
2621 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2622 break;
2623 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2624 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2625 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2626 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2627 break;
2628 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2631 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2632 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2633 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2634 break;
2635 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2636 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2637 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2638 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2639 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2640 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2641 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2642 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2643 radeon_encoder->rmx_type = RMX_FULL;
2644 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2645 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2646 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2647 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2648 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2649 } else {
2650 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2651 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2652 }
2653 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2654 break;
2655 case ENCODER_OBJECT_ID_SI170B:
2656 case ENCODER_OBJECT_ID_CH7303:
2657 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2658 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2659 case ENCODER_OBJECT_ID_TITFP513:
2660 case ENCODER_OBJECT_ID_VT1623:
2661 case ENCODER_OBJECT_ID_HDMI_SI1930:
2662 case ENCODER_OBJECT_ID_TRAVIS:
2663 case ENCODER_OBJECT_ID_NUTMEG:
2664 /* these are handled by the primary encoders */
2665 radeon_encoder->is_ext_encoder = true;
2666 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2667 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2668 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2669 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2670 else
2671 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2672 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2673 break;
2674 }
2675}
Linux kernel - Deliverables
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