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drm/radeon: clean up audio dto programming
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8
AD		 29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35static u8
36radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37{
38 u8 backlight_level;
39 u32 bios_2_scratch;
40
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 else
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48
49 return backlight_level;
50}
51
52static void
53radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 u8 backlight_level)
55{
56 u32 bios_2_scratch;
57
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 else
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
66
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 else
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71}
72
6d92f81d
AD		 73u8
74atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75{
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
78
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 return 0;
81
82 return radeon_atom_get_backlight_level_from_reg(rdev);
83}
84
fda4b25c 85void
37e9b6a6 86atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 87{
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 int index;
94
37e9b6a6
AD		 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 return;
97
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
f3728734 100 dig = radeon_encoder->enc_priv;
37e9b6a6 101 dig->backlight_level = level;
f3728734
AD		 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 } else {
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 }
117 break;
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
124 else {
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
127 }
128 break;
129 default:
130 break;
131 }
132 }
133}
134
bced76f2
AD		 135#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
136
f3728734
AD		 137static u8 radeon_atom_bl_level(struct backlight_device *bd)
138{
139 u8 level;
140
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
143 level = 0;
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
146 else
147 level = bd->props.brightness;
148
149 return level;
150}
151
152static int radeon_atom_backlight_update_status(struct backlight_device *bd)
153{
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
156
37e9b6a6 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 158
159 return 0;
160}
161
162static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
163{
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168
169 return radeon_atom_get_backlight_level_from_reg(rdev);
170}
171
172static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
175};
176
177void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
179{
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
186 u8 backlight_level;
614499b4 187 char bl_name[16];
f3728734
AD		 188
189 if (!radeon_encoder->enc_priv)
190 return;
191
192 if (!rdev->is_atom_bios)
193 return;
194
195 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
196 return;
197
198 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
199 if (!pdata) {
200 DRM_ERROR("Memory allocation failed\n");
201 goto error;
202 }
203
204 memset(&props, 0, sizeof(props));
205 props.max_brightness = RADEON_MAX_BL_LEVEL;
206 props.type = BACKLIGHT_RAW;
614499b4
AD		 207 snprintf(bl_name, sizeof(bl_name),
208 "radeon_bl%d", dev->primary->index);
209 bd = backlight_device_register(bl_name, &drm_connector->kdev,
f3728734
AD		 210 pdata, &radeon_atom_backlight_ops, &props);
211 if (IS_ERR(bd)) {
212 DRM_ERROR("Backlight registration failed\n");
213 goto error;
214 }
215
216 pdata->encoder = radeon_encoder;
217
218 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
219
220 dig = radeon_encoder->enc_priv;
221 dig->bl_dev = bd;
222
223 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
224 bd->props.power = FB_BLANK_UNBLANK;
225 backlight_update_status(bd);
226
227 DRM_INFO("radeon atom DIG backlight initialized\n");
228
229 return;
230
231error:
232 kfree(pdata);
233 return;
234}
235
236static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
237{
238 struct drm_device *dev = radeon_encoder->base.dev;
239 struct radeon_device *rdev = dev->dev_private;
240 struct backlight_device *bd = NULL;
241 struct radeon_encoder_atom_dig *dig;
242
243 if (!radeon_encoder->enc_priv)
244 return;
245
246 if (!rdev->is_atom_bios)
247 return;
248
249 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
250 return;
251
252 dig = radeon_encoder->enc_priv;
253 bd = dig->bl_dev;
254 dig->bl_dev = NULL;
255
256 if (bd) {
257 struct radeon_legacy_backlight_privdata *pdata;
258
259 pdata = bl_get_data(bd);
260 backlight_device_unregister(bd);
261 kfree(pdata);
262
263 DRM_INFO("radeon atom LVDS backlight unloaded\n");
264 }
265}
266
267#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
268
269void radeon_atom_backlight_init(struct radeon_encoder *encoder)
270{
271}
272
273static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
274{
275}
276
277#endif
278
3f03ced8
AD		 279/* evil but including atombios.h is much worse */
280bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
281 struct drm_display_mode *mode);
282
283
284static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
285{
286 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
287 switch (radeon_encoder->encoder_id) {
288 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
289 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
290 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
291 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
292 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
293 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
294 case ENCODER_OBJECT_ID_INTERNAL_DDI:
295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
299 return true;
300 default:
301 return false;
302 }
303}
304
3f03ced8 305static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 306 const struct drm_display_mode *mode,
3f03ced8
AD		 307 struct drm_display_mode *adjusted_mode)
308{
309 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
310 struct drm_device *dev = encoder->dev;
311 struct radeon_device *rdev = dev->dev_private;
312
313 /* set the active encoder to connector routing */
314 radeon_encoder_set_active_device(encoder);
315 drm_mode_set_crtcinfo(adjusted_mode, 0);
316
317 /* hw bug */
318 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
319 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
320 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
321
322 /* get the native mode for LVDS */
323 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
324 radeon_panel_mode_fixup(encoder, adjusted_mode);
325
326 /* get the native mode for TV */
327 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
328 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
329 if (tv_dac) {
330 if (tv_dac->tv_std == TV_STD_NTSC ||
331 tv_dac->tv_std == TV_STD_NTSC_J ||
332 tv_dac->tv_std == TV_STD_PAL_M)
333 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
334 else
335 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
336 }
337 }
338
339 if (ASIC_IS_DCE3(rdev) &&
340 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
341 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 343 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 344 }
345
346 return true;
347}
348
349static void
350atombios_dac_setup(struct drm_encoder *encoder, int action)
351{
352 struct drm_device *dev = encoder->dev;
353 struct radeon_device *rdev = dev->dev_private;
354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
355 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
356 int index = 0;
357 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
358
359 memset(&args, 0, sizeof(args));
360
361 switch (radeon_encoder->encoder_id) {
362 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
364 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
365 break;
366 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
368 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
369 break;
370 }
371
372 args.ucAction = action;
373
374 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
375 args.ucDacStandard = ATOM_DAC1_PS2;
376 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
377 args.ucDacStandard = ATOM_DAC1_CV;
378 else {
379 switch (dac_info->tv_std) {
380 case TV_STD_PAL:
381 case TV_STD_PAL_M:
382 case TV_STD_SCART_PAL:
383 case TV_STD_SECAM:
384 case TV_STD_PAL_CN:
385 args.ucDacStandard = ATOM_DAC1_PAL;
386 break;
387 case TV_STD_NTSC:
388 case TV_STD_NTSC_J:
389 case TV_STD_PAL_60:
390 default:
391 args.ucDacStandard = ATOM_DAC1_NTSC;
392 break;
393 }
394 }
395 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
396
397 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
398
399}
400
401static void
402atombios_tv_setup(struct drm_encoder *encoder, int action)
403{
404 struct drm_device *dev = encoder->dev;
405 struct radeon_device *rdev = dev->dev_private;
406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
407 TV_ENCODER_CONTROL_PS_ALLOCATION args;
408 int index = 0;
409 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
410
411 memset(&args, 0, sizeof(args));
412
413 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
414
415 args.sTVEncoder.ucAction = action;
416
417 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
418 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
419 else {
420 switch (dac_info->tv_std) {
421 case TV_STD_NTSC:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
423 break;
424 case TV_STD_PAL:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
426 break;
427 case TV_STD_PAL_M:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
429 break;
430 case TV_STD_PAL_60:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
432 break;
433 case TV_STD_NTSC_J:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
435 break;
436 case TV_STD_SCART_PAL:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
438 break;
439 case TV_STD_SECAM:
440 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
441 break;
442 case TV_STD_PAL_CN:
443 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
444 break;
445 default:
446 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
447 break;
448 }
449 }
450
451 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
452
453 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
454
455}
456
1f0e2943
AD		 457static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
458{
459 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
460 int bpc = 8;
461
462 if (connector)
463 bpc = radeon_get_monitor_bpc(connector);
464
465 switch (bpc) {
466 case 0:
467 return PANEL_BPC_UNDEFINE;
468 case 6:
469 return PANEL_6BIT_PER_COLOR;
470 case 8:
471 default:
472 return PANEL_8BIT_PER_COLOR;
473 case 10:
474 return PANEL_10BIT_PER_COLOR;
475 case 12:
476 return PANEL_12BIT_PER_COLOR;
477 case 16:
478 return PANEL_16BIT_PER_COLOR;
479 }
480}
481
482
3f03ced8
AD		 483union dvo_encoder_control {
484 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
485 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
486 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
487};
488
489void
490atombios_dvo_setup(struct drm_encoder *encoder, int action)
491{
492 struct drm_device *dev = encoder->dev;
493 struct radeon_device *rdev = dev->dev_private;
494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
495 union dvo_encoder_control args;
496 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 497 uint8_t frev, crev;
3f03ced8
AD		 498
499 memset(&args, 0, sizeof(args));
500
24153dd3
AD		 501 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
502 return;
503
afceb931
AD		 504 /* some R4xx chips have the wrong frev */
505 if (rdev->family <= CHIP_RV410)
506 frev = 1;
507
24153dd3
AD		 508 switch (frev) {
509 case 1:
510 switch (crev) {
511 case 1:
512 /* R4xx, R5xx */
513 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
514
9aa59993 515 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 516 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
517
518 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
519 break;
520 case 2:
521 /* RS600/690/740 */
522 args.dvo.sDVOEncoder.ucAction = action;
523 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
524 /* DFP1, CRT1, TV1 depending on the type of port */
525 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
526
9aa59993 527 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 528 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
529 break;
530 case 3:
531 /* R6xx */
532 args.dvo_v3.ucAction = action;
533 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
534 args.dvo_v3.ucDVOConfig = 0; /* XXX */
535 break;
536 default:
537 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
538 break;
539 }
540 break;
541 default:
542 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
543 break;
3f03ced8
AD		 544 }
545
546 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
547}
548
549union lvds_encoder_control {
550 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
551 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
552};
553
554void
555atombios_digital_setup(struct drm_encoder *encoder, int action)
556{
557 struct drm_device *dev = encoder->dev;
558 struct radeon_device *rdev = dev->dev_private;
559 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
560 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
561 union lvds_encoder_control args;
562 int index = 0;
563 int hdmi_detected = 0;
564 uint8_t frev, crev;
565
566 if (!dig)
567 return;
568
569 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
570 hdmi_detected = 1;
571
572 memset(&args, 0, sizeof(args));
573
574 switch (radeon_encoder->encoder_id) {
575 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
576 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
577 break;
578 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
580 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
581 break;
582 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
584 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 else
586 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
587 break;
588 }
589
590 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
591 return;
592
593 switch (frev) {
594 case 1:
595 case 2:
596 switch (crev) {
597 case 1:
598 args.v1.ucMisc = 0;
599 args.v1.ucAction = action;
600 if (hdmi_detected)
601 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
602 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
604 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
605 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
606 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
607 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
608 } else {
609 if (dig->linkb)
610 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 611 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 612 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
613 /*if (pScrn->rgbBits == 8) */
614 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
615 }
616 break;
617 case 2:
618 case 3:
619 args.v2.ucMisc = 0;
620 args.v2.ucAction = action;
621 if (crev == 3) {
622 if (dig->coherent_mode)
623 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
624 }
625 if (hdmi_detected)
626 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
627 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
628 args.v2.ucTruncate = 0;
629 args.v2.ucSpatial = 0;
630 args.v2.ucTemporal = 0;
631 args.v2.ucFRC = 0;
632 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
633 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
635 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
636 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
637 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
638 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
639 }
640 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
641 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
642 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
644 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
645 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
646 }
647 } else {
648 if (dig->linkb)
649 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 650 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 651 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
652 }
653 break;
654 default:
655 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
656 break;
657 }
658 break;
659 default:
660 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
661 break;
662 }
663
664 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
665}
666
667int
668atombios_get_encoder_mode(struct drm_encoder *encoder)
669{
670 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 671 struct drm_connector *connector;
672 struct radeon_connector *radeon_connector;
673 struct radeon_connector_atom_dig *dig_connector;
674
675 /* dp bridges are always DP */
676 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
677 return ATOM_ENCODER_MODE_DP;
678
679 /* DVO is always DVO */
a59fbb8e
AD		 680 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
681 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 682 return ATOM_ENCODER_MODE_DVO;
683
684 connector = radeon_get_connector_for_encoder(encoder);
685 /* if we don't have an active device yet, just use one of
686 * the connectors tied to the encoder.
687 */
688 if (!connector)
689 connector = radeon_get_connector_for_encoder_init(encoder);
690 radeon_connector = to_radeon_connector(connector);
691
692 switch (connector->connector_type) {
693 case DRM_MODE_CONNECTOR_DVII:
694 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 695 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 696 radeon_audio)
697 return ATOM_ENCODER_MODE_HDMI;
698 else if (radeon_connector->use_digital)
3f03ced8
AD		 699 return ATOM_ENCODER_MODE_DVI;
700 else
701 return ATOM_ENCODER_MODE_CRT;
702 break;
703 case DRM_MODE_CONNECTOR_DVID:
704 case DRM_MODE_CONNECTOR_HDMIA:
705 default:
27d9cc84 706 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 707 radeon_audio)
708 return ATOM_ENCODER_MODE_HDMI;
709 else
3f03ced8
AD		 710 return ATOM_ENCODER_MODE_DVI;
711 break;
712 case DRM_MODE_CONNECTOR_LVDS:
713 return ATOM_ENCODER_MODE_LVDS;
714 break;
715 case DRM_MODE_CONNECTOR_DisplayPort:
716 dig_connector = radeon_connector->con_priv;
717 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
718 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
719 return ATOM_ENCODER_MODE_DP;
27d9cc84 720 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 721 radeon_audio)
722 return ATOM_ENCODER_MODE_HDMI;
723 else
3f03ced8
AD		 724 return ATOM_ENCODER_MODE_DVI;
725 break;
726 case DRM_MODE_CONNECTOR_eDP:
727 return ATOM_ENCODER_MODE_DP;
728 case DRM_MODE_CONNECTOR_DVIA:
729 case DRM_MODE_CONNECTOR_VGA:
730 return ATOM_ENCODER_MODE_CRT;
731 break;
732 case DRM_MODE_CONNECTOR_Composite:
733 case DRM_MODE_CONNECTOR_SVIDEO:
734 case DRM_MODE_CONNECTOR_9PinDIN:
735 /* fix me */
736 return ATOM_ENCODER_MODE_TV;
737 /*return ATOM_ENCODER_MODE_CV;*/
738 break;
739 }
740}
741
742/*
743 * DIG Encoder/Transmitter Setup
744 *
745 * DCE 3.0/3.1
746 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
747 * Supports up to 3 digital outputs
748 * - 2 DIG encoder blocks.
749 * DIG1 can drive UNIPHY link A or link B
750 * DIG2 can drive UNIPHY link B or LVTMA
751 *
752 * DCE 3.2
753 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
754 * Supports up to 5 digital outputs
755 * - 2 DIG encoder blocks.
756 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
757 *
2d415869 758 * DCE 4.0/5.0/6.0
3f03ced8
AD		 759 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
760 * Supports up to 6 digital outputs
761 * - 6 DIG encoder blocks.
762 * - DIG to PHY mapping is hardcoded
763 * DIG1 drives UNIPHY0 link A, A+B
764 * DIG2 drives UNIPHY0 link B
765 * DIG3 drives UNIPHY1 link A, A+B
766 * DIG4 drives UNIPHY1 link B
767 * DIG5 drives UNIPHY2 link A, A+B
768 * DIG6 drives UNIPHY2 link B
769 *
770 * DCE 4.1
771 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
772 * Supports up to 6 digital outputs
773 * - 2 DIG encoder blocks.
2d415869 774 * llano
3f03ced8 775 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 776 * ontario
777 * DIG1 drives UNIPHY0/1/2 link A
778 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 779 *
780 * Routing
781 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
782 * Examples:
783 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
784 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
785 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
786 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
787 */
788
789union dig_encoder_control {
790 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
791 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
792 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
793 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
794};
795
796void
797atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
798{
799 struct drm_device *dev = encoder->dev;
800 struct radeon_device *rdev = dev->dev_private;
801 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
802 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
803 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
804 union dig_encoder_control args;
805 int index = 0;
806 uint8_t frev, crev;
807 int dp_clock = 0;
808 int dp_lane_count = 0;
809 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 810
811 if (connector) {
812 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
813 struct radeon_connector_atom_dig *dig_connector =
814 radeon_connector->con_priv;
815
816 dp_clock = dig_connector->dp_clock;
817 dp_lane_count = dig_connector->dp_lane_count;
818 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 819 }
820
821 /* no dig encoder assigned */
822 if (dig->dig_encoder == -1)
823 return;
824
825 memset(&args, 0, sizeof(args));
826
827 if (ASIC_IS_DCE4(rdev))
828 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
829 else {
830 if (dig->dig_encoder)
831 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
832 else
833 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
834 }
835
836 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
837 return;
838
58cdcb8b
AD		 839 switch (frev) {
840 case 1:
841 switch (crev) {
842 case 1:
843 args.v1.ucAction = action;
844 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
845 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
846 args.v3.ucPanelMode = panel_mode;
847 else
848 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
849
850 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
851 args.v1.ucLaneNum = dp_lane_count;
9aa59993 852 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 853 args.v1.ucLaneNum = 8;
854 else
855 args.v1.ucLaneNum = 4;
856
857 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
858 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
859 switch (radeon_encoder->encoder_id) {
860 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
861 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
862 break;
863 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
864 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
865 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
866 break;
867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
868 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
869 break;
870 }
871 if (dig->linkb)
872 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
873 else
874 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 875 break;
58cdcb8b
AD		 876 case 2:
877 case 3:
878 args.v3.ucAction = action;
879 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
880 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
881 args.v3.ucPanelMode = panel_mode;
882 else
883 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
884
2f6fa79a 885 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 886 args.v3.ucLaneNum = dp_lane_count;
9aa59993 887 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 888 args.v3.ucLaneNum = 8;
889 else
890 args.v3.ucLaneNum = 4;
891
2f6fa79a 892 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 893 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
894 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 895 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 896 break;
58cdcb8b
AD		 897 case 4:
898 args.v4.ucAction = action;
899 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
900 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
901 args.v4.ucPanelMode = panel_mode;
902 else
903 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
904
2f6fa79a 905 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 906 args.v4.ucLaneNum = dp_lane_count;
9aa59993 907 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 908 args.v4.ucLaneNum = 8;
909 else
910 args.v4.ucLaneNum = 4;
911
2f6fa79a 912 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
58cdcb8b
AD		 913 if (dp_clock == 270000)
914 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
915 else if (dp_clock == 540000)
916 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
917 }
918 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 919 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 920 if (hpd_id == RADEON_HPD_NONE)
921 args.v4.ucHPD_ID = 0;
922 else
923 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 924 break;
3f03ced8 925 default:
58cdcb8b 926 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 927 break;
928 }
58cdcb8b
AD		 929 break;
930 default:
931 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
932 break;
3f03ced8
AD		 933 }
934
935 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
936
937}
938
939union dig_transmitter_control {
940 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
941 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
942 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
943 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 944 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 945};
946
947void
948atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
949{
950 struct drm_device *dev = encoder->dev;
951 struct radeon_device *rdev = dev->dev_private;
952 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
953 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
954 struct drm_connector *connector;
955 union dig_transmitter_control args;
956 int index = 0;
957 uint8_t frev, crev;
958 bool is_dp = false;
959 int pll_id = 0;
960 int dp_clock = 0;
961 int dp_lane_count = 0;
962 int connector_object_id = 0;
963 int igp_lane_info = 0;
964 int dig_encoder = dig->dig_encoder;
47aef7a8 965 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 966
967 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
968 connector = radeon_get_connector_for_encoder_init(encoder);
969 /* just needed to avoid bailing in the encoder check. the encoder
970 * isn't used for init
971 */
972 dig_encoder = 0;
973 } else
974 connector = radeon_get_connector_for_encoder(encoder);
975
976 if (connector) {
977 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
978 struct radeon_connector_atom_dig *dig_connector =
979 radeon_connector->con_priv;
980
47aef7a8 981 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 982 dp_clock = dig_connector->dp_clock;
983 dp_lane_count = dig_connector->dp_lane_count;
984 connector_object_id =
985 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
986 igp_lane_info = dig_connector->igp_lane_info;
987 }
988
a3b08294
AD		 989 if (encoder->crtc) {
990 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
991 pll_id = radeon_crtc->pll_id;
992 }
993
3f03ced8
AD		 994 /* no dig encoder assigned */
995 if (dig_encoder == -1)
996 return;
997
998 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
999 is_dp = true;
1000
1001 memset(&args, 0, sizeof(args));
1002
1003 switch (radeon_encoder->encoder_id) {
1004 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1005 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1006 break;
1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1008 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1009 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1010 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1011 break;
1012 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1013 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1014 break;
1015 }
1016
1017 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1018 return;
1019
a3b08294
AD		 1020 switch (frev) {
1021 case 1:
1022 switch (crev) {
1023 case 1:
1024 args.v1.ucAction = action;
1025 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1026 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1027 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1028 args.v1.asMode.ucLaneSel = lane_num;
1029 args.v1.asMode.ucLaneSet = lane_set;
1030 } else {
1031 if (is_dp)
6e76a2df 1032 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1033 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1034 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1035 else
1036 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1037 }
3f03ced8 1038
a3b08294 1039 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1040
a3b08294
AD		 1041 if (dig_encoder)
1042 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1043 else
1044 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1045
1046 if ((rdev->flags & RADEON_IS_IGP) &&
1047 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1048 if (is_dp ||
1049 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1050 if (igp_lane_info & 0x1)
1051 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1052 else if (igp_lane_info & 0x2)
1053 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1054 else if (igp_lane_info & 0x4)
1055 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1056 else if (igp_lane_info & 0x8)
1057 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1058 } else {
1059 if (igp_lane_info & 0x3)
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1061 else if (igp_lane_info & 0xc)
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1063 }
1064 }
1065
1066 if (dig->linkb)
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1068 else
1069 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1070
1071 if (is_dp)
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1073 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1074 if (dig->coherent_mode)
1075 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1076 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1078 }
1079 break;
1080 case 2:
1081 args.v2.ucAction = action;
1082 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1083 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1084 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1085 args.v2.asMode.ucLaneSel = lane_num;
1086 args.v2.asMode.ucLaneSet = lane_set;
1087 } else {
1088 if (is_dp)
6e76a2df 1089 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1090 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1091 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1092 else
1093 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1094 }
1095
1096 args.v2.acConfig.ucEncoderSel = dig_encoder;
1097 if (dig->linkb)
1098 args.v2.acConfig.ucLinkSel = 1;
1099
1100 switch (radeon_encoder->encoder_id) {
1101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1102 args.v2.acConfig.ucTransmitterSel = 0;
1103 break;
1104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1105 args.v2.acConfig.ucTransmitterSel = 1;
1106 break;
1107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1108 args.v2.acConfig.ucTransmitterSel = 2;
1109 break;
1110 }
3f03ced8 1111
3f03ced8 1112 if (is_dp) {
a3b08294
AD		 1113 args.v2.acConfig.fCoherentMode = 1;
1114 args.v2.acConfig.fDPConnector = 1;
1115 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1116 if (dig->coherent_mode)
1117 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1118 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1119 args.v2.acConfig.fDualLinkConnector = 1;
1120 }
1121 break;
1122 case 3:
1123 args.v3.ucAction = action;
1124 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1125 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1126 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1127 args.v3.asMode.ucLaneSel = lane_num;
1128 args.v3.asMode.ucLaneSet = lane_set;
1129 } else {
1130 if (is_dp)
6e76a2df 1131 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1132 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1133 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1134 else
a3b08294
AD		 1135 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1136 }
1137
1138 if (is_dp)
1139 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1140 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1141 args.v3.ucLaneNum = 8;
1142 else
1143 args.v3.ucLaneNum = 4;
1144
1145 if (dig->linkb)
1146 args.v3.acConfig.ucLinkSel = 1;
1147 if (dig_encoder & 1)
1148 args.v3.acConfig.ucEncoderSel = 1;
1149
1150 /* Select the PLL for the PHY
1151 * DP PHY should be clocked from external src if there is
1152 * one.
1153 */
3f03ced8
AD		 1154 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1155 if (is_dp && rdev->clock.dp_extclk)
1156 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1157 else
1158 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1159
a3b08294
AD		 1160 switch (radeon_encoder->encoder_id) {
1161 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1162 args.v3.acConfig.ucTransmitterSel = 0;
1163 break;
1164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1165 args.v3.acConfig.ucTransmitterSel = 1;
1166 break;
1167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1168 args.v3.acConfig.ucTransmitterSel = 2;
1169 break;
1170 }
3f03ced8 1171
a3b08294
AD		 1172 if (is_dp)
1173 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1174 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1175 if (dig->coherent_mode)
1176 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1177 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1178 args.v3.acConfig.fDualLinkConnector = 1;
1179 }
3f03ced8 1180 break;
a3b08294
AD		 1181 case 4:
1182 args.v4.ucAction = action;
1183 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1184 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1185 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1186 args.v4.asMode.ucLaneSel = lane_num;
1187 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1188 } else {
a3b08294 1189 if (is_dp)
6e76a2df 1190 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1191 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1192 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1193 else
1194 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1195 }
3f03ced8 1196
a3b08294
AD		 1197 if (is_dp)
1198 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1199 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1200 args.v4.ucLaneNum = 8;
1201 else
1202 args.v4.ucLaneNum = 4;
3f03ced8 1203
a3b08294
AD		 1204 if (dig->linkb)
1205 args.v4.acConfig.ucLinkSel = 1;
1206 if (dig_encoder & 1)
1207 args.v4.acConfig.ucEncoderSel = 1;
1208
1209 /* Select the PLL for the PHY
1210 * DP PHY should be clocked from external src if there is
1211 * one.
1212 */
1213 /* On DCE5 DCPLL usually generates the DP ref clock */
1214 if (is_dp) {
1215 if (rdev->clock.dp_extclk)
1216 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1217 else
1218 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1219 } else
1220 args.v4.acConfig.ucRefClkSource = pll_id;
1221
1222 switch (radeon_encoder->encoder_id) {
1223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1224 args.v4.acConfig.ucTransmitterSel = 0;
1225 break;
1226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1227 args.v4.acConfig.ucTransmitterSel = 1;
1228 break;
1229 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1230 args.v4.acConfig.ucTransmitterSel = 2;
1231 break;
1232 }
1233
1234 if (is_dp)
1235 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1236 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1237 if (dig->coherent_mode)
1238 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1239 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1240 args.v4.acConfig.fDualLinkConnector = 1;
1241 }
1242 break;
47aef7a8
AD		 1243 case 5:
1244 args.v5.ucAction = action;
1245 if (is_dp)
1246 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1247 else
1248 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1249
1250 switch (radeon_encoder->encoder_id) {
1251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1252 if (dig->linkb)
1253 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1254 else
1255 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1256 break;
1257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1258 if (dig->linkb)
1259 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1260 else
1261 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1262 break;
1263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1264 if (dig->linkb)
1265 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1266 else
1267 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1268 break;
1269 }
1270 if (is_dp)
1271 args.v5.ucLaneNum = dp_lane_count;
1272 else if (radeon_encoder->pixel_clock > 165000)
1273 args.v5.ucLaneNum = 8;
1274 else
1275 args.v5.ucLaneNum = 4;
1276 args.v5.ucConnObjId = connector_object_id;
1277 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1278
1279 if (is_dp && rdev->clock.dp_extclk)
1280 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1281 else
1282 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1283
1284 if (is_dp)
1285 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1286 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1287 if (dig->coherent_mode)
1288 args.v5.asConfig.ucCoherentMode = 1;
1289 }
1290 if (hpd_id == RADEON_HPD_NONE)
1291 args.v5.asConfig.ucHPDSel = 0;
1292 else
1293 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1294 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1295 args.v5.ucDPLaneSet = lane_set;
1296 break;
a3b08294
AD		 1297 default:
1298 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1299 break;
3f03ced8 1300 }
a3b08294
AD		 1301 break;
1302 default:
1303 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1304 break;
3f03ced8
AD		 1305 }
1306
1307 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1308}
1309
1310bool
1311atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1312{
1313 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1314 struct drm_device *dev = radeon_connector->base.dev;
1315 struct radeon_device *rdev = dev->dev_private;
1316 union dig_transmitter_control args;
1317 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1318 uint8_t frev, crev;
1319
1320 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1321 goto done;
1322
1323 if (!ASIC_IS_DCE4(rdev))
1324 goto done;
1325
1326 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1327 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1328 goto done;
1329
1330 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1331 goto done;
1332
1333 memset(&args, 0, sizeof(args));
1334
1335 args.v1.ucAction = action;
1336
1337 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1338
1339 /* wait for the panel to power up */
1340 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1341 int i;
1342
1343 for (i = 0; i < 300; i++) {
1344 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1345 return true;
1346 mdelay(1);
1347 }
1348 return false;
1349 }
1350done:
1351 return true;
1352}
1353
1354union external_encoder_control {
1355 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1356 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1357};
1358
1359static void
1360atombios_external_encoder_setup(struct drm_encoder *encoder,
1361 struct drm_encoder *ext_encoder,
1362 int action)
1363{
1364 struct drm_device *dev = encoder->dev;
1365 struct radeon_device *rdev = dev->dev_private;
1366 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1367 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1368 union external_encoder_control args;
1369 struct drm_connector *connector;
1370 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1371 u8 frev, crev;
1372 int dp_clock = 0;
1373 int dp_lane_count = 0;
1374 int connector_object_id = 0;
1375 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1376
1377 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1378 connector = radeon_get_connector_for_encoder_init(encoder);
1379 else
1380 connector = radeon_get_connector_for_encoder(encoder);
1381
1382 if (connector) {
1383 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1384 struct radeon_connector_atom_dig *dig_connector =
1385 radeon_connector->con_priv;
1386
1387 dp_clock = dig_connector->dp_clock;
1388 dp_lane_count = dig_connector->dp_lane_count;
1389 connector_object_id =
1390 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1391 }
1392
1393 memset(&args, 0, sizeof(args));
1394
1395 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1396 return;
1397
1398 switch (frev) {
1399 case 1:
1400 /* no params on frev 1 */
1401 break;
1402 case 2:
1403 switch (crev) {
1404 case 1:
1405 case 2:
1406 args.v1.sDigEncoder.ucAction = action;
1407 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1408 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1409
1410 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1411 if (dp_clock == 270000)
1412 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1413 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1414 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1415 args.v1.sDigEncoder.ucLaneNum = 8;
1416 else
1417 args.v1.sDigEncoder.ucLaneNum = 4;
1418 break;
1419 case 3:
1420 args.v3.sExtEncoder.ucAction = action;
1421 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1422 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1423 else
1424 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1425 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1426
1427 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1428 if (dp_clock == 270000)
1429 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1430 else if (dp_clock == 540000)
1431 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1432 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1433 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1434 args.v3.sExtEncoder.ucLaneNum = 8;
1435 else
1436 args.v3.sExtEncoder.ucLaneNum = 4;
1437 switch (ext_enum) {
1438 case GRAPH_OBJECT_ENUM_ID1:
1439 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1440 break;
1441 case GRAPH_OBJECT_ENUM_ID2:
1442 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1443 break;
1444 case GRAPH_OBJECT_ENUM_ID3:
1445 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1446 break;
1447 }
1f0e2943 1448 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1449 break;
1450 default:
1451 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1452 return;
1453 }
1454 break;
1455 default:
1456 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1457 return;
1458 }
1459 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1460}
1461
1462static void
1463atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1464{
1465 struct drm_device *dev = encoder->dev;
1466 struct radeon_device *rdev = dev->dev_private;
1467 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1468 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1469 ENABLE_YUV_PS_ALLOCATION args;
1470 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1471 uint32_t temp, reg;
1472
1473 memset(&args, 0, sizeof(args));
1474
1475 if (rdev->family >= CHIP_R600)
1476 reg = R600_BIOS_3_SCRATCH;
1477 else
1478 reg = RADEON_BIOS_3_SCRATCH;
1479
1480 /* XXX: fix up scratch reg handling */
1481 temp = RREG32(reg);
1482 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1483 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1484 (radeon_crtc->crtc_id << 18)));
1485 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1486 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1487 else
1488 WREG32(reg, 0);
1489
1490 if (enable)
1491 args.ucEnable = ATOM_ENABLE;
1492 args.ucCRTC = radeon_crtc->crtc_id;
1493
1494 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1495
1496 WREG32(reg, temp);
1497}
1498
1499static void
1500radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1501{
1502 struct drm_device *dev = encoder->dev;
1503 struct radeon_device *rdev = dev->dev_private;
1504 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1505 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1506 int index = 0;
1507
1508 memset(&args, 0, sizeof(args));
1509
1510 switch (radeon_encoder->encoder_id) {
1511 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1513 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1514 break;
1515 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1516 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1518 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1519 break;
1520 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1521 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1522 break;
1523 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1524 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1525 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1526 else
1527 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1528 break;
1529 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1530 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1531 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1532 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1533 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1534 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1535 else
1536 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1537 break;
1538 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1540 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1541 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1542 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1543 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1544 else
1545 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1546 break;
1547 default:
1548 return;
1549 }
1550
1551 switch (mode) {
1552 case DRM_MODE_DPMS_ON:
1553 args.ucAction = ATOM_ENABLE;
1554 /* workaround for DVOOutputControl on some RS690 systems */
1555 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1556 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1557 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1558 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1559 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1560 } else
1561 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1562 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1563 args.ucAction = ATOM_LCD_BLON;
1564 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1565 }
1566 break;
1567 case DRM_MODE_DPMS_STANDBY:
1568 case DRM_MODE_DPMS_SUSPEND:
1569 case DRM_MODE_DPMS_OFF:
1570 args.ucAction = ATOM_DISABLE;
1571 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1573 args.ucAction = ATOM_LCD_BLOFF;
1574 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1575 }
1576 break;
1577 }
1578}
1579
1580static void
1581radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1582{
1583 struct drm_device *dev = encoder->dev;
1584 struct radeon_device *rdev = dev->dev_private;
1585 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1586 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1587 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1588 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1589 struct radeon_connector *radeon_connector = NULL;
1590 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1591
1592 if (connector) {
1593 radeon_connector = to_radeon_connector(connector);
1594 radeon_dig_connector = radeon_connector->con_priv;
1595 }
1596
1597 switch (mode) {
1598 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1599 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1600 if (!connector)
1601 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1602 else
1603 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1604
1605 /* setup and enable the encoder */
1606 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1607 atombios_dig_encoder_setup(encoder,
1608 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1609 dig->panel_mode);
1610 if (ext_encoder) {
1611 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1612 atombios_external_encoder_setup(encoder, ext_encoder,
1613 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1614 }
3f03ced8 1615 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1616 } else if (ASIC_IS_DCE4(rdev)) {
1617 /* setup and enable the encoder */
1618 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1619 /* enable the transmitter */
1620 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1621 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1622 } else {
1623 /* setup and enable the encoder and transmitter */
1624 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1627 /* some early dce3.2 boards have a bug in their transmitter control table */
b9196395 1628 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
8d1af57a 1629 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1630 }
3f03ced8
AD		 1631 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1632 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1633 atombios_set_edp_panel_power(connector,
1634 ATOM_TRANSMITTER_ACTION_POWER_ON);
1635 radeon_dig_connector->edp_on = true;
1636 }
3f03ced8
AD		 1637 radeon_dp_link_train(encoder, connector);
1638 if (ASIC_IS_DCE4(rdev))
1639 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1640 }
1641 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1642 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1643 break;
1644 case DRM_MODE_DPMS_STANDBY:
1645 case DRM_MODE_DPMS_SUSPEND:
1646 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1647 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1648 /* disable the transmitter */
3a47824d 1649 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1650 } else if (ASIC_IS_DCE4(rdev)) {
1651 /* disable the transmitter */
1652 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1653 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1654 } else {
1655 /* disable the encoder and transmitter */
3a47824d 1656 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1657 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1658 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1659 }
3f03ced8
AD		 1660 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1661 if (ASIC_IS_DCE4(rdev))
1662 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1663 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1664 atombios_set_edp_panel_power(connector,
1665 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1666 radeon_dig_connector->edp_on = false;
1667 }
1668 }
1669 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1670 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1671 break;
1672 }
1673}
1674
1675static void
1676radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1677 struct drm_encoder *ext_encoder,
1678 int mode)
1679{
1680 struct drm_device *dev = encoder->dev;
1681 struct radeon_device *rdev = dev->dev_private;
1682
1683 switch (mode) {
1684 case DRM_MODE_DPMS_ON:
1685 default:
1d3949c4 1686 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1687 atombios_external_encoder_setup(encoder, ext_encoder,
1688 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1689 atombios_external_encoder_setup(encoder, ext_encoder,
1690 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1691 } else
1692 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1693 break;
1694 case DRM_MODE_DPMS_STANDBY:
1695 case DRM_MODE_DPMS_SUSPEND:
1696 case DRM_MODE_DPMS_OFF:
1d3949c4 1697 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1698 atombios_external_encoder_setup(encoder, ext_encoder,
1699 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1700 atombios_external_encoder_setup(encoder, ext_encoder,
1701 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1702 } else
1703 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1704 break;
1705 }
1706}
1707
1708static void
1709radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1710{
1711 struct drm_device *dev = encoder->dev;
1712 struct radeon_device *rdev = dev->dev_private;
1713 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1714 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1715
1716 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1717 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1718 radeon_encoder->active_device);
1719 switch (radeon_encoder->encoder_id) {
1720 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1721 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1722 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1723 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1724 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1725 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1726 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1728 radeon_atom_encoder_dpms_avivo(encoder, mode);
1729 break;
1730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1731 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1732 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1734 radeon_atom_encoder_dpms_dig(encoder, mode);
1735 break;
1736 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1737 if (ASIC_IS_DCE5(rdev)) {
1738 switch (mode) {
1739 case DRM_MODE_DPMS_ON:
1740 atombios_dvo_setup(encoder, ATOM_ENABLE);
1741 break;
1742 case DRM_MODE_DPMS_STANDBY:
1743 case DRM_MODE_DPMS_SUSPEND:
1744 case DRM_MODE_DPMS_OFF:
1745 atombios_dvo_setup(encoder, ATOM_DISABLE);
1746 break;
1747 }
1748 } else if (ASIC_IS_DCE3(rdev))
1749 radeon_atom_encoder_dpms_dig(encoder, mode);
1750 else
1751 radeon_atom_encoder_dpms_avivo(encoder, mode);
1752 break;
1753 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1754 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1755 if (ASIC_IS_DCE5(rdev)) {
1756 switch (mode) {
1757 case DRM_MODE_DPMS_ON:
1758 atombios_dac_setup(encoder, ATOM_ENABLE);
1759 break;
1760 case DRM_MODE_DPMS_STANDBY:
1761 case DRM_MODE_DPMS_SUSPEND:
1762 case DRM_MODE_DPMS_OFF:
1763 atombios_dac_setup(encoder, ATOM_DISABLE);
1764 break;
1765 }
1766 } else
1767 radeon_atom_encoder_dpms_avivo(encoder, mode);
1768 break;
1769 default:
1770 return;
1771 }
1772
1773 if (ext_encoder)
1774 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1775
1776 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1777
1778}
1779
1780union crtc_source_param {
1781 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1782 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1783};
1784
1785static void
1786atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1787{
1788 struct drm_device *dev = encoder->dev;
1789 struct radeon_device *rdev = dev->dev_private;
1790 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1791 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1792 union crtc_source_param args;
1793 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1794 uint8_t frev, crev;
1795 struct radeon_encoder_atom_dig *dig;
1796
1797 memset(&args, 0, sizeof(args));
1798
1799 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1800 return;
1801
1802 switch (frev) {
1803 case 1:
1804 switch (crev) {
1805 case 1:
1806 default:
1807 if (ASIC_IS_AVIVO(rdev))
1808 args.v1.ucCRTC = radeon_crtc->crtc_id;
1809 else {
1810 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1811 args.v1.ucCRTC = radeon_crtc->crtc_id;
1812 } else {
1813 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1814 }
1815 }
1816 switch (radeon_encoder->encoder_id) {
1817 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1818 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1819 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1820 break;
1821 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1822 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1823 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1824 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1825 else
1826 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1827 break;
1828 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1829 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1830 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1831 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1832 break;
1833 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1834 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1835 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1836 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1837 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1838 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1839 else
1840 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1841 break;
1842 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1843 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1844 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1845 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1846 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1847 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1848 else
1849 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1850 break;
1851 }
1852 break;
1853 case 2:
1854 args.v2.ucCRTC = radeon_crtc->crtc_id;
1855 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1856 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1857
1858 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1859 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1860 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1861 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1862 else
1863 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1864 } else
1865 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1866 switch (radeon_encoder->encoder_id) {
1867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1869 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1870 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1871 dig = radeon_encoder->enc_priv;
1872 switch (dig->dig_encoder) {
1873 case 0:
1874 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1875 break;
1876 case 1:
1877 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1878 break;
1879 case 2:
1880 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1881 break;
1882 case 3:
1883 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1884 break;
1885 case 4:
1886 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1887 break;
1888 case 5:
1889 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1890 break;
1891 }
1892 break;
1893 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1894 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1895 break;
1896 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1897 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1898 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1899 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1900 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1901 else
1902 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1903 break;
1904 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1905 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1906 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1907 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1908 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1909 else
1910 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1911 break;
1912 }
1913 break;
1914 }
1915 break;
1916 default:
1917 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1918 return;
1919 }
1920
1921 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1922
1923 /* update scratch regs with new routing */
1924 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1925}
1926
1927static void
1928atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1929 struct drm_display_mode *mode)
1930{
1931 struct drm_device *dev = encoder->dev;
1932 struct radeon_device *rdev = dev->dev_private;
1933 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1934 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1935
1936 /* Funky macbooks */
1937 if ((dev->pdev->device == 0x71C5) &&
1938 (dev->pdev->subsystem_vendor == 0x106b) &&
1939 (dev->pdev->subsystem_device == 0x0080)) {
1940 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1941 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1942
1943 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1944 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1945
1946 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1947 }
1948 }
1949
1950 /* set scaler clears this on some chips */
1951 if (ASIC_IS_AVIVO(rdev) &&
1952 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1953 if (ASIC_IS_DCE4(rdev)) {
1954 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1955 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1956 EVERGREEN_INTERLEAVE_EN);
1957 else
1958 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1959 } else {
1960 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1961 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1962 AVIVO_D1MODE_INTERLEAVE_EN);
1963 else
1964 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1965 }
1966 }
1967}
1968
1969static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1970{
1971 struct drm_device *dev = encoder->dev;
1972 struct radeon_device *rdev = dev->dev_private;
1973 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1974 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1975 struct drm_encoder *test_encoder;
41fa5437 1976 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1977 uint32_t dig_enc_in_use = 0;
1978
41fa5437
AD		 1979 if (ASIC_IS_DCE6(rdev)) {
1980 /* DCE6 */
1981 switch (radeon_encoder->encoder_id) {
1982 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1983 if (dig->linkb)
1984 return 1;
1985 else
1986 return 0;
1987 break;
1988 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1989 if (dig->linkb)
1990 return 3;
1991 else
1992 return 2;
1993 break;
1994 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1995 if (dig->linkb)
1996 return 5;
1997 else
1998 return 4;
1999 break;
2000 }
2001 } else if (ASIC_IS_DCE4(rdev)) {
2002 /* DCE4/5 */
2003 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2004 /* ontario follows DCE4 */
2005 if (rdev->family == CHIP_PALM) {
2006 if (dig->linkb)
2007 return 1;
2008 else
2009 return 0;
2010 } else
2011 /* llano follows DCE3.2 */
2012 return radeon_crtc->crtc_id;
2013 } else {
2014 switch (radeon_encoder->encoder_id) {
2015 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2016 if (dig->linkb)
2017 return 1;
2018 else
2019 return 0;
2020 break;
2021 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2022 if (dig->linkb)
2023 return 3;
2024 else
2025 return 2;
2026 break;
2027 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2028 if (dig->linkb)
2029 return 5;
2030 else
2031 return 4;
2032 break;
2033 }
2034 }
2035 }
2036
2037 /* on DCE32 and encoder can driver any block so just crtc id */
2038 if (ASIC_IS_DCE32(rdev)) {
2039 return radeon_crtc->crtc_id;
2040 }
2041
2042 /* on DCE3 - LVTMA can only be driven by DIGB */
2043 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2044 struct radeon_encoder *radeon_test_encoder;
2045
2046 if (encoder == test_encoder)
2047 continue;
2048
2049 if (!radeon_encoder_is_digital(test_encoder))
2050 continue;
2051
2052 radeon_test_encoder = to_radeon_encoder(test_encoder);
2053 dig = radeon_test_encoder->enc_priv;
2054
2055 if (dig->dig_encoder >= 0)
2056 dig_enc_in_use |= (1 << dig->dig_encoder);
2057 }
2058
2059 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2060 if (dig_enc_in_use & 0x2)
2061 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2062 return 1;
2063 }
2064 if (!(dig_enc_in_use & 1))
2065 return 0;
2066 return 1;
2067}
2068
2069/* This only needs to be called once at startup */
2070void
2071radeon_atom_encoder_init(struct radeon_device *rdev)
2072{
2073 struct drm_device *dev = rdev->ddev;
2074 struct drm_encoder *encoder;
2075
2076 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2077 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2078 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2079
2080 switch (radeon_encoder->encoder_id) {
2081 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2083 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2084 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2085 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2086 break;
2087 default:
2088 break;
2089 }
2090
1d3949c4 2091 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2092 atombios_external_encoder_setup(encoder, ext_encoder,
2093 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2094 }
2095}
2096
2097static void
2098radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2099 struct drm_display_mode *mode,
2100 struct drm_display_mode *adjusted_mode)
2101{
2102 struct drm_device *dev = encoder->dev;
2103 struct radeon_device *rdev = dev->dev_private;
2104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2105
2106 radeon_encoder->pixel_clock = adjusted_mode->clock;
2107
8d1af57a
AD		 2108 /* need to call this here rather than in prepare() since we need some crtc info */
2109 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2110
3f03ced8
AD		 2111 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2112 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2113 atombios_yuv_setup(encoder, true);
2114 else
2115 atombios_yuv_setup(encoder, false);
2116 }
2117
2118 switch (radeon_encoder->encoder_id) {
2119 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2121 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2122 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2123 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2124 break;
2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2128 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2129 /* handled in dpms */
3f03ced8
AD		 2130 break;
2131 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2132 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2133 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2134 atombios_dvo_setup(encoder, ATOM_ENABLE);
2135 break;
2136 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2137 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2138 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2139 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2140 atombios_dac_setup(encoder, ATOM_ENABLE);
2141 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2142 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2143 atombios_tv_setup(encoder, ATOM_ENABLE);
2144 else
2145 atombios_tv_setup(encoder, ATOM_DISABLE);
2146 }
2147 break;
2148 }
2149
3f03ced8
AD		 2150 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2151
2152 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2153 r600_hdmi_enable(encoder);
6b53a050
RM		 2154 if (ASIC_IS_DCE6(rdev))
2155 ; /* TODO (use pointers instead of if-s?) */
2156 else if (ASIC_IS_DCE4(rdev))
e55d3e6c
RM		 2157 evergreen_hdmi_setmode(encoder, adjusted_mode);
2158 else
2159 r600_hdmi_setmode(encoder, adjusted_mode);
3f03ced8
AD		 2160 }
2161}
2162
2163static bool
2164atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2165{
2166 struct drm_device *dev = encoder->dev;
2167 struct radeon_device *rdev = dev->dev_private;
2168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2169 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2170
2171 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2172 ATOM_DEVICE_CV_SUPPORT |
2173 ATOM_DEVICE_CRT_SUPPORT)) {
2174 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2175 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2176 uint8_t frev, crev;
2177
2178 memset(&args, 0, sizeof(args));
2179
2180 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2181 return false;
2182
2183 args.sDacload.ucMisc = 0;
2184
2185 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2186 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2187 args.sDacload.ucDacType = ATOM_DAC_A;
2188 else
2189 args.sDacload.ucDacType = ATOM_DAC_B;
2190
2191 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2192 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2193 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2194 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2195 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2196 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2197 if (crev >= 3)
2198 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2199 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2200 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2201 if (crev >= 3)
2202 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2203 }
2204
2205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2206
2207 return true;
2208 } else
2209 return false;
2210}
2211
2212static enum drm_connector_status
2213radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2214{
2215 struct drm_device *dev = encoder->dev;
2216 struct radeon_device *rdev = dev->dev_private;
2217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2218 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2219 uint32_t bios_0_scratch;
2220
2221 if (!atombios_dac_load_detect(encoder, connector)) {
2222 DRM_DEBUG_KMS("detect returned false \n");
2223 return connector_status_unknown;
2224 }
2225
2226 if (rdev->family >= CHIP_R600)
2227 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2228 else
2229 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2230
2231 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2232 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2233 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2234 return connector_status_connected;
2235 }
2236 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2237 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2238 return connector_status_connected;
2239 }
2240 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2241 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2242 return connector_status_connected;
2243 }
2244 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2245 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2246 return connector_status_connected; /* CTV */
2247 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2248 return connector_status_connected; /* STV */
2249 }
2250 return connector_status_disconnected;
2251}
2252
2253static enum drm_connector_status
2254radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2255{
2256 struct drm_device *dev = encoder->dev;
2257 struct radeon_device *rdev = dev->dev_private;
2258 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2259 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2260 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2261 u32 bios_0_scratch;
2262
2263 if (!ASIC_IS_DCE4(rdev))
2264 return connector_status_unknown;
2265
2266 if (!ext_encoder)
2267 return connector_status_unknown;
2268
2269 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2270 return connector_status_unknown;
2271
2272 /* load detect on the dp bridge */
2273 atombios_external_encoder_setup(encoder, ext_encoder,
2274 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2275
2276 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2277
2278 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2279 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2280 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2281 return connector_status_connected;
2282 }
2283 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2284 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2285 return connector_status_connected;
2286 }
2287 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2288 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2289 return connector_status_connected;
2290 }
2291 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2292 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2293 return connector_status_connected; /* CTV */
2294 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2295 return connector_status_connected; /* STV */
2296 }
2297 return connector_status_disconnected;
2298}
2299
2300void
2301radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2302{
2303 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2304
2305 if (ext_encoder)
2306 /* ddc_setup on the dp bridge */
2307 atombios_external_encoder_setup(encoder, ext_encoder,
2308 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2309
2310}
2311
2312static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2313{
cfcbd6d3 2314 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2315 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2316 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2317
2318 if ((radeon_encoder->active_device &
2319 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2320 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2321 ENCODER_OBJECT_ID_NONE)) {
2322 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2323 if (dig) {
3f03ced8 2324 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2325 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2326 if (rdev->family >= CHIP_R600)
2327 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2328 else
2329 /* RS600/690/740 have only 1 afmt block */
2330 dig->afmt = rdev->mode_info.afmt[0];
2331 }
2332 }
3f03ced8
AD		 2333 }
2334
2335 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2336
2337 if (connector) {
2338 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2339
2340 /* select the clock/data port if it uses a router */
2341 if (radeon_connector->router.cd_valid)
2342 radeon_router_select_cd_port(radeon_connector);
2343
2344 /* turn eDP panel on for mode set */
2345 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2346 atombios_set_edp_panel_power(connector,
2347 ATOM_TRANSMITTER_ACTION_POWER_ON);
2348 }
2349
2350 /* this is needed for the pll/ss setup to work correctly in some cases */
2351 atombios_set_encoder_crtc_source(encoder);
2352}
2353
2354static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2355{
8d1af57a 2356 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2357 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2358 radeon_atom_output_lock(encoder, false);
2359}
2360
2361static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2362{
2363 struct drm_device *dev = encoder->dev;
2364 struct radeon_device *rdev = dev->dev_private;
2365 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2366 struct radeon_encoder_atom_dig *dig;
2367
2368 /* check for pre-DCE3 cards with shared encoders;
2369 * can't really use the links individually, so don't disable
2370 * the encoder if it's in use by another connector
2371 */
2372 if (!ASIC_IS_DCE3(rdev)) {
2373 struct drm_encoder *other_encoder;
2374 struct radeon_encoder *other_radeon_encoder;
2375
2376 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2377 other_radeon_encoder = to_radeon_encoder(other_encoder);
2378 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2379 drm_helper_encoder_in_use(other_encoder))
2380 goto disable_done;
2381 }
2382 }
2383
2384 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2385
2386 switch (radeon_encoder->encoder_id) {
2387 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2388 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2389 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2390 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2391 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2392 break;
2393 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2394 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2395 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2397 /* handled in dpms */
3f03ced8
AD		 2398 break;
2399 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2400 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2402 atombios_dvo_setup(encoder, ATOM_DISABLE);
2403 break;
2404 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2405 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2406 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2407 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2408 atombios_dac_setup(encoder, ATOM_DISABLE);
2409 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2410 atombios_tv_setup(encoder, ATOM_DISABLE);
2411 break;
2412 }
2413
2414disable_done:
2415 if (radeon_encoder_is_digital(encoder)) {
2416 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2417 r600_hdmi_disable(encoder);
2418 dig = radeon_encoder->enc_priv;
2419 dig->dig_encoder = -1;
2420 }
2421 radeon_encoder->active_device = 0;
2422}
2423
2424/* these are handled by the primary encoders */
2425static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2426{
2427
2428}
2429
2430static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2431{
2432
2433}
2434
2435static void
2436radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2437 struct drm_display_mode *mode,
2438 struct drm_display_mode *adjusted_mode)
2439{
2440
2441}
2442
2443static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2444{
2445
2446}
2447
2448static void
2449radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2450{
2451
2452}
2453
2454static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2455 const struct drm_display_mode *mode,
3f03ced8
AD		 2456 struct drm_display_mode *adjusted_mode)
2457{
2458 return true;
2459}
2460
2461static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2462 .dpms = radeon_atom_ext_dpms,
2463 .mode_fixup = radeon_atom_ext_mode_fixup,
2464 .prepare = radeon_atom_ext_prepare,
2465 .mode_set = radeon_atom_ext_mode_set,
2466 .commit = radeon_atom_ext_commit,
2467 .disable = radeon_atom_ext_disable,
2468 /* no detect for TMDS/LVDS yet */
2469};
2470
2471static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2472 .dpms = radeon_atom_encoder_dpms,
2473 .mode_fixup = radeon_atom_mode_fixup,
2474 .prepare = radeon_atom_encoder_prepare,
2475 .mode_set = radeon_atom_encoder_mode_set,
2476 .commit = radeon_atom_encoder_commit,
2477 .disable = radeon_atom_encoder_disable,
2478 .detect = radeon_atom_dig_detect,
2479};
2480
2481static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2482 .dpms = radeon_atom_encoder_dpms,
2483 .mode_fixup = radeon_atom_mode_fixup,
2484 .prepare = radeon_atom_encoder_prepare,
2485 .mode_set = radeon_atom_encoder_mode_set,
2486 .commit = radeon_atom_encoder_commit,
2487 .detect = radeon_atom_dac_detect,
2488};
2489
2490void radeon_enc_destroy(struct drm_encoder *encoder)
2491{
2492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2493 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2494 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2495 kfree(radeon_encoder->enc_priv);
2496 drm_encoder_cleanup(encoder);
2497 kfree(radeon_encoder);
2498}
2499
2500static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2501 .destroy = radeon_enc_destroy,
2502};
2503
1109ca09 2504static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2505radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2506{
2507 struct drm_device *dev = radeon_encoder->base.dev;
2508 struct radeon_device *rdev = dev->dev_private;
2509 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2510
2511 if (!dac)
2512 return NULL;
2513
2514 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2515 return dac;
2516}
2517
1109ca09 2518static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2519radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2520{
2521 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2522 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2523
2524 if (!dig)
2525 return NULL;
2526
2527 /* coherent mode by default */
2528 dig->coherent_mode = true;
2529 dig->dig_encoder = -1;
2530
2531 if (encoder_enum == 2)
2532 dig->linkb = true;
2533 else
2534 dig->linkb = false;
2535
2536 return dig;
2537}
2538
2539void
2540radeon_add_atom_encoder(struct drm_device *dev,
2541 uint32_t encoder_enum,
2542 uint32_t supported_device,
2543 u16 caps)
2544{
2545 struct radeon_device *rdev = dev->dev_private;
2546 struct drm_encoder *encoder;
2547 struct radeon_encoder *radeon_encoder;
2548
2549 /* see if we already added it */
2550 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2551 radeon_encoder = to_radeon_encoder(encoder);
2552 if (radeon_encoder->encoder_enum == encoder_enum) {
2553 radeon_encoder->devices |= supported_device;
2554 return;
2555 }
2556
2557 }
2558
2559 /* add a new one */
2560 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2561 if (!radeon_encoder)
2562 return;
2563
2564 encoder = &radeon_encoder->base;
2565 switch (rdev->num_crtc) {
2566 case 1:
2567 encoder->possible_crtcs = 0x1;
2568 break;
2569 case 2:
2570 default:
2571 encoder->possible_crtcs = 0x3;
2572 break;
2573 case 4:
2574 encoder->possible_crtcs = 0xf;
2575 break;
2576 case 6:
2577 encoder->possible_crtcs = 0x3f;
2578 break;
2579 }
2580
2581 radeon_encoder->enc_priv = NULL;
2582
2583 radeon_encoder->encoder_enum = encoder_enum;
2584 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2585 radeon_encoder->devices = supported_device;
2586 radeon_encoder->rmx_type = RMX_OFF;
2587 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2588 radeon_encoder->is_ext_encoder = false;
2589 radeon_encoder->caps = caps;
2590
2591 switch (radeon_encoder->encoder_id) {
2592 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2593 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2595 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2596 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2597 radeon_encoder->rmx_type = RMX_FULL;
2598 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2599 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2600 } else {
2601 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2602 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2603 }
2604 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2605 break;
2606 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2607 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2608 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2609 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2610 break;
2611 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2612 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2614 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2615 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2616 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2617 break;
2618 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2619 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2620 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2621 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2623 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2624 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2625 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2626 radeon_encoder->rmx_type = RMX_FULL;
2627 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2628 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2629 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2630 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2631 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2632 } else {
2633 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2634 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2635 }
2636 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2637 break;
2638 case ENCODER_OBJECT_ID_SI170B:
2639 case ENCODER_OBJECT_ID_CH7303:
2640 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2641 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2642 case ENCODER_OBJECT_ID_TITFP513:
2643 case ENCODER_OBJECT_ID_VT1623:
2644 case ENCODER_OBJECT_ID_HDMI_SI1930:
2645 case ENCODER_OBJECT_ID_TRAVIS:
2646 case ENCODER_OBJECT_ID_NUTMEG:
2647 /* these are handled by the primary encoders */
2648 radeon_encoder->is_ext_encoder = true;
2649 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2650 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2651 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2653 else
2654 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2655 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2656 break;
2657 }
2658}
Linux kernel - Deliverables
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