projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: implement wrapper for GET_SYSTEM_PARAMS
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
36
37static u8
38radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
39{
40 u8 backlight_level;
41 u32 bios_2_scratch;
42
43 if (rdev->family >= CHIP_R600)
44 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 else
46 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47
48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50
51 return backlight_level;
52}
53
54static void
55radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
56 u8 backlight_level)
57{
58 u32 bios_2_scratch;
59
60 if (rdev->family >= CHIP_R600)
61 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 else
63 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64
65 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
66 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
67 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68
69 if (rdev->family >= CHIP_R600)
70 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 else
72 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
73}
74
75static void
76atombios_set_panel_brightness(struct radeon_encoder *radeon_encoder)
77{
78 struct drm_encoder *encoder = &radeon_encoder->base;
79 struct drm_device *dev = radeon_encoder->base.dev;
80 struct radeon_device *rdev = dev->dev_private;
81 struct radeon_encoder_atom_dig *dig;
82 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
83 int index;
84
85 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
86 dig = radeon_encoder->enc_priv;
87 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
88
89 switch (radeon_encoder->encoder_id) {
90 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
91 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
92 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
93 if (dig->backlight_level == 0) {
94 args.ucAction = ATOM_LCD_BLOFF;
95 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
96 } else {
97 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
98 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
99 args.ucAction = ATOM_LCD_BLON;
100 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
101 }
102 break;
103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
104 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
107 if (dig->backlight_level == 0)
108 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
109 else {
110 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
111 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
112 }
113 break;
114 default:
115 break;
116 }
117 }
118}
119
120static u8 radeon_atom_bl_level(struct backlight_device *bd)
121{
122 u8 level;
123
124 /* Convert brightness to hardware level */
125 if (bd->props.brightness < 0)
126 level = 0;
127 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
128 level = RADEON_MAX_BL_LEVEL;
129 else
130 level = bd->props.brightness;
131
132 return level;
133}
134
135static int radeon_atom_backlight_update_status(struct backlight_device *bd)
136{
137 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
138 struct radeon_encoder *radeon_encoder = pdata->encoder;
139
140 if (radeon_encoder->enc_priv) {
141 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
142 dig->backlight_level = radeon_atom_bl_level(bd);
143 atombios_set_panel_brightness(radeon_encoder);
144 }
145
146 return 0;
147}
148
149static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
150{
151 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
152 struct radeon_encoder *radeon_encoder = pdata->encoder;
153 struct drm_device *dev = radeon_encoder->base.dev;
154 struct radeon_device *rdev = dev->dev_private;
155
156 return radeon_atom_get_backlight_level_from_reg(rdev);
157}
158
159static const struct backlight_ops radeon_atom_backlight_ops = {
160 .get_brightness = radeon_atom_backlight_get_brightness,
161 .update_status = radeon_atom_backlight_update_status,
162};
163
164void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
165 struct drm_connector *drm_connector)
166{
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
169 struct backlight_device *bd;
170 struct backlight_properties props;
171 struct radeon_backlight_privdata *pdata;
172 struct radeon_encoder_atom_dig *dig;
173 u8 backlight_level;
174
175 if (!radeon_encoder->enc_priv)
176 return;
177
178 if (!rdev->is_atom_bios)
179 return;
180
181 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
182 return;
183
184 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
185 if (!pdata) {
186 DRM_ERROR("Memory allocation failed\n");
187 goto error;
188 }
189
190 memset(&props, 0, sizeof(props));
191 props.max_brightness = RADEON_MAX_BL_LEVEL;
192 props.type = BACKLIGHT_RAW;
193 bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
194 pdata, &radeon_atom_backlight_ops, &props);
195 if (IS_ERR(bd)) {
196 DRM_ERROR("Backlight registration failed\n");
197 goto error;
198 }
199
200 pdata->encoder = radeon_encoder;
201
202 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
203
204 dig = radeon_encoder->enc_priv;
205 dig->bl_dev = bd;
206
207 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
208 bd->props.power = FB_BLANK_UNBLANK;
209 backlight_update_status(bd);
210
211 DRM_INFO("radeon atom DIG backlight initialized\n");
212
213 return;
214
215error:
216 kfree(pdata);
217 return;
218}
219
220static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
221{
222 struct drm_device *dev = radeon_encoder->base.dev;
223 struct radeon_device *rdev = dev->dev_private;
224 struct backlight_device *bd = NULL;
225 struct radeon_encoder_atom_dig *dig;
226
227 if (!radeon_encoder->enc_priv)
228 return;
229
230 if (!rdev->is_atom_bios)
231 return;
232
233 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
234 return;
235
236 dig = radeon_encoder->enc_priv;
237 bd = dig->bl_dev;
238 dig->bl_dev = NULL;
239
240 if (bd) {
241 struct radeon_legacy_backlight_privdata *pdata;
242
243 pdata = bl_get_data(bd);
244 backlight_device_unregister(bd);
245 kfree(pdata);
246
247 DRM_INFO("radeon atom LVDS backlight unloaded\n");
248 }
249}
250
251#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
252
253void radeon_atom_backlight_init(struct radeon_encoder *encoder)
254{
255}
256
257static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
258{
259}
260
261#endif
262
3f03ced8
AD		 263/* evil but including atombios.h is much worse */
264bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
265 struct drm_display_mode *mode);
266
267
268static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
269{
270 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
271 switch (radeon_encoder->encoder_id) {
272 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
273 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
274 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
275 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
276 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
277 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
278 case ENCODER_OBJECT_ID_INTERNAL_DDI:
279 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
281 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
282 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
283 return true;
284 default:
285 return false;
286 }
287}
288
3f03ced8 289static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 290 const struct drm_display_mode *mode,
3f03ced8
AD		 291 struct drm_display_mode *adjusted_mode)
292{
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 struct drm_device *dev = encoder->dev;
295 struct radeon_device *rdev = dev->dev_private;
296
297 /* set the active encoder to connector routing */
298 radeon_encoder_set_active_device(encoder);
299 drm_mode_set_crtcinfo(adjusted_mode, 0);
300
301 /* hw bug */
302 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
303 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
304 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
305
306 /* get the native mode for LVDS */
307 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
308 radeon_panel_mode_fixup(encoder, adjusted_mode);
309
310 /* get the native mode for TV */
311 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
312 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
313 if (tv_dac) {
314 if (tv_dac->tv_std == TV_STD_NTSC ||
315 tv_dac->tv_std == TV_STD_NTSC_J ||
316 tv_dac->tv_std == TV_STD_PAL_M)
317 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
318 else
319 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
320 }
321 }
322
323 if (ASIC_IS_DCE3(rdev) &&
324 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
325 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
326 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
327 radeon_dp_set_link_config(connector, mode);
328 }
329
330 return true;
331}
332
333static void
334atombios_dac_setup(struct drm_encoder *encoder, int action)
335{
336 struct drm_device *dev = encoder->dev;
337 struct radeon_device *rdev = dev->dev_private;
338 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
339 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
340 int index = 0;
341 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
342
343 memset(&args, 0, sizeof(args));
344
345 switch (radeon_encoder->encoder_id) {
346 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
347 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
348 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
349 break;
350 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
351 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
352 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
353 break;
354 }
355
356 args.ucAction = action;
357
358 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
359 args.ucDacStandard = ATOM_DAC1_PS2;
360 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
361 args.ucDacStandard = ATOM_DAC1_CV;
362 else {
363 switch (dac_info->tv_std) {
364 case TV_STD_PAL:
365 case TV_STD_PAL_M:
366 case TV_STD_SCART_PAL:
367 case TV_STD_SECAM:
368 case TV_STD_PAL_CN:
369 args.ucDacStandard = ATOM_DAC1_PAL;
370 break;
371 case TV_STD_NTSC:
372 case TV_STD_NTSC_J:
373 case TV_STD_PAL_60:
374 default:
375 args.ucDacStandard = ATOM_DAC1_NTSC;
376 break;
377 }
378 }
379 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
380
381 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
382
383}
384
385static void
386atombios_tv_setup(struct drm_encoder *encoder, int action)
387{
388 struct drm_device *dev = encoder->dev;
389 struct radeon_device *rdev = dev->dev_private;
390 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
391 TV_ENCODER_CONTROL_PS_ALLOCATION args;
392 int index = 0;
393 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
394
395 memset(&args, 0, sizeof(args));
396
397 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
398
399 args.sTVEncoder.ucAction = action;
400
401 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
402 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
403 else {
404 switch (dac_info->tv_std) {
405 case TV_STD_NTSC:
406 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
407 break;
408 case TV_STD_PAL:
409 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
410 break;
411 case TV_STD_PAL_M:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
413 break;
414 case TV_STD_PAL_60:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
416 break;
417 case TV_STD_NTSC_J:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
419 break;
420 case TV_STD_SCART_PAL:
421 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
422 break;
423 case TV_STD_SECAM:
424 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
425 break;
426 case TV_STD_PAL_CN:
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
428 break;
429 default:
430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
431 break;
432 }
433 }
434
435 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
436
437 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
438
439}
440
441union dvo_encoder_control {
442 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
443 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
444 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
445};
446
447void
448atombios_dvo_setup(struct drm_encoder *encoder, int action)
449{
450 struct drm_device *dev = encoder->dev;
451 struct radeon_device *rdev = dev->dev_private;
452 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
453 union dvo_encoder_control args;
454 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 455 uint8_t frev, crev;
3f03ced8
AD		 456
457 memset(&args, 0, sizeof(args));
458
24153dd3
AD		 459 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
460 return;
461
afceb931
AD		 462 /* some R4xx chips have the wrong frev */
463 if (rdev->family <= CHIP_RV410)
464 frev = 1;
465
24153dd3
AD		 466 switch (frev) {
467 case 1:
468 switch (crev) {
469 case 1:
470 /* R4xx, R5xx */
471 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
472
9aa59993 473 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 474 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
475
476 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
477 break;
478 case 2:
479 /* RS600/690/740 */
480 args.dvo.sDVOEncoder.ucAction = action;
481 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
482 /* DFP1, CRT1, TV1 depending on the type of port */
483 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
484
9aa59993 485 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 486 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
487 break;
488 case 3:
489 /* R6xx */
490 args.dvo_v3.ucAction = action;
491 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
492 args.dvo_v3.ucDVOConfig = 0; /* XXX */
493 break;
494 default:
495 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
496 break;
497 }
498 break;
499 default:
500 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
501 break;
3f03ced8
AD		 502 }
503
504 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
505}
506
507union lvds_encoder_control {
508 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
509 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
510};
511
512void
513atombios_digital_setup(struct drm_encoder *encoder, int action)
514{
515 struct drm_device *dev = encoder->dev;
516 struct radeon_device *rdev = dev->dev_private;
517 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
518 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
519 union lvds_encoder_control args;
520 int index = 0;
521 int hdmi_detected = 0;
522 uint8_t frev, crev;
523
524 if (!dig)
525 return;
526
527 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
528 hdmi_detected = 1;
529
530 memset(&args, 0, sizeof(args));
531
532 switch (radeon_encoder->encoder_id) {
533 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
534 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
535 break;
536 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
537 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
538 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
539 break;
540 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
541 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
542 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
543 else
544 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
545 break;
546 }
547
548 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
549 return;
550
551 switch (frev) {
552 case 1:
553 case 2:
554 switch (crev) {
555 case 1:
556 args.v1.ucMisc = 0;
557 args.v1.ucAction = action;
558 if (hdmi_detected)
559 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
560 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
561 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
562 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
563 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
564 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
565 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
566 } else {
567 if (dig->linkb)
568 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 569 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 570 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
571 /*if (pScrn->rgbBits == 8) */
572 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
573 }
574 break;
575 case 2:
576 case 3:
577 args.v2.ucMisc = 0;
578 args.v2.ucAction = action;
579 if (crev == 3) {
580 if (dig->coherent_mode)
581 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
582 }
583 if (hdmi_detected)
584 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
585 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
586 args.v2.ucTruncate = 0;
587 args.v2.ucSpatial = 0;
588 args.v2.ucTemporal = 0;
589 args.v2.ucFRC = 0;
590 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
591 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
592 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
593 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
594 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
595 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
596 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
597 }
598 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
599 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
600 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
601 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
602 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
603 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
604 }
605 } else {
606 if (dig->linkb)
607 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 608 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 609 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
610 }
611 break;
612 default:
613 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
614 break;
615 }
616 break;
617 default:
618 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
619 break;
620 }
621
622 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
623}
624
625int
626atombios_get_encoder_mode(struct drm_encoder *encoder)
627{
628 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 629 struct drm_connector *connector;
630 struct radeon_connector *radeon_connector;
631 struct radeon_connector_atom_dig *dig_connector;
632
633 /* dp bridges are always DP */
634 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
635 return ATOM_ENCODER_MODE_DP;
636
637 /* DVO is always DVO */
638 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
639 return ATOM_ENCODER_MODE_DVO;
640
641 connector = radeon_get_connector_for_encoder(encoder);
642 /* if we don't have an active device yet, just use one of
643 * the connectors tied to the encoder.
644 */
645 if (!connector)
646 connector = radeon_get_connector_for_encoder_init(encoder);
647 radeon_connector = to_radeon_connector(connector);
648
649 switch (connector->connector_type) {
650 case DRM_MODE_CONNECTOR_DVII:
651 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 652 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 653 radeon_audio)
654 return ATOM_ENCODER_MODE_HDMI;
655 else if (radeon_connector->use_digital)
3f03ced8
AD		 656 return ATOM_ENCODER_MODE_DVI;
657 else
658 return ATOM_ENCODER_MODE_CRT;
659 break;
660 case DRM_MODE_CONNECTOR_DVID:
661 case DRM_MODE_CONNECTOR_HDMIA:
662 default:
27d9cc84 663 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 664 radeon_audio)
665 return ATOM_ENCODER_MODE_HDMI;
666 else
3f03ced8
AD		 667 return ATOM_ENCODER_MODE_DVI;
668 break;
669 case DRM_MODE_CONNECTOR_LVDS:
670 return ATOM_ENCODER_MODE_LVDS;
671 break;
672 case DRM_MODE_CONNECTOR_DisplayPort:
673 dig_connector = radeon_connector->con_priv;
674 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
675 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
676 return ATOM_ENCODER_MODE_DP;
27d9cc84 677 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 678 radeon_audio)
679 return ATOM_ENCODER_MODE_HDMI;
680 else
3f03ced8
AD		 681 return ATOM_ENCODER_MODE_DVI;
682 break;
683 case DRM_MODE_CONNECTOR_eDP:
684 return ATOM_ENCODER_MODE_DP;
685 case DRM_MODE_CONNECTOR_DVIA:
686 case DRM_MODE_CONNECTOR_VGA:
687 return ATOM_ENCODER_MODE_CRT;
688 break;
689 case DRM_MODE_CONNECTOR_Composite:
690 case DRM_MODE_CONNECTOR_SVIDEO:
691 case DRM_MODE_CONNECTOR_9PinDIN:
692 /* fix me */
693 return ATOM_ENCODER_MODE_TV;
694 /*return ATOM_ENCODER_MODE_CV;*/
695 break;
696 }
697}
698
699/*
700 * DIG Encoder/Transmitter Setup
701 *
702 * DCE 3.0/3.1
703 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
704 * Supports up to 3 digital outputs
705 * - 2 DIG encoder blocks.
706 * DIG1 can drive UNIPHY link A or link B
707 * DIG2 can drive UNIPHY link B or LVTMA
708 *
709 * DCE 3.2
710 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
711 * Supports up to 5 digital outputs
712 * - 2 DIG encoder blocks.
713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
714 *
2d415869 715 * DCE 4.0/5.0/6.0
3f03ced8
AD		 716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
717 * Supports up to 6 digital outputs
718 * - 6 DIG encoder blocks.
719 * - DIG to PHY mapping is hardcoded
720 * DIG1 drives UNIPHY0 link A, A+B
721 * DIG2 drives UNIPHY0 link B
722 * DIG3 drives UNIPHY1 link A, A+B
723 * DIG4 drives UNIPHY1 link B
724 * DIG5 drives UNIPHY2 link A, A+B
725 * DIG6 drives UNIPHY2 link B
726 *
727 * DCE 4.1
728 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
729 * Supports up to 6 digital outputs
730 * - 2 DIG encoder blocks.
2d415869 731 * llano
3f03ced8 732 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 733 * ontario
734 * DIG1 drives UNIPHY0/1/2 link A
735 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 736 *
737 * Routing
738 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
739 * Examples:
740 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
741 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
742 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
743 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
744 */
745
746union dig_encoder_control {
747 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
748 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
749 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
750 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
751};
752
753void
754atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
755{
756 struct drm_device *dev = encoder->dev;
757 struct radeon_device *rdev = dev->dev_private;
758 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
759 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
760 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
761 union dig_encoder_control args;
762 int index = 0;
763 uint8_t frev, crev;
764 int dp_clock = 0;
765 int dp_lane_count = 0;
766 int hpd_id = RADEON_HPD_NONE;
767 int bpc = 8;
768
769 if (connector) {
770 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771 struct radeon_connector_atom_dig *dig_connector =
772 radeon_connector->con_priv;
773
774 dp_clock = dig_connector->dp_clock;
775 dp_lane_count = dig_connector->dp_lane_count;
776 hpd_id = radeon_connector->hpd.hpd;
eccea792 777 bpc = radeon_get_monitor_bpc(connector);
3f03ced8
AD		 778 }
779
780 /* no dig encoder assigned */
781 if (dig->dig_encoder == -1)
782 return;
783
784 memset(&args, 0, sizeof(args));
785
786 if (ASIC_IS_DCE4(rdev))
787 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
788 else {
789 if (dig->dig_encoder)
790 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
791 else
792 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
793 }
794
795 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
796 return;
797
58cdcb8b
AD		 798 switch (frev) {
799 case 1:
800 switch (crev) {
801 case 1:
802 args.v1.ucAction = action;
803 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
804 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
805 args.v3.ucPanelMode = panel_mode;
806 else
807 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
808
809 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
810 args.v1.ucLaneNum = dp_lane_count;
9aa59993 811 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 812 args.v1.ucLaneNum = 8;
813 else
814 args.v1.ucLaneNum = 4;
815
816 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
817 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
818 switch (radeon_encoder->encoder_id) {
819 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
820 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
821 break;
822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
824 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
825 break;
826 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
827 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
828 break;
829 }
830 if (dig->linkb)
831 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
832 else
833 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 834 break;
58cdcb8b
AD		 835 case 2:
836 case 3:
837 args.v3.ucAction = action;
838 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
839 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
840 args.v3.ucPanelMode = panel_mode;
841 else
842 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
843
844 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
845 args.v3.ucLaneNum = dp_lane_count;
9aa59993 846 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 847 args.v3.ucLaneNum = 8;
848 else
849 args.v3.ucLaneNum = 4;
850
851 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
852 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
853 args.v3.acConfig.ucDigSel = dig->dig_encoder;
854 switch (bpc) {
855 case 0:
856 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
857 break;
858 case 6:
859 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
860 break;
861 case 8:
862 default:
863 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
864 break;
865 case 10:
866 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
867 break;
868 case 12:
869 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
870 break;
871 case 16:
872 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
873 break;
874 }
3f03ced8 875 break;
58cdcb8b
AD		 876 case 4:
877 args.v4.ucAction = action;
878 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
879 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
880 args.v4.ucPanelMode = panel_mode;
881 else
882 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
883
884 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
885 args.v4.ucLaneNum = dp_lane_count;
9aa59993 886 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 887 args.v4.ucLaneNum = 8;
888 else
889 args.v4.ucLaneNum = 4;
890
891 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
892 if (dp_clock == 270000)
893 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
894 else if (dp_clock == 540000)
895 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
896 }
897 args.v4.acConfig.ucDigSel = dig->dig_encoder;
898 switch (bpc) {
899 case 0:
900 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
901 break;
902 case 6:
903 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
904 break;
905 case 8:
906 default:
907 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
908 break;
909 case 10:
910 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
911 break;
912 case 12:
913 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
914 break;
915 case 16:
916 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
917 break;
918 }
919 if (hpd_id == RADEON_HPD_NONE)
920 args.v4.ucHPD_ID = 0;
921 else
922 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 923 break;
3f03ced8 924 default:
58cdcb8b 925 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 926 break;
927 }
58cdcb8b
AD		 928 break;
929 default:
930 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
931 break;
3f03ced8
AD		 932 }
933
934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
935
936}
937
938union dig_transmitter_control {
939 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
940 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
941 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
942 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 943 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 944};
945
946void
947atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
948{
949 struct drm_device *dev = encoder->dev;
950 struct radeon_device *rdev = dev->dev_private;
951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
952 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
953 struct drm_connector *connector;
954 union dig_transmitter_control args;
955 int index = 0;
956 uint8_t frev, crev;
957 bool is_dp = false;
958 int pll_id = 0;
959 int dp_clock = 0;
960 int dp_lane_count = 0;
961 int connector_object_id = 0;
962 int igp_lane_info = 0;
963 int dig_encoder = dig->dig_encoder;
47aef7a8 964 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 965
966 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
967 connector = radeon_get_connector_for_encoder_init(encoder);
968 /* just needed to avoid bailing in the encoder check. the encoder
969 * isn't used for init
970 */
971 dig_encoder = 0;
972 } else
973 connector = radeon_get_connector_for_encoder(encoder);
974
975 if (connector) {
976 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
977 struct radeon_connector_atom_dig *dig_connector =
978 radeon_connector->con_priv;
979
47aef7a8 980 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 981 dp_clock = dig_connector->dp_clock;
982 dp_lane_count = dig_connector->dp_lane_count;
983 connector_object_id =
984 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
985 igp_lane_info = dig_connector->igp_lane_info;
986 }
987
a3b08294
AD		 988 if (encoder->crtc) {
989 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
990 pll_id = radeon_crtc->pll_id;
991 }
992
3f03ced8
AD		 993 /* no dig encoder assigned */
994 if (dig_encoder == -1)
995 return;
996
997 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
998 is_dp = true;
999
1000 memset(&args, 0, sizeof(args));
1001
1002 switch (radeon_encoder->encoder_id) {
1003 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1004 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1005 break;
1006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1008 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1009 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1010 break;
1011 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1012 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1013 break;
1014 }
1015
1016 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1017 return;
1018
a3b08294
AD		 1019 switch (frev) {
1020 case 1:
1021 switch (crev) {
1022 case 1:
1023 args.v1.ucAction = action;
1024 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1025 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1026 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1027 args.v1.asMode.ucLaneSel = lane_num;
1028 args.v1.asMode.ucLaneSet = lane_set;
1029 } else {
1030 if (is_dp)
1031 args.v1.usPixelClock =
1032 cpu_to_le16(dp_clock / 10);
9aa59993 1033 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1034 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1035 else
1036 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1037 }
3f03ced8 1038
a3b08294 1039 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1040
a3b08294
AD		 1041 if (dig_encoder)
1042 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1043 else
1044 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1045
1046 if ((rdev->flags & RADEON_IS_IGP) &&
1047 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1048 if (is_dp ||
1049 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1050 if (igp_lane_info & 0x1)
1051 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1052 else if (igp_lane_info & 0x2)
1053 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1054 else if (igp_lane_info & 0x4)
1055 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1056 else if (igp_lane_info & 0x8)
1057 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1058 } else {
1059 if (igp_lane_info & 0x3)
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1061 else if (igp_lane_info & 0xc)
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1063 }
1064 }
1065
1066 if (dig->linkb)
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1068 else
1069 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1070
1071 if (is_dp)
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1073 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1074 if (dig->coherent_mode)
1075 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1076 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1078 }
1079 break;
1080 case 2:
1081 args.v2.ucAction = action;
1082 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1083 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1084 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1085 args.v2.asMode.ucLaneSel = lane_num;
1086 args.v2.asMode.ucLaneSet = lane_set;
1087 } else {
1088 if (is_dp)
1089 args.v2.usPixelClock =
1090 cpu_to_le16(dp_clock / 10);
9aa59993 1091 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1092 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1093 else
1094 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1095 }
1096
1097 args.v2.acConfig.ucEncoderSel = dig_encoder;
1098 if (dig->linkb)
1099 args.v2.acConfig.ucLinkSel = 1;
1100
1101 switch (radeon_encoder->encoder_id) {
1102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1103 args.v2.acConfig.ucTransmitterSel = 0;
1104 break;
1105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1106 args.v2.acConfig.ucTransmitterSel = 1;
1107 break;
1108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1109 args.v2.acConfig.ucTransmitterSel = 2;
1110 break;
1111 }
3f03ced8 1112
3f03ced8 1113 if (is_dp) {
a3b08294
AD		 1114 args.v2.acConfig.fCoherentMode = 1;
1115 args.v2.acConfig.fDPConnector = 1;
1116 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1117 if (dig->coherent_mode)
1118 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1119 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1120 args.v2.acConfig.fDualLinkConnector = 1;
1121 }
1122 break;
1123 case 3:
1124 args.v3.ucAction = action;
1125 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1126 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1127 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1128 args.v3.asMode.ucLaneSel = lane_num;
1129 args.v3.asMode.ucLaneSet = lane_set;
1130 } else {
1131 if (is_dp)
1132 args.v3.usPixelClock =
1133 cpu_to_le16(dp_clock / 10);
9aa59993 1134 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1135 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1136 else
a3b08294
AD		 1137 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1138 }
1139
1140 if (is_dp)
1141 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1142 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1143 args.v3.ucLaneNum = 8;
1144 else
1145 args.v3.ucLaneNum = 4;
1146
1147 if (dig->linkb)
1148 args.v3.acConfig.ucLinkSel = 1;
1149 if (dig_encoder & 1)
1150 args.v3.acConfig.ucEncoderSel = 1;
1151
1152 /* Select the PLL for the PHY
1153 * DP PHY should be clocked from external src if there is
1154 * one.
1155 */
3f03ced8
AD		 1156 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1157 if (is_dp && rdev->clock.dp_extclk)
1158 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1159 else
1160 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1161
a3b08294
AD		 1162 switch (radeon_encoder->encoder_id) {
1163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1164 args.v3.acConfig.ucTransmitterSel = 0;
1165 break;
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1167 args.v3.acConfig.ucTransmitterSel = 1;
1168 break;
1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1170 args.v3.acConfig.ucTransmitterSel = 2;
1171 break;
1172 }
3f03ced8 1173
a3b08294
AD		 1174 if (is_dp)
1175 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1176 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1177 if (dig->coherent_mode)
1178 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1179 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1180 args.v3.acConfig.fDualLinkConnector = 1;
1181 }
3f03ced8 1182 break;
a3b08294
AD		 1183 case 4:
1184 args.v4.ucAction = action;
1185 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1186 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1187 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1188 args.v4.asMode.ucLaneSel = lane_num;
1189 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1190 } else {
a3b08294
AD		 1191 if (is_dp)
1192 args.v4.usPixelClock =
1193 cpu_to_le16(dp_clock / 10);
9aa59993 1194 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1195 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1196 else
1197 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1198 }
3f03ced8 1199
a3b08294
AD		 1200 if (is_dp)
1201 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1202 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1203 args.v4.ucLaneNum = 8;
1204 else
1205 args.v4.ucLaneNum = 4;
3f03ced8 1206
a3b08294
AD		 1207 if (dig->linkb)
1208 args.v4.acConfig.ucLinkSel = 1;
1209 if (dig_encoder & 1)
1210 args.v4.acConfig.ucEncoderSel = 1;
1211
1212 /* Select the PLL for the PHY
1213 * DP PHY should be clocked from external src if there is
1214 * one.
1215 */
1216 /* On DCE5 DCPLL usually generates the DP ref clock */
1217 if (is_dp) {
1218 if (rdev->clock.dp_extclk)
1219 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1220 else
1221 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1222 } else
1223 args.v4.acConfig.ucRefClkSource = pll_id;
1224
1225 switch (radeon_encoder->encoder_id) {
1226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1227 args.v4.acConfig.ucTransmitterSel = 0;
1228 break;
1229 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1230 args.v4.acConfig.ucTransmitterSel = 1;
1231 break;
1232 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1233 args.v4.acConfig.ucTransmitterSel = 2;
1234 break;
1235 }
1236
1237 if (is_dp)
1238 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1239 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1240 if (dig->coherent_mode)
1241 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1242 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1243 args.v4.acConfig.fDualLinkConnector = 1;
1244 }
1245 break;
47aef7a8
AD		 1246 case 5:
1247 args.v5.ucAction = action;
1248 if (is_dp)
1249 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1250 else
1251 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1252
1253 switch (radeon_encoder->encoder_id) {
1254 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1255 if (dig->linkb)
1256 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1257 else
1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1259 break;
1260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1261 if (dig->linkb)
1262 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1263 else
1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1265 break;
1266 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1267 if (dig->linkb)
1268 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1269 else
1270 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1271 break;
1272 }
1273 if (is_dp)
1274 args.v5.ucLaneNum = dp_lane_count;
1275 else if (radeon_encoder->pixel_clock > 165000)
1276 args.v5.ucLaneNum = 8;
1277 else
1278 args.v5.ucLaneNum = 4;
1279 args.v5.ucConnObjId = connector_object_id;
1280 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1281
1282 if (is_dp && rdev->clock.dp_extclk)
1283 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1284 else
1285 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1286
1287 if (is_dp)
1288 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1289 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1290 if (dig->coherent_mode)
1291 args.v5.asConfig.ucCoherentMode = 1;
1292 }
1293 if (hpd_id == RADEON_HPD_NONE)
1294 args.v5.asConfig.ucHPDSel = 0;
1295 else
1296 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1297 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1298 args.v5.ucDPLaneSet = lane_set;
1299 break;
a3b08294
AD		 1300 default:
1301 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1302 break;
3f03ced8 1303 }
a3b08294
AD		 1304 break;
1305 default:
1306 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1307 break;
3f03ced8
AD		 1308 }
1309
1310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1311}
1312
1313bool
1314atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1315{
1316 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1317 struct drm_device *dev = radeon_connector->base.dev;
1318 struct radeon_device *rdev = dev->dev_private;
1319 union dig_transmitter_control args;
1320 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1321 uint8_t frev, crev;
1322
1323 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1324 goto done;
1325
1326 if (!ASIC_IS_DCE4(rdev))
1327 goto done;
1328
1329 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1330 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1331 goto done;
1332
1333 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1334 goto done;
1335
1336 memset(&args, 0, sizeof(args));
1337
1338 args.v1.ucAction = action;
1339
1340 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1341
1342 /* wait for the panel to power up */
1343 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1344 int i;
1345
1346 for (i = 0; i < 300; i++) {
1347 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1348 return true;
1349 mdelay(1);
1350 }
1351 return false;
1352 }
1353done:
1354 return true;
1355}
1356
1357union external_encoder_control {
1358 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1359 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1360};
1361
1362static void
1363atombios_external_encoder_setup(struct drm_encoder *encoder,
1364 struct drm_encoder *ext_encoder,
1365 int action)
1366{
1367 struct drm_device *dev = encoder->dev;
1368 struct radeon_device *rdev = dev->dev_private;
1369 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1370 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1371 union external_encoder_control args;
1372 struct drm_connector *connector;
1373 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1374 u8 frev, crev;
1375 int dp_clock = 0;
1376 int dp_lane_count = 0;
1377 int connector_object_id = 0;
1378 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1379 int bpc = 8;
1380
1381 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1382 connector = radeon_get_connector_for_encoder_init(encoder);
1383 else
1384 connector = radeon_get_connector_for_encoder(encoder);
1385
1386 if (connector) {
1387 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1388 struct radeon_connector_atom_dig *dig_connector =
1389 radeon_connector->con_priv;
1390
1391 dp_clock = dig_connector->dp_clock;
1392 dp_lane_count = dig_connector->dp_lane_count;
1393 connector_object_id =
1394 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
eccea792 1395 bpc = radeon_get_monitor_bpc(connector);
3f03ced8
AD		 1396 }
1397
1398 memset(&args, 0, sizeof(args));
1399
1400 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1401 return;
1402
1403 switch (frev) {
1404 case 1:
1405 /* no params on frev 1 */
1406 break;
1407 case 2:
1408 switch (crev) {
1409 case 1:
1410 case 2:
1411 args.v1.sDigEncoder.ucAction = action;
1412 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1413 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1414
1415 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1416 if (dp_clock == 270000)
1417 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1418 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1419 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1420 args.v1.sDigEncoder.ucLaneNum = 8;
1421 else
1422 args.v1.sDigEncoder.ucLaneNum = 4;
1423 break;
1424 case 3:
1425 args.v3.sExtEncoder.ucAction = action;
1426 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1427 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1428 else
1429 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1430 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1431
1432 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1433 if (dp_clock == 270000)
1434 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1435 else if (dp_clock == 540000)
1436 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1437 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1438 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1439 args.v3.sExtEncoder.ucLaneNum = 8;
1440 else
1441 args.v3.sExtEncoder.ucLaneNum = 4;
1442 switch (ext_enum) {
1443 case GRAPH_OBJECT_ENUM_ID1:
1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1445 break;
1446 case GRAPH_OBJECT_ENUM_ID2:
1447 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1448 break;
1449 case GRAPH_OBJECT_ENUM_ID3:
1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1451 break;
1452 }
1453 switch (bpc) {
1454 case 0:
1455 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1456 break;
1457 case 6:
1458 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1459 break;
1460 case 8:
1461 default:
1462 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1463 break;
1464 case 10:
1465 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1466 break;
1467 case 12:
1468 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1469 break;
1470 case 16:
1471 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1472 break;
1473 }
1474 break;
1475 default:
1476 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1477 return;
1478 }
1479 break;
1480 default:
1481 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1482 return;
1483 }
1484 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1485}
1486
1487static void
1488atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1489{
1490 struct drm_device *dev = encoder->dev;
1491 struct radeon_device *rdev = dev->dev_private;
1492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1494 ENABLE_YUV_PS_ALLOCATION args;
1495 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1496 uint32_t temp, reg;
1497
1498 memset(&args, 0, sizeof(args));
1499
1500 if (rdev->family >= CHIP_R600)
1501 reg = R600_BIOS_3_SCRATCH;
1502 else
1503 reg = RADEON_BIOS_3_SCRATCH;
1504
1505 /* XXX: fix up scratch reg handling */
1506 temp = RREG32(reg);
1507 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1508 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1509 (radeon_crtc->crtc_id << 18)));
1510 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1511 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1512 else
1513 WREG32(reg, 0);
1514
1515 if (enable)
1516 args.ucEnable = ATOM_ENABLE;
1517 args.ucCRTC = radeon_crtc->crtc_id;
1518
1519 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1520
1521 WREG32(reg, temp);
1522}
1523
1524static void
1525radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1526{
1527 struct drm_device *dev = encoder->dev;
1528 struct radeon_device *rdev = dev->dev_private;
1529 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1530 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1531 int index = 0;
1532
1533 memset(&args, 0, sizeof(args));
1534
1535 switch (radeon_encoder->encoder_id) {
1536 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1537 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1538 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1539 break;
1540 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1541 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1542 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1543 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1544 break;
1545 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1546 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1547 break;
1548 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1549 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1550 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1551 else
1552 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1553 break;
1554 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1555 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1556 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1557 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1558 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1559 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1560 else
1561 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1562 break;
1563 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1564 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1565 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1566 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1567 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1568 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1569 else
1570 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1571 break;
1572 default:
1573 return;
1574 }
1575
1576 switch (mode) {
1577 case DRM_MODE_DPMS_ON:
1578 args.ucAction = ATOM_ENABLE;
1579 /* workaround for DVOOutputControl on some RS690 systems */
1580 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1581 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1582 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1583 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1584 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1585 } else
1586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1587 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1588 args.ucAction = ATOM_LCD_BLON;
1589 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1590 }
1591 break;
1592 case DRM_MODE_DPMS_STANDBY:
1593 case DRM_MODE_DPMS_SUSPEND:
1594 case DRM_MODE_DPMS_OFF:
1595 args.ucAction = ATOM_DISABLE;
1596 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1597 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1598 args.ucAction = ATOM_LCD_BLOFF;
1599 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1600 }
1601 break;
1602 }
1603}
1604
1605static void
1606radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1607{
1608 struct drm_device *dev = encoder->dev;
1609 struct radeon_device *rdev = dev->dev_private;
1610 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1611 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1612 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1613 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1614 struct radeon_connector *radeon_connector = NULL;
1615 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1616
1617 if (connector) {
1618 radeon_connector = to_radeon_connector(connector);
1619 radeon_dig_connector = radeon_connector->con_priv;
1620 }
1621
1622 switch (mode) {
1623 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1624 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1625 if (!connector)
1626 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1627 else
1628 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1629
1630 /* setup and enable the encoder */
1631 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1632 atombios_dig_encoder_setup(encoder,
1633 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1634 dig->panel_mode);
1635 if (ext_encoder) {
1636 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1637 atombios_external_encoder_setup(encoder, ext_encoder,
1638 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1639 }
3f03ced8 1640 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1641 } else if (ASIC_IS_DCE4(rdev)) {
1642 /* setup and enable the encoder */
1643 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1644 /* enable the transmitter */
1645 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1646 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1647 } else {
1648 /* setup and enable the encoder and transmitter */
1649 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1650 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1651 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1652 /* some early dce3.2 boards have a bug in their transmitter control table */
1653 if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1654 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1655 }
3f03ced8
AD		 1656 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1657 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1658 atombios_set_edp_panel_power(connector,
1659 ATOM_TRANSMITTER_ACTION_POWER_ON);
1660 radeon_dig_connector->edp_on = true;
1661 }
3f03ced8
AD		 1662 radeon_dp_link_train(encoder, connector);
1663 if (ASIC_IS_DCE4(rdev))
1664 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1665 }
1666 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1667 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1668 break;
1669 case DRM_MODE_DPMS_STANDBY:
1670 case DRM_MODE_DPMS_SUSPEND:
1671 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1672 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1673 /* disable the transmitter */
3a47824d 1674 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1675 } else if (ASIC_IS_DCE4(rdev)) {
1676 /* disable the transmitter */
1677 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1678 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1679 } else {
1680 /* disable the encoder and transmitter */
3a47824d 1681 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1682 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1683 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1684 }
3f03ced8
AD		 1685 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1686 if (ASIC_IS_DCE4(rdev))
1687 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1688 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1689 atombios_set_edp_panel_power(connector,
1690 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1691 radeon_dig_connector->edp_on = false;
1692 }
1693 }
1694 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1695 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1696 break;
1697 }
1698}
1699
1700static void
1701radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1702 struct drm_encoder *ext_encoder,
1703 int mode)
1704{
1705 struct drm_device *dev = encoder->dev;
1706 struct radeon_device *rdev = dev->dev_private;
1707
1708 switch (mode) {
1709 case DRM_MODE_DPMS_ON:
1710 default:
1d3949c4 1711 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1712 atombios_external_encoder_setup(encoder, ext_encoder,
1713 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1714 atombios_external_encoder_setup(encoder, ext_encoder,
1715 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1716 } else
1717 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1718 break;
1719 case DRM_MODE_DPMS_STANDBY:
1720 case DRM_MODE_DPMS_SUSPEND:
1721 case DRM_MODE_DPMS_OFF:
1d3949c4 1722 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1723 atombios_external_encoder_setup(encoder, ext_encoder,
1724 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1725 atombios_external_encoder_setup(encoder, ext_encoder,
1726 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1727 } else
1728 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1729 break;
1730 }
1731}
1732
1733static void
1734radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1735{
1736 struct drm_device *dev = encoder->dev;
1737 struct radeon_device *rdev = dev->dev_private;
1738 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1739 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1740
1741 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1742 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1743 radeon_encoder->active_device);
1744 switch (radeon_encoder->encoder_id) {
1745 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1746 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1747 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1748 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1749 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1750 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1751 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1752 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1753 radeon_atom_encoder_dpms_avivo(encoder, mode);
1754 break;
1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1757 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1758 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1759 radeon_atom_encoder_dpms_dig(encoder, mode);
1760 break;
1761 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1762 if (ASIC_IS_DCE5(rdev)) {
1763 switch (mode) {
1764 case DRM_MODE_DPMS_ON:
1765 atombios_dvo_setup(encoder, ATOM_ENABLE);
1766 break;
1767 case DRM_MODE_DPMS_STANDBY:
1768 case DRM_MODE_DPMS_SUSPEND:
1769 case DRM_MODE_DPMS_OFF:
1770 atombios_dvo_setup(encoder, ATOM_DISABLE);
1771 break;
1772 }
1773 } else if (ASIC_IS_DCE3(rdev))
1774 radeon_atom_encoder_dpms_dig(encoder, mode);
1775 else
1776 radeon_atom_encoder_dpms_avivo(encoder, mode);
1777 break;
1778 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1779 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1780 if (ASIC_IS_DCE5(rdev)) {
1781 switch (mode) {
1782 case DRM_MODE_DPMS_ON:
1783 atombios_dac_setup(encoder, ATOM_ENABLE);
1784 break;
1785 case DRM_MODE_DPMS_STANDBY:
1786 case DRM_MODE_DPMS_SUSPEND:
1787 case DRM_MODE_DPMS_OFF:
1788 atombios_dac_setup(encoder, ATOM_DISABLE);
1789 break;
1790 }
1791 } else
1792 radeon_atom_encoder_dpms_avivo(encoder, mode);
1793 break;
1794 default:
1795 return;
1796 }
1797
1798 if (ext_encoder)
1799 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1800
1801 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1802
1803}
1804
1805union crtc_source_param {
1806 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1807 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1808};
1809
1810static void
1811atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1812{
1813 struct drm_device *dev = encoder->dev;
1814 struct radeon_device *rdev = dev->dev_private;
1815 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1816 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1817 union crtc_source_param args;
1818 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1819 uint8_t frev, crev;
1820 struct radeon_encoder_atom_dig *dig;
1821
1822 memset(&args, 0, sizeof(args));
1823
1824 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1825 return;
1826
1827 switch (frev) {
1828 case 1:
1829 switch (crev) {
1830 case 1:
1831 default:
1832 if (ASIC_IS_AVIVO(rdev))
1833 args.v1.ucCRTC = radeon_crtc->crtc_id;
1834 else {
1835 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1836 args.v1.ucCRTC = radeon_crtc->crtc_id;
1837 } else {
1838 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1839 }
1840 }
1841 switch (radeon_encoder->encoder_id) {
1842 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1843 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1844 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1845 break;
1846 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1847 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1848 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1849 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1850 else
1851 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1852 break;
1853 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1854 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1855 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1856 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1857 break;
1858 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1859 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1860 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1861 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1862 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1863 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1864 else
1865 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1866 break;
1867 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1868 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1869 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1870 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1871 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1872 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1873 else
1874 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1875 break;
1876 }
1877 break;
1878 case 2:
1879 args.v2.ucCRTC = radeon_crtc->crtc_id;
1880 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1881 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1882
1883 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1884 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1885 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1886 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1887 else
1888 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1889 } else
1890 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1891 switch (radeon_encoder->encoder_id) {
1892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1893 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1896 dig = radeon_encoder->enc_priv;
1897 switch (dig->dig_encoder) {
1898 case 0:
1899 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1900 break;
1901 case 1:
1902 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1903 break;
1904 case 2:
1905 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1906 break;
1907 case 3:
1908 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1909 break;
1910 case 4:
1911 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1912 break;
1913 case 5:
1914 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1915 break;
1916 }
1917 break;
1918 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1919 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1920 break;
1921 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1922 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1923 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1924 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1925 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1926 else
1927 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1928 break;
1929 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1930 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1931 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1932 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1933 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1934 else
1935 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1936 break;
1937 }
1938 break;
1939 }
1940 break;
1941 default:
1942 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1943 return;
1944 }
1945
1946 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1947
1948 /* update scratch regs with new routing */
1949 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1950}
1951
1952static void
1953atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1954 struct drm_display_mode *mode)
1955{
1956 struct drm_device *dev = encoder->dev;
1957 struct radeon_device *rdev = dev->dev_private;
1958 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1959 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1960
1961 /* Funky macbooks */
1962 if ((dev->pdev->device == 0x71C5) &&
1963 (dev->pdev->subsystem_vendor == 0x106b) &&
1964 (dev->pdev->subsystem_device == 0x0080)) {
1965 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1966 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1967
1968 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1969 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1970
1971 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1972 }
1973 }
1974
1975 /* set scaler clears this on some chips */
1976 if (ASIC_IS_AVIVO(rdev) &&
1977 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1978 if (ASIC_IS_DCE4(rdev)) {
1979 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1980 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1981 EVERGREEN_INTERLEAVE_EN);
1982 else
1983 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1984 } else {
1985 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1986 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1987 AVIVO_D1MODE_INTERLEAVE_EN);
1988 else
1989 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1990 }
1991 }
1992}
1993
1994static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1995{
1996 struct drm_device *dev = encoder->dev;
1997 struct radeon_device *rdev = dev->dev_private;
1998 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1999 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2000 struct drm_encoder *test_encoder;
41fa5437 2001 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 2002 uint32_t dig_enc_in_use = 0;
2003
41fa5437
AD		 2004 if (ASIC_IS_DCE6(rdev)) {
2005 /* DCE6 */
2006 switch (radeon_encoder->encoder_id) {
2007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2008 if (dig->linkb)
2009 return 1;
2010 else
2011 return 0;
2012 break;
2013 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2014 if (dig->linkb)
2015 return 3;
2016 else
2017 return 2;
2018 break;
2019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2020 if (dig->linkb)
2021 return 5;
2022 else
2023 return 4;
2024 break;
2025 }
2026 } else if (ASIC_IS_DCE4(rdev)) {
2027 /* DCE4/5 */
2028 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2029 /* ontario follows DCE4 */
2030 if (rdev->family == CHIP_PALM) {
2031 if (dig->linkb)
2032 return 1;
2033 else
2034 return 0;
2035 } else
2036 /* llano follows DCE3.2 */
2037 return radeon_crtc->crtc_id;
2038 } else {
2039 switch (radeon_encoder->encoder_id) {
2040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2041 if (dig->linkb)
2042 return 1;
2043 else
2044 return 0;
2045 break;
2046 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2047 if (dig->linkb)
2048 return 3;
2049 else
2050 return 2;
2051 break;
2052 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2053 if (dig->linkb)
2054 return 5;
2055 else
2056 return 4;
2057 break;
2058 }
2059 }
2060 }
2061
2062 /* on DCE32 and encoder can driver any block so just crtc id */
2063 if (ASIC_IS_DCE32(rdev)) {
2064 return radeon_crtc->crtc_id;
2065 }
2066
2067 /* on DCE3 - LVTMA can only be driven by DIGB */
2068 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2069 struct radeon_encoder *radeon_test_encoder;
2070
2071 if (encoder == test_encoder)
2072 continue;
2073
2074 if (!radeon_encoder_is_digital(test_encoder))
2075 continue;
2076
2077 radeon_test_encoder = to_radeon_encoder(test_encoder);
2078 dig = radeon_test_encoder->enc_priv;
2079
2080 if (dig->dig_encoder >= 0)
2081 dig_enc_in_use |= (1 << dig->dig_encoder);
2082 }
2083
2084 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2085 if (dig_enc_in_use & 0x2)
2086 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2087 return 1;
2088 }
2089 if (!(dig_enc_in_use & 1))
2090 return 0;
2091 return 1;
2092}
2093
2094/* This only needs to be called once at startup */
2095void
2096radeon_atom_encoder_init(struct radeon_device *rdev)
2097{
2098 struct drm_device *dev = rdev->ddev;
2099 struct drm_encoder *encoder;
2100
2101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2102 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2103 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2104
2105 switch (radeon_encoder->encoder_id) {
2106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2109 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2110 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2111 break;
2112 default:
2113 break;
2114 }
2115
1d3949c4 2116 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2117 atombios_external_encoder_setup(encoder, ext_encoder,
2118 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2119 }
2120}
2121
2122static void
2123radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2124 struct drm_display_mode *mode,
2125 struct drm_display_mode *adjusted_mode)
2126{
2127 struct drm_device *dev = encoder->dev;
2128 struct radeon_device *rdev = dev->dev_private;
2129 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2130
2131 radeon_encoder->pixel_clock = adjusted_mode->clock;
2132
8d1af57a
AD		 2133 /* need to call this here rather than in prepare() since we need some crtc info */
2134 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2135
3f03ced8
AD		 2136 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2137 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2138 atombios_yuv_setup(encoder, true);
2139 else
2140 atombios_yuv_setup(encoder, false);
2141 }
2142
2143 switch (radeon_encoder->encoder_id) {
2144 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2145 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2146 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2147 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2148 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2149 break;
2150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2152 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2154 /* handled in dpms */
3f03ced8
AD		 2155 break;
2156 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2157 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2158 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2159 atombios_dvo_setup(encoder, ATOM_ENABLE);
2160 break;
2161 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2162 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2163 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2165 atombios_dac_setup(encoder, ATOM_ENABLE);
2166 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2167 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2168 atombios_tv_setup(encoder, ATOM_ENABLE);
2169 else
2170 atombios_tv_setup(encoder, ATOM_DISABLE);
2171 }
2172 break;
2173 }
2174
3f03ced8
AD		 2175 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2176
2177 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2178 r600_hdmi_enable(encoder);
6b53a050
RM		 2179 if (ASIC_IS_DCE6(rdev))
2180 ; /* TODO (use pointers instead of if-s?) */
2181 else if (ASIC_IS_DCE4(rdev))
e55d3e6c
RM		 2182 evergreen_hdmi_setmode(encoder, adjusted_mode);
2183 else
2184 r600_hdmi_setmode(encoder, adjusted_mode);
3f03ced8
AD		 2185 }
2186}
2187
2188static bool
2189atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2190{
2191 struct drm_device *dev = encoder->dev;
2192 struct radeon_device *rdev = dev->dev_private;
2193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2194 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2195
2196 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2197 ATOM_DEVICE_CV_SUPPORT |
2198 ATOM_DEVICE_CRT_SUPPORT)) {
2199 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2200 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2201 uint8_t frev, crev;
2202
2203 memset(&args, 0, sizeof(args));
2204
2205 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2206 return false;
2207
2208 args.sDacload.ucMisc = 0;
2209
2210 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2211 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2212 args.sDacload.ucDacType = ATOM_DAC_A;
2213 else
2214 args.sDacload.ucDacType = ATOM_DAC_B;
2215
2216 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2217 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2218 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2219 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2220 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2221 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2222 if (crev >= 3)
2223 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2224 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2225 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2226 if (crev >= 3)
2227 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2228 }
2229
2230 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2231
2232 return true;
2233 } else
2234 return false;
2235}
2236
2237static enum drm_connector_status
2238radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2239{
2240 struct drm_device *dev = encoder->dev;
2241 struct radeon_device *rdev = dev->dev_private;
2242 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2243 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2244 uint32_t bios_0_scratch;
2245
2246 if (!atombios_dac_load_detect(encoder, connector)) {
2247 DRM_DEBUG_KMS("detect returned false \n");
2248 return connector_status_unknown;
2249 }
2250
2251 if (rdev->family >= CHIP_R600)
2252 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2253 else
2254 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2255
2256 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2257 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2258 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2259 return connector_status_connected;
2260 }
2261 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2262 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2263 return connector_status_connected;
2264 }
2265 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2266 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2267 return connector_status_connected;
2268 }
2269 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2270 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2271 return connector_status_connected; /* CTV */
2272 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2273 return connector_status_connected; /* STV */
2274 }
2275 return connector_status_disconnected;
2276}
2277
2278static enum drm_connector_status
2279radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2280{
2281 struct drm_device *dev = encoder->dev;
2282 struct radeon_device *rdev = dev->dev_private;
2283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2284 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2285 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2286 u32 bios_0_scratch;
2287
2288 if (!ASIC_IS_DCE4(rdev))
2289 return connector_status_unknown;
2290
2291 if (!ext_encoder)
2292 return connector_status_unknown;
2293
2294 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2295 return connector_status_unknown;
2296
2297 /* load detect on the dp bridge */
2298 atombios_external_encoder_setup(encoder, ext_encoder,
2299 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2300
2301 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2302
2303 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2304 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2305 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2306 return connector_status_connected;
2307 }
2308 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2309 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2310 return connector_status_connected;
2311 }
2312 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2313 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2314 return connector_status_connected;
2315 }
2316 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2317 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2318 return connector_status_connected; /* CTV */
2319 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2320 return connector_status_connected; /* STV */
2321 }
2322 return connector_status_disconnected;
2323}
2324
2325void
2326radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2327{
2328 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2329
2330 if (ext_encoder)
2331 /* ddc_setup on the dp bridge */
2332 atombios_external_encoder_setup(encoder, ext_encoder,
2333 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2334
2335}
2336
2337static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2338{
cfcbd6d3 2339 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2340 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2341 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2342
2343 if ((radeon_encoder->active_device &
2344 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2345 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2346 ENCODER_OBJECT_ID_NONE)) {
2347 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2348 if (dig) {
3f03ced8 2349 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2350 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2351 if (rdev->family >= CHIP_R600)
2352 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2353 else
2354 /* RS600/690/740 have only 1 afmt block */
2355 dig->afmt = rdev->mode_info.afmt[0];
2356 }
2357 }
3f03ced8
AD		 2358 }
2359
2360 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2361
2362 if (connector) {
2363 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2364
2365 /* select the clock/data port if it uses a router */
2366 if (radeon_connector->router.cd_valid)
2367 radeon_router_select_cd_port(radeon_connector);
2368
2369 /* turn eDP panel on for mode set */
2370 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2371 atombios_set_edp_panel_power(connector,
2372 ATOM_TRANSMITTER_ACTION_POWER_ON);
2373 }
2374
2375 /* this is needed for the pll/ss setup to work correctly in some cases */
2376 atombios_set_encoder_crtc_source(encoder);
2377}
2378
2379static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2380{
8d1af57a 2381 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2382 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2383 radeon_atom_output_lock(encoder, false);
2384}
2385
2386static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2387{
2388 struct drm_device *dev = encoder->dev;
2389 struct radeon_device *rdev = dev->dev_private;
2390 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2391 struct radeon_encoder_atom_dig *dig;
2392
2393 /* check for pre-DCE3 cards with shared encoders;
2394 * can't really use the links individually, so don't disable
2395 * the encoder if it's in use by another connector
2396 */
2397 if (!ASIC_IS_DCE3(rdev)) {
2398 struct drm_encoder *other_encoder;
2399 struct radeon_encoder *other_radeon_encoder;
2400
2401 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2402 other_radeon_encoder = to_radeon_encoder(other_encoder);
2403 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2404 drm_helper_encoder_in_use(other_encoder))
2405 goto disable_done;
2406 }
2407 }
2408
2409 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2410
2411 switch (radeon_encoder->encoder_id) {
2412 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2413 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2414 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2415 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2416 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2417 break;
2418 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2419 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2420 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2421 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2422 /* handled in dpms */
3f03ced8
AD		 2423 break;
2424 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2425 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2426 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2427 atombios_dvo_setup(encoder, ATOM_DISABLE);
2428 break;
2429 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2431 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2432 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2433 atombios_dac_setup(encoder, ATOM_DISABLE);
2434 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2435 atombios_tv_setup(encoder, ATOM_DISABLE);
2436 break;
2437 }
2438
2439disable_done:
2440 if (radeon_encoder_is_digital(encoder)) {
2441 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2442 r600_hdmi_disable(encoder);
2443 dig = radeon_encoder->enc_priv;
2444 dig->dig_encoder = -1;
2445 }
2446 radeon_encoder->active_device = 0;
2447}
2448
2449/* these are handled by the primary encoders */
2450static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2451{
2452
2453}
2454
2455static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2456{
2457
2458}
2459
2460static void
2461radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2462 struct drm_display_mode *mode,
2463 struct drm_display_mode *adjusted_mode)
2464{
2465
2466}
2467
2468static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2469{
2470
2471}
2472
2473static void
2474radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2475{
2476
2477}
2478
2479static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2480 const struct drm_display_mode *mode,
3f03ced8
AD		 2481 struct drm_display_mode *adjusted_mode)
2482{
2483 return true;
2484}
2485
2486static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2487 .dpms = radeon_atom_ext_dpms,
2488 .mode_fixup = radeon_atom_ext_mode_fixup,
2489 .prepare = radeon_atom_ext_prepare,
2490 .mode_set = radeon_atom_ext_mode_set,
2491 .commit = radeon_atom_ext_commit,
2492 .disable = radeon_atom_ext_disable,
2493 /* no detect for TMDS/LVDS yet */
2494};
2495
2496static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2497 .dpms = radeon_atom_encoder_dpms,
2498 .mode_fixup = radeon_atom_mode_fixup,
2499 .prepare = radeon_atom_encoder_prepare,
2500 .mode_set = radeon_atom_encoder_mode_set,
2501 .commit = radeon_atom_encoder_commit,
2502 .disable = radeon_atom_encoder_disable,
2503 .detect = radeon_atom_dig_detect,
2504};
2505
2506static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2507 .dpms = radeon_atom_encoder_dpms,
2508 .mode_fixup = radeon_atom_mode_fixup,
2509 .prepare = radeon_atom_encoder_prepare,
2510 .mode_set = radeon_atom_encoder_mode_set,
2511 .commit = radeon_atom_encoder_commit,
2512 .detect = radeon_atom_dac_detect,
2513};
2514
2515void radeon_enc_destroy(struct drm_encoder *encoder)
2516{
2517 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2519 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2520 kfree(radeon_encoder->enc_priv);
2521 drm_encoder_cleanup(encoder);
2522 kfree(radeon_encoder);
2523}
2524
2525static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2526 .destroy = radeon_enc_destroy,
2527};
2528
2529struct radeon_encoder_atom_dac *
2530radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2531{
2532 struct drm_device *dev = radeon_encoder->base.dev;
2533 struct radeon_device *rdev = dev->dev_private;
2534 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2535
2536 if (!dac)
2537 return NULL;
2538
2539 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2540 return dac;
2541}
2542
2543struct radeon_encoder_atom_dig *
2544radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2545{
2546 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2547 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2548
2549 if (!dig)
2550 return NULL;
2551
2552 /* coherent mode by default */
2553 dig->coherent_mode = true;
2554 dig->dig_encoder = -1;
2555
2556 if (encoder_enum == 2)
2557 dig->linkb = true;
2558 else
2559 dig->linkb = false;
2560
2561 return dig;
2562}
2563
2564void
2565radeon_add_atom_encoder(struct drm_device *dev,
2566 uint32_t encoder_enum,
2567 uint32_t supported_device,
2568 u16 caps)
2569{
2570 struct radeon_device *rdev = dev->dev_private;
2571 struct drm_encoder *encoder;
2572 struct radeon_encoder *radeon_encoder;
2573
2574 /* see if we already added it */
2575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2576 radeon_encoder = to_radeon_encoder(encoder);
2577 if (radeon_encoder->encoder_enum == encoder_enum) {
2578 radeon_encoder->devices |= supported_device;
2579 return;
2580 }
2581
2582 }
2583
2584 /* add a new one */
2585 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2586 if (!radeon_encoder)
2587 return;
2588
2589 encoder = &radeon_encoder->base;
2590 switch (rdev->num_crtc) {
2591 case 1:
2592 encoder->possible_crtcs = 0x1;
2593 break;
2594 case 2:
2595 default:
2596 encoder->possible_crtcs = 0x3;
2597 break;
2598 case 4:
2599 encoder->possible_crtcs = 0xf;
2600 break;
2601 case 6:
2602 encoder->possible_crtcs = 0x3f;
2603 break;
2604 }
2605
2606 radeon_encoder->enc_priv = NULL;
2607
2608 radeon_encoder->encoder_enum = encoder_enum;
2609 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2610 radeon_encoder->devices = supported_device;
2611 radeon_encoder->rmx_type = RMX_OFF;
2612 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2613 radeon_encoder->is_ext_encoder = false;
2614 radeon_encoder->caps = caps;
2615
2616 switch (radeon_encoder->encoder_id) {
2617 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2618 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2619 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2620 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2621 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2622 radeon_encoder->rmx_type = RMX_FULL;
2623 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2624 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2625 } else {
2626 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2627 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2628 }
2629 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2630 break;
2631 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2632 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2633 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2634 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2635 break;
2636 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2637 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2639 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2640 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2641 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2642 break;
2643 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2644 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2645 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2646 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2648 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2649 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2650 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2651 radeon_encoder->rmx_type = RMX_FULL;
2652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2653 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2654 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2655 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2656 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2657 } else {
2658 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2659 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2660 }
2661 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2662 break;
2663 case ENCODER_OBJECT_ID_SI170B:
2664 case ENCODER_OBJECT_ID_CH7303:
2665 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2666 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2667 case ENCODER_OBJECT_ID_TITFP513:
2668 case ENCODER_OBJECT_ID_VT1623:
2669 case ENCODER_OBJECT_ID_HDMI_SI1930:
2670 case ENCODER_OBJECT_ID_TRAVIS:
2671 case ENCODER_OBJECT_ID_NUTMEG:
2672 /* these are handled by the primary encoders */
2673 radeon_encoder->is_ext_encoder = true;
2674 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2675 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2676 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2677 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2678 else
2679 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2680 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2681 break;
2682 }
2683}
Linux kernel - Deliverables
This page took 0.198318 seconds and 5 git commands to generate.