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drm/radeon/kms: parse the extended LCD info block
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
42
6f34be50
AD		 43void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
44{
45 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
46 u32 tmp;
47
48 /* make sure flip is at vb rather than hb */
49 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
50 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
51 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
52
53 /* set pageflip to happen anywhere in vblank interval */
54 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
55
56 /* enable the pflip int */
57 radeon_irq_kms_pflip_irq_get(rdev, crtc);
58}
59
60void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
61{
62 /* disable the pflip int */
63 radeon_irq_kms_pflip_irq_put(rdev, crtc);
64}
65
66u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
67{
68 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
69 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
70
71 /* Lock the graphics update lock */
72 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
73 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
74
75 /* update the scanout addresses */
76 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
77 upper_32_bits(crtc_base));
78 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
79 (u32)crtc_base);
80
81 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
82 upper_32_bits(crtc_base));
83 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
84 (u32)crtc_base);
85
86 /* Wait for update_pending to go high. */
87 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
88 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
89
90 /* Unlock the lock, so double-buffering can take place inside vblank */
91 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
92 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
93
94 /* Return current update_pending status: */
95 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
96}
97
21a8122a
AD		 98/* get temperature in millidegrees */
99u32 evergreen_get_temp(struct radeon_device *rdev)
100{
101 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
102 ASIC_T_SHIFT;
103 u32 actual_temp = 0;
104
105 if ((temp >> 10) & 1)
106 actual_temp = 0;
107 else if ((temp >> 9) & 1)
108 actual_temp = 255;
109 else
110 actual_temp = (temp >> 1) & 0xff;
111
112 return actual_temp * 1000;
113}
114
e33df25f
AD		 115u32 sumo_get_temp(struct radeon_device *rdev)
116{
117 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
118 u32 actual_temp = (temp >> 1) & 0xff;
119
120 return actual_temp * 1000;
121}
122
49e02b73
AD		 123void evergreen_pm_misc(struct radeon_device *rdev)
124{
a081a9d6
RM		 125 int req_ps_idx = rdev->pm.requested_power_state_index;
126 int req_cm_idx = rdev->pm.requested_clock_mode_index;
127 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
128 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 129
4d60173f
AD		 130 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
131 if (voltage->voltage != rdev->pm.current_vddc) {
132 radeon_atom_set_voltage(rdev, voltage->voltage);
133 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 134 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 135 }
136 }
49e02b73
AD		 137}
138
139void evergreen_pm_prepare(struct radeon_device *rdev)
140{
141 struct drm_device *ddev = rdev->ddev;
142 struct drm_crtc *crtc;
143 struct radeon_crtc *radeon_crtc;
144 u32 tmp;
145
146 /* disable any active CRTCs */
147 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
148 radeon_crtc = to_radeon_crtc(crtc);
149 if (radeon_crtc->enabled) {
150 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
151 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
152 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
153 }
154 }
155}
156
157void evergreen_pm_finish(struct radeon_device *rdev)
158{
159 struct drm_device *ddev = rdev->ddev;
160 struct drm_crtc *crtc;
161 struct radeon_crtc *radeon_crtc;
162 u32 tmp;
163
164 /* enable any active CRTCs */
165 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
166 radeon_crtc = to_radeon_crtc(crtc);
167 if (radeon_crtc->enabled) {
168 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
169 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
170 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
171 }
172 }
173}
174
bcc1c2a1
AD		 175bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
176{
177 bool connected = false;
0ca2ab52
AD		 178
179 switch (hpd) {
180 case RADEON_HPD_1:
181 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
182 connected = true;
183 break;
184 case RADEON_HPD_2:
185 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
186 connected = true;
187 break;
188 case RADEON_HPD_3:
189 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
190 connected = true;
191 break;
192 case RADEON_HPD_4:
193 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
194 connected = true;
195 break;
196 case RADEON_HPD_5:
197 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
198 connected = true;
199 break;
200 case RADEON_HPD_6:
201 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
202 connected = true;
203 break;
204 default:
205 break;
206 }
207
bcc1c2a1
AD		 208 return connected;
209}
210
211void evergreen_hpd_set_polarity(struct radeon_device *rdev,
212 enum radeon_hpd_id hpd)
213{
0ca2ab52
AD		 214 u32 tmp;
215 bool connected = evergreen_hpd_sense(rdev, hpd);
216
217 switch (hpd) {
218 case RADEON_HPD_1:
219 tmp = RREG32(DC_HPD1_INT_CONTROL);
220 if (connected)
221 tmp &= ~DC_HPDx_INT_POLARITY;
222 else
223 tmp |= DC_HPDx_INT_POLARITY;
224 WREG32(DC_HPD1_INT_CONTROL, tmp);
225 break;
226 case RADEON_HPD_2:
227 tmp = RREG32(DC_HPD2_INT_CONTROL);
228 if (connected)
229 tmp &= ~DC_HPDx_INT_POLARITY;
230 else
231 tmp |= DC_HPDx_INT_POLARITY;
232 WREG32(DC_HPD2_INT_CONTROL, tmp);
233 break;
234 case RADEON_HPD_3:
235 tmp = RREG32(DC_HPD3_INT_CONTROL);
236 if (connected)
237 tmp &= ~DC_HPDx_INT_POLARITY;
238 else
239 tmp |= DC_HPDx_INT_POLARITY;
240 WREG32(DC_HPD3_INT_CONTROL, tmp);
241 break;
242 case RADEON_HPD_4:
243 tmp = RREG32(DC_HPD4_INT_CONTROL);
244 if (connected)
245 tmp &= ~DC_HPDx_INT_POLARITY;
246 else
247 tmp |= DC_HPDx_INT_POLARITY;
248 WREG32(DC_HPD4_INT_CONTROL, tmp);
249 break;
250 case RADEON_HPD_5:
251 tmp = RREG32(DC_HPD5_INT_CONTROL);
252 if (connected)
253 tmp &= ~DC_HPDx_INT_POLARITY;
254 else
255 tmp |= DC_HPDx_INT_POLARITY;
256 WREG32(DC_HPD5_INT_CONTROL, tmp);
257 break;
258 case RADEON_HPD_6:
259 tmp = RREG32(DC_HPD6_INT_CONTROL);
260 if (connected)
261 tmp &= ~DC_HPDx_INT_POLARITY;
262 else
263 tmp |= DC_HPDx_INT_POLARITY;
264 WREG32(DC_HPD6_INT_CONTROL, tmp);
265 break;
266 default:
267 break;
268 }
bcc1c2a1
AD		 269}
270
271void evergreen_hpd_init(struct radeon_device *rdev)
272{
0ca2ab52
AD		 273 struct drm_device *dev = rdev->ddev;
274 struct drm_connector *connector;
275 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
276 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 277
0ca2ab52
AD		 278 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
279 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
280 switch (radeon_connector->hpd.hpd) {
281 case RADEON_HPD_1:
282 WREG32(DC_HPD1_CONTROL, tmp);
283 rdev->irq.hpd[0] = true;
284 break;
285 case RADEON_HPD_2:
286 WREG32(DC_HPD2_CONTROL, tmp);
287 rdev->irq.hpd[1] = true;
288 break;
289 case RADEON_HPD_3:
290 WREG32(DC_HPD3_CONTROL, tmp);
291 rdev->irq.hpd[2] = true;
292 break;
293 case RADEON_HPD_4:
294 WREG32(DC_HPD4_CONTROL, tmp);
295 rdev->irq.hpd[3] = true;
296 break;
297 case RADEON_HPD_5:
298 WREG32(DC_HPD5_CONTROL, tmp);
299 rdev->irq.hpd[4] = true;
300 break;
301 case RADEON_HPD_6:
302 WREG32(DC_HPD6_CONTROL, tmp);
303 rdev->irq.hpd[5] = true;
304 break;
305 default:
306 break;
307 }
308 }
309 if (rdev->irq.installed)
310 evergreen_irq_set(rdev);
bcc1c2a1
AD		 311}
312
0ca2ab52 313void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 314{
0ca2ab52
AD		 315 struct drm_device *dev = rdev->ddev;
316 struct drm_connector *connector;
317
318 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
319 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
320 switch (radeon_connector->hpd.hpd) {
321 case RADEON_HPD_1:
322 WREG32(DC_HPD1_CONTROL, 0);
323 rdev->irq.hpd[0] = false;
324 break;
325 case RADEON_HPD_2:
326 WREG32(DC_HPD2_CONTROL, 0);
327 rdev->irq.hpd[1] = false;
328 break;
329 case RADEON_HPD_3:
330 WREG32(DC_HPD3_CONTROL, 0);
331 rdev->irq.hpd[2] = false;
332 break;
333 case RADEON_HPD_4:
334 WREG32(DC_HPD4_CONTROL, 0);
335 rdev->irq.hpd[3] = false;
336 break;
337 case RADEON_HPD_5:
338 WREG32(DC_HPD5_CONTROL, 0);
339 rdev->irq.hpd[4] = false;
340 break;
341 case RADEON_HPD_6:
342 WREG32(DC_HPD6_CONTROL, 0);
343 rdev->irq.hpd[5] = false;
344 break;
345 default:
346 break;
347 }
348 }
bcc1c2a1
AD		 349}
350
f9d9c362
AD		 351/* watermark setup */
352
353static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
354 struct radeon_crtc *radeon_crtc,
355 struct drm_display_mode *mode,
356 struct drm_display_mode *other_mode)
357{
358 u32 tmp = 0;
359 /*
360 * Line Buffer Setup
361 * There are 3 line buffers, each one shared by 2 display controllers.
362 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
363 * the display controllers. The paritioning is done via one of four
364 * preset allocations specified in bits 2:0:
365 * first display controller
366 * 0 - first half of lb (3840 * 2)
367 * 1 - first 3/4 of lb (5760 * 2)
368 * 2 - whole lb (7680 * 2)
369 * 3 - first 1/4 of lb (1920 * 2)
370 * second display controller
371 * 4 - second half of lb (3840 * 2)
372 * 5 - second 3/4 of lb (5760 * 2)
373 * 6 - whole lb (7680 * 2)
374 * 7 - last 1/4 of lb (1920 * 2)
375 */
376 if (mode && other_mode) {
377 if (mode->hdisplay > other_mode->hdisplay) {
378 if (mode->hdisplay > 2560)
379 tmp = 1; /* 3/4 */
380 else
381 tmp = 0; /* 1/2 */
382 } else if (other_mode->hdisplay > mode->hdisplay) {
383 if (other_mode->hdisplay > 2560)
384 tmp = 3; /* 1/4 */
385 else
386 tmp = 0; /* 1/2 */
387 } else
388 tmp = 0; /* 1/2 */
389 } else if (mode)
390 tmp = 2; /* whole */
391 else if (other_mode)
392 tmp = 3; /* 1/4 */
393
394 /* second controller of the pair uses second half of the lb */
395 if (radeon_crtc->crtc_id % 2)
396 tmp += 4;
397 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
398
399 switch (tmp) {
400 case 0:
401 case 4:
402 default:
403 return 3840 * 2;
404 case 1:
405 case 5:
406 return 5760 * 2;
407 case 2:
408 case 6:
409 return 7680 * 2;
410 case 3:
411 case 7:
412 return 1920 * 2;
413 }
414}
415
416static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
417{
418 u32 tmp = RREG32(MC_SHARED_CHMAP);
419
420 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
421 case 0:
422 default:
423 return 1;
424 case 1:
425 return 2;
426 case 2:
427 return 4;
428 case 3:
429 return 8;
430 }
431}
432
433struct evergreen_wm_params {
434 u32 dram_channels; /* number of dram channels */
435 u32 yclk; /* bandwidth per dram data pin in kHz */
436 u32 sclk; /* engine clock in kHz */
437 u32 disp_clk; /* display clock in kHz */
438 u32 src_width; /* viewport width */
439 u32 active_time; /* active display time in ns */
440 u32 blank_time; /* blank time in ns */
441 bool interlaced; /* mode is interlaced */
442 fixed20_12 vsc; /* vertical scale ratio */
443 u32 num_heads; /* number of active crtcs */
444 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
445 u32 lb_size; /* line buffer allocated to pipe */
446 u32 vtaps; /* vertical scaler taps */
447};
448
449static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
450{
451 /* Calculate DRAM Bandwidth and the part allocated to display. */
452 fixed20_12 dram_efficiency; /* 0.7 */
453 fixed20_12 yclk, dram_channels, bandwidth;
454 fixed20_12 a;
455
456 a.full = dfixed_const(1000);
457 yclk.full = dfixed_const(wm->yclk);
458 yclk.full = dfixed_div(yclk, a);
459 dram_channels.full = dfixed_const(wm->dram_channels * 4);
460 a.full = dfixed_const(10);
461 dram_efficiency.full = dfixed_const(7);
462 dram_efficiency.full = dfixed_div(dram_efficiency, a);
463 bandwidth.full = dfixed_mul(dram_channels, yclk);
464 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
465
466 return dfixed_trunc(bandwidth);
467}
468
469static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
470{
471 /* Calculate DRAM Bandwidth and the part allocated to display. */
472 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
473 fixed20_12 yclk, dram_channels, bandwidth;
474 fixed20_12 a;
475
476 a.full = dfixed_const(1000);
477 yclk.full = dfixed_const(wm->yclk);
478 yclk.full = dfixed_div(yclk, a);
479 dram_channels.full = dfixed_const(wm->dram_channels * 4);
480 a.full = dfixed_const(10);
481 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
482 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
483 bandwidth.full = dfixed_mul(dram_channels, yclk);
484 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
485
486 return dfixed_trunc(bandwidth);
487}
488
489static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
490{
491 /* Calculate the display Data return Bandwidth */
492 fixed20_12 return_efficiency; /* 0.8 */
493 fixed20_12 sclk, bandwidth;
494 fixed20_12 a;
495
496 a.full = dfixed_const(1000);
497 sclk.full = dfixed_const(wm->sclk);
498 sclk.full = dfixed_div(sclk, a);
499 a.full = dfixed_const(10);
500 return_efficiency.full = dfixed_const(8);
501 return_efficiency.full = dfixed_div(return_efficiency, a);
502 a.full = dfixed_const(32);
503 bandwidth.full = dfixed_mul(a, sclk);
504 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
505
506 return dfixed_trunc(bandwidth);
507}
508
509static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
510{
511 /* Calculate the DMIF Request Bandwidth */
512 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
513 fixed20_12 disp_clk, bandwidth;
514 fixed20_12 a;
515
516 a.full = dfixed_const(1000);
517 disp_clk.full = dfixed_const(wm->disp_clk);
518 disp_clk.full = dfixed_div(disp_clk, a);
519 a.full = dfixed_const(10);
520 disp_clk_request_efficiency.full = dfixed_const(8);
521 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
522 a.full = dfixed_const(32);
523 bandwidth.full = dfixed_mul(a, disp_clk);
524 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
525
526 return dfixed_trunc(bandwidth);
527}
528
529static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
530{
531 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
532 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
533 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
534 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
535
536 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
537}
538
539static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
540{
541 /* Calculate the display mode Average Bandwidth
542 * DisplayMode should contain the source and destination dimensions,
543 * timing, etc.
544 */
545 fixed20_12 bpp;
546 fixed20_12 line_time;
547 fixed20_12 src_width;
548 fixed20_12 bandwidth;
549 fixed20_12 a;
550
551 a.full = dfixed_const(1000);
552 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
553 line_time.full = dfixed_div(line_time, a);
554 bpp.full = dfixed_const(wm->bytes_per_pixel);
555 src_width.full = dfixed_const(wm->src_width);
556 bandwidth.full = dfixed_mul(src_width, bpp);
557 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
558 bandwidth.full = dfixed_div(bandwidth, line_time);
559
560 return dfixed_trunc(bandwidth);
561}
562
563static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
564{
565 /* First calcualte the latency in ns */
566 u32 mc_latency = 2000; /* 2000 ns. */
567 u32 available_bandwidth = evergreen_available_bandwidth(wm);
568 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
569 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
570 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
571 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
572 (wm->num_heads * cursor_line_pair_return_time);
573 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
574 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
575 fixed20_12 a, b, c;
576
577 if (wm->num_heads == 0)
578 return 0;
579
580 a.full = dfixed_const(2);
581 b.full = dfixed_const(1);
582 if ((wm->vsc.full > a.full) ||
583 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
584 (wm->vtaps >= 5) ||
585 ((wm->vsc.full >= a.full) && wm->interlaced))
586 max_src_lines_per_dst_line = 4;
587 else
588 max_src_lines_per_dst_line = 2;
589
590 a.full = dfixed_const(available_bandwidth);
591 b.full = dfixed_const(wm->num_heads);
592 a.full = dfixed_div(a, b);
593
594 b.full = dfixed_const(1000);
595 c.full = dfixed_const(wm->disp_clk);
596 b.full = dfixed_div(c, b);
597 c.full = dfixed_const(wm->bytes_per_pixel);
598 b.full = dfixed_mul(b, c);
599
600 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
601
602 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
603 b.full = dfixed_const(1000);
604 c.full = dfixed_const(lb_fill_bw);
605 b.full = dfixed_div(c, b);
606 a.full = dfixed_div(a, b);
607 line_fill_time = dfixed_trunc(a);
608
609 if (line_fill_time < wm->active_time)
610 return latency;
611 else
612 return latency + (line_fill_time - wm->active_time);
613
614}
615
616static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
617{
618 if (evergreen_average_bandwidth(wm) <=
619 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
620 return true;
621 else
622 return false;
623};
624
625static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
626{
627 if (evergreen_average_bandwidth(wm) <=
628 (evergreen_available_bandwidth(wm) / wm->num_heads))
629 return true;
630 else
631 return false;
632};
633
634static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
635{
636 u32 lb_partitions = wm->lb_size / wm->src_width;
637 u32 line_time = wm->active_time + wm->blank_time;
638 u32 latency_tolerant_lines;
639 u32 latency_hiding;
640 fixed20_12 a;
641
642 a.full = dfixed_const(1);
643 if (wm->vsc.full > a.full)
644 latency_tolerant_lines = 1;
645 else {
646 if (lb_partitions <= (wm->vtaps + 1))
647 latency_tolerant_lines = 1;
648 else
649 latency_tolerant_lines = 2;
650 }
651
652 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
653
654 if (evergreen_latency_watermark(wm) <= latency_hiding)
655 return true;
656 else
657 return false;
658}
659
660static void evergreen_program_watermarks(struct radeon_device *rdev,
661 struct radeon_crtc *radeon_crtc,
662 u32 lb_size, u32 num_heads)
663{
664 struct drm_display_mode *mode = &radeon_crtc->base.mode;
665 struct evergreen_wm_params wm;
666 u32 pixel_period;
667 u32 line_time = 0;
668 u32 latency_watermark_a = 0, latency_watermark_b = 0;
669 u32 priority_a_mark = 0, priority_b_mark = 0;
670 u32 priority_a_cnt = PRIORITY_OFF;
671 u32 priority_b_cnt = PRIORITY_OFF;
672 u32 pipe_offset = radeon_crtc->crtc_id * 16;
673 u32 tmp, arb_control3;
674 fixed20_12 a, b, c;
675
676 if (radeon_crtc->base.enabled && num_heads && mode) {
677 pixel_period = 1000000 / (u32)mode->clock;
678 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
679 priority_a_cnt = 0;
680 priority_b_cnt = 0;
681
682 wm.yclk = rdev->pm.current_mclk * 10;
683 wm.sclk = rdev->pm.current_sclk * 10;
684 wm.disp_clk = mode->clock;
685 wm.src_width = mode->crtc_hdisplay;
686 wm.active_time = mode->crtc_hdisplay * pixel_period;
687 wm.blank_time = line_time - wm.active_time;
688 wm.interlaced = false;
689 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
690 wm.interlaced = true;
691 wm.vsc = radeon_crtc->vsc;
692 wm.vtaps = 1;
693 if (radeon_crtc->rmx_type != RMX_OFF)
694 wm.vtaps = 2;
695 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
696 wm.lb_size = lb_size;
697 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
698 wm.num_heads = num_heads;
699
700 /* set for high clocks */
701 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
702 /* set for low clocks */
703 /* wm.yclk = low clk; wm.sclk = low clk */
704 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
705
706 /* possibly force display priority to high */
707 /* should really do this at mode validation time... */
708 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
709 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
710 !evergreen_check_latency_hiding(&wm) ||
711 (rdev->disp_priority == 2)) {
712 DRM_INFO("force priority to high\n");
713 priority_a_cnt |= PRIORITY_ALWAYS_ON;
714 priority_b_cnt |= PRIORITY_ALWAYS_ON;
715 }
716
717 a.full = dfixed_const(1000);
718 b.full = dfixed_const(mode->clock);
719 b.full = dfixed_div(b, a);
720 c.full = dfixed_const(latency_watermark_a);
721 c.full = dfixed_mul(c, b);
722 c.full = dfixed_mul(c, radeon_crtc->hsc);
723 c.full = dfixed_div(c, a);
724 a.full = dfixed_const(16);
725 c.full = dfixed_div(c, a);
726 priority_a_mark = dfixed_trunc(c);
727 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
728
729 a.full = dfixed_const(1000);
730 b.full = dfixed_const(mode->clock);
731 b.full = dfixed_div(b, a);
732 c.full = dfixed_const(latency_watermark_b);
733 c.full = dfixed_mul(c, b);
734 c.full = dfixed_mul(c, radeon_crtc->hsc);
735 c.full = dfixed_div(c, a);
736 a.full = dfixed_const(16);
737 c.full = dfixed_div(c, a);
738 priority_b_mark = dfixed_trunc(c);
739 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
740 }
741
742 /* select wm A */
743 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
744 tmp = arb_control3;
745 tmp &= ~LATENCY_WATERMARK_MASK(3);
746 tmp |= LATENCY_WATERMARK_MASK(1);
747 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
748 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
749 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
750 LATENCY_HIGH_WATERMARK(line_time)));
751 /* select wm B */
752 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
753 tmp &= ~LATENCY_WATERMARK_MASK(3);
754 tmp |= LATENCY_WATERMARK_MASK(2);
755 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
756 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
757 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
758 LATENCY_HIGH_WATERMARK(line_time)));
759 /* restore original selection */
760 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
761
762 /* write the priority marks */
763 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
764 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
765
766}
767
0ca2ab52 768void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 769{
f9d9c362
AD		 770 struct drm_display_mode *mode0 = NULL;
771 struct drm_display_mode *mode1 = NULL;
772 u32 num_heads = 0, lb_size;
773 int i;
774
775 radeon_update_display_priority(rdev);
776
777 for (i = 0; i < rdev->num_crtc; i++) {
778 if (rdev->mode_info.crtcs[i]->base.enabled)
779 num_heads++;
780 }
781 for (i = 0; i < rdev->num_crtc; i += 2) {
782 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
783 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
784 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
785 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
786 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
787 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
788 }
bcc1c2a1
AD		 789}
790
791static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
792{
793 unsigned i;
794 u32 tmp;
795
796 for (i = 0; i < rdev->usec_timeout; i++) {
797 /* read MC_STATUS */
798 tmp = RREG32(SRBM_STATUS) & 0x1F00;
799 if (!tmp)
800 return 0;
801 udelay(1);
802 }
803 return -1;
804}
805
806/*
807 * GART
808 */
0fcdb61e
AD		 809void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
810{
811 unsigned i;
812 u32 tmp;
813
814 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
815 for (i = 0; i < rdev->usec_timeout; i++) {
816 /* read MC_STATUS */
817 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
818 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
819 if (tmp == 2) {
820 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
821 return;
822 }
823 if (tmp) {
824 return;
825 }
826 udelay(1);
827 }
828}
829
bcc1c2a1
AD		 830int evergreen_pcie_gart_enable(struct radeon_device *rdev)
831{
832 u32 tmp;
0fcdb61e 833 int r;
bcc1c2a1
AD		 834
835 if (rdev->gart.table.vram.robj == NULL) {
836 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
837 return -EINVAL;
838 }
839 r = radeon_gart_table_vram_pin(rdev);
840 if (r)
841 return r;
82568565 842 radeon_gart_restore(rdev);
bcc1c2a1
AD		 843 /* Setup L2 cache */
844 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
845 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
846 EFFECTIVE_L2_QUEUE_SIZE(7));
847 WREG32(VM_L2_CNTL2, 0);
848 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
849 /* Setup TLB control */
850 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
851 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
852 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
853 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
854 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
855 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
856 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
857 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
858 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
859 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
860 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
861 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
862 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
863 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
864 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
865 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
866 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
867 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 868 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 869
0fcdb61e 870 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 871 rdev->gart.ready = true;
872 return 0;
873}
874
875void evergreen_pcie_gart_disable(struct radeon_device *rdev)
876{
877 u32 tmp;
0fcdb61e 878 int r;
bcc1c2a1
AD		 879
880 /* Disable all tables */
0fcdb61e
AD		 881 WREG32(VM_CONTEXT0_CNTL, 0);
882 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 883
884 /* Setup L2 cache */
885 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
886 EFFECTIVE_L2_QUEUE_SIZE(7));
887 WREG32(VM_L2_CNTL2, 0);
888 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
889 /* Setup TLB control */
890 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
891 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
892 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
893 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
894 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
895 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
896 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
897 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
898 if (rdev->gart.table.vram.robj) {
899 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
900 if (likely(r == 0)) {
901 radeon_bo_kunmap(rdev->gart.table.vram.robj);
902 radeon_bo_unpin(rdev->gart.table.vram.robj);
903 radeon_bo_unreserve(rdev->gart.table.vram.robj);
904 }
905 }
906}
907
908void evergreen_pcie_gart_fini(struct radeon_device *rdev)
909{
910 evergreen_pcie_gart_disable(rdev);
911 radeon_gart_table_vram_free(rdev);
912 radeon_gart_fini(rdev);
913}
914
915
916void evergreen_agp_enable(struct radeon_device *rdev)
917{
918 u32 tmp;
bcc1c2a1
AD		 919
920 /* Setup L2 cache */
921 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
922 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
923 EFFECTIVE_L2_QUEUE_SIZE(7));
924 WREG32(VM_L2_CNTL2, 0);
925 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
926 /* Setup TLB control */
927 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
928 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
929 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
930 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
931 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
932 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
933 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
934 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
935 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
936 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
937 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 938 WREG32(VM_CONTEXT0_CNTL, 0);
939 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 940}
941
942static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
943{
944 save->vga_control[0] = RREG32(D1VGA_CONTROL);
945 save->vga_control[1] = RREG32(D2VGA_CONTROL);
946 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
947 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
948 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
949 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
950 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
951 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
952 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
953 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
18007401
AD		 954 if (!(rdev->flags & RADEON_IS_IGP)) {
955 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
956 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
957 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
958 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
959 }
bcc1c2a1
AD		 960
961 /* Stop all video */
962 WREG32(VGA_RENDER_CONTROL, 0);
963 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
964 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 965 if (!(rdev->flags & RADEON_IS_IGP)) {
966 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
967 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
968 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
969 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
970 }
bcc1c2a1
AD		 971 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
972 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 973 if (!(rdev->flags & RADEON_IS_IGP)) {
974 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
975 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
976 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
977 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
978 }
bcc1c2a1
AD		 979 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
980 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 981 if (!(rdev->flags & RADEON_IS_IGP)) {
982 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
983 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
984 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
985 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
986 }
bcc1c2a1
AD		 987
988 WREG32(D1VGA_CONTROL, 0);
989 WREG32(D2VGA_CONTROL, 0);
990 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
991 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
992 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
993 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
994}
995
996static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
997{
998 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
999 upper_32_bits(rdev->mc.vram_start));
1000 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1001 upper_32_bits(rdev->mc.vram_start));
1002 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1003 (u32)rdev->mc.vram_start);
1004 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1005 (u32)rdev->mc.vram_start);
1006
1007 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1008 upper_32_bits(rdev->mc.vram_start));
1009 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1010 upper_32_bits(rdev->mc.vram_start));
1011 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1012 (u32)rdev->mc.vram_start);
1013 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1014 (u32)rdev->mc.vram_start);
1015
18007401
AD		 1016 if (!(rdev->flags & RADEON_IS_IGP)) {
1017 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1018 upper_32_bits(rdev->mc.vram_start));
1019 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1020 upper_32_bits(rdev->mc.vram_start));
1021 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1022 (u32)rdev->mc.vram_start);
1023 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1024 (u32)rdev->mc.vram_start);
1025
1026 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1027 upper_32_bits(rdev->mc.vram_start));
1028 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1029 upper_32_bits(rdev->mc.vram_start));
1030 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1031 (u32)rdev->mc.vram_start);
1032 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1033 (u32)rdev->mc.vram_start);
1034
1035 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1036 upper_32_bits(rdev->mc.vram_start));
1037 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1038 upper_32_bits(rdev->mc.vram_start));
1039 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1040 (u32)rdev->mc.vram_start);
1041 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1042 (u32)rdev->mc.vram_start);
1043
1044 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1045 upper_32_bits(rdev->mc.vram_start));
1046 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1047 upper_32_bits(rdev->mc.vram_start));
1048 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1049 (u32)rdev->mc.vram_start);
1050 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1051 (u32)rdev->mc.vram_start);
1052 }
bcc1c2a1
AD		 1053
1054 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1055 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1056 /* Unlock host access */
1057 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1058 mdelay(1);
1059 /* Restore video state */
1060 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1061 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1062 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1063 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1064 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1065 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1066 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1067 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 1068 if (!(rdev->flags & RADEON_IS_IGP)) {
1069 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1070 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1071 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1072 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1073 }
bcc1c2a1
AD		 1074 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1075 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
18007401
AD		 1076 if (!(rdev->flags & RADEON_IS_IGP)) {
1077 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1078 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1079 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1080 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1081 }
bcc1c2a1
AD		 1082 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1083 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 1084 if (!(rdev->flags & RADEON_IS_IGP)) {
1085 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1086 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1087 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1088 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1089 }
bcc1c2a1
AD		 1090 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1091}
1092
1093static void evergreen_mc_program(struct radeon_device *rdev)
1094{
1095 struct evergreen_mc_save save;
1096 u32 tmp;
1097 int i, j;
1098
1099 /* Initialize HDP */
1100 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1101 WREG32((0x2c14 + j), 0x00000000);
1102 WREG32((0x2c18 + j), 0x00000000);
1103 WREG32((0x2c1c + j), 0x00000000);
1104 WREG32((0x2c20 + j), 0x00000000);
1105 WREG32((0x2c24 + j), 0x00000000);
1106 }
1107 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1108
1109 evergreen_mc_stop(rdev, &save);
1110 if (evergreen_mc_wait_for_idle(rdev)) {
1111 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1112 }
1113 /* Lockout access through VGA aperture*/
1114 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1115 /* Update configuration */
1116 if (rdev->flags & RADEON_IS_AGP) {
1117 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1118 /* VRAM before AGP */
1119 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1120 rdev->mc.vram_start >> 12);
1121 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1122 rdev->mc.gtt_end >> 12);
1123 } else {
1124 /* VRAM after AGP */
1125 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1126 rdev->mc.gtt_start >> 12);
1127 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1128 rdev->mc.vram_end >> 12);
1129 }
1130 } else {
1131 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1132 rdev->mc.vram_start >> 12);
1133 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1134 rdev->mc.vram_end >> 12);
1135 }
1136 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
b4183e30
AD		 1137 if (rdev->flags & RADEON_IS_IGP) {
1138 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1139 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1140 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1141 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1142 }
bcc1c2a1
AD		 1143 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1144 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1145 WREG32(MC_VM_FB_LOCATION, tmp);
1146 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1147 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1148 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1149 if (rdev->flags & RADEON_IS_AGP) {
1150 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1151 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1152 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1153 } else {
1154 WREG32(MC_VM_AGP_BASE, 0);
1155 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1156 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1157 }
1158 if (evergreen_mc_wait_for_idle(rdev)) {
1159 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1160 }
1161 evergreen_mc_resume(rdev, &save);
1162 /* we need to own VRAM, so turn off the VGA renderer here
1163 * to stop it overwriting our objects */
1164 rv515_vga_render_disable(rdev);
1165}
1166
bcc1c2a1
AD		 1167/*
1168 * CP.
1169 */
bcc1c2a1
AD		 1170
1171static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1172{
fe251e2f
AD		 1173 const __be32 *fw_data;
1174 int i;
1175
1176 if (!rdev->me_fw || !rdev->pfp_fw)
1177 return -EINVAL;
bcc1c2a1 1178
fe251e2f
AD		 1179 r700_cp_stop(rdev);
1180 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1181
1182 fw_data = (const __be32 *)rdev->pfp_fw->data;
1183 WREG32(CP_PFP_UCODE_ADDR, 0);
1184 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1185 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1186 WREG32(CP_PFP_UCODE_ADDR, 0);
1187
1188 fw_data = (const __be32 *)rdev->me_fw->data;
1189 WREG32(CP_ME_RAM_WADDR, 0);
1190 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1191 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1192
1193 WREG32(CP_PFP_UCODE_ADDR, 0);
1194 WREG32(CP_ME_RAM_WADDR, 0);
1195 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1196 return 0;
1197}
1198
7e7b41d2
AD		 1199static int evergreen_cp_start(struct radeon_device *rdev)
1200{
2281a378 1201 int r, i;
7e7b41d2
AD		 1202 uint32_t cp_me;
1203
1204 r = radeon_ring_lock(rdev, 7);
1205 if (r) {
1206 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1207 return r;
1208 }
1209 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1210 radeon_ring_write(rdev, 0x1);
1211 radeon_ring_write(rdev, 0x0);
1212 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1213 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1214 radeon_ring_write(rdev, 0);
1215 radeon_ring_write(rdev, 0);
1216 radeon_ring_unlock_commit(rdev);
1217
1218 cp_me = 0xff;
1219 WREG32(CP_ME_CNTL, cp_me);
1220
2281a378 1221 r = radeon_ring_lock(rdev, evergreen_default_size + 15);
7e7b41d2
AD		 1222 if (r) {
1223 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1224 return r;
1225 }
2281a378
AD		 1226
1227 /* setup clear context state */
1228 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1229 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1230
1231 for (i = 0; i < evergreen_default_size; i++)
1232 radeon_ring_write(rdev, evergreen_default_state[i]);
1233
1234 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1235 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1236
1237 /* set clear context state */
1238 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1239 radeon_ring_write(rdev, 0);
1240
1241 /* SQ_VTX_BASE_VTX_LOC */
1242 radeon_ring_write(rdev, 0xc0026f00);
1243 radeon_ring_write(rdev, 0x00000000);
1244 radeon_ring_write(rdev, 0x00000000);
1245 radeon_ring_write(rdev, 0x00000000);
1246
1247 /* Clear consts */
1248 radeon_ring_write(rdev, 0xc0036f00);
1249 radeon_ring_write(rdev, 0x00000bc4);
1250 radeon_ring_write(rdev, 0xffffffff);
1251 radeon_ring_write(rdev, 0xffffffff);
1252 radeon_ring_write(rdev, 0xffffffff);
1253
7e7b41d2
AD		 1254 radeon_ring_unlock_commit(rdev);
1255
1256 return 0;
1257}
1258
fe251e2f
AD		 1259int evergreen_cp_resume(struct radeon_device *rdev)
1260{
1261 u32 tmp;
1262 u32 rb_bufsz;
1263 int r;
1264
1265 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1266 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1267 SOFT_RESET_PA |
1268 SOFT_RESET_SH |
1269 SOFT_RESET_VGT |
1270 SOFT_RESET_SX));
1271 RREG32(GRBM_SOFT_RESET);
1272 mdelay(15);
1273 WREG32(GRBM_SOFT_RESET, 0);
1274 RREG32(GRBM_SOFT_RESET);
1275
1276 /* Set ring buffer size */
1277 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 1278 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1279#ifdef __BIG_ENDIAN
1280 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1281#endif
fe251e2f
AD		 1282 WREG32(CP_RB_CNTL, tmp);
1283 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1284
1285 /* Set the write pointer delay */
1286 WREG32(CP_RB_WPTR_DELAY, 0);
1287
1288 /* Initialize the ring buffer's read and write pointers */
1289 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1290 WREG32(CP_RB_RPTR_WR, 0);
1291 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 1292
1293 /* set the wb address wether it's enabled or not */
1294 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1295 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1296 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1297
1298 if (rdev->wb.enabled)
1299 WREG32(SCRATCH_UMSK, 0xff);
1300 else {
1301 tmp |= RB_NO_UPDATE;
1302 WREG32(SCRATCH_UMSK, 0);
1303 }
1304
fe251e2f
AD		 1305 mdelay(1);
1306 WREG32(CP_RB_CNTL, tmp);
1307
1308 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1309 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1310
1311 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1312 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1313
7e7b41d2 1314 evergreen_cp_start(rdev);
fe251e2f
AD		 1315 rdev->cp.ready = true;
1316 r = radeon_ring_test(rdev);
1317 if (r) {
1318 rdev->cp.ready = false;
1319 return r;
1320 }
1321 return 0;
1322}
bcc1c2a1
AD		 1323
1324/*
1325 * Core functions
1326 */
32fcdbf4
AD		 1327static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1328 u32 num_tile_pipes,
bcc1c2a1
AD		 1329 u32 num_backends,
1330 u32 backend_disable_mask)
1331{
1332 u32 backend_map = 0;
32fcdbf4
AD		 1333 u32 enabled_backends_mask = 0;
1334 u32 enabled_backends_count = 0;
1335 u32 cur_pipe;
1336 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1337 u32 cur_backend = 0;
1338 u32 i;
1339 bool force_no_swizzle;
1340
1341 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1342 num_tile_pipes = EVERGREEN_MAX_PIPES;
1343 if (num_tile_pipes < 1)
1344 num_tile_pipes = 1;
1345 if (num_backends > EVERGREEN_MAX_BACKENDS)
1346 num_backends = EVERGREEN_MAX_BACKENDS;
1347 if (num_backends < 1)
1348 num_backends = 1;
1349
1350 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1351 if (((backend_disable_mask >> i) & 1) == 0) {
1352 enabled_backends_mask |= (1 << i);
1353 ++enabled_backends_count;
1354 }
1355 if (enabled_backends_count == num_backends)
1356 break;
1357 }
1358
1359 if (enabled_backends_count == 0) {
1360 enabled_backends_mask = 1;
1361 enabled_backends_count = 1;
1362 }
1363
1364 if (enabled_backends_count != num_backends)
1365 num_backends = enabled_backends_count;
1366
1367 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1368 switch (rdev->family) {
1369 case CHIP_CEDAR:
1370 case CHIP_REDWOOD:
d5e455e4 1371 case CHIP_PALM:
32fcdbf4
AD		 1372 force_no_swizzle = false;
1373 break;
1374 case CHIP_CYPRESS:
1375 case CHIP_HEMLOCK:
1376 case CHIP_JUNIPER:
1377 default:
1378 force_no_swizzle = true;
1379 break;
1380 }
1381 if (force_no_swizzle) {
1382 bool last_backend_enabled = false;
1383
1384 force_no_swizzle = false;
1385 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1386 if (((enabled_backends_mask >> i) & 1) == 1) {
1387 if (last_backend_enabled)
1388 force_no_swizzle = true;
1389 last_backend_enabled = true;
1390 } else
1391 last_backend_enabled = false;
1392 }
1393 }
1394
1395 switch (num_tile_pipes) {
1396 case 1:
1397 case 3:
1398 case 5:
1399 case 7:
1400 DRM_ERROR("odd number of pipes!\n");
1401 break;
1402 case 2:
1403 swizzle_pipe[0] = 0;
1404 swizzle_pipe[1] = 1;
1405 break;
1406 case 4:
1407 if (force_no_swizzle) {
1408 swizzle_pipe[0] = 0;
1409 swizzle_pipe[1] = 1;
1410 swizzle_pipe[2] = 2;
1411 swizzle_pipe[3] = 3;
1412 } else {
1413 swizzle_pipe[0] = 0;
1414 swizzle_pipe[1] = 2;
1415 swizzle_pipe[2] = 1;
1416 swizzle_pipe[3] = 3;
1417 }
1418 break;
1419 case 6:
1420 if (force_no_swizzle) {
1421 swizzle_pipe[0] = 0;
1422 swizzle_pipe[1] = 1;
1423 swizzle_pipe[2] = 2;
1424 swizzle_pipe[3] = 3;
1425 swizzle_pipe[4] = 4;
1426 swizzle_pipe[5] = 5;
1427 } else {
1428 swizzle_pipe[0] = 0;
1429 swizzle_pipe[1] = 2;
1430 swizzle_pipe[2] = 4;
1431 swizzle_pipe[3] = 1;
1432 swizzle_pipe[4] = 3;
1433 swizzle_pipe[5] = 5;
1434 }
1435 break;
1436 case 8:
1437 if (force_no_swizzle) {
1438 swizzle_pipe[0] = 0;
1439 swizzle_pipe[1] = 1;
1440 swizzle_pipe[2] = 2;
1441 swizzle_pipe[3] = 3;
1442 swizzle_pipe[4] = 4;
1443 swizzle_pipe[5] = 5;
1444 swizzle_pipe[6] = 6;
1445 swizzle_pipe[7] = 7;
1446 } else {
1447 swizzle_pipe[0] = 0;
1448 swizzle_pipe[1] = 2;
1449 swizzle_pipe[2] = 4;
1450 swizzle_pipe[3] = 6;
1451 swizzle_pipe[4] = 1;
1452 swizzle_pipe[5] = 3;
1453 swizzle_pipe[6] = 5;
1454 swizzle_pipe[7] = 7;
1455 }
1456 break;
1457 }
1458
1459 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1460 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1461 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1462
1463 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1464
1465 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1466 }
bcc1c2a1
AD		 1467
1468 return backend_map;
1469}
bcc1c2a1 1470
9535ab73
AD		 1471static void evergreen_program_channel_remap(struct radeon_device *rdev)
1472{
1473 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1474
1475 tmp = RREG32(MC_SHARED_CHMAP);
1476 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1477 case 0:
1478 case 1:
1479 case 2:
1480 case 3:
1481 default:
1482 /* default mapping */
1483 mc_shared_chremap = 0x00fac688;
1484 break;
1485 }
1486
1487 switch (rdev->family) {
1488 case CHIP_HEMLOCK:
1489 case CHIP_CYPRESS:
1490 tcp_chan_steer_lo = 0x54763210;
1491 tcp_chan_steer_hi = 0x0000ba98;
1492 break;
1493 case CHIP_JUNIPER:
1494 case CHIP_REDWOOD:
1495 case CHIP_CEDAR:
d5e455e4 1496 case CHIP_PALM:
9535ab73
AD		 1497 default:
1498 tcp_chan_steer_lo = 0x76543210;
1499 tcp_chan_steer_hi = 0x0000ba98;
1500 break;
1501 }
1502
1503 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1504 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1505 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1506}
1507
bcc1c2a1
AD		 1508static void evergreen_gpu_init(struct radeon_device *rdev)
1509{
32fcdbf4
AD		 1510 u32 cc_rb_backend_disable = 0;
1511 u32 cc_gc_shader_pipe_config;
1512 u32 gb_addr_config = 0;
1513 u32 mc_shared_chmap, mc_arb_ramcfg;
1514 u32 gb_backend_map;
1515 u32 grbm_gfx_index;
1516 u32 sx_debug_1;
1517 u32 smx_dc_ctl0;
1518 u32 sq_config;
1519 u32 sq_lds_resource_mgmt;
1520 u32 sq_gpr_resource_mgmt_1;
1521 u32 sq_gpr_resource_mgmt_2;
1522 u32 sq_gpr_resource_mgmt_3;
1523 u32 sq_thread_resource_mgmt;
1524 u32 sq_thread_resource_mgmt_2;
1525 u32 sq_stack_resource_mgmt_1;
1526 u32 sq_stack_resource_mgmt_2;
1527 u32 sq_stack_resource_mgmt_3;
1528 u32 vgt_cache_invalidation;
1529 u32 hdp_host_path_cntl;
1530 int i, j, num_shader_engines, ps_thread_count;
1531
1532 switch (rdev->family) {
1533 case CHIP_CYPRESS:
1534 case CHIP_HEMLOCK:
1535 rdev->config.evergreen.num_ses = 2;
1536 rdev->config.evergreen.max_pipes = 4;
1537 rdev->config.evergreen.max_tile_pipes = 8;
1538 rdev->config.evergreen.max_simds = 10;
1539 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1540 rdev->config.evergreen.max_gprs = 256;
1541 rdev->config.evergreen.max_threads = 248;
1542 rdev->config.evergreen.max_gs_threads = 32;
1543 rdev->config.evergreen.max_stack_entries = 512;
1544 rdev->config.evergreen.sx_num_of_sets = 4;
1545 rdev->config.evergreen.sx_max_export_size = 256;
1546 rdev->config.evergreen.sx_max_export_pos_size = 64;
1547 rdev->config.evergreen.sx_max_export_smx_size = 192;
1548 rdev->config.evergreen.max_hw_contexts = 8;
1549 rdev->config.evergreen.sq_num_cf_insts = 2;
1550
1551 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1552 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1553 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1554 break;
1555 case CHIP_JUNIPER:
1556 rdev->config.evergreen.num_ses = 1;
1557 rdev->config.evergreen.max_pipes = 4;
1558 rdev->config.evergreen.max_tile_pipes = 4;
1559 rdev->config.evergreen.max_simds = 10;
1560 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1561 rdev->config.evergreen.max_gprs = 256;
1562 rdev->config.evergreen.max_threads = 248;
1563 rdev->config.evergreen.max_gs_threads = 32;
1564 rdev->config.evergreen.max_stack_entries = 512;
1565 rdev->config.evergreen.sx_num_of_sets = 4;
1566 rdev->config.evergreen.sx_max_export_size = 256;
1567 rdev->config.evergreen.sx_max_export_pos_size = 64;
1568 rdev->config.evergreen.sx_max_export_smx_size = 192;
1569 rdev->config.evergreen.max_hw_contexts = 8;
1570 rdev->config.evergreen.sq_num_cf_insts = 2;
1571
1572 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1573 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1574 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1575 break;
1576 case CHIP_REDWOOD:
1577 rdev->config.evergreen.num_ses = 1;
1578 rdev->config.evergreen.max_pipes = 4;
1579 rdev->config.evergreen.max_tile_pipes = 4;
1580 rdev->config.evergreen.max_simds = 5;
1581 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1582 rdev->config.evergreen.max_gprs = 256;
1583 rdev->config.evergreen.max_threads = 248;
1584 rdev->config.evergreen.max_gs_threads = 32;
1585 rdev->config.evergreen.max_stack_entries = 256;
1586 rdev->config.evergreen.sx_num_of_sets = 4;
1587 rdev->config.evergreen.sx_max_export_size = 256;
1588 rdev->config.evergreen.sx_max_export_pos_size = 64;
1589 rdev->config.evergreen.sx_max_export_smx_size = 192;
1590 rdev->config.evergreen.max_hw_contexts = 8;
1591 rdev->config.evergreen.sq_num_cf_insts = 2;
1592
1593 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1594 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1595 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1596 break;
1597 case CHIP_CEDAR:
1598 default:
1599 rdev->config.evergreen.num_ses = 1;
1600 rdev->config.evergreen.max_pipes = 2;
1601 rdev->config.evergreen.max_tile_pipes = 2;
1602 rdev->config.evergreen.max_simds = 2;
1603 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1604 rdev->config.evergreen.max_gprs = 256;
1605 rdev->config.evergreen.max_threads = 192;
1606 rdev->config.evergreen.max_gs_threads = 16;
1607 rdev->config.evergreen.max_stack_entries = 256;
1608 rdev->config.evergreen.sx_num_of_sets = 4;
1609 rdev->config.evergreen.sx_max_export_size = 128;
1610 rdev->config.evergreen.sx_max_export_pos_size = 32;
1611 rdev->config.evergreen.sx_max_export_smx_size = 96;
1612 rdev->config.evergreen.max_hw_contexts = 4;
1613 rdev->config.evergreen.sq_num_cf_insts = 1;
1614
d5e455e4
AD		 1615 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1616 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1617 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1618 break;
1619 case CHIP_PALM:
1620 rdev->config.evergreen.num_ses = 1;
1621 rdev->config.evergreen.max_pipes = 2;
1622 rdev->config.evergreen.max_tile_pipes = 2;
1623 rdev->config.evergreen.max_simds = 2;
1624 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1625 rdev->config.evergreen.max_gprs = 256;
1626 rdev->config.evergreen.max_threads = 192;
1627 rdev->config.evergreen.max_gs_threads = 16;
1628 rdev->config.evergreen.max_stack_entries = 256;
1629 rdev->config.evergreen.sx_num_of_sets = 4;
1630 rdev->config.evergreen.sx_max_export_size = 128;
1631 rdev->config.evergreen.sx_max_export_pos_size = 32;
1632 rdev->config.evergreen.sx_max_export_smx_size = 96;
1633 rdev->config.evergreen.max_hw_contexts = 4;
1634 rdev->config.evergreen.sq_num_cf_insts = 1;
1635
32fcdbf4
AD		 1636 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1637 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1638 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1639 break;
1640 }
1641
1642 /* Initialize HDP */
1643 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1644 WREG32((0x2c14 + j), 0x00000000);
1645 WREG32((0x2c18 + j), 0x00000000);
1646 WREG32((0x2c1c + j), 0x00000000);
1647 WREG32((0x2c20 + j), 0x00000000);
1648 WREG32((0x2c24 + j), 0x00000000);
1649 }
1650
1651 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1652
1653 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1654
1655 cc_gc_shader_pipe_config |=
1656 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1657 & EVERGREEN_MAX_PIPES_MASK);
1658 cc_gc_shader_pipe_config |=
1659 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1660 & EVERGREEN_MAX_SIMDS_MASK);
1661
1662 cc_rb_backend_disable =
1663 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1664 & EVERGREEN_MAX_BACKENDS_MASK);
1665
1666
1667 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1668 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1669
1670 switch (rdev->config.evergreen.max_tile_pipes) {
1671 case 1:
1672 default:
1673 gb_addr_config |= NUM_PIPES(0);
1674 break;
1675 case 2:
1676 gb_addr_config |= NUM_PIPES(1);
1677 break;
1678 case 4:
1679 gb_addr_config |= NUM_PIPES(2);
1680 break;
1681 case 8:
1682 gb_addr_config |= NUM_PIPES(3);
1683 break;
1684 }
1685
1686 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1687 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1688 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1689 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1690 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1691 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1692
1693 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1694 gb_addr_config |= ROW_SIZE(2);
1695 else
1696 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1697
1698 if (rdev->ddev->pdev->device == 0x689e) {
1699 u32 efuse_straps_4;
1700 u32 efuse_straps_3;
1701 u8 efuse_box_bit_131_124;
1702
1703 WREG32(RCU_IND_INDEX, 0x204);
1704 efuse_straps_4 = RREG32(RCU_IND_DATA);
1705 WREG32(RCU_IND_INDEX, 0x203);
1706 efuse_straps_3 = RREG32(RCU_IND_DATA);
1707 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1708
1709 switch(efuse_box_bit_131_124) {
1710 case 0x00:
1711 gb_backend_map = 0x76543210;
1712 break;
1713 case 0x55:
1714 gb_backend_map = 0x77553311;
1715 break;
1716 case 0x56:
1717 gb_backend_map = 0x77553300;
1718 break;
1719 case 0x59:
1720 gb_backend_map = 0x77552211;
1721 break;
1722 case 0x66:
1723 gb_backend_map = 0x77443300;
1724 break;
1725 case 0x99:
1726 gb_backend_map = 0x66552211;
1727 break;
1728 case 0x5a:
1729 gb_backend_map = 0x77552200;
1730 break;
1731 case 0xaa:
1732 gb_backend_map = 0x66442200;
1733 break;
1734 case 0x95:
1735 gb_backend_map = 0x66553311;
1736 break;
1737 default:
1738 DRM_ERROR("bad backend map, using default\n");
1739 gb_backend_map =
1740 evergreen_get_tile_pipe_to_backend_map(rdev,
1741 rdev->config.evergreen.max_tile_pipes,
1742 rdev->config.evergreen.max_backends,
1743 ((EVERGREEN_MAX_BACKENDS_MASK <<
1744 rdev->config.evergreen.max_backends) &
1745 EVERGREEN_MAX_BACKENDS_MASK));
1746 break;
1747 }
1748 } else if (rdev->ddev->pdev->device == 0x68b9) {
1749 u32 efuse_straps_3;
1750 u8 efuse_box_bit_127_124;
1751
1752 WREG32(RCU_IND_INDEX, 0x203);
1753 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 1754 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 1755
1756 switch(efuse_box_bit_127_124) {
1757 case 0x0:
1758 gb_backend_map = 0x00003210;
1759 break;
1760 case 0x5:
1761 case 0x6:
1762 case 0x9:
1763 case 0xa:
1764 gb_backend_map = 0x00003311;
1765 break;
1766 default:
1767 DRM_ERROR("bad backend map, using default\n");
1768 gb_backend_map =
1769 evergreen_get_tile_pipe_to_backend_map(rdev,
1770 rdev->config.evergreen.max_tile_pipes,
1771 rdev->config.evergreen.max_backends,
1772 ((EVERGREEN_MAX_BACKENDS_MASK <<
1773 rdev->config.evergreen.max_backends) &
1774 EVERGREEN_MAX_BACKENDS_MASK));
1775 break;
1776 }
b741be82
AD		 1777 } else {
1778 switch (rdev->family) {
1779 case CHIP_CYPRESS:
1780 case CHIP_HEMLOCK:
1781 gb_backend_map = 0x66442200;
1782 break;
1783 case CHIP_JUNIPER:
1784 gb_backend_map = 0x00006420;
1785 break;
1786 default:
1787 gb_backend_map =
1788 evergreen_get_tile_pipe_to_backend_map(rdev,
1789 rdev->config.evergreen.max_tile_pipes,
1790 rdev->config.evergreen.max_backends,
1791 ((EVERGREEN_MAX_BACKENDS_MASK <<
1792 rdev->config.evergreen.max_backends) &
1793 EVERGREEN_MAX_BACKENDS_MASK));
1794 }
1795 }
32fcdbf4 1796
1aa52bd3
AD		 1797 /* setup tiling info dword. gb_addr_config is not adequate since it does
1798 * not have bank info, so create a custom tiling dword.
1799 * bits 3:0 num_pipes
1800 * bits 7:4 num_banks
1801 * bits 11:8 group_size
1802 * bits 15:12 row_size
1803 */
1804 rdev->config.evergreen.tile_config = 0;
1805 switch (rdev->config.evergreen.max_tile_pipes) {
1806 case 1:
1807 default:
1808 rdev->config.evergreen.tile_config |= (0 << 0);
1809 break;
1810 case 2:
1811 rdev->config.evergreen.tile_config |= (1 << 0);
1812 break;
1813 case 4:
1814 rdev->config.evergreen.tile_config |= (2 << 0);
1815 break;
1816 case 8:
1817 rdev->config.evergreen.tile_config |= (3 << 0);
1818 break;
1819 }
1820 rdev->config.evergreen.tile_config |=
1821 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1822 rdev->config.evergreen.tile_config |=
1823 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1824 rdev->config.evergreen.tile_config |=
1825 ((gb_addr_config & 0x30000000) >> 28) << 12;
1826
32fcdbf4
AD		 1827 WREG32(GB_BACKEND_MAP, gb_backend_map);
1828 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1829 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1830 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1831
9535ab73
AD		 1832 evergreen_program_channel_remap(rdev);
1833
32fcdbf4
AD		 1834 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1835 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1836
1837 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1838 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1839 u32 sp = cc_gc_shader_pipe_config;
1840 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1841
1842 if (i == num_shader_engines) {
1843 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1844 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1845 }
1846
1847 WREG32(GRBM_GFX_INDEX, gfx);
1848 WREG32(RLC_GFX_INDEX, gfx);
1849
1850 WREG32(CC_RB_BACKEND_DISABLE, rb);
1851 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1852 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1853 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1854 }
1855
1856 grbm_gfx_index |= SE_BROADCAST_WRITES;
1857 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1858 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1859
1860 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1861 WREG32(CGTS_TCC_DISABLE, 0);
1862 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1863 WREG32(CGTS_USER_TCC_DISABLE, 0);
1864
1865 /* set HW defaults for 3D engine */
1866 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1867 ROQ_IB2_START(0x2b)));
1868
1869 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1870
1871 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1872 SYNC_GRADIENT |
1873 SYNC_WALKER |
1874 SYNC_ALIGNER));
1875
1876 sx_debug_1 = RREG32(SX_DEBUG_1);
1877 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1878 WREG32(SX_DEBUG_1, sx_debug_1);
1879
1880
1881 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1882 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1883 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1884 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1885
1886 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1887 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1888 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1889
1890 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1891 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1892 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1893
1894 WREG32(VGT_NUM_INSTANCES, 1);
1895 WREG32(SPI_CONFIG_CNTL, 0);
1896 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1897 WREG32(CP_PERFMON_CNTL, 0);
1898
1899 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1900 FETCH_FIFO_HIWATER(0x4) |
1901 DONE_FIFO_HIWATER(0xe0) |
1902 ALU_UPDATE_FIFO_HIWATER(0x8)));
1903
1904 sq_config = RREG32(SQ_CONFIG);
1905 sq_config &= ~(PS_PRIO(3) |
1906 VS_PRIO(3) |
1907 GS_PRIO(3) |
1908 ES_PRIO(3));
1909 sq_config |= (VC_ENABLE |
1910 EXPORT_SRC_C |
1911 PS_PRIO(0) |
1912 VS_PRIO(1) |
1913 GS_PRIO(2) |
1914 ES_PRIO(3));
1915
d5e455e4
AD		 1916 switch (rdev->family) {
1917 case CHIP_CEDAR:
1918 case CHIP_PALM:
32fcdbf4
AD		 1919 /* no vertex cache */
1920 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 1921 break;
1922 default:
1923 break;
1924 }
32fcdbf4
AD		 1925
1926 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1927
1928 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1929 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1930 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1931 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1932 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1933 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1934 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1935
d5e455e4
AD		 1936 switch (rdev->family) {
1937 case CHIP_CEDAR:
1938 case CHIP_PALM:
32fcdbf4 1939 ps_thread_count = 96;
d5e455e4
AD		 1940 break;
1941 default:
32fcdbf4 1942 ps_thread_count = 128;
d5e455e4
AD		 1943 break;
1944 }
32fcdbf4
AD		 1945
1946 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 1947 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1948 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1949 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1950 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1951 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 1952
1953 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1954 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1955 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1956 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1957 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1958 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1959
1960 WREG32(SQ_CONFIG, sq_config);
1961 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1962 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1963 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1964 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1965 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1966 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1967 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1968 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1969 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1970 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1971
1972 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1973 FORCE_EOV_MAX_REZ_CNT(255)));
1974
d5e455e4
AD		 1975 switch (rdev->family) {
1976 case CHIP_CEDAR:
1977 case CHIP_PALM:
32fcdbf4 1978 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 1979 break;
1980 default:
32fcdbf4 1981 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 1982 break;
1983 }
32fcdbf4
AD		 1984 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1985 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1986
1987 WREG32(VGT_GS_VERTEX_REUSE, 16);
1988 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1989
60a4a3e0
AD		 1990 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1991 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1992
32fcdbf4
AD		 1993 WREG32(CB_PERF_CTR0_SEL_0, 0);
1994 WREG32(CB_PERF_CTR0_SEL_1, 0);
1995 WREG32(CB_PERF_CTR1_SEL_0, 0);
1996 WREG32(CB_PERF_CTR1_SEL_1, 0);
1997 WREG32(CB_PERF_CTR2_SEL_0, 0);
1998 WREG32(CB_PERF_CTR2_SEL_1, 0);
1999 WREG32(CB_PERF_CTR3_SEL_0, 0);
2000 WREG32(CB_PERF_CTR3_SEL_1, 0);
2001
60a4a3e0
AD		 2002 /* clear render buffer base addresses */
2003 WREG32(CB_COLOR0_BASE, 0);
2004 WREG32(CB_COLOR1_BASE, 0);
2005 WREG32(CB_COLOR2_BASE, 0);
2006 WREG32(CB_COLOR3_BASE, 0);
2007 WREG32(CB_COLOR4_BASE, 0);
2008 WREG32(CB_COLOR5_BASE, 0);
2009 WREG32(CB_COLOR6_BASE, 0);
2010 WREG32(CB_COLOR7_BASE, 0);
2011 WREG32(CB_COLOR8_BASE, 0);
2012 WREG32(CB_COLOR9_BASE, 0);
2013 WREG32(CB_COLOR10_BASE, 0);
2014 WREG32(CB_COLOR11_BASE, 0);
2015
2016 /* set the shader const cache sizes to 0 */
2017 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2018 WREG32(i, 0);
2019 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2020 WREG32(i, 0);
2021
32fcdbf4
AD		 2022 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2023 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2024
2025 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2026
2027 udelay(50);
2028
bcc1c2a1
AD		 2029}
2030
2031int evergreen_mc_init(struct radeon_device *rdev)
2032{
bcc1c2a1
AD		 2033 u32 tmp;
2034 int chansize, numchan;
bcc1c2a1
AD		 2035
2036 /* Get VRAM informations */
2037 rdev->mc.vram_is_ddr = true;
2038 tmp = RREG32(MC_ARB_RAMCFG);
2039 if (tmp & CHANSIZE_OVERRIDE) {
2040 chansize = 16;
2041 } else if (tmp & CHANSIZE_MASK) {
2042 chansize = 64;
2043 } else {
2044 chansize = 32;
2045 }
2046 tmp = RREG32(MC_SHARED_CHMAP);
2047 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2048 case 0:
2049 default:
2050 numchan = 1;
2051 break;
2052 case 1:
2053 numchan = 2;
2054 break;
2055 case 2:
2056 numchan = 4;
2057 break;
2058 case 3:
2059 numchan = 8;
2060 break;
2061 }
2062 rdev->mc.vram_width = numchan * chansize;
2063 /* Could aper size report 0 ? */
01d73a69
JC		 2064 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2065 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2066 /* Setup GPU memory space */
6eb18f8b
AD		 2067 if (rdev->flags & RADEON_IS_IGP) {
2068 /* size in bytes on fusion */
2069 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2070 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2071 } else {
2072 /* size in MB on evergreen */
2073 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2074 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2075 }
51e5fcd3 2076 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 2077 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
0ef0c1f7 2078 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2079 radeon_update_bandwidth_info(rdev);
2080
bcc1c2a1
AD		 2081 return 0;
2082}
d594e46a 2083
225758d8
JG		 2084bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2085{
2086 /* FIXME: implement for evergreen */
2087 return false;
2088}
2089
747943ea 2090static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2091{
747943ea
AD		 2092 struct evergreen_mc_save save;
2093 u32 srbm_reset = 0;
2094 u32 grbm_reset = 0;
2095
2096 dev_info(rdev->dev, "GPU softreset \n");
2097 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2098 RREG32(GRBM_STATUS));
2099 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2100 RREG32(GRBM_STATUS_SE0));
2101 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2102 RREG32(GRBM_STATUS_SE1));
2103 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2104 RREG32(SRBM_STATUS));
2105 evergreen_mc_stop(rdev, &save);
2106 if (evergreen_mc_wait_for_idle(rdev)) {
2107 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2108 }
2109 /* Disable CP parsing/prefetching */
2110 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2111
2112 /* reset all the gfx blocks */
2113 grbm_reset = (SOFT_RESET_CP |
2114 SOFT_RESET_CB |
2115 SOFT_RESET_DB |
2116 SOFT_RESET_PA |
2117 SOFT_RESET_SC |
2118 SOFT_RESET_SPI |
2119 SOFT_RESET_SH |
2120 SOFT_RESET_SX |
2121 SOFT_RESET_TC |
2122 SOFT_RESET_TA |
2123 SOFT_RESET_VC |
2124 SOFT_RESET_VGT);
2125
2126 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2127 WREG32(GRBM_SOFT_RESET, grbm_reset);
2128 (void)RREG32(GRBM_SOFT_RESET);
2129 udelay(50);
2130 WREG32(GRBM_SOFT_RESET, 0);
2131 (void)RREG32(GRBM_SOFT_RESET);
2132
2133 /* reset all the system blocks */
2134 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
2135
2136 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
2137 WREG32(SRBM_SOFT_RESET, srbm_reset);
2138 (void)RREG32(SRBM_SOFT_RESET);
2139 udelay(50);
2140 WREG32(SRBM_SOFT_RESET, 0);
2141 (void)RREG32(SRBM_SOFT_RESET);
2142 /* Wait a little for things to settle down */
2143 udelay(50);
2144 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2145 RREG32(GRBM_STATUS));
2146 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2147 RREG32(GRBM_STATUS_SE0));
2148 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2149 RREG32(GRBM_STATUS_SE1));
2150 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2151 RREG32(SRBM_STATUS));
2152 /* After reset we need to reinit the asic as GPU often endup in an
2153 * incoherent state.
2154 */
2155 atom_asic_init(rdev->mode_info.atom_context);
2156 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2157 return 0;
2158}
2159
a2d07b74 2160int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2161{
747943ea
AD		 2162 return evergreen_gpu_soft_reset(rdev);
2163}
2164
45f9a39b
AD		 2165/* Interrupts */
2166
2167u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2168{
2169 switch (crtc) {
2170 case 0:
2171 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2172 case 1:
2173 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2174 case 2:
2175 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2176 case 3:
2177 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2178 case 4:
2179 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2180 case 5:
2181 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2182 default:
2183 return 0;
2184 }
2185}
2186
2187void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2188{
2189 u32 tmp;
2190
3555e53b 2191 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2192 WREG32(GRBM_INT_CNTL, 0);
2193 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2194 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2195 if (!(rdev->flags & RADEON_IS_IGP)) {
2196 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2197 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2198 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2199 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2200 }
45f9a39b
AD		 2201
2202 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2203 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2204 if (!(rdev->flags & RADEON_IS_IGP)) {
2205 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2206 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2207 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2208 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2209 }
45f9a39b
AD		 2210
2211 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2212 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2213
2214 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2215 WREG32(DC_HPD1_INT_CONTROL, tmp);
2216 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2217 WREG32(DC_HPD2_INT_CONTROL, tmp);
2218 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2219 WREG32(DC_HPD3_INT_CONTROL, tmp);
2220 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2221 WREG32(DC_HPD4_INT_CONTROL, tmp);
2222 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2223 WREG32(DC_HPD5_INT_CONTROL, tmp);
2224 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2225 WREG32(DC_HPD6_INT_CONTROL, tmp);
2226
2227}
2228
2229int evergreen_irq_set(struct radeon_device *rdev)
2230{
2231 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2232 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2233 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2234 u32 grbm_int_cntl = 0;
6f34be50 2235 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
45f9a39b
AD		 2236
2237 if (!rdev->irq.installed) {
fce7d61b 2238 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2239 return -EINVAL;
2240 }
2241 /* don't enable anything if the ih is disabled */
2242 if (!rdev->ih.enabled) {
2243 r600_disable_interrupts(rdev);
2244 /* force the active interrupt state to all disabled */
2245 evergreen_disable_interrupt_state(rdev);
2246 return 0;
2247 }
2248
2249 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2250 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2251 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2252 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2253 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2254 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2255
2256 if (rdev->irq.sw_int) {
2257 DRM_DEBUG("evergreen_irq_set: sw int\n");
2258 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 2259 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
45f9a39b 2260 }
6f34be50
AD		 2261 if (rdev->irq.crtc_vblank_int[0] ||
2262 rdev->irq.pflip[0]) {
45f9a39b
AD		 2263 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2264 crtc1 |= VBLANK_INT_MASK;
2265 }
6f34be50
AD		 2266 if (rdev->irq.crtc_vblank_int[1] ||
2267 rdev->irq.pflip[1]) {
45f9a39b
AD		 2268 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2269 crtc2 |= VBLANK_INT_MASK;
2270 }
6f34be50
AD		 2271 if (rdev->irq.crtc_vblank_int[2] ||
2272 rdev->irq.pflip[2]) {
45f9a39b
AD		 2273 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2274 crtc3 |= VBLANK_INT_MASK;
2275 }
6f34be50
AD		 2276 if (rdev->irq.crtc_vblank_int[3] ||
2277 rdev->irq.pflip[3]) {
45f9a39b
AD		 2278 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2279 crtc4 |= VBLANK_INT_MASK;
2280 }
6f34be50
AD		 2281 if (rdev->irq.crtc_vblank_int[4] ||
2282 rdev->irq.pflip[4]) {
45f9a39b
AD		 2283 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2284 crtc5 |= VBLANK_INT_MASK;
2285 }
6f34be50
AD		 2286 if (rdev->irq.crtc_vblank_int[5] ||
2287 rdev->irq.pflip[5]) {
45f9a39b
AD		 2288 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2289 crtc6 |= VBLANK_INT_MASK;
2290 }
2291 if (rdev->irq.hpd[0]) {
2292 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2293 hpd1 |= DC_HPDx_INT_EN;
2294 }
2295 if (rdev->irq.hpd[1]) {
2296 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2297 hpd2 |= DC_HPDx_INT_EN;
2298 }
2299 if (rdev->irq.hpd[2]) {
2300 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2301 hpd3 |= DC_HPDx_INT_EN;
2302 }
2303 if (rdev->irq.hpd[3]) {
2304 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2305 hpd4 |= DC_HPDx_INT_EN;
2306 }
2307 if (rdev->irq.hpd[4]) {
2308 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2309 hpd5 |= DC_HPDx_INT_EN;
2310 }
2311 if (rdev->irq.hpd[5]) {
2312 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2313 hpd6 |= DC_HPDx_INT_EN;
2314 }
2031f77c
AD		 2315 if (rdev->irq.gui_idle) {
2316 DRM_DEBUG("gui idle\n");
2317 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2318 }
45f9a39b
AD		 2319
2320 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2321 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2322
2323 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2324 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
18007401
AD		 2325 if (!(rdev->flags & RADEON_IS_IGP)) {
2326 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2327 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2328 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2329 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2330 }
45f9a39b 2331
6f34be50
AD		 2332 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2333 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2334 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2335 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2336 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2337 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2338
45f9a39b
AD		 2339 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2340 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2341 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2342 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2343 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2344 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2345
bcc1c2a1
AD		 2346 return 0;
2347}
2348
6f34be50 2349static inline void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2350{
2351 u32 tmp;
2352
6f34be50
AD		 2353 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2354 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2355 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2356 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2357 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2358 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2359 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2360 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2361 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2362 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2363 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2364 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2365
2366 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2367 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2368 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2369 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2370 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2371 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2372 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2373 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2374 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2375 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2376 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2377 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2378
2379 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2380 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2381 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b
AD		 2382 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2383
6f34be50 2384 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2385 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2386 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2387 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2388
6f34be50 2389 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
45f9a39b 2390 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2391 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
45f9a39b
AD		 2392 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2393
6f34be50 2394 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
45f9a39b 2395 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2396 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
45f9a39b
AD		 2397 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2398
6f34be50 2399 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
45f9a39b 2400 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2401 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
45f9a39b
AD		 2402 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2403
6f34be50 2404 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
45f9a39b 2405 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2406 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
45f9a39b
AD		 2407 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2408
6f34be50 2409 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2410 tmp = RREG32(DC_HPD1_INT_CONTROL);
2411 tmp |= DC_HPDx_INT_ACK;
2412 WREG32(DC_HPD1_INT_CONTROL, tmp);
2413 }
6f34be50 2414 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2415 tmp = RREG32(DC_HPD2_INT_CONTROL);
2416 tmp |= DC_HPDx_INT_ACK;
2417 WREG32(DC_HPD2_INT_CONTROL, tmp);
2418 }
6f34be50 2419 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2420 tmp = RREG32(DC_HPD3_INT_CONTROL);
2421 tmp |= DC_HPDx_INT_ACK;
2422 WREG32(DC_HPD3_INT_CONTROL, tmp);
2423 }
6f34be50 2424 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2425 tmp = RREG32(DC_HPD4_INT_CONTROL);
2426 tmp |= DC_HPDx_INT_ACK;
2427 WREG32(DC_HPD4_INT_CONTROL, tmp);
2428 }
6f34be50 2429 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2430 tmp = RREG32(DC_HPD5_INT_CONTROL);
2431 tmp |= DC_HPDx_INT_ACK;
2432 WREG32(DC_HPD5_INT_CONTROL, tmp);
2433 }
6f34be50 2434 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2435 tmp = RREG32(DC_HPD5_INT_CONTROL);
2436 tmp |= DC_HPDx_INT_ACK;
2437 WREG32(DC_HPD6_INT_CONTROL, tmp);
2438 }
2439}
2440
2441void evergreen_irq_disable(struct radeon_device *rdev)
2442{
45f9a39b
AD		 2443 r600_disable_interrupts(rdev);
2444 /* Wait and acknowledge irq */
2445 mdelay(1);
6f34be50 2446 evergreen_irq_ack(rdev);
45f9a39b
AD		 2447 evergreen_disable_interrupt_state(rdev);
2448}
2449
2450static void evergreen_irq_suspend(struct radeon_device *rdev)
2451{
2452 evergreen_irq_disable(rdev);
2453 r600_rlc_stop(rdev);
2454}
2455
2456static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2457{
2458 u32 wptr, tmp;
2459
724c80e1
AD		 2460 if (rdev->wb.enabled)
2461 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2462 else
2463 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2464
2465 if (wptr & RB_OVERFLOW) {
2466 /* When a ring buffer overflow happen start parsing interrupt
2467 * from the last not overwritten vector (wptr + 16). Hopefully
2468 * this should allow us to catchup.
2469 */
2470 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2471 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2472 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2473 tmp = RREG32(IH_RB_CNTL);
2474 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2475 WREG32(IH_RB_CNTL, tmp);
2476 }
2477 return (wptr & rdev->ih.ptr_mask);
2478}
2479
2480int evergreen_irq_process(struct radeon_device *rdev)
2481{
2482 u32 wptr = evergreen_get_ih_wptr(rdev);
2483 u32 rptr = rdev->ih.rptr;
2484 u32 src_id, src_data;
2485 u32 ring_index;
45f9a39b
AD		 2486 unsigned long flags;
2487 bool queue_hotplug = false;
2488
2489 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2490 if (!rdev->ih.enabled)
2491 return IRQ_NONE;
2492
2493 spin_lock_irqsave(&rdev->ih.lock, flags);
2494
2495 if (rptr == wptr) {
2496 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2497 return IRQ_NONE;
2498 }
2499 if (rdev->shutdown) {
2500 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2501 return IRQ_NONE;
2502 }
2503
2504restart_ih:
2505 /* display interrupts */
6f34be50 2506 evergreen_irq_ack(rdev);
45f9a39b
AD		 2507
2508 rdev->ih.wptr = wptr;
2509 while (rptr != wptr) {
2510 /* wptr/rptr are in bytes! */
2511 ring_index = rptr / 4;
2512 src_id = rdev->ih.ring[ring_index] & 0xff;
2513 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2514
2515 switch (src_id) {
2516 case 1: /* D1 vblank/vline */
2517 switch (src_data) {
2518 case 0: /* D1 vblank */
6f34be50 2519 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2520 if (rdev->irq.crtc_vblank_int[0]) {
2521 drm_handle_vblank(rdev->ddev, 0);
2522 rdev->pm.vblank_sync = true;
2523 wake_up(&rdev->irq.vblank_queue);
2524 }
3e4ea742
MK		 2525 if (rdev->irq.pflip[0])
2526 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2527 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2528 DRM_DEBUG("IH: D1 vblank\n");
2529 }
2530 break;
2531 case 1: /* D1 vline */
6f34be50
AD		 2532 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2533 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2534 DRM_DEBUG("IH: D1 vline\n");
2535 }
2536 break;
2537 default:
2538 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2539 break;
2540 }
2541 break;
2542 case 2: /* D2 vblank/vline */
2543 switch (src_data) {
2544 case 0: /* D2 vblank */
6f34be50 2545 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2546 if (rdev->irq.crtc_vblank_int[1]) {
2547 drm_handle_vblank(rdev->ddev, 1);
2548 rdev->pm.vblank_sync = true;
2549 wake_up(&rdev->irq.vblank_queue);
2550 }
3e4ea742
MK		 2551 if (rdev->irq.pflip[1])
2552 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2553 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2554 DRM_DEBUG("IH: D2 vblank\n");
2555 }
2556 break;
2557 case 1: /* D2 vline */
6f34be50
AD		 2558 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2559 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2560 DRM_DEBUG("IH: D2 vline\n");
2561 }
2562 break;
2563 default:
2564 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2565 break;
2566 }
2567 break;
2568 case 3: /* D3 vblank/vline */
2569 switch (src_data) {
2570 case 0: /* D3 vblank */
6f34be50
AD		 2571 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2572 if (rdev->irq.crtc_vblank_int[2]) {
2573 drm_handle_vblank(rdev->ddev, 2);
2574 rdev->pm.vblank_sync = true;
2575 wake_up(&rdev->irq.vblank_queue);
2576 }
2577 if (rdev->irq.pflip[2])
2578 radeon_crtc_handle_flip(rdev, 2);
2579 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2580 DRM_DEBUG("IH: D3 vblank\n");
2581 }
2582 break;
2583 case 1: /* D3 vline */
6f34be50
AD		 2584 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2585 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2586 DRM_DEBUG("IH: D3 vline\n");
2587 }
2588 break;
2589 default:
2590 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2591 break;
2592 }
2593 break;
2594 case 4: /* D4 vblank/vline */
2595 switch (src_data) {
2596 case 0: /* D4 vblank */
6f34be50
AD		 2597 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2598 if (rdev->irq.crtc_vblank_int[3]) {
2599 drm_handle_vblank(rdev->ddev, 3);
2600 rdev->pm.vblank_sync = true;
2601 wake_up(&rdev->irq.vblank_queue);
2602 }
2603 if (rdev->irq.pflip[3])
2604 radeon_crtc_handle_flip(rdev, 3);
2605 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2606 DRM_DEBUG("IH: D4 vblank\n");
2607 }
2608 break;
2609 case 1: /* D4 vline */
6f34be50
AD		 2610 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2611 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2612 DRM_DEBUG("IH: D4 vline\n");
2613 }
2614 break;
2615 default:
2616 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2617 break;
2618 }
2619 break;
2620 case 5: /* D5 vblank/vline */
2621 switch (src_data) {
2622 case 0: /* D5 vblank */
6f34be50
AD		 2623 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2624 if (rdev->irq.crtc_vblank_int[4]) {
2625 drm_handle_vblank(rdev->ddev, 4);
2626 rdev->pm.vblank_sync = true;
2627 wake_up(&rdev->irq.vblank_queue);
2628 }
2629 if (rdev->irq.pflip[4])
2630 radeon_crtc_handle_flip(rdev, 4);
2631 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 2632 DRM_DEBUG("IH: D5 vblank\n");
2633 }
2634 break;
2635 case 1: /* D5 vline */
6f34be50
AD		 2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2637 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 2638 DRM_DEBUG("IH: D5 vline\n");
2639 }
2640 break;
2641 default:
2642 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2643 break;
2644 }
2645 break;
2646 case 6: /* D6 vblank/vline */
2647 switch (src_data) {
2648 case 0: /* D6 vblank */
6f34be50
AD		 2649 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2650 if (rdev->irq.crtc_vblank_int[5]) {
2651 drm_handle_vblank(rdev->ddev, 5);
2652 rdev->pm.vblank_sync = true;
2653 wake_up(&rdev->irq.vblank_queue);
2654 }
2655 if (rdev->irq.pflip[5])
2656 radeon_crtc_handle_flip(rdev, 5);
2657 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 2658 DRM_DEBUG("IH: D6 vblank\n");
2659 }
2660 break;
2661 case 1: /* D6 vline */
6f34be50
AD		 2662 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2663 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 2664 DRM_DEBUG("IH: D6 vline\n");
2665 }
2666 break;
2667 default:
2668 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2669 break;
2670 }
2671 break;
2672 case 42: /* HPD hotplug */
2673 switch (src_data) {
2674 case 0:
6f34be50
AD		 2675 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2676 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 2677 queue_hotplug = true;
2678 DRM_DEBUG("IH: HPD1\n");
2679 }
2680 break;
2681 case 1:
6f34be50
AD		 2682 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2683 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 2684 queue_hotplug = true;
2685 DRM_DEBUG("IH: HPD2\n");
2686 }
2687 break;
2688 case 2:
6f34be50
AD		 2689 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2690 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 2691 queue_hotplug = true;
2692 DRM_DEBUG("IH: HPD3\n");
2693 }
2694 break;
2695 case 3:
6f34be50
AD		 2696 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2697 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 2698 queue_hotplug = true;
2699 DRM_DEBUG("IH: HPD4\n");
2700 }
2701 break;
2702 case 4:
6f34be50
AD		 2703 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2704 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 2705 queue_hotplug = true;
2706 DRM_DEBUG("IH: HPD5\n");
2707 }
2708 break;
2709 case 5:
6f34be50
AD		 2710 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2711 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 2712 queue_hotplug = true;
2713 DRM_DEBUG("IH: HPD6\n");
2714 }
2715 break;
2716 default:
2717 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2718 break;
2719 }
2720 break;
2721 case 176: /* CP_INT in ring buffer */
2722 case 177: /* CP_INT in IB1 */
2723 case 178: /* CP_INT in IB2 */
2724 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2725 radeon_fence_process(rdev);
2726 break;
2727 case 181: /* CP EOP event */
2728 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 2729 radeon_fence_process(rdev);
45f9a39b 2730 break;
2031f77c
AD		 2731 case 233: /* GUI IDLE */
2732 DRM_DEBUG("IH: CP EOP\n");
2733 rdev->pm.gui_idle = true;
2734 wake_up(&rdev->irq.idle_queue);
2735 break;
45f9a39b
AD		 2736 default:
2737 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2738 break;
2739 }
2740
2741 /* wptr/rptr are in bytes! */
2742 rptr += 16;
2743 rptr &= rdev->ih.ptr_mask;
2744 }
2745 /* make sure wptr hasn't changed while processing */
2746 wptr = evergreen_get_ih_wptr(rdev);
2747 if (wptr != rdev->ih.wptr)
2748 goto restart_ih;
2749 if (queue_hotplug)
2750 queue_work(rdev->wq, &rdev->hotplug_work);
2751 rdev->ih.rptr = rptr;
2752 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2753 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2754 return IRQ_HANDLED;
2755}
2756
bcc1c2a1
AD		 2757static int evergreen_startup(struct radeon_device *rdev)
2758{
bcc1c2a1
AD		 2759 int r;
2760
2761 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2762 r = r600_init_microcode(rdev);
2763 if (r) {
2764 DRM_ERROR("Failed to load firmware!\n");
2765 return r;
2766 }
2767 }
fe251e2f 2768
bcc1c2a1 2769 evergreen_mc_program(rdev);
bcc1c2a1 2770 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 2771 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 2772 } else {
2773 r = evergreen_pcie_gart_enable(rdev);
2774 if (r)
2775 return r;
2776 }
bcc1c2a1 2777 evergreen_gpu_init(rdev);
bcc1c2a1 2778
d7ccd8fc 2779 r = evergreen_blit_init(rdev);
bcc1c2a1 2780 if (r) {
d7ccd8fc
AD		 2781 evergreen_blit_fini(rdev);
2782 rdev->asic->copy = NULL;
2783 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 2784 }
2785
724c80e1
AD		 2786 /* allocate wb buffer */
2787 r = radeon_wb_init(rdev);
2788 if (r)
2789 return r;
2790
bcc1c2a1
AD		 2791 /* Enable IRQ */
2792 r = r600_irq_init(rdev);
2793 if (r) {
2794 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2795 radeon_irq_kms_fini(rdev);
2796 return r;
2797 }
45f9a39b 2798 evergreen_irq_set(rdev);
bcc1c2a1
AD		 2799
2800 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2801 if (r)
2802 return r;
2803 r = evergreen_cp_load_microcode(rdev);
2804 if (r)
2805 return r;
fe251e2f 2806 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 2807 if (r)
2808 return r;
fe251e2f 2809
bcc1c2a1
AD		 2810 return 0;
2811}
2812
2813int evergreen_resume(struct radeon_device *rdev)
2814{
2815 int r;
2816
2817 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2818 * posting will perform necessary task to bring back GPU into good
2819 * shape.
2820 */
2821 /* post card */
2822 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1
AD		 2823
2824 r = evergreen_startup(rdev);
2825 if (r) {
2826 DRM_ERROR("r600 startup failed on resume\n");
2827 return r;
2828 }
fe251e2f 2829
bcc1c2a1
AD		 2830 r = r600_ib_test(rdev);
2831 if (r) {
2832 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2833 return r;
2834 }
fe251e2f 2835
bcc1c2a1
AD		 2836 return r;
2837
2838}
2839
2840int evergreen_suspend(struct radeon_device *rdev)
2841{
bcc1c2a1 2842 int r;
d7ccd8fc 2843
bcc1c2a1
AD		 2844 /* FIXME: we should wait for ring to be empty */
2845 r700_cp_stop(rdev);
2846 rdev->cp.ready = false;
45f9a39b 2847 evergreen_irq_suspend(rdev);
724c80e1 2848 radeon_wb_disable(rdev);
bcc1c2a1 2849 evergreen_pcie_gart_disable(rdev);
d7ccd8fc 2850
bcc1c2a1
AD		 2851 /* unpin shaders bo */
2852 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2853 if (likely(r == 0)) {
2854 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2855 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2856 }
d7ccd8fc
AD		 2857
2858 return 0;
2859}
2860
2861int evergreen_copy_blit(struct radeon_device *rdev,
2862 uint64_t src_offset, uint64_t dst_offset,
2863 unsigned num_pages, struct radeon_fence *fence)
2864{
2865 int r;
2866
2867 mutex_lock(&rdev->r600_blit.mutex);
2868 rdev->r600_blit.vb_ib = NULL;
2869 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2870 if (r) {
2871 if (rdev->r600_blit.vb_ib)
2872 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2873 mutex_unlock(&rdev->r600_blit.mutex);
2874 return r;
2875 }
2876 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2877 evergreen_blit_done_copy(rdev, fence);
2878 mutex_unlock(&rdev->r600_blit.mutex);
bcc1c2a1
AD		 2879 return 0;
2880}
2881
2882static bool evergreen_card_posted(struct radeon_device *rdev)
2883{
2884 u32 reg;
2885
2886 /* first check CRTCs */
18007401
AD		 2887 if (rdev->flags & RADEON_IS_IGP)
2888 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2889 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2890 else
2891 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2892 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2893 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2894 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2895 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2896 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
bcc1c2a1
AD		 2897 if (reg & EVERGREEN_CRTC_MASTER_EN)
2898 return true;
2899
2900 /* then check MEM_SIZE, in case the crtcs are off */
2901 if (RREG32(CONFIG_MEMSIZE))
2902 return true;
2903
2904 return false;
2905}
2906
2907/* Plan is to move initialization in that function and use
2908 * helper function so that radeon_device_init pretty much
2909 * do nothing more than calling asic specific function. This
2910 * should also allow to remove a bunch of callback function
2911 * like vram_info.
2912 */
2913int evergreen_init(struct radeon_device *rdev)
2914{
2915 int r;
2916
2917 r = radeon_dummy_page_init(rdev);
2918 if (r)
2919 return r;
2920 /* This don't do much */
2921 r = radeon_gem_init(rdev);
2922 if (r)
2923 return r;
2924 /* Read BIOS */
2925 if (!radeon_get_bios(rdev)) {
2926 if (ASIC_IS_AVIVO(rdev))
2927 return -EINVAL;
2928 }
2929 /* Must be an ATOMBIOS */
2930 if (!rdev->is_atom_bios) {
2931 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2932 return -EINVAL;
2933 }
2934 r = radeon_atombios_init(rdev);
2935 if (r)
2936 return r;
2937 /* Post card if necessary */
2938 if (!evergreen_card_posted(rdev)) {
2939 if (!rdev->bios) {
2940 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2941 return -EINVAL;
2942 }
2943 DRM_INFO("GPU not posted. posting now...\n");
2944 atom_asic_init(rdev->mode_info.atom_context);
2945 }
2946 /* Initialize scratch registers */
2947 r600_scratch_init(rdev);
2948 /* Initialize surface registers */
2949 radeon_surface_init(rdev);
2950 /* Initialize clocks */
2951 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 2952 /* Fence driver */
2953 r = radeon_fence_driver_init(rdev);
2954 if (r)
2955 return r;
d594e46a
JG		 2956 /* initialize AGP */
2957 if (rdev->flags & RADEON_IS_AGP) {
2958 r = radeon_agp_init(rdev);
2959 if (r)
2960 radeon_agp_disable(rdev);
2961 }
2962 /* initialize memory controller */
bcc1c2a1
AD		 2963 r = evergreen_mc_init(rdev);
2964 if (r)
2965 return r;
2966 /* Memory manager */
2967 r = radeon_bo_init(rdev);
2968 if (r)
2969 return r;
45f9a39b 2970
bcc1c2a1
AD		 2971 r = radeon_irq_kms_init(rdev);
2972 if (r)
2973 return r;
2974
2975 rdev->cp.ring_obj = NULL;
2976 r600_ring_init(rdev, 1024 * 1024);
2977
2978 rdev->ih.ring_obj = NULL;
2979 r600_ih_ring_init(rdev, 64 * 1024);
2980
2981 r = r600_pcie_gart_init(rdev);
2982 if (r)
2983 return r;
0fcdb61e 2984
148a03bc 2985 rdev->accel_working = true;
bcc1c2a1
AD		 2986 r = evergreen_startup(rdev);
2987 if (r) {
fe251e2f
AD		 2988 dev_err(rdev->dev, "disabling GPU acceleration\n");
2989 r700_cp_fini(rdev);
fe251e2f 2990 r600_irq_fini(rdev);
724c80e1 2991 radeon_wb_fini(rdev);
fe251e2f 2992 radeon_irq_kms_fini(rdev);
0fcdb61e 2993 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2994 rdev->accel_working = false;
2995 }
2996 if (rdev->accel_working) {
2997 r = radeon_ib_pool_init(rdev);
2998 if (r) {
2999 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3000 rdev->accel_working = false;
3001 }
3002 r = r600_ib_test(rdev);
3003 if (r) {
3004 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3005 rdev->accel_working = false;
3006 }
3007 }
3008 return 0;
3009}
3010
3011void evergreen_fini(struct radeon_device *rdev)
3012{
d7ccd8fc 3013 evergreen_blit_fini(rdev);
45f9a39b 3014 r700_cp_fini(rdev);
bcc1c2a1 3015 r600_irq_fini(rdev);
724c80e1 3016 radeon_wb_fini(rdev);
bcc1c2a1 3017 radeon_irq_kms_fini(rdev);
bcc1c2a1 3018 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3019 radeon_gem_fini(rdev);
3020 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3021 radeon_agp_fini(rdev);
3022 radeon_bo_fini(rdev);
3023 radeon_atombios_fini(rdev);
3024 kfree(rdev->bios);
3025 rdev->bios = NULL;
3026 radeon_dummy_page_fini(rdev);
3027}
Linux kernel - Deliverables
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