[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen_hdmi.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Christian König.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 *          Rafał Miłecki
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_asic.h"
#include "evergreend.h"
#include "atom.h"

/*
 * update the N and CTS parameters for a given pixel clock rate
 */
static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;

	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
	WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);

	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
	WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);

	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
}

/*
 * build a HDMI Video Info Frame
 */
static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
						void *buffer, size_t size)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;
	uint8_t *frame = buffer + 3;

	/* Our header values (type, version, length) should be alright, Intel
	 * is using the same. Checksum function also seems to be OK, it works
	 * fine for audio infoframe. However calculated value is always lower
	 * by 2 in comparison to fglrx. It breaks displaying anything in case
	 * of TVs that strictly check the checksum. Hack it manually here to
	 * workaround this issue. */
	frame[0x0] += 2;

	WREG32(AFMT_AVI_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(AFMT_AVI_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
	WREG32(AFMT_AVI_INFO2 + offset,
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
	WREG32(AFMT_AVI_INFO3 + offset,
		frame[0xC] | (frame[0xD] << 8));
}

static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
	u32 base_rate = 48000;

	if (!dig || !dig->afmt)
		return;

	/* XXX: properly calculate this */
	/* XXX two dtos; generally use dto0 for hdmi */
	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
}


/*
 * update the info frames with the data from the current display mode
 */
void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
	struct hdmi_avi_infoframe frame;
	uint32_t offset;
	ssize_t err;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (!dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	evergreen_audio_set_dto(encoder, mode->clock);

	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	       HDMI_NULL_SEND); /* send null packets when required */

	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);

	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	       HDMI_NULL_SEND | /* send null packets when required */
	       HDMI_GC_SEND | /* send general control packets */
	       HDMI_GC_CONT); /* send general control packets every frame */

	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */

	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */

	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */

	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */

	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */

	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */

	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
	       HDMI_ACR_SOURCE); /* select SW CTS value */

	evergreen_hdmi_update_ACR(encoder, mode->clock);

	WREG32(AFMT_60958_0 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_L(1));

	WREG32(AFMT_60958_1 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_R(2));

	WREG32(AFMT_60958_2 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
	       AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
	       AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
	       AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
	       AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
	       AFMT_60958_CS_CHANNEL_NUMBER_7(8));

	/* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */

	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));

	/* fglrx sets 0x40 in 0x5f80 here */

	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	if (err < 0) {
		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
		return;
	}

	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
		return;
	}

	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));

	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */

	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
		 ~HDMI_AVI_INFO_LINE_MASK);

	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */

	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
}

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
{
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (enable && dig->afmt->enabled)
		return;
	if (!enable && !dig->afmt->enabled)
		return;

	dig->afmt->enabled = enable;

	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
}
Commit	Line	Data
e55d3e6c RM	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Christian König.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Christian König
	25	* Rafał Miłecki
	26	*/
e3b2e034	27	#include <linux/hdmi.h>
760285e7 DH	28	#include <drm/drmP.h>
760285e7 DH	29	#include <drm/radeon_drm.h>
e55d3e6c RM	30	#include "radeon.h"
	31	#include "radeon_asic.h"
	32	#include "evergreend.h"
	33	#include "atom.h"
	34
	35	/*
	36	* update the N and CTS parameters for a given pixel clock rate
	37	*/
	38	static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
	39	{
	40	struct drm_device *dev = encoder->dev;
	41	struct radeon_device *rdev = dev->dev_private;
	42	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
cfcbd6d3 RM	43	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	44	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	45	uint32_t offset = dig->afmt->offset;
e55d3e6c RM	46
	47	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
	48	WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
	49
	50	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
	51	WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
	52
	53	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
	54	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
	55	}
	56
e55d3e6c RM	57	/*
	58	* build a HDMI Video Info Frame
	59	*/
e3b2e034 TR	60	static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
e3b2e034 TR	61	void *buffer, size_t size)
e55d3e6c RM	62	{
	63	struct drm_device *dev = encoder->dev;
	64	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	65	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	66	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	67	uint32_t offset = dig->afmt->offset;
e3b2e034	68	uint8_t *frame = buffer + 3;
e55d3e6c	69
e55d3e6c RM	70	/* Our header values (type, version, length) should be alright, Intel
	71	* is using the same. Checksum function also seems to be OK, it works
	72	* fine for audio infoframe. However calculated value is always lower
	73	* by 2 in comparison to fglrx. It breaks displaying anything in case
	74	* of TVs that strictly check the checksum. Hack it manually here to
	75	* workaround this issue. */
	76	frame[0x0] += 2;
	77
	78	WREG32(AFMT_AVI_INFO0 + offset,
	79	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
	80	WREG32(AFMT_AVI_INFO1 + offset,
	81	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x7] << 24));
	82	WREG32(AFMT_AVI_INFO2 + offset,
	83	frame[0x8] \| (frame[0x9] << 8) \| (frame[0xA] << 16) \| (frame[0xB] << 24));
	84	WREG32(AFMT_AVI_INFO3 + offset,
	85	frame[0xC] \| (frame[0xD] << 8));
	86	}
	87
b1f6f47e AD	88	static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
	89	{
	90	struct drm_device *dev = encoder->dev;
	91	struct radeon_device *rdev = dev->dev_private;
	92	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	93	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	94	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
	95	u32 base_rate = 48000;
	96
	97	if (!dig \|\| !dig->afmt)
	98	return;
	99
	100	/* XXX: properly calculate this */
	101	/* XXX two dtos; generally use dto0 for hdmi */
	102	/* Express [24MHz / target pixel clock] as an exact rational
	103	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	104	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	105	*/
	106	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
	107	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
	108	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
	109	}
	110
	111
e55d3e6c RM	112	/*
	113	* update the info frames with the data from the current display mode
	114	*/
	115	void evergreen_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mode)
	116	{
	117	struct drm_device *dev = encoder->dev;
	118	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	119	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	120	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
e3b2e034 TR	121	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
e3b2e034 TR	122	struct hdmi_avi_infoframe frame;
cfcbd6d3	123	uint32_t offset;
e3b2e034	124	ssize_t err;
e55d3e6c	125
cfcbd6d3 RM	126	/* Silent, r600_hdmi_enable will raise WARN for us */
cfcbd6d3 RM	127	if (!dig->afmt->enabled)
e55d3e6c	128	return;
cfcbd6d3	129	offset = dig->afmt->offset;
e55d3e6c	130
b1f6f47e	131	evergreen_audio_set_dto(encoder, mode->clock);
e55d3e6c	132
1c3439f2 RM	133	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	134	HDMI_NULL_SEND); /* send null packets when required */
	135
e55d3e6c	136	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
e55d3e6c	137
1c3439f2 RM	138	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	139	HDMI_NULL_SEND \| /* send null packets when required */
	140	HDMI_GC_SEND \| /* send general control packets */
	141	HDMI_GC_CONT); /* send general control packets every frame */
	142
	143	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
1c3439f2 RM	144	HDMI_AUDIO_INFO_SEND \| /* enable audio info frames (frames won't be set until audio is enabled) */
1c3439f2 RM	145	HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
e55d3e6c	146
1c3439f2 RM	147	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
1c3439f2 RM	148	AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
e55d3e6c	149
1c3439f2	150	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
1c3439f2 RM	151	HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
	152
	153	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
e55d3e6c	154
91a44019 RM	155	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
	156	HDMI_AUDIO_DELAY_EN(1) \| /* set the default audio delay */
	157	HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
	158
	159	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	160	AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	161
	162	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
	163
	164	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
	165	HDMI_ACR_AUTO_SEND \| /* allow hw to sent ACR packets when required */
	166	HDMI_ACR_SOURCE); /* select SW CTS value */
	167
	168	evergreen_hdmi_update_ACR(encoder, mode->clock);
	169
f93e3fc3 RM	170	WREG32(AFMT_60958_0 + offset,
	171	AFMT_60958_CS_CHANNEL_NUMBER_L(1));
	172
	173	WREG32(AFMT_60958_1 + offset,
	174	AFMT_60958_CS_CHANNEL_NUMBER_R(2));
	175
	176	WREG32(AFMT_60958_2 + offset,
	177	AFMT_60958_CS_CHANNEL_NUMBER_2(3) \|
	178	AFMT_60958_CS_CHANNEL_NUMBER_3(4) \|
	179	AFMT_60958_CS_CHANNEL_NUMBER_4(5) \|
	180	AFMT_60958_CS_CHANNEL_NUMBER_5(6) \|
	181	AFMT_60958_CS_CHANNEL_NUMBER_6(7) \|
	182	AFMT_60958_CS_CHANNEL_NUMBER_7(8));
	183
	184	/* fglrx sets 0x0001005f \| (x & 0x00fc0000) in 0x5f78 here */
	185
	186	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
	187	AFMT_AUDIO_CHANNEL_ENABLE(0xff));
	188
	189	/* fglrx sets 0x40 in 0x5f80 here */
	190
e3b2e034 TR	191	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	192	if (err < 0) {
	193	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
	194	return;
	195	}
	196
	197	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	198	if (err < 0) {
	199	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
	200	return;
	201	}
e55d3e6c	202
e3b2e034	203	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1c3439f2	204
d3418eac RM	205	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
	206	HDMI_AVI_INFO_SEND \| /* enable AVI info frames */
	207	HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
	208
	209	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
	210	HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
	211	~HDMI_AVI_INFO_LINE_MASK);
	212
	213	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
	214	AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
	215
e55d3e6c RM	216	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	217	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	218	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
	219	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
	220	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
e55d3e6c	221	}
a973bea1 AD	222
	223	void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
	224	{
	225	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	226	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	227
	228	/* Silent, r600_hdmi_enable will raise WARN for us */
	229	if (enable && dig->afmt->enabled)
	230	return;
	231	if (!enable && !dig->afmt->enabled)
	232	return;
	233
	234	dig->afmt->enabled = enable;
	235
	236	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
	237	enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
	238	}