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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
32 | #include "radeon_reg.h" |
33 | #include "radeon.h" | |
e6990375 | 34 | #include "radeon_asic.h" |
3ce0a23d | 35 | #include "r100d.h" |
d4550907 JG |
36 | #include "rs100d.h" |
37 | #include "rv200d.h" | |
38 | #include "rv250d.h" | |
49e02b73 | 39 | #include "atom.h" |
3ce0a23d | 40 | |
70967ab9 | 41 | #include <linux/firmware.h> |
e0cd3608 | 42 | #include <linux/module.h> |
70967ab9 | 43 | |
551ebd83 DA |
44 | #include "r100_reg_safe.h" |
45 | #include "rn50_reg_safe.h" | |
46 | ||
70967ab9 BH |
47 | /* Firmware Names */ |
48 | #define FIRMWARE_R100 "radeon/R100_cp.bin" | |
49 | #define FIRMWARE_R200 "radeon/R200_cp.bin" | |
50 | #define FIRMWARE_R300 "radeon/R300_cp.bin" | |
51 | #define FIRMWARE_R420 "radeon/R420_cp.bin" | |
52 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" | |
53 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" | |
54 | #define FIRMWARE_R520 "radeon/R520_cp.bin" | |
55 | ||
56 | MODULE_FIRMWARE(FIRMWARE_R100); | |
57 | MODULE_FIRMWARE(FIRMWARE_R200); | |
58 | MODULE_FIRMWARE(FIRMWARE_R300); | |
59 | MODULE_FIRMWARE(FIRMWARE_R420); | |
60 | MODULE_FIRMWARE(FIRMWARE_RS690); | |
61 | MODULE_FIRMWARE(FIRMWARE_RS600); | |
62 | MODULE_FIRMWARE(FIRMWARE_R520); | |
771fe6b9 | 63 | |
551ebd83 DA |
64 | #include "r100_track.h" |
65 | ||
48ef779f AD |
66 | /* This files gather functions specifics to: |
67 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 | |
68 | * and others in some cases. | |
69 | */ | |
70 | ||
2b48b968 AD |
71 | static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) |
72 | { | |
73 | if (crtc == 0) { | |
74 | if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) | |
75 | return true; | |
76 | else | |
77 | return false; | |
78 | } else { | |
79 | if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) | |
80 | return true; | |
81 | else | |
82 | return false; | |
83 | } | |
84 | } | |
85 | ||
86 | static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) | |
87 | { | |
88 | u32 vline1, vline2; | |
89 | ||
90 | if (crtc == 0) { | |
91 | vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
92 | vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
93 | } else { | |
94 | vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
95 | vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; | |
96 | } | |
97 | if (vline1 != vline2) | |
98 | return true; | |
99 | else | |
100 | return false; | |
101 | } | |
102 | ||
48ef779f AD |
103 | /** |
104 | * r100_wait_for_vblank - vblank wait asic callback. | |
105 | * | |
106 | * @rdev: radeon_device pointer | |
107 | * @crtc: crtc to wait for vblank on | |
108 | * | |
109 | * Wait for vblank on the requested crtc (r1xx-r4xx). | |
110 | */ | |
3ae19b75 AD |
111 | void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) |
112 | { | |
2b48b968 | 113 | unsigned i = 0; |
3ae19b75 | 114 | |
94f768fd AD |
115 | if (crtc >= rdev->num_crtc) |
116 | return; | |
117 | ||
118 | if (crtc == 0) { | |
2b48b968 AD |
119 | if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) |
120 | return; | |
3ae19b75 | 121 | } else { |
2b48b968 AD |
122 | if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) |
123 | return; | |
124 | } | |
125 | ||
126 | /* depending on when we hit vblank, we may be close to active; if so, | |
127 | * wait for another frame. | |
128 | */ | |
129 | while (r100_is_in_vblank(rdev, crtc)) { | |
130 | if (i++ % 100 == 0) { | |
131 | if (!r100_is_counter_moving(rdev, crtc)) | |
132 | break; | |
133 | } | |
134 | } | |
135 | ||
136 | while (!r100_is_in_vblank(rdev, crtc)) { | |
137 | if (i++ % 100 == 0) { | |
138 | if (!r100_is_counter_moving(rdev, crtc)) | |
139 | break; | |
3ae19b75 AD |
140 | } |
141 | } | |
142 | } | |
143 | ||
48ef779f AD |
144 | /** |
145 | * r100_pre_page_flip - pre-pageflip callback. | |
146 | * | |
147 | * @rdev: radeon_device pointer | |
148 | * @crtc: crtc to prepare for pageflip on | |
149 | * | |
150 | * Pre-pageflip callback (r1xx-r4xx). | |
151 | * Enables the pageflip irq (vblank irq). | |
771fe6b9 | 152 | */ |
6f34be50 AD |
153 | void r100_pre_page_flip(struct radeon_device *rdev, int crtc) |
154 | { | |
6f34be50 AD |
155 | /* enable the pflip int */ |
156 | radeon_irq_kms_pflip_irq_get(rdev, crtc); | |
157 | } | |
158 | ||
48ef779f AD |
159 | /** |
160 | * r100_post_page_flip - pos-pageflip callback. | |
161 | * | |
162 | * @rdev: radeon_device pointer | |
163 | * @crtc: crtc to cleanup pageflip on | |
164 | * | |
165 | * Post-pageflip callback (r1xx-r4xx). | |
166 | * Disables the pageflip irq (vblank irq). | |
167 | */ | |
6f34be50 AD |
168 | void r100_post_page_flip(struct radeon_device *rdev, int crtc) |
169 | { | |
170 | /* disable the pflip int */ | |
171 | radeon_irq_kms_pflip_irq_put(rdev, crtc); | |
172 | } | |
173 | ||
48ef779f AD |
174 | /** |
175 | * r100_page_flip - pageflip callback. | |
176 | * | |
177 | * @rdev: radeon_device pointer | |
178 | * @crtc_id: crtc to cleanup pageflip on | |
179 | * @crtc_base: new address of the crtc (GPU MC address) | |
180 | * | |
181 | * Does the actual pageflip (r1xx-r4xx). | |
182 | * During vblank we take the crtc lock and wait for the update_pending | |
183 | * bit to go high, when it does, we release the lock, and allow the | |
184 | * double buffered update to take place. | |
185 | * Returns the current update pending status. | |
186 | */ | |
6f34be50 AD |
187 | u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
188 | { | |
189 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
190 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; | |
f6496479 | 191 | int i; |
6f34be50 AD |
192 | |
193 | /* Lock the graphics update lock */ | |
194 | /* update the scanout addresses */ | |
195 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); | |
196 | ||
acb32506 | 197 | /* Wait for update_pending to go high. */ |
f6496479 AD |
198 | for (i = 0; i < rdev->usec_timeout; i++) { |
199 | if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) | |
200 | break; | |
201 | udelay(1); | |
202 | } | |
acb32506 | 203 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
6f34be50 AD |
204 | |
205 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
206 | tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; | |
207 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); | |
208 | ||
209 | /* Return current update_pending status: */ | |
210 | return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; | |
211 | } | |
212 | ||
48ef779f AD |
213 | /** |
214 | * r100_pm_get_dynpm_state - look up dynpm power state callback. | |
215 | * | |
216 | * @rdev: radeon_device pointer | |
217 | * | |
218 | * Look up the optimal power state based on the | |
219 | * current state of the GPU (r1xx-r5xx). | |
220 | * Used for dynpm only. | |
221 | */ | |
ce8f5370 | 222 | void r100_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
223 | { |
224 | int i; | |
ce8f5370 AD |
225 | rdev->pm.dynpm_can_upclock = true; |
226 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e | 227 | |
ce8f5370 AD |
228 | switch (rdev->pm.dynpm_planned_action) { |
229 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 230 | rdev->pm.requested_power_state_index = 0; |
ce8f5370 | 231 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 232 | break; |
ce8f5370 | 233 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
234 | if (rdev->pm.current_power_state_index == 0) { |
235 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 236 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
237 | } else { |
238 | if (rdev->pm.active_crtc_count > 1) { | |
239 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 240 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
241 | continue; |
242 | else if (i >= rdev->pm.current_power_state_index) { | |
243 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
244 | break; | |
245 | } else { | |
246 | rdev->pm.requested_power_state_index = i; | |
247 | break; | |
248 | } | |
249 | } | |
250 | } else | |
251 | rdev->pm.requested_power_state_index = | |
252 | rdev->pm.current_power_state_index - 1; | |
253 | } | |
d7311171 AD |
254 | /* don't use the power state if crtcs are active and no display flag is set */ |
255 | if ((rdev->pm.active_crtc_count > 0) && | |
256 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & | |
257 | RADEON_PM_MODE_NO_DISPLAY)) { | |
258 | rdev->pm.requested_power_state_index++; | |
259 | } | |
a48b9b4e | 260 | break; |
ce8f5370 | 261 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
262 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
263 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 264 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
265 | } else { |
266 | if (rdev->pm.active_crtc_count > 1) { | |
267 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 268 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
269 | continue; |
270 | else if (i <= rdev->pm.current_power_state_index) { | |
271 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
272 | break; | |
273 | } else { | |
274 | rdev->pm.requested_power_state_index = i; | |
275 | break; | |
276 | } | |
277 | } | |
278 | } else | |
279 | rdev->pm.requested_power_state_index = | |
280 | rdev->pm.current_power_state_index + 1; | |
281 | } | |
282 | break; | |
ce8f5370 | 283 | case DYNPM_ACTION_DEFAULT: |
58e21dff | 284 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
ce8f5370 | 285 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 286 | break; |
ce8f5370 | 287 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
288 | default: |
289 | DRM_ERROR("Requested mode for not defined action\n"); | |
290 | return; | |
291 | } | |
292 | /* only one clock mode per power state */ | |
293 | rdev->pm.requested_clock_mode_index = 0; | |
294 | ||
d9fdaafb | 295 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
ce8a3eb2 AD |
296 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
297 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
298 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
299 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
300 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
301 | pcie_lanes); | |
a48b9b4e AD |
302 | } |
303 | ||
48ef779f AD |
304 | /** |
305 | * r100_pm_init_profile - Initialize power profiles callback. | |
306 | * | |
307 | * @rdev: radeon_device pointer | |
308 | * | |
309 | * Initialize the power states used in profile mode | |
310 | * (r1xx-r3xx). | |
311 | * Used for profile mode only. | |
312 | */ | |
ce8f5370 AD |
313 | void r100_pm_init_profile(struct radeon_device *rdev) |
314 | { | |
315 | /* default */ | |
316 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
317 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
318 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
319 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
320 | /* low sh */ | |
321 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
322 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
323 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
324 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
325 | /* mid sh */ |
326 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; | |
327 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; | |
328 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
329 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
330 | /* high sh */ |
331 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
332 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
333 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
334 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
335 | /* low mh */ | |
336 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
337 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
338 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
339 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
340 | /* mid mh */ |
341 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; | |
342 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
343 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
344 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
345 | /* high mh */ |
346 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
347 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
348 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
349 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
bae6b562 AD |
350 | } |
351 | ||
48ef779f AD |
352 | /** |
353 | * r100_pm_misc - set additional pm hw parameters callback. | |
354 | * | |
355 | * @rdev: radeon_device pointer | |
356 | * | |
357 | * Set non-clock parameters associated with a power state | |
358 | * (voltage, pcie lanes, etc.) (r1xx-r4xx). | |
359 | */ | |
49e02b73 AD |
360 | void r100_pm_misc(struct radeon_device *rdev) |
361 | { | |
49e02b73 AD |
362 | int requested_index = rdev->pm.requested_power_state_index; |
363 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; | |
364 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; | |
365 | u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; | |
366 | ||
367 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { | |
368 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
369 | tmp = RREG32(voltage->gpio.reg); | |
370 | if (voltage->active_high) | |
371 | tmp |= voltage->gpio.mask; | |
372 | else | |
373 | tmp &= ~(voltage->gpio.mask); | |
374 | WREG32(voltage->gpio.reg, tmp); | |
375 | if (voltage->delay) | |
376 | udelay(voltage->delay); | |
377 | } else { | |
378 | tmp = RREG32(voltage->gpio.reg); | |
379 | if (voltage->active_high) | |
380 | tmp &= ~voltage->gpio.mask; | |
381 | else | |
382 | tmp |= voltage->gpio.mask; | |
383 | WREG32(voltage->gpio.reg, tmp); | |
384 | if (voltage->delay) | |
385 | udelay(voltage->delay); | |
386 | } | |
387 | } | |
388 | ||
389 | sclk_cntl = RREG32_PLL(SCLK_CNTL); | |
390 | sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); | |
391 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); | |
392 | sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); | |
393 | sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); | |
394 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { | |
395 | sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; | |
396 | if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) | |
397 | sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; | |
398 | else | |
399 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; | |
400 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) | |
401 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); | |
402 | else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) | |
403 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); | |
404 | } else | |
405 | sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; | |
406 | ||
407 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { | |
408 | sclk_more_cntl |= IO_CG_VOLTAGE_DROP; | |
409 | if (voltage->delay) { | |
410 | sclk_more_cntl |= VOLTAGE_DROP_SYNC; | |
411 | switch (voltage->delay) { | |
412 | case 33: | |
413 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); | |
414 | break; | |
415 | case 66: | |
416 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); | |
417 | break; | |
418 | case 99: | |
419 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); | |
420 | break; | |
421 | case 132: | |
422 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); | |
423 | break; | |
424 | } | |
425 | } else | |
426 | sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; | |
427 | } else | |
428 | sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; | |
429 | ||
430 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) | |
431 | sclk_cntl &= ~FORCE_HDP; | |
432 | else | |
433 | sclk_cntl |= FORCE_HDP; | |
434 | ||
435 | WREG32_PLL(SCLK_CNTL, sclk_cntl); | |
436 | WREG32_PLL(SCLK_CNTL2, sclk_cntl2); | |
437 | WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); | |
438 | ||
439 | /* set pcie lanes */ | |
440 | if ((rdev->flags & RADEON_IS_PCIE) && | |
441 | !(rdev->flags & RADEON_IS_IGP) && | |
798bcf73 | 442 | rdev->asic->pm.set_pcie_lanes && |
49e02b73 AD |
443 | (ps->pcie_lanes != |
444 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { | |
445 | radeon_set_pcie_lanes(rdev, | |
446 | ps->pcie_lanes); | |
d9fdaafb | 447 | DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); |
49e02b73 | 448 | } |
49e02b73 AD |
449 | } |
450 | ||
48ef779f AD |
451 | /** |
452 | * r100_pm_prepare - pre-power state change callback. | |
453 | * | |
454 | * @rdev: radeon_device pointer | |
455 | * | |
456 | * Prepare for a power state change (r1xx-r4xx). | |
457 | */ | |
49e02b73 AD |
458 | void r100_pm_prepare(struct radeon_device *rdev) |
459 | { | |
460 | struct drm_device *ddev = rdev->ddev; | |
461 | struct drm_crtc *crtc; | |
462 | struct radeon_crtc *radeon_crtc; | |
463 | u32 tmp; | |
464 | ||
465 | /* disable any active CRTCs */ | |
466 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
467 | radeon_crtc = to_radeon_crtc(crtc); | |
468 | if (radeon_crtc->enabled) { | |
469 | if (radeon_crtc->crtc_id) { | |
470 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); | |
471 | tmp |= RADEON_CRTC2_DISP_REQ_EN_B; | |
472 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); | |
473 | } else { | |
474 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | |
475 | tmp |= RADEON_CRTC_DISP_REQ_EN_B; | |
476 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | |
477 | } | |
478 | } | |
479 | } | |
480 | } | |
481 | ||
48ef779f AD |
482 | /** |
483 | * r100_pm_finish - post-power state change callback. | |
484 | * | |
485 | * @rdev: radeon_device pointer | |
486 | * | |
487 | * Clean up after a power state change (r1xx-r4xx). | |
488 | */ | |
49e02b73 AD |
489 | void r100_pm_finish(struct radeon_device *rdev) |
490 | { | |
491 | struct drm_device *ddev = rdev->ddev; | |
492 | struct drm_crtc *crtc; | |
493 | struct radeon_crtc *radeon_crtc; | |
494 | u32 tmp; | |
495 | ||
496 | /* enable any active CRTCs */ | |
497 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
498 | radeon_crtc = to_radeon_crtc(crtc); | |
499 | if (radeon_crtc->enabled) { | |
500 | if (radeon_crtc->crtc_id) { | |
501 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); | |
502 | tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; | |
503 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); | |
504 | } else { | |
505 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | |
506 | tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; | |
507 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | |
508 | } | |
509 | } | |
510 | } | |
511 | } | |
512 | ||
48ef779f AD |
513 | /** |
514 | * r100_gui_idle - gui idle callback. | |
515 | * | |
516 | * @rdev: radeon_device pointer | |
517 | * | |
518 | * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). | |
519 | * Returns true if idle, false if not. | |
520 | */ | |
def9ba9c AD |
521 | bool r100_gui_idle(struct radeon_device *rdev) |
522 | { | |
523 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) | |
524 | return false; | |
525 | else | |
526 | return true; | |
527 | } | |
528 | ||
05a05c50 | 529 | /* hpd for digital panel detect/disconnect */ |
48ef779f AD |
530 | /** |
531 | * r100_hpd_sense - hpd sense callback. | |
532 | * | |
533 | * @rdev: radeon_device pointer | |
534 | * @hpd: hpd (hotplug detect) pin | |
535 | * | |
536 | * Checks if a digital monitor is connected (r1xx-r4xx). | |
537 | * Returns true if connected, false if not connected. | |
538 | */ | |
05a05c50 AD |
539 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
540 | { | |
541 | bool connected = false; | |
542 | ||
543 | switch (hpd) { | |
544 | case RADEON_HPD_1: | |
545 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) | |
546 | connected = true; | |
547 | break; | |
548 | case RADEON_HPD_2: | |
549 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) | |
550 | connected = true; | |
551 | break; | |
552 | default: | |
553 | break; | |
554 | } | |
555 | return connected; | |
556 | } | |
557 | ||
48ef779f AD |
558 | /** |
559 | * r100_hpd_set_polarity - hpd set polarity callback. | |
560 | * | |
561 | * @rdev: radeon_device pointer | |
562 | * @hpd: hpd (hotplug detect) pin | |
563 | * | |
564 | * Set the polarity of the hpd pin (r1xx-r4xx). | |
565 | */ | |
05a05c50 AD |
566 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
567 | enum radeon_hpd_id hpd) | |
568 | { | |
569 | u32 tmp; | |
570 | bool connected = r100_hpd_sense(rdev, hpd); | |
571 | ||
572 | switch (hpd) { | |
573 | case RADEON_HPD_1: | |
574 | tmp = RREG32(RADEON_FP_GEN_CNTL); | |
575 | if (connected) | |
576 | tmp &= ~RADEON_FP_DETECT_INT_POL; | |
577 | else | |
578 | tmp |= RADEON_FP_DETECT_INT_POL; | |
579 | WREG32(RADEON_FP_GEN_CNTL, tmp); | |
580 | break; | |
581 | case RADEON_HPD_2: | |
582 | tmp = RREG32(RADEON_FP2_GEN_CNTL); | |
583 | if (connected) | |
584 | tmp &= ~RADEON_FP2_DETECT_INT_POL; | |
585 | else | |
586 | tmp |= RADEON_FP2_DETECT_INT_POL; | |
587 | WREG32(RADEON_FP2_GEN_CNTL, tmp); | |
588 | break; | |
589 | default: | |
590 | break; | |
591 | } | |
592 | } | |
593 | ||
48ef779f AD |
594 | /** |
595 | * r100_hpd_init - hpd setup callback. | |
596 | * | |
597 | * @rdev: radeon_device pointer | |
598 | * | |
599 | * Setup the hpd pins used by the card (r1xx-r4xx). | |
600 | * Set the polarity, and enable the hpd interrupts. | |
601 | */ | |
05a05c50 AD |
602 | void r100_hpd_init(struct radeon_device *rdev) |
603 | { | |
604 | struct drm_device *dev = rdev->ddev; | |
605 | struct drm_connector *connector; | |
fb98257a | 606 | unsigned enable = 0; |
05a05c50 AD |
607 | |
608 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
609 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
fb98257a | 610 | enable |= 1 << radeon_connector->hpd.hpd; |
64912e99 | 611 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
05a05c50 | 612 | } |
fb98257a | 613 | radeon_irq_kms_enable_hpd(rdev, enable); |
05a05c50 AD |
614 | } |
615 | ||
48ef779f AD |
616 | /** |
617 | * r100_hpd_fini - hpd tear down callback. | |
618 | * | |
619 | * @rdev: radeon_device pointer | |
620 | * | |
621 | * Tear down the hpd pins used by the card (r1xx-r4xx). | |
622 | * Disable the hpd interrupts. | |
623 | */ | |
05a05c50 AD |
624 | void r100_hpd_fini(struct radeon_device *rdev) |
625 | { | |
626 | struct drm_device *dev = rdev->ddev; | |
627 | struct drm_connector *connector; | |
fb98257a | 628 | unsigned disable = 0; |
05a05c50 AD |
629 | |
630 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
631 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
fb98257a | 632 | disable |= 1 << radeon_connector->hpd.hpd; |
05a05c50 | 633 | } |
fb98257a | 634 | radeon_irq_kms_disable_hpd(rdev, disable); |
05a05c50 AD |
635 | } |
636 | ||
771fe6b9 JG |
637 | /* |
638 | * PCI GART | |
639 | */ | |
640 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) | |
641 | { | |
642 | /* TODO: can we do somethings here ? */ | |
643 | /* It seems hw only cache one entry so we should discard this | |
644 | * entry otherwise if first GPU GART read hit this entry it | |
645 | * could end up in wrong address. */ | |
646 | } | |
647 | ||
4aac0473 | 648 | int r100_pci_gart_init(struct radeon_device *rdev) |
771fe6b9 | 649 | { |
771fe6b9 JG |
650 | int r; |
651 | ||
c9a1be96 | 652 | if (rdev->gart.ptr) { |
fce7d61b | 653 | WARN(1, "R100 PCI GART already initialized\n"); |
4aac0473 JG |
654 | return 0; |
655 | } | |
771fe6b9 JG |
656 | /* Initialize common gart structure */ |
657 | r = radeon_gart_init(rdev); | |
4aac0473 | 658 | if (r) |
771fe6b9 | 659 | return r; |
4aac0473 | 660 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
c5b3b850 AD |
661 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
662 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
4aac0473 JG |
663 | return radeon_gart_table_ram_alloc(rdev); |
664 | } | |
665 | ||
666 | int r100_pci_gart_enable(struct radeon_device *rdev) | |
667 | { | |
668 | uint32_t tmp; | |
669 | ||
82568565 | 670 | radeon_gart_restore(rdev); |
771fe6b9 JG |
671 | /* discard memory request outside of configured range */ |
672 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
673 | WREG32(RADEON_AIC_CNTL, tmp); | |
674 | /* set address range for PCI address translate */ | |
d594e46a JG |
675 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
676 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); | |
771fe6b9 JG |
677 | /* set PCI GART page-table base address */ |
678 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); | |
679 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; | |
680 | WREG32(RADEON_AIC_CNTL, tmp); | |
681 | r100_pci_gart_tlb_flush(rdev); | |
43caf451 | 682 | DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", |
fcf4de5a TV |
683 | (unsigned)(rdev->mc.gtt_size >> 20), |
684 | (unsigned long long)rdev->gart.table_addr); | |
771fe6b9 JG |
685 | rdev->gart.ready = true; |
686 | return 0; | |
687 | } | |
688 | ||
689 | void r100_pci_gart_disable(struct radeon_device *rdev) | |
690 | { | |
691 | uint32_t tmp; | |
692 | ||
693 | /* discard memory request outside of configured range */ | |
694 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
695 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
696 | WREG32(RADEON_AIC_LO_ADDR, 0); | |
697 | WREG32(RADEON_AIC_HI_ADDR, 0); | |
698 | } | |
699 | ||
700 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
701 | { | |
c9a1be96 JG |
702 | u32 *gtt = rdev->gart.ptr; |
703 | ||
771fe6b9 JG |
704 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
705 | return -EINVAL; | |
706 | } | |
c9a1be96 | 707 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); |
771fe6b9 JG |
708 | return 0; |
709 | } | |
710 | ||
4aac0473 | 711 | void r100_pci_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 712 | { |
f9274562 | 713 | radeon_gart_fini(rdev); |
4aac0473 JG |
714 | r100_pci_gart_disable(rdev); |
715 | radeon_gart_table_ram_free(rdev); | |
771fe6b9 JG |
716 | } |
717 | ||
7ed220d7 MD |
718 | int r100_irq_set(struct radeon_device *rdev) |
719 | { | |
720 | uint32_t tmp = 0; | |
721 | ||
003e69f9 | 722 | if (!rdev->irq.installed) { |
fce7d61b | 723 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
003e69f9 JG |
724 | WREG32(R_000040_GEN_INT_CNTL, 0); |
725 | return -EINVAL; | |
726 | } | |
736fc37f | 727 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
7ed220d7 MD |
728 | tmp |= RADEON_SW_INT_ENABLE; |
729 | } | |
6f34be50 | 730 | if (rdev->irq.crtc_vblank_int[0] || |
736fc37f | 731 | atomic_read(&rdev->irq.pflip[0])) { |
7ed220d7 MD |
732 | tmp |= RADEON_CRTC_VBLANK_MASK; |
733 | } | |
6f34be50 | 734 | if (rdev->irq.crtc_vblank_int[1] || |
736fc37f | 735 | atomic_read(&rdev->irq.pflip[1])) { |
7ed220d7 MD |
736 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
737 | } | |
05a05c50 AD |
738 | if (rdev->irq.hpd[0]) { |
739 | tmp |= RADEON_FP_DETECT_MASK; | |
740 | } | |
741 | if (rdev->irq.hpd[1]) { | |
742 | tmp |= RADEON_FP2_DETECT_MASK; | |
743 | } | |
7ed220d7 MD |
744 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
745 | return 0; | |
746 | } | |
747 | ||
9f022ddf JG |
748 | void r100_irq_disable(struct radeon_device *rdev) |
749 | { | |
750 | u32 tmp; | |
751 | ||
752 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
753 | /* Wait and acknowledge irq */ | |
754 | mdelay(1); | |
755 | tmp = RREG32(R_000044_GEN_INT_STATUS); | |
756 | WREG32(R_000044_GEN_INT_STATUS, tmp); | |
757 | } | |
758 | ||
cbdd4501 | 759 | static uint32_t r100_irq_ack(struct radeon_device *rdev) |
7ed220d7 MD |
760 | { |
761 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); | |
05a05c50 AD |
762 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
763 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | | |
764 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; | |
7ed220d7 MD |
765 | |
766 | if (irqs) { | |
767 | WREG32(RADEON_GEN_INT_STATUS, irqs); | |
768 | } | |
769 | return irqs & irq_mask; | |
770 | } | |
771 | ||
772 | int r100_irq_process(struct radeon_device *rdev) | |
773 | { | |
3e5cb98d | 774 | uint32_t status, msi_rearm; |
d4877cf2 | 775 | bool queue_hotplug = false; |
7ed220d7 MD |
776 | |
777 | status = r100_irq_ack(rdev); | |
778 | if (!status) { | |
779 | return IRQ_NONE; | |
780 | } | |
a513c184 JG |
781 | if (rdev->shutdown) { |
782 | return IRQ_NONE; | |
783 | } | |
7ed220d7 MD |
784 | while (status) { |
785 | /* SW interrupt */ | |
786 | if (status & RADEON_SW_INT_TEST) { | |
7465280c | 787 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
7ed220d7 MD |
788 | } |
789 | /* Vertical blank interrupts */ | |
790 | if (status & RADEON_CRTC_VBLANK_STAT) { | |
6f34be50 AD |
791 | if (rdev->irq.crtc_vblank_int[0]) { |
792 | drm_handle_vblank(rdev->ddev, 0); | |
793 | rdev->pm.vblank_sync = true; | |
794 | wake_up(&rdev->irq.vblank_queue); | |
795 | } | |
736fc37f | 796 | if (atomic_read(&rdev->irq.pflip[0])) |
3e4ea742 | 797 | radeon_crtc_handle_flip(rdev, 0); |
7ed220d7 MD |
798 | } |
799 | if (status & RADEON_CRTC2_VBLANK_STAT) { | |
6f34be50 AD |
800 | if (rdev->irq.crtc_vblank_int[1]) { |
801 | drm_handle_vblank(rdev->ddev, 1); | |
802 | rdev->pm.vblank_sync = true; | |
803 | wake_up(&rdev->irq.vblank_queue); | |
804 | } | |
736fc37f | 805 | if (atomic_read(&rdev->irq.pflip[1])) |
3e4ea742 | 806 | radeon_crtc_handle_flip(rdev, 1); |
7ed220d7 | 807 | } |
05a05c50 | 808 | if (status & RADEON_FP_DETECT_STAT) { |
d4877cf2 AD |
809 | queue_hotplug = true; |
810 | DRM_DEBUG("HPD1\n"); | |
05a05c50 AD |
811 | } |
812 | if (status & RADEON_FP2_DETECT_STAT) { | |
d4877cf2 AD |
813 | queue_hotplug = true; |
814 | DRM_DEBUG("HPD2\n"); | |
05a05c50 | 815 | } |
7ed220d7 MD |
816 | status = r100_irq_ack(rdev); |
817 | } | |
d4877cf2 | 818 | if (queue_hotplug) |
32c87fca | 819 | schedule_work(&rdev->hotplug_work); |
3e5cb98d AD |
820 | if (rdev->msi_enabled) { |
821 | switch (rdev->family) { | |
822 | case CHIP_RS400: | |
823 | case CHIP_RS480: | |
824 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; | |
825 | WREG32(RADEON_AIC_CNTL, msi_rearm); | |
826 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); | |
827 | break; | |
828 | default: | |
b7f5b7de | 829 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
3e5cb98d AD |
830 | break; |
831 | } | |
832 | } | |
7ed220d7 MD |
833 | return IRQ_HANDLED; |
834 | } | |
835 | ||
836 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
837 | { | |
838 | if (crtc == 0) | |
839 | return RREG32(RADEON_CRTC_CRNT_FRAME); | |
840 | else | |
841 | return RREG32(RADEON_CRTC2_CRNT_FRAME); | |
842 | } | |
843 | ||
9e5b2af7 PN |
844 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
845 | * for enough space (today caller are ib schedule and buffer move) */ | |
771fe6b9 JG |
846 | void r100_fence_ring_emit(struct radeon_device *rdev, |
847 | struct radeon_fence *fence) | |
848 | { | |
e32eb50d | 849 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
7b1f2485 | 850 | |
9e5b2af7 PN |
851 | /* We have to make sure that caches are flushed before |
852 | * CPU might read something from VRAM. */ | |
e32eb50d CK |
853 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
854 | radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); | |
855 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); | |
856 | radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); | |
771fe6b9 | 857 | /* Wait until IDLE & CLEAN */ |
e32eb50d CK |
858 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
859 | radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); | |
860 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); | |
861 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl | | |
cafe6609 | 862 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
e32eb50d CK |
863 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
864 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl); | |
771fe6b9 | 865 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
866 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
867 | radeon_ring_write(ring, fence->seq); | |
868 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
869 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); | |
771fe6b9 JG |
870 | } |
871 | ||
15d3332f | 872 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 873 | struct radeon_ring *ring, |
15d3332f | 874 | struct radeon_semaphore *semaphore, |
7b1f2485 | 875 | bool emit_wait) |
15d3332f CK |
876 | { |
877 | /* Unused on older asics, since we don't have semaphores or multiple rings */ | |
878 | BUG(); | |
879 | } | |
880 | ||
771fe6b9 JG |
881 | int r100_copy_blit(struct radeon_device *rdev, |
882 | uint64_t src_offset, | |
883 | uint64_t dst_offset, | |
003cefe0 | 884 | unsigned num_gpu_pages, |
876dc9f3 | 885 | struct radeon_fence **fence) |
771fe6b9 | 886 | { |
e32eb50d | 887 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
771fe6b9 | 888 | uint32_t cur_pages; |
003cefe0 | 889 | uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
771fe6b9 JG |
890 | uint32_t pitch; |
891 | uint32_t stride_pixels; | |
892 | unsigned ndw; | |
893 | int num_loops; | |
894 | int r = 0; | |
895 | ||
896 | /* radeon limited to 16k stride */ | |
897 | stride_bytes &= 0x3fff; | |
898 | /* radeon pitch is /64 */ | |
899 | pitch = stride_bytes / 64; | |
900 | stride_pixels = stride_bytes / 4; | |
003cefe0 | 901 | num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); |
771fe6b9 JG |
902 | |
903 | /* Ask for enough room for blit + flush + fence */ | |
904 | ndw = 64 + (10 * num_loops); | |
e32eb50d | 905 | r = radeon_ring_lock(rdev, ring, ndw); |
771fe6b9 JG |
906 | if (r) { |
907 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); | |
908 | return -EINVAL; | |
909 | } | |
003cefe0 AD |
910 | while (num_gpu_pages > 0) { |
911 | cur_pages = num_gpu_pages; | |
771fe6b9 JG |
912 | if (cur_pages > 8191) { |
913 | cur_pages = 8191; | |
914 | } | |
003cefe0 | 915 | num_gpu_pages -= cur_pages; |
771fe6b9 JG |
916 | |
917 | /* pages are in Y direction - height | |
918 | page width in X direction - width */ | |
e32eb50d CK |
919 | radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
920 | radeon_ring_write(ring, | |
771fe6b9 JG |
921 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
922 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
923 | RADEON_GMC_SRC_CLIPPING | | |
924 | RADEON_GMC_DST_CLIPPING | | |
925 | RADEON_GMC_BRUSH_NONE | | |
926 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | | |
927 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
928 | RADEON_ROP3_S | | |
929 | RADEON_DP_SRC_SOURCE_MEMORY | | |
930 | RADEON_GMC_CLR_CMP_CNTL_DIS | | |
931 | RADEON_GMC_WR_MSK_DIS); | |
e32eb50d CK |
932 | radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); |
933 | radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); | |
934 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); | |
935 | radeon_ring_write(ring, 0); | |
936 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); | |
937 | radeon_ring_write(ring, num_gpu_pages); | |
938 | radeon_ring_write(ring, num_gpu_pages); | |
939 | radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); | |
940 | } | |
941 | radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); | |
942 | radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); | |
943 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
944 | radeon_ring_write(ring, | |
771fe6b9 JG |
945 | RADEON_WAIT_2D_IDLECLEAN | |
946 | RADEON_WAIT_HOST_IDLECLEAN | | |
947 | RADEON_WAIT_DMA_GUI_IDLE); | |
948 | if (fence) { | |
876dc9f3 | 949 | r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
771fe6b9 | 950 | } |
e32eb50d | 951 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
952 | return r; |
953 | } | |
954 | ||
45600232 JG |
955 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
956 | { | |
957 | unsigned i; | |
958 | u32 tmp; | |
959 | ||
960 | for (i = 0; i < rdev->usec_timeout; i++) { | |
961 | tmp = RREG32(R_000E40_RBBM_STATUS); | |
962 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { | |
963 | return 0; | |
964 | } | |
965 | udelay(1); | |
966 | } | |
967 | return -1; | |
968 | } | |
969 | ||
f712812e | 970 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 JG |
971 | { |
972 | int r; | |
973 | ||
e32eb50d | 974 | r = radeon_ring_lock(rdev, ring, 2); |
771fe6b9 JG |
975 | if (r) { |
976 | return; | |
977 | } | |
e32eb50d CK |
978 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
979 | radeon_ring_write(ring, | |
771fe6b9 JG |
980 | RADEON_ISYNC_ANY2D_IDLE3D | |
981 | RADEON_ISYNC_ANY3D_IDLE2D | | |
982 | RADEON_ISYNC_WAIT_IDLEGUI | | |
983 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
e32eb50d | 984 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
985 | } |
986 | ||
70967ab9 BH |
987 | |
988 | /* Load the microcode for the CP */ | |
989 | static int r100_cp_init_microcode(struct radeon_device *rdev) | |
771fe6b9 | 990 | { |
70967ab9 BH |
991 | const char *fw_name = NULL; |
992 | int err; | |
771fe6b9 | 993 | |
d9fdaafb | 994 | DRM_DEBUG_KMS("\n"); |
771fe6b9 | 995 | |
771fe6b9 JG |
996 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
997 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || | |
998 | (rdev->family == CHIP_RS200)) { | |
999 | DRM_INFO("Loading R100 Microcode\n"); | |
70967ab9 | 1000 | fw_name = FIRMWARE_R100; |
771fe6b9 JG |
1001 | } else if ((rdev->family == CHIP_R200) || |
1002 | (rdev->family == CHIP_RV250) || | |
1003 | (rdev->family == CHIP_RV280) || | |
1004 | (rdev->family == CHIP_RS300)) { | |
1005 | DRM_INFO("Loading R200 Microcode\n"); | |
70967ab9 | 1006 | fw_name = FIRMWARE_R200; |
771fe6b9 JG |
1007 | } else if ((rdev->family == CHIP_R300) || |
1008 | (rdev->family == CHIP_R350) || | |
1009 | (rdev->family == CHIP_RV350) || | |
1010 | (rdev->family == CHIP_RV380) || | |
1011 | (rdev->family == CHIP_RS400) || | |
1012 | (rdev->family == CHIP_RS480)) { | |
1013 | DRM_INFO("Loading R300 Microcode\n"); | |
70967ab9 | 1014 | fw_name = FIRMWARE_R300; |
771fe6b9 JG |
1015 | } else if ((rdev->family == CHIP_R420) || |
1016 | (rdev->family == CHIP_R423) || | |
1017 | (rdev->family == CHIP_RV410)) { | |
1018 | DRM_INFO("Loading R400 Microcode\n"); | |
70967ab9 | 1019 | fw_name = FIRMWARE_R420; |
771fe6b9 JG |
1020 | } else if ((rdev->family == CHIP_RS690) || |
1021 | (rdev->family == CHIP_RS740)) { | |
1022 | DRM_INFO("Loading RS690/RS740 Microcode\n"); | |
70967ab9 | 1023 | fw_name = FIRMWARE_RS690; |
771fe6b9 JG |
1024 | } else if (rdev->family == CHIP_RS600) { |
1025 | DRM_INFO("Loading RS600 Microcode\n"); | |
70967ab9 | 1026 | fw_name = FIRMWARE_RS600; |
771fe6b9 JG |
1027 | } else if ((rdev->family == CHIP_RV515) || |
1028 | (rdev->family == CHIP_R520) || | |
1029 | (rdev->family == CHIP_RV530) || | |
1030 | (rdev->family == CHIP_R580) || | |
1031 | (rdev->family == CHIP_RV560) || | |
1032 | (rdev->family == CHIP_RV570)) { | |
1033 | DRM_INFO("Loading R500 Microcode\n"); | |
70967ab9 BH |
1034 | fw_name = FIRMWARE_R520; |
1035 | } | |
1036 | ||
0a168933 | 1037 | err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
70967ab9 BH |
1038 | if (err) { |
1039 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", | |
1040 | fw_name); | |
3ce0a23d | 1041 | } else if (rdev->me_fw->size % 8) { |
70967ab9 BH |
1042 | printk(KERN_ERR |
1043 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", | |
3ce0a23d | 1044 | rdev->me_fw->size, fw_name); |
70967ab9 | 1045 | err = -EINVAL; |
3ce0a23d JG |
1046 | release_firmware(rdev->me_fw); |
1047 | rdev->me_fw = NULL; | |
70967ab9 BH |
1048 | } |
1049 | return err; | |
1050 | } | |
d4550907 | 1051 | |
70967ab9 BH |
1052 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
1053 | { | |
1054 | const __be32 *fw_data; | |
1055 | int i, size; | |
1056 | ||
1057 | if (r100_gui_wait_for_idle(rdev)) { | |
1058 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
1059 | "programming pipes. Bad things might happen.\n"); | |
1060 | } | |
1061 | ||
3ce0a23d JG |
1062 | if (rdev->me_fw) { |
1063 | size = rdev->me_fw->size / 4; | |
1064 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; | |
70967ab9 BH |
1065 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
1066 | for (i = 0; i < size; i += 2) { | |
1067 | WREG32(RADEON_CP_ME_RAM_DATAH, | |
1068 | be32_to_cpup(&fw_data[i])); | |
1069 | WREG32(RADEON_CP_ME_RAM_DATAL, | |
1070 | be32_to_cpup(&fw_data[i + 1])); | |
771fe6b9 JG |
1071 | } |
1072 | } | |
1073 | } | |
1074 | ||
1075 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |
1076 | { | |
e32eb50d | 1077 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
771fe6b9 JG |
1078 | unsigned rb_bufsz; |
1079 | unsigned rb_blksz; | |
1080 | unsigned max_fetch; | |
1081 | unsigned pre_write_timer; | |
1082 | unsigned pre_write_limit; | |
1083 | unsigned indirect2_start; | |
1084 | unsigned indirect1_start; | |
1085 | uint32_t tmp; | |
1086 | int r; | |
1087 | ||
1088 | if (r100_debugfs_cp_init(rdev)) { | |
1089 | DRM_ERROR("Failed to register debugfs file for CP !\n"); | |
1090 | } | |
3ce0a23d | 1091 | if (!rdev->me_fw) { |
70967ab9 BH |
1092 | r = r100_cp_init_microcode(rdev); |
1093 | if (r) { | |
1094 | DRM_ERROR("Failed to load firmware!\n"); | |
1095 | return r; | |
1096 | } | |
1097 | } | |
1098 | ||
771fe6b9 JG |
1099 | /* Align ring size */ |
1100 | rb_bufsz = drm_order(ring_size / 8); | |
1101 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
1102 | r100_cp_load_microcode(rdev); | |
e32eb50d | 1103 | r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, |
78c5560a AD |
1104 | RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, |
1105 | 0, 0x7fffff, RADEON_CP_PACKET2); | |
771fe6b9 JG |
1106 | if (r) { |
1107 | return r; | |
1108 | } | |
1109 | /* Each time the cp read 1024 bytes (16 dword/quadword) update | |
1110 | * the rptr copy in system ram */ | |
1111 | rb_blksz = 9; | |
1112 | /* cp will read 128bytes at a time (4 dwords) */ | |
1113 | max_fetch = 1; | |
e32eb50d | 1114 | ring->align_mask = 16 - 1; |
771fe6b9 JG |
1115 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
1116 | pre_write_timer = 64; | |
1117 | /* Force CP_RB_WPTR write if written more than one time before the | |
1118 | * delay expire | |
1119 | */ | |
1120 | pre_write_limit = 0; | |
1121 | /* Setup the cp cache like this (cache size is 96 dwords) : | |
1122 | * RING 0 to 15 | |
1123 | * INDIRECT1 16 to 79 | |
1124 | * INDIRECT2 80 to 95 | |
1125 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
1126 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) | |
1127 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
1128 | * Idea being that most of the gpu cmd will be through indirect1 buffer | |
1129 | * so it gets the bigger cache. | |
1130 | */ | |
1131 | indirect2_start = 80; | |
1132 | indirect1_start = 16; | |
1133 | /* cp setup */ | |
1134 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); | |
d6f28938 | 1135 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
771fe6b9 | 1136 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
724c80e1 | 1137 | REG_SET(RADEON_MAX_FETCH, max_fetch)); |
d6f28938 AD |
1138 | #ifdef __BIG_ENDIAN |
1139 | tmp |= RADEON_BUF_SWAP_32BIT; | |
1140 | #endif | |
724c80e1 | 1141 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); |
d6f28938 | 1142 | |
771fe6b9 | 1143 | /* Set ring address */ |
e32eb50d CK |
1144 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); |
1145 | WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); | |
771fe6b9 | 1146 | /* Force read & write ptr to 0 */ |
724c80e1 | 1147 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
771fe6b9 | 1148 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
e32eb50d CK |
1149 | ring->wptr = 0; |
1150 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); | |
724c80e1 AD |
1151 | |
1152 | /* set the wb address whether it's enabled or not */ | |
1153 | WREG32(R_00070C_CP_RB_RPTR_ADDR, | |
1154 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); | |
1155 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); | |
1156 | ||
1157 | if (rdev->wb.enabled) | |
1158 | WREG32(R_000770_SCRATCH_UMSK, 0xff); | |
1159 | else { | |
1160 | tmp |= RADEON_RB_NO_UPDATE; | |
1161 | WREG32(R_000770_SCRATCH_UMSK, 0); | |
1162 | } | |
1163 | ||
771fe6b9 JG |
1164 | WREG32(RADEON_CP_RB_CNTL, tmp); |
1165 | udelay(10); | |
e32eb50d | 1166 | ring->rptr = RREG32(RADEON_CP_RB_RPTR); |
771fe6b9 JG |
1167 | /* Set cp mode to bus mastering & enable cp*/ |
1168 | WREG32(RADEON_CP_CSQ_MODE, | |
1169 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | | |
1170 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); | |
d75ee3be AD |
1171 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
1172 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); | |
771fe6b9 | 1173 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
2099810f DA |
1174 | |
1175 | /* at this point everything should be setup correctly to enable master */ | |
1176 | pci_set_master(rdev->pdev); | |
1177 | ||
f712812e AD |
1178 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1179 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); | |
771fe6b9 JG |
1180 | if (r) { |
1181 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); | |
1182 | return r; | |
1183 | } | |
e32eb50d | 1184 | ring->ready = true; |
53595338 | 1185 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
c7eff978 | 1186 | |
16c58081 SK |
1187 | if (!ring->rptr_save_reg /* not resuming from suspend */ |
1188 | && radeon_ring_supports_scratch_reg(rdev, ring)) { | |
c7eff978 AD |
1189 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); |
1190 | if (r) { | |
1191 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); | |
1192 | ring->rptr_save_reg = 0; | |
1193 | } | |
1194 | } | |
771fe6b9 JG |
1195 | return 0; |
1196 | } | |
1197 | ||
1198 | void r100_cp_fini(struct radeon_device *rdev) | |
1199 | { | |
45600232 JG |
1200 | if (r100_cp_wait_for_idle(rdev)) { |
1201 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); | |
1202 | } | |
771fe6b9 | 1203 | /* Disable ring */ |
a18d7ea1 | 1204 | r100_cp_disable(rdev); |
c7eff978 | 1205 | radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); |
e32eb50d | 1206 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
771fe6b9 JG |
1207 | DRM_INFO("radeon: cp finalized\n"); |
1208 | } | |
1209 | ||
1210 | void r100_cp_disable(struct radeon_device *rdev) | |
1211 | { | |
1212 | /* Disable ring */ | |
53595338 | 1213 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
e32eb50d | 1214 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
771fe6b9 JG |
1215 | WREG32(RADEON_CP_CSQ_MODE, 0); |
1216 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
724c80e1 | 1217 | WREG32(R_000770_SCRATCH_UMSK, 0); |
771fe6b9 JG |
1218 | if (r100_gui_wait_for_idle(rdev)) { |
1219 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
1220 | "programming pipes. Bad things might happen.\n"); | |
1221 | } | |
1222 | } | |
1223 | ||
771fe6b9 JG |
1224 | /* |
1225 | * CS functions | |
1226 | */ | |
0242f74d AD |
1227 | int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
1228 | struct radeon_cs_packet *pkt, | |
1229 | unsigned idx, | |
1230 | unsigned reg) | |
1231 | { | |
1232 | int r; | |
1233 | u32 tile_flags = 0; | |
1234 | u32 tmp; | |
1235 | struct radeon_cs_reloc *reloc; | |
1236 | u32 value; | |
1237 | ||
012e976d | 1238 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1239 | if (r) { |
1240 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1241 | idx, reg); | |
c3ad63af | 1242 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1243 | return r; |
1244 | } | |
1245 | ||
1246 | value = radeon_get_ib_value(p, idx); | |
1247 | tmp = value & 0x003fffff; | |
1248 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); | |
1249 | ||
1250 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | |
1251 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
1252 | tile_flags |= RADEON_DST_TILE_MACRO; | |
1253 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | |
1254 | if (reg == RADEON_SRC_PITCH_OFFSET) { | |
1255 | DRM_ERROR("Cannot src blit from microtiled surface\n"); | |
c3ad63af | 1256 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1257 | return -EINVAL; |
1258 | } | |
1259 | tile_flags |= RADEON_DST_TILE_MICRO; | |
1260 | } | |
1261 | ||
1262 | tmp |= tile_flags; | |
1263 | p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; | |
1264 | } else | |
1265 | p->ib.ptr[idx] = (value & 0xffc00000) | tmp; | |
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |
1270 | struct radeon_cs_packet *pkt, | |
1271 | int idx) | |
1272 | { | |
1273 | unsigned c, i; | |
1274 | struct radeon_cs_reloc *reloc; | |
1275 | struct r100_cs_track *track; | |
1276 | int r = 0; | |
1277 | volatile uint32_t *ib; | |
1278 | u32 idx_value; | |
1279 | ||
1280 | ib = p->ib.ptr; | |
1281 | track = (struct r100_cs_track *)p->track; | |
1282 | c = radeon_get_ib_value(p, idx++) & 0x1F; | |
1283 | if (c > 16) { | |
1284 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", | |
1285 | pkt->opcode); | |
c3ad63af | 1286 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1287 | return -EINVAL; |
1288 | } | |
1289 | track->num_arrays = c; | |
1290 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | |
012e976d | 1291 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1292 | if (r) { |
1293 | DRM_ERROR("No reloc for packet3 %d\n", | |
1294 | pkt->opcode); | |
c3ad63af | 1295 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1296 | return r; |
1297 | } | |
1298 | idx_value = radeon_get_ib_value(p, idx); | |
1299 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | |
1300 | ||
1301 | track->arrays[i + 0].esize = idx_value >> 8; | |
1302 | track->arrays[i + 0].robj = reloc->robj; | |
1303 | track->arrays[i + 0].esize &= 0x7F; | |
012e976d | 1304 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1305 | if (r) { |
1306 | DRM_ERROR("No reloc for packet3 %d\n", | |
1307 | pkt->opcode); | |
c3ad63af | 1308 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1309 | return r; |
1310 | } | |
1311 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); | |
1312 | track->arrays[i + 1].robj = reloc->robj; | |
1313 | track->arrays[i + 1].esize = idx_value >> 24; | |
1314 | track->arrays[i + 1].esize &= 0x7F; | |
1315 | } | |
1316 | if (c & 1) { | |
012e976d | 1317 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
0242f74d AD |
1318 | if (r) { |
1319 | DRM_ERROR("No reloc for packet3 %d\n", | |
1320 | pkt->opcode); | |
c3ad63af | 1321 | radeon_cs_dump_packet(p, pkt); |
0242f74d AD |
1322 | return r; |
1323 | } | |
1324 | idx_value = radeon_get_ib_value(p, idx); | |
1325 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | |
1326 | track->arrays[i + 0].robj = reloc->robj; | |
1327 | track->arrays[i + 0].esize = idx_value >> 8; | |
1328 | track->arrays[i + 0].esize &= 0x7F; | |
1329 | } | |
1330 | return r; | |
1331 | } | |
1332 | ||
771fe6b9 JG |
1333 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1334 | struct radeon_cs_packet *pkt, | |
068a117c | 1335 | const unsigned *auth, unsigned n, |
771fe6b9 JG |
1336 | radeon_packet0_check_t check) |
1337 | { | |
1338 | unsigned reg; | |
1339 | unsigned i, j, m; | |
1340 | unsigned idx; | |
1341 | int r; | |
1342 | ||
1343 | idx = pkt->idx + 1; | |
1344 | reg = pkt->reg; | |
068a117c JG |
1345 | /* Check that register fall into register range |
1346 | * determined by the number of entry (n) in the | |
1347 | * safe register bitmap. | |
1348 | */ | |
771fe6b9 JG |
1349 | if (pkt->one_reg_wr) { |
1350 | if ((reg >> 7) > n) { | |
1351 | return -EINVAL; | |
1352 | } | |
1353 | } else { | |
1354 | if (((reg + (pkt->count << 2)) >> 7) > n) { | |
1355 | return -EINVAL; | |
1356 | } | |
1357 | } | |
1358 | for (i = 0; i <= pkt->count; i++, idx++) { | |
1359 | j = (reg >> 7); | |
1360 | m = 1 << ((reg >> 2) & 31); | |
1361 | if (auth[j] & m) { | |
1362 | r = check(p, pkt, idx, reg); | |
1363 | if (r) { | |
1364 | return r; | |
1365 | } | |
1366 | } | |
1367 | if (pkt->one_reg_wr) { | |
1368 | if (!(auth[j] & m)) { | |
1369 | break; | |
1370 | } | |
1371 | } else { | |
1372 | reg += 4; | |
1373 | } | |
1374 | } | |
1375 | return 0; | |
1376 | } | |
1377 | ||
531369e6 DA |
1378 | /** |
1379 | * r100_cs_packet_next_vline() - parse userspace VLINE packet | |
1380 | * @parser: parser structure holding parsing context. | |
1381 | * | |
1382 | * Userspace sends a special sequence for VLINE waits. | |
1383 | * PACKET0 - VLINE_START_END + value | |
1384 | * PACKET0 - WAIT_UNTIL +_value | |
1385 | * RELOC (P3) - crtc_id in reloc. | |
1386 | * | |
1387 | * This function parses this and relocates the VLINE START END | |
1388 | * and WAIT UNTIL packets to the correct crtc. | |
1389 | * It also detects a switched off crtc and nulls out the | |
1390 | * wait in that case. | |
1391 | */ | |
1392 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |
1393 | { | |
531369e6 DA |
1394 | struct drm_mode_object *obj; |
1395 | struct drm_crtc *crtc; | |
1396 | struct radeon_crtc *radeon_crtc; | |
1397 | struct radeon_cs_packet p3reloc, waitreloc; | |
1398 | int crtc_id; | |
1399 | int r; | |
1400 | uint32_t header, h_idx, reg; | |
513bcb46 | 1401 | volatile uint32_t *ib; |
531369e6 | 1402 | |
f2e39221 | 1403 | ib = p->ib.ptr; |
531369e6 DA |
1404 | |
1405 | /* parse the wait until */ | |
c38f34b5 | 1406 | r = radeon_cs_packet_parse(p, &waitreloc, p->idx); |
531369e6 DA |
1407 | if (r) |
1408 | return r; | |
1409 | ||
1410 | /* check its a wait until and only 1 count */ | |
1411 | if (waitreloc.reg != RADEON_WAIT_UNTIL || | |
1412 | waitreloc.count != 0) { | |
1413 | DRM_ERROR("vline wait had illegal wait until segment\n"); | |
a3a88a66 | 1414 | return -EINVAL; |
531369e6 DA |
1415 | } |
1416 | ||
513bcb46 | 1417 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
531369e6 | 1418 | DRM_ERROR("vline wait had illegal wait until\n"); |
a3a88a66 | 1419 | return -EINVAL; |
531369e6 DA |
1420 | } |
1421 | ||
1422 | /* jump over the NOP */ | |
c38f34b5 | 1423 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
531369e6 DA |
1424 | if (r) |
1425 | return r; | |
1426 | ||
1427 | h_idx = p->idx - 2; | |
90ebd065 AD |
1428 | p->idx += waitreloc.count + 2; |
1429 | p->idx += p3reloc.count + 2; | |
531369e6 | 1430 | |
513bcb46 DA |
1431 | header = radeon_get_ib_value(p, h_idx); |
1432 | crtc_id = radeon_get_ib_value(p, h_idx + 5); | |
4e872ae2 | 1433 | reg = R100_CP_PACKET0_GET_REG(header); |
531369e6 DA |
1434 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
1435 | if (!obj) { | |
1436 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | |
a3a88a66 | 1437 | return -EINVAL; |
531369e6 DA |
1438 | } |
1439 | crtc = obj_to_crtc(obj); | |
1440 | radeon_crtc = to_radeon_crtc(crtc); | |
1441 | crtc_id = radeon_crtc->crtc_id; | |
1442 | ||
1443 | if (!crtc->enabled) { | |
1444 | /* if the CRTC isn't enabled - we need to nop out the wait until */ | |
513bcb46 DA |
1445 | ib[h_idx + 2] = PACKET2(0); |
1446 | ib[h_idx + 3] = PACKET2(0); | |
531369e6 DA |
1447 | } else if (crtc_id == 1) { |
1448 | switch (reg) { | |
1449 | case AVIVO_D1MODE_VLINE_START_END: | |
90ebd065 | 1450 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
1451 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1452 | break; | |
1453 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
90ebd065 | 1454 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
1455 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1456 | break; | |
1457 | default: | |
1458 | DRM_ERROR("unknown crtc reloc\n"); | |
a3a88a66 | 1459 | return -EINVAL; |
531369e6 | 1460 | } |
513bcb46 DA |
1461 | ib[h_idx] = header; |
1462 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; | |
531369e6 | 1463 | } |
a3a88a66 PB |
1464 | |
1465 | return 0; | |
531369e6 DA |
1466 | } |
1467 | ||
551ebd83 DA |
1468 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1469 | { | |
1470 | int vtx_size; | |
1471 | vtx_size = 2; | |
1472 | /* ordered according to bits in spec */ | |
1473 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) | |
1474 | vtx_size++; | |
1475 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) | |
1476 | vtx_size += 3; | |
1477 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) | |
1478 | vtx_size++; | |
1479 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) | |
1480 | vtx_size++; | |
1481 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) | |
1482 | vtx_size += 3; | |
1483 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) | |
1484 | vtx_size++; | |
1485 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) | |
1486 | vtx_size++; | |
1487 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) | |
1488 | vtx_size += 2; | |
1489 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) | |
1490 | vtx_size += 2; | |
1491 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) | |
1492 | vtx_size++; | |
1493 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) | |
1494 | vtx_size += 2; | |
1495 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) | |
1496 | vtx_size++; | |
1497 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) | |
1498 | vtx_size += 2; | |
1499 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) | |
1500 | vtx_size++; | |
1501 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) | |
1502 | vtx_size++; | |
1503 | /* blend weight */ | |
1504 | if (vtx_fmt & (0x7 << 15)) | |
1505 | vtx_size += (vtx_fmt >> 15) & 0x7; | |
1506 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) | |
1507 | vtx_size += 3; | |
1508 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) | |
1509 | vtx_size += 2; | |
1510 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) | |
1511 | vtx_size++; | |
1512 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) | |
1513 | vtx_size++; | |
1514 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) | |
1515 | vtx_size++; | |
1516 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) | |
1517 | vtx_size++; | |
1518 | return vtx_size; | |
1519 | } | |
1520 | ||
771fe6b9 | 1521 | static int r100_packet0_check(struct radeon_cs_parser *p, |
551ebd83 DA |
1522 | struct radeon_cs_packet *pkt, |
1523 | unsigned idx, unsigned reg) | |
771fe6b9 | 1524 | { |
771fe6b9 | 1525 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1526 | struct r100_cs_track *track; |
771fe6b9 JG |
1527 | volatile uint32_t *ib; |
1528 | uint32_t tmp; | |
771fe6b9 | 1529 | int r; |
551ebd83 | 1530 | int i, face; |
e024e110 | 1531 | u32 tile_flags = 0; |
513bcb46 | 1532 | u32 idx_value; |
771fe6b9 | 1533 | |
f2e39221 | 1534 | ib = p->ib.ptr; |
551ebd83 DA |
1535 | track = (struct r100_cs_track *)p->track; |
1536 | ||
513bcb46 DA |
1537 | idx_value = radeon_get_ib_value(p, idx); |
1538 | ||
551ebd83 DA |
1539 | switch (reg) { |
1540 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
1541 | r = r100_cs_packet_parse_vline(p); | |
1542 | if (r) { | |
1543 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1544 | idx, reg); | |
c3ad63af | 1545 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1546 | return r; |
1547 | } | |
1548 | break; | |
771fe6b9 JG |
1549 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1550 | * range access */ | |
551ebd83 DA |
1551 | case RADEON_DST_PITCH_OFFSET: |
1552 | case RADEON_SRC_PITCH_OFFSET: | |
1553 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); | |
1554 | if (r) | |
1555 | return r; | |
1556 | break; | |
1557 | case RADEON_RB3D_DEPTHOFFSET: | |
012e976d | 1558 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1559 | if (r) { |
1560 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1561 | idx, reg); | |
c3ad63af | 1562 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1563 | return r; |
1564 | } | |
1565 | track->zb.robj = reloc->robj; | |
513bcb46 | 1566 | track->zb.offset = idx_value; |
40b4a759 | 1567 | track->zb_dirty = true; |
513bcb46 | 1568 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1569 | break; |
1570 | case RADEON_RB3D_COLOROFFSET: | |
012e976d | 1571 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1572 | if (r) { |
1573 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1574 | idx, reg); | |
c3ad63af | 1575 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1576 | return r; |
1577 | } | |
1578 | track->cb[0].robj = reloc->robj; | |
513bcb46 | 1579 | track->cb[0].offset = idx_value; |
40b4a759 | 1580 | track->cb_dirty = true; |
513bcb46 | 1581 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1582 | break; |
1583 | case RADEON_PP_TXOFFSET_0: | |
1584 | case RADEON_PP_TXOFFSET_1: | |
1585 | case RADEON_PP_TXOFFSET_2: | |
1586 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; | |
012e976d | 1587 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1588 | if (r) { |
1589 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1590 | idx, reg); | |
c3ad63af | 1591 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1592 | return r; |
1593 | } | |
f2746f83 AD |
1594 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1595 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
1596 | tile_flags |= RADEON_TXO_MACRO_TILE; | |
1597 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
1598 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; | |
1599 | ||
1600 | tmp = idx_value & ~(0x7 << 2); | |
1601 | tmp |= tile_flags; | |
1602 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); | |
1603 | } else | |
1604 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 | 1605 | track->textures[i].robj = reloc->robj; |
40b4a759 | 1606 | track->tex_dirty = true; |
551ebd83 DA |
1607 | break; |
1608 | case RADEON_PP_CUBIC_OFFSET_T0_0: | |
1609 | case RADEON_PP_CUBIC_OFFSET_T0_1: | |
1610 | case RADEON_PP_CUBIC_OFFSET_T0_2: | |
1611 | case RADEON_PP_CUBIC_OFFSET_T0_3: | |
1612 | case RADEON_PP_CUBIC_OFFSET_T0_4: | |
1613 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; | |
012e976d | 1614 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1615 | if (r) { |
1616 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1617 | idx, reg); | |
c3ad63af | 1618 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1619 | return r; |
1620 | } | |
513bcb46 DA |
1621 | track->textures[0].cube_info[i].offset = idx_value; |
1622 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 | 1623 | track->textures[0].cube_info[i].robj = reloc->robj; |
40b4a759 | 1624 | track->tex_dirty = true; |
551ebd83 DA |
1625 | break; |
1626 | case RADEON_PP_CUBIC_OFFSET_T1_0: | |
1627 | case RADEON_PP_CUBIC_OFFSET_T1_1: | |
1628 | case RADEON_PP_CUBIC_OFFSET_T1_2: | |
1629 | case RADEON_PP_CUBIC_OFFSET_T1_3: | |
1630 | case RADEON_PP_CUBIC_OFFSET_T1_4: | |
1631 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; | |
012e976d | 1632 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1633 | if (r) { |
1634 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1635 | idx, reg); | |
c3ad63af | 1636 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1637 | return r; |
1638 | } | |
513bcb46 DA |
1639 | track->textures[1].cube_info[i].offset = idx_value; |
1640 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 | 1641 | track->textures[1].cube_info[i].robj = reloc->robj; |
40b4a759 | 1642 | track->tex_dirty = true; |
551ebd83 DA |
1643 | break; |
1644 | case RADEON_PP_CUBIC_OFFSET_T2_0: | |
1645 | case RADEON_PP_CUBIC_OFFSET_T2_1: | |
1646 | case RADEON_PP_CUBIC_OFFSET_T2_2: | |
1647 | case RADEON_PP_CUBIC_OFFSET_T2_3: | |
1648 | case RADEON_PP_CUBIC_OFFSET_T2_4: | |
1649 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; | |
012e976d | 1650 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1651 | if (r) { |
1652 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1653 | idx, reg); | |
c3ad63af | 1654 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1655 | return r; |
1656 | } | |
513bcb46 DA |
1657 | track->textures[2].cube_info[i].offset = idx_value; |
1658 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 | 1659 | track->textures[2].cube_info[i].robj = reloc->robj; |
40b4a759 | 1660 | track->tex_dirty = true; |
551ebd83 DA |
1661 | break; |
1662 | case RADEON_RE_WIDTH_HEIGHT: | |
513bcb46 | 1663 | track->maxy = ((idx_value >> 16) & 0x7FF); |
40b4a759 MO |
1664 | track->cb_dirty = true; |
1665 | track->zb_dirty = true; | |
551ebd83 DA |
1666 | break; |
1667 | case RADEON_RB3D_COLORPITCH: | |
012e976d | 1668 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1669 | if (r) { |
1670 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1671 | idx, reg); | |
c3ad63af | 1672 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1673 | return r; |
1674 | } | |
c9068eb2 AD |
1675 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1676 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
1677 | tile_flags |= RADEON_COLOR_TILE_ENABLE; | |
1678 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
1679 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | |
1680 | ||
1681 | tmp = idx_value & ~(0x7 << 16); | |
1682 | tmp |= tile_flags; | |
1683 | ib[idx] = tmp; | |
1684 | } else | |
1685 | ib[idx] = idx_value; | |
e024e110 | 1686 | |
513bcb46 | 1687 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
40b4a759 | 1688 | track->cb_dirty = true; |
551ebd83 DA |
1689 | break; |
1690 | case RADEON_RB3D_DEPTHPITCH: | |
513bcb46 | 1691 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
40b4a759 | 1692 | track->zb_dirty = true; |
551ebd83 DA |
1693 | break; |
1694 | case RADEON_RB3D_CNTL: | |
513bcb46 | 1695 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
551ebd83 DA |
1696 | case 7: |
1697 | case 8: | |
1698 | case 9: | |
1699 | case 11: | |
1700 | case 12: | |
1701 | track->cb[0].cpp = 1; | |
e024e110 | 1702 | break; |
551ebd83 DA |
1703 | case 3: |
1704 | case 4: | |
1705 | case 15: | |
1706 | track->cb[0].cpp = 2; | |
1707 | break; | |
1708 | case 6: | |
1709 | track->cb[0].cpp = 4; | |
1710 | break; | |
1711 | default: | |
1712 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 1713 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
551ebd83 DA |
1714 | return -EINVAL; |
1715 | } | |
513bcb46 | 1716 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
40b4a759 MO |
1717 | track->cb_dirty = true; |
1718 | track->zb_dirty = true; | |
551ebd83 DA |
1719 | break; |
1720 | case RADEON_RB3D_ZSTENCILCNTL: | |
513bcb46 | 1721 | switch (idx_value & 0xf) { |
551ebd83 DA |
1722 | case 0: |
1723 | track->zb.cpp = 2; | |
1724 | break; | |
1725 | case 2: | |
1726 | case 3: | |
1727 | case 4: | |
1728 | case 5: | |
1729 | case 9: | |
1730 | case 11: | |
1731 | track->zb.cpp = 4; | |
17782d99 | 1732 | break; |
771fe6b9 | 1733 | default: |
771fe6b9 JG |
1734 | break; |
1735 | } | |
40b4a759 | 1736 | track->zb_dirty = true; |
551ebd83 DA |
1737 | break; |
1738 | case RADEON_RB3D_ZPASS_ADDR: | |
012e976d | 1739 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
551ebd83 DA |
1740 | if (r) { |
1741 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1742 | idx, reg); | |
c3ad63af | 1743 | radeon_cs_dump_packet(p, pkt); |
551ebd83 DA |
1744 | return r; |
1745 | } | |
513bcb46 | 1746 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1747 | break; |
1748 | case RADEON_PP_CNTL: | |
1749 | { | |
513bcb46 | 1750 | uint32_t temp = idx_value >> 4; |
551ebd83 DA |
1751 | for (i = 0; i < track->num_texture; i++) |
1752 | track->textures[i].enabled = !!(temp & (1 << i)); | |
40b4a759 | 1753 | track->tex_dirty = true; |
551ebd83 DA |
1754 | } |
1755 | break; | |
1756 | case RADEON_SE_VF_CNTL: | |
513bcb46 | 1757 | track->vap_vf_cntl = idx_value; |
551ebd83 DA |
1758 | break; |
1759 | case RADEON_SE_VTX_FMT: | |
513bcb46 | 1760 | track->vtx_size = r100_get_vtx_size(idx_value); |
551ebd83 DA |
1761 | break; |
1762 | case RADEON_PP_TEX_SIZE_0: | |
1763 | case RADEON_PP_TEX_SIZE_1: | |
1764 | case RADEON_PP_TEX_SIZE_2: | |
1765 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; | |
513bcb46 DA |
1766 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1767 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | |
40b4a759 | 1768 | track->tex_dirty = true; |
551ebd83 DA |
1769 | break; |
1770 | case RADEON_PP_TEX_PITCH_0: | |
1771 | case RADEON_PP_TEX_PITCH_1: | |
1772 | case RADEON_PP_TEX_PITCH_2: | |
1773 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; | |
513bcb46 | 1774 | track->textures[i].pitch = idx_value + 32; |
40b4a759 | 1775 | track->tex_dirty = true; |
551ebd83 DA |
1776 | break; |
1777 | case RADEON_PP_TXFILTER_0: | |
1778 | case RADEON_PP_TXFILTER_1: | |
1779 | case RADEON_PP_TXFILTER_2: | |
1780 | i = (reg - RADEON_PP_TXFILTER_0) / 24; | |
513bcb46 | 1781 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
551ebd83 | 1782 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
513bcb46 | 1783 | tmp = (idx_value >> 23) & 0x7; |
551ebd83 DA |
1784 | if (tmp == 2 || tmp == 6) |
1785 | track->textures[i].roundup_w = false; | |
513bcb46 | 1786 | tmp = (idx_value >> 27) & 0x7; |
551ebd83 DA |
1787 | if (tmp == 2 || tmp == 6) |
1788 | track->textures[i].roundup_h = false; | |
40b4a759 | 1789 | track->tex_dirty = true; |
551ebd83 DA |
1790 | break; |
1791 | case RADEON_PP_TXFORMAT_0: | |
1792 | case RADEON_PP_TXFORMAT_1: | |
1793 | case RADEON_PP_TXFORMAT_2: | |
1794 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; | |
513bcb46 | 1795 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
551ebd83 DA |
1796 | track->textures[i].use_pitch = 1; |
1797 | } else { | |
1798 | track->textures[i].use_pitch = 0; | |
513bcb46 DA |
1799 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1800 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); | |
551ebd83 | 1801 | } |
513bcb46 | 1802 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
551ebd83 | 1803 | track->textures[i].tex_coord_type = 2; |
513bcb46 | 1804 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
551ebd83 DA |
1805 | case RADEON_TXFORMAT_I8: |
1806 | case RADEON_TXFORMAT_RGB332: | |
1807 | case RADEON_TXFORMAT_Y8: | |
1808 | track->textures[i].cpp = 1; | |
f9da52d5 | 1809 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
551ebd83 DA |
1810 | break; |
1811 | case RADEON_TXFORMAT_AI88: | |
1812 | case RADEON_TXFORMAT_ARGB1555: | |
1813 | case RADEON_TXFORMAT_RGB565: | |
1814 | case RADEON_TXFORMAT_ARGB4444: | |
1815 | case RADEON_TXFORMAT_VYUY422: | |
1816 | case RADEON_TXFORMAT_YVYU422: | |
551ebd83 DA |
1817 | case RADEON_TXFORMAT_SHADOW16: |
1818 | case RADEON_TXFORMAT_LDUDV655: | |
1819 | case RADEON_TXFORMAT_DUDV88: | |
1820 | track->textures[i].cpp = 2; | |
f9da52d5 | 1821 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
771fe6b9 | 1822 | break; |
551ebd83 DA |
1823 | case RADEON_TXFORMAT_ARGB8888: |
1824 | case RADEON_TXFORMAT_RGBA8888: | |
551ebd83 DA |
1825 | case RADEON_TXFORMAT_SHADOW32: |
1826 | case RADEON_TXFORMAT_LDUDUV8888: | |
1827 | track->textures[i].cpp = 4; | |
f9da52d5 | 1828 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
551ebd83 | 1829 | break; |
d785d78b DA |
1830 | case RADEON_TXFORMAT_DXT1: |
1831 | track->textures[i].cpp = 1; | |
1832 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
1833 | break; | |
1834 | case RADEON_TXFORMAT_DXT23: | |
1835 | case RADEON_TXFORMAT_DXT45: | |
1836 | track->textures[i].cpp = 1; | |
1837 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
1838 | break; | |
551ebd83 | 1839 | } |
513bcb46 DA |
1840 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1841 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); | |
40b4a759 | 1842 | track->tex_dirty = true; |
551ebd83 DA |
1843 | break; |
1844 | case RADEON_PP_CUBIC_FACES_0: | |
1845 | case RADEON_PP_CUBIC_FACES_1: | |
1846 | case RADEON_PP_CUBIC_FACES_2: | |
513bcb46 | 1847 | tmp = idx_value; |
551ebd83 DA |
1848 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1849 | for (face = 0; face < 4; face++) { | |
1850 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | |
1851 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); | |
771fe6b9 | 1852 | } |
40b4a759 | 1853 | track->tex_dirty = true; |
551ebd83 DA |
1854 | break; |
1855 | default: | |
1856 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | |
1857 | reg, idx); | |
1858 | return -EINVAL; | |
771fe6b9 JG |
1859 | } |
1860 | return 0; | |
1861 | } | |
1862 | ||
068a117c JG |
1863 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1864 | struct radeon_cs_packet *pkt, | |
4c788679 | 1865 | struct radeon_bo *robj) |
068a117c | 1866 | { |
068a117c | 1867 | unsigned idx; |
513bcb46 | 1868 | u32 value; |
068a117c | 1869 | idx = pkt->idx + 1; |
513bcb46 | 1870 | value = radeon_get_ib_value(p, idx + 2); |
4c788679 | 1871 | if ((value + 1) > radeon_bo_size(robj)) { |
068a117c JG |
1872 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1873 | "(need %u have %lu) !\n", | |
513bcb46 | 1874 | value + 1, |
4c788679 | 1875 | radeon_bo_size(robj)); |
068a117c JG |
1876 | return -EINVAL; |
1877 | } | |
1878 | return 0; | |
1879 | } | |
1880 | ||
771fe6b9 JG |
1881 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1882 | struct radeon_cs_packet *pkt) | |
1883 | { | |
771fe6b9 | 1884 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1885 | struct r100_cs_track *track; |
771fe6b9 | 1886 | unsigned idx; |
771fe6b9 JG |
1887 | volatile uint32_t *ib; |
1888 | int r; | |
1889 | ||
f2e39221 | 1890 | ib = p->ib.ptr; |
771fe6b9 | 1891 | idx = pkt->idx + 1; |
551ebd83 | 1892 | track = (struct r100_cs_track *)p->track; |
771fe6b9 JG |
1893 | switch (pkt->opcode) { |
1894 | case PACKET3_3D_LOAD_VBPNTR: | |
513bcb46 DA |
1895 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1896 | if (r) | |
1897 | return r; | |
771fe6b9 JG |
1898 | break; |
1899 | case PACKET3_INDX_BUFFER: | |
012e976d | 1900 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
1901 | if (r) { |
1902 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
c3ad63af | 1903 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
1904 | return r; |
1905 | } | |
513bcb46 | 1906 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
068a117c JG |
1907 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1908 | if (r) { | |
1909 | return r; | |
1910 | } | |
771fe6b9 JG |
1911 | break; |
1912 | case 0x23: | |
771fe6b9 | 1913 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
012e976d | 1914 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
1915 | if (r) { |
1916 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
c3ad63af | 1917 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
1918 | return r; |
1919 | } | |
513bcb46 | 1920 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
551ebd83 | 1921 | track->num_arrays = 1; |
513bcb46 | 1922 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
551ebd83 DA |
1923 | |
1924 | track->arrays[0].robj = reloc->robj; | |
1925 | track->arrays[0].esize = track->vtx_size; | |
1926 | ||
513bcb46 | 1927 | track->max_indx = radeon_get_ib_value(p, idx+1); |
551ebd83 | 1928 | |
513bcb46 | 1929 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
551ebd83 DA |
1930 | track->immd_dwords = pkt->count - 1; |
1931 | r = r100_cs_track_check(p->rdev, track); | |
1932 | if (r) | |
1933 | return r; | |
771fe6b9 JG |
1934 | break; |
1935 | case PACKET3_3D_DRAW_IMMD: | |
513bcb46 | 1936 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1937 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1938 | return -EINVAL; | |
1939 | } | |
cf57fc7a | 1940 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
513bcb46 | 1941 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1942 | track->immd_dwords = pkt->count - 1; |
1943 | r = r100_cs_track_check(p->rdev, track); | |
1944 | if (r) | |
1945 | return r; | |
1946 | break; | |
771fe6b9 JG |
1947 | /* triggers drawing using in-packet vertex data */ |
1948 | case PACKET3_3D_DRAW_IMMD_2: | |
513bcb46 | 1949 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1950 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1951 | return -EINVAL; | |
1952 | } | |
513bcb46 | 1953 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1954 | track->immd_dwords = pkt->count; |
1955 | r = r100_cs_track_check(p->rdev, track); | |
1956 | if (r) | |
1957 | return r; | |
1958 | break; | |
771fe6b9 JG |
1959 | /* triggers drawing using in-packet vertex data */ |
1960 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1961 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1962 | r = r100_cs_track_check(p->rdev, track); |
1963 | if (r) | |
1964 | return r; | |
1965 | break; | |
771fe6b9 JG |
1966 | /* triggers drawing of vertex buffers setup elsewhere */ |
1967 | case PACKET3_3D_DRAW_INDX_2: | |
513bcb46 | 1968 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1969 | r = r100_cs_track_check(p->rdev, track); |
1970 | if (r) | |
1971 | return r; | |
1972 | break; | |
771fe6b9 JG |
1973 | /* triggers drawing using indices to vertex buffer */ |
1974 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1975 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1976 | r = r100_cs_track_check(p->rdev, track); |
1977 | if (r) | |
1978 | return r; | |
1979 | break; | |
771fe6b9 JG |
1980 | /* triggers drawing of vertex buffers setup elsewhere */ |
1981 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1982 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1983 | r = r100_cs_track_check(p->rdev, track); |
1984 | if (r) | |
1985 | return r; | |
1986 | break; | |
771fe6b9 | 1987 | /* triggers drawing using indices to vertex buffer */ |
ab9e1f59 DA |
1988 | case PACKET3_3D_CLEAR_HIZ: |
1989 | case PACKET3_3D_CLEAR_ZMASK: | |
1990 | if (p->rdev->hyperz_filp != p->filp) | |
1991 | return -EINVAL; | |
1992 | break; | |
771fe6b9 JG |
1993 | case PACKET3_NOP: |
1994 | break; | |
1995 | default: | |
1996 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
1997 | return -EINVAL; | |
1998 | } | |
1999 | return 0; | |
2000 | } | |
2001 | ||
2002 | int r100_cs_parse(struct radeon_cs_parser *p) | |
2003 | { | |
2004 | struct radeon_cs_packet pkt; | |
9f022ddf | 2005 | struct r100_cs_track *track; |
771fe6b9 JG |
2006 | int r; |
2007 | ||
9f022ddf | 2008 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
ce067913 DC |
2009 | if (!track) |
2010 | return -ENOMEM; | |
9f022ddf JG |
2011 | r100_cs_track_clear(p->rdev, track); |
2012 | p->track = track; | |
771fe6b9 | 2013 | do { |
c38f34b5 | 2014 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
771fe6b9 JG |
2015 | if (r) { |
2016 | return r; | |
2017 | } | |
2018 | p->idx += pkt.count + 2; | |
2019 | switch (pkt.type) { | |
4e872ae2 | 2020 | case RADEON_PACKET_TYPE0: |
66b3543e IH |
2021 | if (p->rdev->family >= CHIP_R200) |
2022 | r = r100_cs_parse_packet0(p, &pkt, | |
2023 | p->rdev->config.r100.reg_safe_bm, | |
2024 | p->rdev->config.r100.reg_safe_bm_size, | |
2025 | &r200_packet0_check); | |
2026 | else | |
2027 | r = r100_cs_parse_packet0(p, &pkt, | |
2028 | p->rdev->config.r100.reg_safe_bm, | |
2029 | p->rdev->config.r100.reg_safe_bm_size, | |
2030 | &r100_packet0_check); | |
2031 | break; | |
4e872ae2 | 2032 | case RADEON_PACKET_TYPE2: |
66b3543e | 2033 | break; |
4e872ae2 | 2034 | case RADEON_PACKET_TYPE3: |
66b3543e IH |
2035 | r = r100_packet3_check(p, &pkt); |
2036 | break; | |
2037 | default: | |
2038 | DRM_ERROR("Unknown packet type %d !\n", | |
2039 | pkt.type); | |
2040 | return -EINVAL; | |
771fe6b9 | 2041 | } |
66b3543e | 2042 | if (r) |
771fe6b9 | 2043 | return r; |
771fe6b9 JG |
2044 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
2045 | return 0; | |
2046 | } | |
2047 | ||
0242f74d | 2048 | static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
771fe6b9 | 2049 | { |
0242f74d AD |
2050 | DRM_ERROR("pitch %d\n", t->pitch); |
2051 | DRM_ERROR("use_pitch %d\n", t->use_pitch); | |
2052 | DRM_ERROR("width %d\n", t->width); | |
2053 | DRM_ERROR("width_11 %d\n", t->width_11); | |
2054 | DRM_ERROR("height %d\n", t->height); | |
2055 | DRM_ERROR("height_11 %d\n", t->height_11); | |
2056 | DRM_ERROR("num levels %d\n", t->num_levels); | |
2057 | DRM_ERROR("depth %d\n", t->txdepth); | |
2058 | DRM_ERROR("bpp %d\n", t->cpp); | |
2059 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); | |
2060 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); | |
2061 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); | |
2062 | DRM_ERROR("compress format %d\n", t->compress_format); | |
771fe6b9 JG |
2063 | } |
2064 | ||
0242f74d | 2065 | static int r100_track_compress_size(int compress_format, int w, int h) |
771fe6b9 | 2066 | { |
0242f74d AD |
2067 | int block_width, block_height, block_bytes; |
2068 | int wblocks, hblocks; | |
2069 | int min_wblocks; | |
2070 | int sz; | |
771fe6b9 | 2071 | |
0242f74d AD |
2072 | block_width = 4; |
2073 | block_height = 4; | |
2074 | ||
2075 | switch (compress_format) { | |
2076 | case R100_TRACK_COMP_DXT1: | |
2077 | block_bytes = 8; | |
2078 | min_wblocks = 4; | |
2079 | break; | |
2080 | default: | |
2081 | case R100_TRACK_COMP_DXT35: | |
2082 | block_bytes = 16; | |
2083 | min_wblocks = 2; | |
2084 | break; | |
771fe6b9 | 2085 | } |
0242f74d AD |
2086 | |
2087 | hblocks = (h + block_height - 1) / block_height; | |
2088 | wblocks = (w + block_width - 1) / block_width; | |
2089 | if (wblocks < min_wblocks) | |
2090 | wblocks = min_wblocks; | |
2091 | sz = wblocks * hblocks * block_bytes; | |
2092 | return sz; | |
771fe6b9 JG |
2093 | } |
2094 | ||
0242f74d AD |
2095 | static int r100_cs_track_cube(struct radeon_device *rdev, |
2096 | struct r100_cs_track *track, unsigned idx) | |
771fe6b9 | 2097 | { |
0242f74d AD |
2098 | unsigned face, w, h; |
2099 | struct radeon_bo *cube_robj; | |
2100 | unsigned long size; | |
2101 | unsigned compress_format = track->textures[idx].compress_format; | |
771fe6b9 | 2102 | |
0242f74d AD |
2103 | for (face = 0; face < 5; face++) { |
2104 | cube_robj = track->textures[idx].cube_info[face].robj; | |
2105 | w = track->textures[idx].cube_info[face].width; | |
2106 | h = track->textures[idx].cube_info[face].height; | |
771fe6b9 | 2107 | |
0242f74d AD |
2108 | if (compress_format) { |
2109 | size = r100_track_compress_size(compress_format, w, h); | |
2110 | } else | |
2111 | size = w * h; | |
2112 | size *= track->textures[idx].cpp; | |
2113 | ||
2114 | size += track->textures[idx].cube_info[face].offset; | |
2115 | ||
2116 | if (size > radeon_bo_size(cube_robj)) { | |
2117 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", | |
2118 | size, radeon_bo_size(cube_robj)); | |
2119 | r100_cs_track_texture_print(&track->textures[idx]); | |
2120 | return -1; | |
771fe6b9 | 2121 | } |
771fe6b9 | 2122 | } |
0242f74d | 2123 | return 0; |
771fe6b9 JG |
2124 | } |
2125 | ||
0242f74d AD |
2126 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
2127 | struct r100_cs_track *track) | |
771fe6b9 | 2128 | { |
0242f74d AD |
2129 | struct radeon_bo *robj; |
2130 | unsigned long size; | |
2131 | unsigned u, i, w, h, d; | |
2132 | int ret; | |
771fe6b9 | 2133 | |
0242f74d AD |
2134 | for (u = 0; u < track->num_texture; u++) { |
2135 | if (!track->textures[u].enabled) | |
2136 | continue; | |
2137 | if (track->textures[u].lookup_disable) | |
2138 | continue; | |
2139 | robj = track->textures[u].robj; | |
2140 | if (robj == NULL) { | |
2141 | DRM_ERROR("No texture bound to unit %u\n", u); | |
2142 | return -EINVAL; | |
771fe6b9 | 2143 | } |
0242f74d AD |
2144 | size = 0; |
2145 | for (i = 0; i <= track->textures[u].num_levels; i++) { | |
2146 | if (track->textures[u].use_pitch) { | |
2147 | if (rdev->family < CHIP_R300) | |
2148 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); | |
2149 | else | |
2150 | w = track->textures[u].pitch / (1 << i); | |
2151 | } else { | |
2152 | w = track->textures[u].width; | |
2153 | if (rdev->family >= CHIP_RV515) | |
2154 | w |= track->textures[u].width_11; | |
2155 | w = w / (1 << i); | |
2156 | if (track->textures[u].roundup_w) | |
2157 | w = roundup_pow_of_two(w); | |
2158 | } | |
2159 | h = track->textures[u].height; | |
2160 | if (rdev->family >= CHIP_RV515) | |
2161 | h |= track->textures[u].height_11; | |
2162 | h = h / (1 << i); | |
2163 | if (track->textures[u].roundup_h) | |
2164 | h = roundup_pow_of_two(h); | |
2165 | if (track->textures[u].tex_coord_type == 1) { | |
2166 | d = (1 << track->textures[u].txdepth) / (1 << i); | |
2167 | if (!d) | |
2168 | d = 1; | |
2169 | } else { | |
2170 | d = 1; | |
2171 | } | |
2172 | if (track->textures[u].compress_format) { | |
771fe6b9 | 2173 | |
0242f74d AD |
2174 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
2175 | /* compressed textures are block based */ | |
2176 | } else | |
2177 | size += w * h * d; | |
2178 | } | |
2179 | size *= track->textures[u].cpp; | |
771fe6b9 | 2180 | |
0242f74d AD |
2181 | switch (track->textures[u].tex_coord_type) { |
2182 | case 0: | |
2183 | case 1: | |
2184 | break; | |
2185 | case 2: | |
2186 | if (track->separate_cube) { | |
2187 | ret = r100_cs_track_cube(rdev, track, u); | |
2188 | if (ret) | |
2189 | return ret; | |
2190 | } else | |
2191 | size *= 6; | |
2192 | break; | |
2193 | default: | |
2194 | DRM_ERROR("Invalid texture coordinate type %u for unit " | |
2195 | "%u\n", track->textures[u].tex_coord_type, u); | |
2196 | return -EINVAL; | |
2197 | } | |
2198 | if (size > radeon_bo_size(robj)) { | |
2199 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " | |
2200 | "%lu\n", u, size, radeon_bo_size(robj)); | |
2201 | r100_cs_track_texture_print(&track->textures[u]); | |
2202 | return -EINVAL; | |
771fe6b9 | 2203 | } |
771fe6b9 | 2204 | } |
0242f74d | 2205 | return 0; |
771fe6b9 JG |
2206 | } |
2207 | ||
0242f74d | 2208 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
771fe6b9 JG |
2209 | { |
2210 | unsigned i; | |
0242f74d AD |
2211 | unsigned long size; |
2212 | unsigned prim_walk; | |
2213 | unsigned nverts; | |
2214 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; | |
771fe6b9 | 2215 | |
0242f74d AD |
2216 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
2217 | !track->blend_read_enable) | |
2218 | num_cb = 0; | |
2219 | ||
2220 | for (i = 0; i < num_cb; i++) { | |
2221 | if (track->cb[i].robj == NULL) { | |
2222 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); | |
2223 | return -EINVAL; | |
2224 | } | |
2225 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; | |
2226 | size += track->cb[i].offset; | |
2227 | if (size > radeon_bo_size(track->cb[i].robj)) { | |
2228 | DRM_ERROR("[drm] Buffer too small for color buffer %d " | |
2229 | "(need %lu have %lu) !\n", i, size, | |
2230 | radeon_bo_size(track->cb[i].robj)); | |
2231 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", | |
2232 | i, track->cb[i].pitch, track->cb[i].cpp, | |
2233 | track->cb[i].offset, track->maxy); | |
2234 | return -EINVAL; | |
771fe6b9 | 2235 | } |
771fe6b9 | 2236 | } |
0242f74d | 2237 | track->cb_dirty = false; |
771fe6b9 | 2238 | |
0242f74d AD |
2239 | if (track->zb_dirty && track->z_enabled) { |
2240 | if (track->zb.robj == NULL) { | |
2241 | DRM_ERROR("[drm] No buffer for z buffer !\n"); | |
2242 | return -EINVAL; | |
2243 | } | |
2244 | size = track->zb.pitch * track->zb.cpp * track->maxy; | |
2245 | size += track->zb.offset; | |
2246 | if (size > radeon_bo_size(track->zb.robj)) { | |
2247 | DRM_ERROR("[drm] Buffer too small for z buffer " | |
2248 | "(need %lu have %lu) !\n", size, | |
2249 | radeon_bo_size(track->zb.robj)); | |
2250 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", | |
2251 | track->zb.pitch, track->zb.cpp, | |
2252 | track->zb.offset, track->maxy); | |
2253 | return -EINVAL; | |
2254 | } | |
225758d8 | 2255 | } |
0242f74d | 2256 | track->zb_dirty = false; |
771fe6b9 | 2257 | |
0242f74d AD |
2258 | if (track->aa_dirty && track->aaresolve) { |
2259 | if (track->aa.robj == NULL) { | |
2260 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); | |
2261 | return -EINVAL; | |
2262 | } | |
2263 | /* I believe the format comes from colorbuffer0. */ | |
2264 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; | |
2265 | size += track->aa.offset; | |
2266 | if (size > radeon_bo_size(track->aa.robj)) { | |
2267 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " | |
2268 | "(need %lu have %lu) !\n", i, size, | |
2269 | radeon_bo_size(track->aa.robj)); | |
2270 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", | |
2271 | i, track->aa.pitch, track->cb[0].cpp, | |
2272 | track->aa.offset, track->maxy); | |
2273 | return -EINVAL; | |
2274 | } | |
2275 | } | |
2276 | track->aa_dirty = false; | |
771fe6b9 | 2277 | |
0242f74d AD |
2278 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
2279 | if (track->vap_vf_cntl & (1 << 14)) { | |
2280 | nverts = track->vap_alt_nverts; | |
2281 | } else { | |
2282 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; | |
2739d49c | 2283 | } |
0242f74d AD |
2284 | switch (prim_walk) { |
2285 | case 1: | |
2286 | for (i = 0; i < track->num_arrays; i++) { | |
2287 | size = track->arrays[i].esize * track->max_indx * 4; | |
2288 | if (track->arrays[i].robj == NULL) { | |
2289 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
2290 | "bound\n", prim_walk, i); | |
2291 | return -EINVAL; | |
2292 | } | |
2293 | if (size > radeon_bo_size(track->arrays[i].robj)) { | |
2294 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
2295 | "need %lu dwords have %lu dwords\n", | |
2296 | prim_walk, i, size >> 2, | |
2297 | radeon_bo_size(track->arrays[i].robj) | |
2298 | >> 2); | |
2299 | DRM_ERROR("Max indices %u\n", track->max_indx); | |
2300 | return -EINVAL; | |
2301 | } | |
771fe6b9 | 2302 | } |
0242f74d AD |
2303 | break; |
2304 | case 2: | |
2305 | for (i = 0; i < track->num_arrays; i++) { | |
2306 | size = track->arrays[i].esize * (nverts - 1) * 4; | |
2307 | if (track->arrays[i].robj == NULL) { | |
2308 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
2309 | "bound\n", prim_walk, i); | |
2310 | return -EINVAL; | |
2311 | } | |
2312 | if (size > radeon_bo_size(track->arrays[i].robj)) { | |
2313 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
2314 | "need %lu dwords have %lu dwords\n", | |
2315 | prim_walk, i, size >> 2, | |
2316 | radeon_bo_size(track->arrays[i].robj) | |
2317 | >> 2); | |
2318 | return -EINVAL; | |
2319 | } | |
771fe6b9 | 2320 | } |
0242f74d AD |
2321 | break; |
2322 | case 3: | |
2323 | size = track->vtx_size * nverts; | |
2324 | if (size != track->immd_dwords) { | |
2325 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", | |
2326 | track->immd_dwords, size); | |
2327 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", | |
2328 | nverts, track->vtx_size); | |
2329 | return -EINVAL; | |
771fe6b9 | 2330 | } |
0242f74d AD |
2331 | break; |
2332 | default: | |
2333 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", | |
2334 | prim_walk); | |
2335 | return -EINVAL; | |
2a0f8918 DA |
2336 | } |
2337 | ||
0242f74d AD |
2338 | if (track->tex_dirty) { |
2339 | track->tex_dirty = false; | |
2340 | return r100_cs_track_texture_check(rdev, track); | |
2a0f8918 | 2341 | } |
0242f74d | 2342 | return 0; |
2a0f8918 DA |
2343 | } |
2344 | ||
0242f74d | 2345 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
2a0f8918 | 2346 | { |
0242f74d | 2347 | unsigned i, face; |
2a0f8918 | 2348 | |
0242f74d AD |
2349 | track->cb_dirty = true; |
2350 | track->zb_dirty = true; | |
2351 | track->tex_dirty = true; | |
2352 | track->aa_dirty = true; | |
b7d8cce5 | 2353 | |
0242f74d AD |
2354 | if (rdev->family < CHIP_R300) { |
2355 | track->num_cb = 1; | |
2356 | if (rdev->family <= CHIP_RS200) | |
2357 | track->num_texture = 3; | |
7a50f01a | 2358 | else |
0242f74d AD |
2359 | track->num_texture = 6; |
2360 | track->maxy = 2048; | |
2361 | track->separate_cube = 1; | |
28d52043 | 2362 | } else { |
0242f74d AD |
2363 | track->num_cb = 4; |
2364 | track->num_texture = 16; | |
2365 | track->maxy = 4096; | |
2366 | track->separate_cube = 0; | |
2367 | track->aaresolve = false; | |
2368 | track->aa.robj = NULL; | |
28d52043 | 2369 | } |
2a0f8918 | 2370 | |
0242f74d AD |
2371 | for (i = 0; i < track->num_cb; i++) { |
2372 | track->cb[i].robj = NULL; | |
2373 | track->cb[i].pitch = 8192; | |
2374 | track->cb[i].cpp = 16; | |
2375 | track->cb[i].offset = 0; | |
771fe6b9 | 2376 | } |
0242f74d AD |
2377 | track->z_enabled = true; |
2378 | track->zb.robj = NULL; | |
2379 | track->zb.pitch = 8192; | |
2380 | track->zb.cpp = 4; | |
2381 | track->zb.offset = 0; | |
2382 | track->vtx_size = 0x7F; | |
2383 | track->immd_dwords = 0xFFFFFFFFUL; | |
2384 | track->num_arrays = 11; | |
2385 | track->max_indx = 0x00FFFFFFUL; | |
2386 | for (i = 0; i < track->num_arrays; i++) { | |
2387 | track->arrays[i].robj = NULL; | |
2388 | track->arrays[i].esize = 0x7F; | |
771fe6b9 | 2389 | } |
0242f74d AD |
2390 | for (i = 0; i < track->num_texture; i++) { |
2391 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; | |
2392 | track->textures[i].pitch = 16536; | |
2393 | track->textures[i].width = 16536; | |
2394 | track->textures[i].height = 16536; | |
2395 | track->textures[i].width_11 = 1 << 11; | |
2396 | track->textures[i].height_11 = 1 << 11; | |
2397 | track->textures[i].num_levels = 12; | |
2398 | if (rdev->family <= CHIP_RS200) { | |
2399 | track->textures[i].tex_coord_type = 0; | |
2400 | track->textures[i].txdepth = 0; | |
2401 | } else { | |
2402 | track->textures[i].txdepth = 16; | |
2403 | track->textures[i].tex_coord_type = 1; | |
2404 | } | |
2405 | track->textures[i].cpp = 64; | |
2406 | track->textures[i].robj = NULL; | |
2407 | /* CS IB emission code makes sure texture unit are disabled */ | |
2408 | track->textures[i].enabled = false; | |
2409 | track->textures[i].lookup_disable = false; | |
2410 | track->textures[i].roundup_w = true; | |
2411 | track->textures[i].roundup_h = true; | |
2412 | if (track->separate_cube) | |
2413 | for (face = 0; face < 5; face++) { | |
2414 | track->textures[i].cube_info[face].robj = NULL; | |
2415 | track->textures[i].cube_info[face].width = 16536; | |
2416 | track->textures[i].cube_info[face].height = 16536; | |
2417 | track->textures[i].cube_info[face].offset = 0; | |
2418 | } | |
771fe6b9 JG |
2419 | } |
2420 | } | |
2421 | ||
0242f74d AD |
2422 | /* |
2423 | * Global GPU functions | |
2424 | */ | |
1109ca09 | 2425 | static void r100_errata(struct radeon_device *rdev) |
771fe6b9 | 2426 | { |
0242f74d | 2427 | rdev->pll_errata = 0; |
771fe6b9 | 2428 | |
0242f74d AD |
2429 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
2430 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; | |
2431 | } | |
771fe6b9 | 2432 | |
0242f74d AD |
2433 | if (rdev->family == CHIP_RV100 || |
2434 | rdev->family == CHIP_RS100 || | |
2435 | rdev->family == CHIP_RS200) { | |
2436 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; | |
2437 | } | |
771fe6b9 JG |
2438 | } |
2439 | ||
1109ca09 | 2440 | static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
771fe6b9 | 2441 | { |
0242f74d AD |
2442 | unsigned i; |
2443 | uint32_t tmp; | |
771fe6b9 | 2444 | |
0242f74d AD |
2445 | for (i = 0; i < rdev->usec_timeout; i++) { |
2446 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; | |
2447 | if (tmp >= n) { | |
2448 | return 0; | |
2449 | } | |
2450 | DRM_UDELAY(1); | |
771fe6b9 | 2451 | } |
0242f74d | 2452 | return -1; |
771fe6b9 JG |
2453 | } |
2454 | ||
0242f74d | 2455 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 | 2456 | { |
771fe6b9 | 2457 | unsigned i; |
0242f74d | 2458 | uint32_t tmp; |
771fe6b9 | 2459 | |
0242f74d AD |
2460 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
2461 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" | |
2462 | " Bad things might happen.\n"); | |
771fe6b9 | 2463 | } |
0242f74d AD |
2464 | for (i = 0; i < rdev->usec_timeout; i++) { |
2465 | tmp = RREG32(RADEON_RBBM_STATUS); | |
2466 | if (!(tmp & RADEON_RBBM_ACTIVE)) { | |
2467 | return 0; | |
2468 | } | |
2469 | DRM_UDELAY(1); | |
771fe6b9 | 2470 | } |
0242f74d | 2471 | return -1; |
771fe6b9 JG |
2472 | } |
2473 | ||
0242f74d | 2474 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 | 2475 | { |
0242f74d | 2476 | unsigned i; |
771fe6b9 JG |
2477 | uint32_t tmp; |
2478 | ||
0242f74d AD |
2479 | for (i = 0; i < rdev->usec_timeout; i++) { |
2480 | /* read MC_STATUS */ | |
2481 | tmp = RREG32(RADEON_MC_STATUS); | |
2482 | if (tmp & RADEON_MC_IDLE) { | |
2483 | return 0; | |
2484 | } | |
2485 | DRM_UDELAY(1); | |
2486 | } | |
2487 | return -1; | |
771fe6b9 JG |
2488 | } |
2489 | ||
0242f74d | 2490 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 2491 | { |
0242f74d | 2492 | u32 rbbm_status; |
771fe6b9 | 2493 | |
0242f74d AD |
2494 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
2495 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { | |
2496 | radeon_ring_lockup_update(ring); | |
2497 | return false; | |
2498 | } | |
2499 | /* force CP activities */ | |
2500 | radeon_ring_force_activity(rdev, ring); | |
2501 | return radeon_ring_test_lockup(rdev, ring); | |
771fe6b9 JG |
2502 | } |
2503 | ||
74da01dc AD |
2504 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
2505 | void r100_enable_bm(struct radeon_device *rdev) | |
2506 | { | |
2507 | uint32_t tmp; | |
2508 | /* Enable bus mastering */ | |
2509 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
2510 | WREG32(RADEON_BUS_CNTL, tmp); | |
2511 | } | |
2512 | ||
0242f74d | 2513 | void r100_bm_disable(struct radeon_device *rdev) |
771fe6b9 | 2514 | { |
0242f74d AD |
2515 | u32 tmp; |
2516 | ||
2517 | /* disable bus mastering */ | |
2518 | tmp = RREG32(R_000030_BUS_CNTL); | |
2519 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); | |
2520 | mdelay(1); | |
2521 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); | |
2522 | mdelay(1); | |
2523 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); | |
2524 | tmp = RREG32(RADEON_BUS_CNTL); | |
2525 | mdelay(1); | |
2526 | pci_clear_master(rdev->pdev); | |
2527 | mdelay(1); | |
771fe6b9 | 2528 | } |
e024e110 | 2529 | |
0242f74d | 2530 | int r100_asic_reset(struct radeon_device *rdev) |
e024e110 | 2531 | { |
0242f74d AD |
2532 | struct r100_mc_save save; |
2533 | u32 status, tmp; | |
2534 | int ret = 0; | |
e024e110 | 2535 | |
0242f74d AD |
2536 | status = RREG32(R_000E40_RBBM_STATUS); |
2537 | if (!G_000E40_GUI_ACTIVE(status)) { | |
2538 | return 0; | |
e024e110 | 2539 | } |
0242f74d AD |
2540 | r100_mc_stop(rdev, &save); |
2541 | status = RREG32(R_000E40_RBBM_STATUS); | |
2542 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2543 | /* stop CP */ | |
2544 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
2545 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
2546 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
2547 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
2548 | WREG32(RADEON_CP_RB_WPTR, 0); | |
2549 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
2550 | /* save PCI state */ | |
2551 | pci_save_state(rdev->pdev); | |
2552 | /* disable bus mastering */ | |
2553 | r100_bm_disable(rdev); | |
2554 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | | |
2555 | S_0000F0_SOFT_RESET_RE(1) | | |
2556 | S_0000F0_SOFT_RESET_PP(1) | | |
2557 | S_0000F0_SOFT_RESET_RB(1)); | |
2558 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
2559 | mdelay(500); | |
2560 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
2561 | mdelay(1); | |
2562 | status = RREG32(R_000E40_RBBM_STATUS); | |
2563 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2564 | /* reset CP */ | |
2565 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | |
2566 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
2567 | mdelay(500); | |
2568 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
2569 | mdelay(1); | |
2570 | status = RREG32(R_000E40_RBBM_STATUS); | |
2571 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2572 | /* restore PCI & busmastering */ | |
2573 | pci_restore_state(rdev->pdev); | |
2574 | r100_enable_bm(rdev); | |
2575 | /* Check if GPU is idle */ | |
2576 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || | |
2577 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { | |
2578 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
2579 | ret = -1; | |
2580 | } else | |
2581 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
2582 | r100_mc_resume(rdev, &save); | |
2583 | return ret; | |
2584 | } | |
e024e110 | 2585 | |
0242f74d AD |
2586 | void r100_set_common_regs(struct radeon_device *rdev) |
2587 | { | |
2588 | struct drm_device *dev = rdev->ddev; | |
2589 | bool force_dac2 = false; | |
2590 | u32 tmp; | |
f5c5f040 | 2591 | |
0242f74d AD |
2592 | /* set these so they don't interfere with anything */ |
2593 | WREG32(RADEON_OV0_SCALE_CNTL, 0); | |
2594 | WREG32(RADEON_SUBPIC_CNTL, 0); | |
2595 | WREG32(RADEON_VIPH_CONTROL, 0); | |
2596 | WREG32(RADEON_I2C_CNTL_1, 0); | |
2597 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); | |
2598 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); | |
2599 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); | |
f5c5f040 | 2600 | |
0242f74d AD |
2601 | /* always set up dac2 on rn50 and some rv100 as lots |
2602 | * of servers seem to wire it up to a VGA port but | |
2603 | * don't report it in the bios connector | |
2604 | * table. | |
2605 | */ | |
2606 | switch (dev->pdev->device) { | |
2607 | /* RN50 */ | |
2608 | case 0x515e: | |
2609 | case 0x5969: | |
2610 | force_dac2 = true; | |
2611 | break; | |
2612 | /* RV100*/ | |
2613 | case 0x5159: | |
2614 | case 0x515a: | |
2615 | /* DELL triple head servers */ | |
2616 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && | |
2617 | ((dev->pdev->subsystem_device == 0x016c) || | |
2618 | (dev->pdev->subsystem_device == 0x016d) || | |
2619 | (dev->pdev->subsystem_device == 0x016e) || | |
2620 | (dev->pdev->subsystem_device == 0x016f) || | |
2621 | (dev->pdev->subsystem_device == 0x0170) || | |
2622 | (dev->pdev->subsystem_device == 0x017d) || | |
2623 | (dev->pdev->subsystem_device == 0x017e) || | |
2624 | (dev->pdev->subsystem_device == 0x0183) || | |
2625 | (dev->pdev->subsystem_device == 0x018a) || | |
2626 | (dev->pdev->subsystem_device == 0x019a))) | |
2627 | force_dac2 = true; | |
2628 | break; | |
2629 | } | |
f5c5f040 | 2630 | |
0242f74d AD |
2631 | if (force_dac2) { |
2632 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); | |
2633 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); | |
2634 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
e024e110 | 2635 | |
0242f74d AD |
2636 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
2637 | enable it, even it's detected. | |
2638 | */ | |
c93bb85b | 2639 | |
0242f74d AD |
2640 | /* force it to crtc0 */ |
2641 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; | |
2642 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; | |
2643 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; | |
c93bb85b | 2644 | |
0242f74d AD |
2645 | /* set up the TV DAC */ |
2646 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | | |
2647 | RADEON_TV_DAC_STD_MASK | | |
2648 | RADEON_TV_DAC_RDACPD | | |
2649 | RADEON_TV_DAC_GDACPD | | |
2650 | RADEON_TV_DAC_BDACPD | | |
2651 | RADEON_TV_DAC_BGADJ_MASK | | |
2652 | RADEON_TV_DAC_DACADJ_MASK); | |
2653 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | | |
2654 | RADEON_TV_DAC_NHOLD | | |
2655 | RADEON_TV_DAC_STD_PS2 | | |
2656 | (0x58 << 16)); | |
f46c0120 | 2657 | |
0242f74d AD |
2658 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
2659 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); | |
2660 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
c93bb85b | 2661 | } |
0242f74d AD |
2662 | |
2663 | /* switch PM block to ACPI mode */ | |
2664 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); | |
2665 | tmp &= ~RADEON_PM_MODE_SEL; | |
2666 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); | |
2667 | ||
2668 | } | |
2669 | ||
2670 | /* | |
2671 | * VRAM info | |
2672 | */ | |
2673 | static void r100_vram_get_type(struct radeon_device *rdev) | |
2674 | { | |
2675 | uint32_t tmp; | |
2676 | ||
2677 | rdev->mc.vram_is_ddr = false; | |
2678 | if (rdev->flags & RADEON_IS_IGP) | |
2679 | rdev->mc.vram_is_ddr = true; | |
2680 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) | |
2681 | rdev->mc.vram_is_ddr = true; | |
2682 | if ((rdev->family == CHIP_RV100) || | |
2683 | (rdev->family == CHIP_RS100) || | |
2684 | (rdev->family == CHIP_RS200)) { | |
2685 | tmp = RREG32(RADEON_MEM_CNTL); | |
2686 | if (tmp & RV100_HALF_MODE) { | |
2687 | rdev->mc.vram_width = 32; | |
2688 | } else { | |
2689 | rdev->mc.vram_width = 64; | |
2690 | } | |
2691 | if (rdev->flags & RADEON_SINGLE_CRTC) { | |
2692 | rdev->mc.vram_width /= 4; | |
2693 | rdev->mc.vram_is_ddr = true; | |
dfee5614 | 2694 | } |
0242f74d AD |
2695 | } else if (rdev->family <= CHIP_RV280) { |
2696 | tmp = RREG32(RADEON_MEM_CNTL); | |
2697 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { | |
2698 | rdev->mc.vram_width = 128; | |
2699 | } else { | |
2700 | rdev->mc.vram_width = 64; | |
2701 | } | |
2702 | } else { | |
2703 | /* newer IGPs */ | |
2704 | rdev->mc.vram_width = 128; | |
c93bb85b | 2705 | } |
0242f74d | 2706 | } |
c93bb85b | 2707 | |
0242f74d AD |
2708 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
2709 | { | |
2710 | u32 aper_size; | |
2711 | u8 byte; | |
2712 | ||
2713 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | |
2714 | ||
2715 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, | |
2716 | * that is has the 2nd generation multifunction PCI interface | |
2717 | */ | |
2718 | if (rdev->family == CHIP_RV280 || | |
2719 | rdev->family >= CHIP_RV350) { | |
2720 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, | |
2721 | ~RADEON_HDP_APER_CNTL); | |
2722 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); | |
2723 | return aper_size * 2; | |
c93bb85b JG |
2724 | } |
2725 | ||
0242f74d AD |
2726 | /* Older cards have all sorts of funny issues to deal with. First |
2727 | * check if it's a multifunction card by reading the PCI config | |
2728 | * header type... Limit those to one aperture size | |
c93bb85b | 2729 | */ |
0242f74d AD |
2730 | pci_read_config_byte(rdev->pdev, 0xe, &byte); |
2731 | if (byte & 0x80) { | |
2732 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); | |
2733 | DRM_INFO("Limiting VRAM to one aperture\n"); | |
2734 | return aper_size; | |
2735 | } | |
c93bb85b | 2736 | |
0242f74d AD |
2737 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
2738 | * have set it up. We don't write this as it's broken on some ASICs but | |
2739 | * we expect the BIOS to have done the right thing (might be too optimistic...) | |
2740 | */ | |
2741 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) | |
2742 | return aper_size * 2; | |
2743 | return aper_size; | |
2744 | } | |
c93bb85b | 2745 | |
0242f74d AD |
2746 | void r100_vram_init_sizes(struct radeon_device *rdev) |
2747 | { | |
2748 | u64 config_aper_size; | |
c93bb85b | 2749 | |
0242f74d AD |
2750 | /* work out accessible VRAM */ |
2751 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); | |
2752 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
2753 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); | |
2754 | /* FIXME we don't use the second aperture yet when we could use it */ | |
2755 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) | |
2756 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | |
2757 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | |
2758 | if (rdev->flags & RADEON_IS_IGP) { | |
2759 | uint32_t tom; | |
2760 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | |
2761 | tom = RREG32(RADEON_NB_TOM); | |
2762 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); | |
2763 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
2764 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
2765 | } else { | |
2766 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | |
2767 | /* Some production boards of m6 will report 0 | |
2768 | * if it's 8 MB | |
2769 | */ | |
2770 | if (rdev->mc.real_vram_size == 0) { | |
2771 | rdev->mc.real_vram_size = 8192 * 1024; | |
2772 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
2773 | } | |
2774 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - | |
2775 | * Novell bug 204882 + along with lots of ubuntu ones | |
2776 | */ | |
2777 | if (rdev->mc.aper_size > config_aper_size) | |
2778 | config_aper_size = rdev->mc.aper_size; | |
2779 | ||
2780 | if (config_aper_size > rdev->mc.real_vram_size) | |
2781 | rdev->mc.mc_vram_size = config_aper_size; | |
2782 | else | |
2783 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
c93bb85b | 2784 | } |
0242f74d | 2785 | } |
c93bb85b | 2786 | |
0242f74d AD |
2787 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2788 | { | |
2789 | uint32_t temp; | |
2790 | ||
2791 | temp = RREG32(RADEON_CONFIG_CNTL); | |
2792 | if (state == false) { | |
2793 | temp &= ~RADEON_CFG_VGA_RAM_EN; | |
2794 | temp |= RADEON_CFG_VGA_IO_DIS; | |
2795 | } else { | |
2796 | temp &= ~RADEON_CFG_VGA_IO_DIS; | |
c93bb85b | 2797 | } |
0242f74d AD |
2798 | WREG32(RADEON_CONFIG_CNTL, temp); |
2799 | } | |
c93bb85b | 2800 | |
1109ca09 | 2801 | static void r100_mc_init(struct radeon_device *rdev) |
0242f74d AD |
2802 | { |
2803 | u64 base; | |
c93bb85b | 2804 | |
0242f74d AD |
2805 | r100_vram_get_type(rdev); |
2806 | r100_vram_init_sizes(rdev); | |
2807 | base = rdev->mc.aper_base; | |
2808 | if (rdev->flags & RADEON_IS_IGP) | |
2809 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
2810 | radeon_vram_location(rdev, &rdev->mc, base); | |
2811 | rdev->mc.gtt_base_align = 0; | |
2812 | if (!(rdev->flags & RADEON_IS_AGP)) | |
2813 | radeon_gtt_location(rdev, &rdev->mc); | |
2814 | radeon_update_bandwidth_info(rdev); | |
2815 | } | |
2816 | ||
2817 | ||
2818 | /* | |
2819 | * Indirect registers accessor | |
2820 | */ | |
2821 | void r100_pll_errata_after_index(struct radeon_device *rdev) | |
2822 | { | |
2823 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { | |
2824 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); | |
2825 | (void)RREG32(RADEON_CRTC_GEN_CNTL); | |
c93bb85b | 2826 | } |
0242f74d | 2827 | } |
c93bb85b | 2828 | |
0242f74d AD |
2829 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
2830 | { | |
2831 | /* This workarounds is necessary on RV100, RS100 and RS200 chips | |
2832 | * or the chip could hang on a subsequent access | |
2833 | */ | |
2834 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { | |
2835 | mdelay(5); | |
c93bb85b JG |
2836 | } |
2837 | ||
0242f74d AD |
2838 | /* This function is required to workaround a hardware bug in some (all?) |
2839 | * revisions of the R300. This workaround should be called after every | |
2840 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward | |
2841 | * may not be correct. | |
2842 | */ | |
2843 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { | |
2844 | uint32_t save, tmp; | |
c93bb85b | 2845 | |
0242f74d AD |
2846 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
2847 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); | |
2848 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); | |
2849 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2850 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); | |
c93bb85b | 2851 | } |
0242f74d | 2852 | } |
c93bb85b | 2853 | |
0242f74d AD |
2854 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
2855 | { | |
2856 | uint32_t data; | |
c93bb85b | 2857 | |
0242f74d AD |
2858 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
2859 | r100_pll_errata_after_index(rdev); | |
2860 | data = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2861 | r100_pll_errata_after_data(rdev); | |
2862 | return data; | |
2863 | } | |
c93bb85b | 2864 | |
0242f74d AD |
2865 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
2866 | { | |
2867 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); | |
2868 | r100_pll_errata_after_index(rdev); | |
2869 | WREG32(RADEON_CLOCK_CNTL_DATA, v); | |
2870 | r100_pll_errata_after_data(rdev); | |
2871 | } | |
2872 | ||
1109ca09 | 2873 | static void r100_set_safe_registers(struct radeon_device *rdev) |
0242f74d AD |
2874 | { |
2875 | if (ASIC_IS_RN50(rdev)) { | |
2876 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; | |
2877 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); | |
2878 | } else if (rdev->family < CHIP_R200) { | |
2879 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; | |
2880 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); | |
c93bb85b | 2881 | } else { |
0242f74d | 2882 | r200_set_safe_registers(rdev); |
c93bb85b | 2883 | } |
0242f74d | 2884 | } |
c93bb85b | 2885 | |
0242f74d AD |
2886 | /* |
2887 | * Debugfs info | |
2888 | */ | |
2889 | #if defined(CONFIG_DEBUG_FS) | |
2890 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) | |
2891 | { | |
2892 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2893 | struct drm_device *dev = node->minor->dev; | |
2894 | struct radeon_device *rdev = dev->dev_private; | |
2895 | uint32_t reg, value; | |
2896 | unsigned i; | |
c93bb85b | 2897 | |
0242f74d AD |
2898 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
2899 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); | |
2900 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2901 | for (i = 0; i < 64; i++) { | |
2902 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); | |
2903 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; | |
2904 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); | |
2905 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); | |
2906 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); | |
2907 | } | |
2908 | return 0; | |
2909 | } | |
c93bb85b | 2910 | |
0242f74d AD |
2911 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
2912 | { | |
2913 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2914 | struct drm_device *dev = node->minor->dev; | |
2915 | struct radeon_device *rdev = dev->dev_private; | |
2916 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
2917 | uint32_t rdp, wdp; | |
2918 | unsigned count, i, j; | |
c93bb85b | 2919 | |
0242f74d AD |
2920 | radeon_ring_free_size(rdev, ring); |
2921 | rdp = RREG32(RADEON_CP_RB_RPTR); | |
2922 | wdp = RREG32(RADEON_CP_RB_WPTR); | |
2923 | count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; | |
2924 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2925 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); | |
2926 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); | |
2927 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | |
2928 | seq_printf(m, "%u dwords in ring\n", count); | |
2929 | for (j = 0; j <= count; j++) { | |
2930 | i = (rdp + j) & ring->ptr_mask; | |
2931 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); | |
2932 | } | |
2933 | return 0; | |
2934 | } | |
c93bb85b | 2935 | |
c93bb85b | 2936 | |
0242f74d AD |
2937 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
2938 | { | |
2939 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2940 | struct drm_device *dev = node->minor->dev; | |
2941 | struct radeon_device *rdev = dev->dev_private; | |
2942 | uint32_t csq_stat, csq2_stat, tmp; | |
2943 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; | |
2944 | unsigned i; | |
c93bb85b | 2945 | |
0242f74d AD |
2946 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2947 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); | |
2948 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); | |
2949 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); | |
2950 | r_rptr = (csq_stat >> 0) & 0x3ff; | |
2951 | r_wptr = (csq_stat >> 10) & 0x3ff; | |
2952 | ib1_rptr = (csq_stat >> 20) & 0x3ff; | |
2953 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; | |
2954 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; | |
2955 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; | |
2956 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); | |
2957 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); | |
2958 | seq_printf(m, "Ring rptr %u\n", r_rptr); | |
2959 | seq_printf(m, "Ring wptr %u\n", r_wptr); | |
2960 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); | |
2961 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); | |
2962 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); | |
2963 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); | |
2964 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms | |
2965 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ | |
2966 | seq_printf(m, "Ring fifo:\n"); | |
2967 | for (i = 0; i < 256; i++) { | |
2968 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2969 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2970 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); | |
2971 | } | |
2972 | seq_printf(m, "Indirect1 fifo:\n"); | |
2973 | for (i = 256; i <= 512; i++) { | |
2974 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2975 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2976 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); | |
2977 | } | |
2978 | seq_printf(m, "Indirect2 fifo:\n"); | |
2979 | for (i = 640; i < ib1_wptr; i++) { | |
2980 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2981 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2982 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); | |
2983 | } | |
2984 | return 0; | |
2985 | } | |
2986 | ||
2987 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) | |
2988 | { | |
2989 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2990 | struct drm_device *dev = node->minor->dev; | |
2991 | struct radeon_device *rdev = dev->dev_private; | |
2992 | uint32_t tmp; | |
c93bb85b | 2993 | |
0242f74d AD |
2994 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
2995 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); | |
2996 | tmp = RREG32(RADEON_MC_FB_LOCATION); | |
2997 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); | |
2998 | tmp = RREG32(RADEON_BUS_CNTL); | |
2999 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); | |
3000 | tmp = RREG32(RADEON_MC_AGP_LOCATION); | |
3001 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); | |
3002 | tmp = RREG32(RADEON_AGP_BASE); | |
3003 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); | |
3004 | tmp = RREG32(RADEON_HOST_PATH_CNTL); | |
3005 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); | |
3006 | tmp = RREG32(0x01D0); | |
3007 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); | |
3008 | tmp = RREG32(RADEON_AIC_LO_ADDR); | |
3009 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); | |
3010 | tmp = RREG32(RADEON_AIC_HI_ADDR); | |
3011 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); | |
3012 | tmp = RREG32(0x01E4); | |
3013 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); | |
3014 | return 0; | |
3015 | } | |
c93bb85b | 3016 | |
0242f74d AD |
3017 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
3018 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, | |
3019 | }; | |
c93bb85b | 3020 | |
0242f74d AD |
3021 | static struct drm_info_list r100_debugfs_cp_list[] = { |
3022 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, | |
3023 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, | |
3024 | }; | |
c93bb85b | 3025 | |
0242f74d AD |
3026 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
3027 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, | |
3028 | }; | |
3029 | #endif | |
c93bb85b | 3030 | |
0242f74d AD |
3031 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
3032 | { | |
3033 | #if defined(CONFIG_DEBUG_FS) | |
3034 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); | |
3035 | #else | |
3036 | return 0; | |
3037 | #endif | |
3038 | } | |
c93bb85b | 3039 | |
0242f74d AD |
3040 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
3041 | { | |
3042 | #if defined(CONFIG_DEBUG_FS) | |
3043 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); | |
3044 | #else | |
3045 | return 0; | |
3046 | #endif | |
3047 | } | |
c93bb85b | 3048 | |
0242f74d AD |
3049 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
3050 | { | |
3051 | #if defined(CONFIG_DEBUG_FS) | |
3052 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); | |
3053 | #else | |
3054 | return 0; | |
3055 | #endif | |
3056 | } | |
c93bb85b | 3057 | |
0242f74d AD |
3058 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
3059 | uint32_t tiling_flags, uint32_t pitch, | |
3060 | uint32_t offset, uint32_t obj_size) | |
3061 | { | |
3062 | int surf_index = reg * 16; | |
3063 | int flags = 0; | |
c93bb85b | 3064 | |
0242f74d AD |
3065 | if (rdev->family <= CHIP_RS200) { |
3066 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
3067 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
3068 | flags |= RADEON_SURF_TILE_COLOR_BOTH; | |
3069 | if (tiling_flags & RADEON_TILING_MACRO) | |
3070 | flags |= RADEON_SURF_TILE_COLOR_MACRO; | |
67d5ced5 AD |
3071 | /* setting pitch to 0 disables tiling */ |
3072 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
3073 | == 0) | |
3074 | pitch = 0; | |
0242f74d AD |
3075 | } else if (rdev->family <= CHIP_RV280) { |
3076 | if (tiling_flags & (RADEON_TILING_MACRO)) | |
3077 | flags |= R200_SURF_TILE_COLOR_MACRO; | |
3078 | if (tiling_flags & RADEON_TILING_MICRO) | |
3079 | flags |= R200_SURF_TILE_COLOR_MICRO; | |
3080 | } else { | |
3081 | if (tiling_flags & RADEON_TILING_MACRO) | |
3082 | flags |= R300_SURF_TILE_MACRO; | |
3083 | if (tiling_flags & RADEON_TILING_MICRO) | |
3084 | flags |= R300_SURF_TILE_MICRO; | |
3085 | } | |
c93bb85b | 3086 | |
0242f74d AD |
3087 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
3088 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; | |
3089 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) | |
3090 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; | |
3091 | ||
0242f74d AD |
3092 | /* r100/r200 divide by 16 */ |
3093 | if (rdev->family < CHIP_R300) | |
3094 | flags |= pitch / 16; | |
3095 | else | |
3096 | flags |= pitch / 8; | |
c93bb85b | 3097 | |
c93bb85b | 3098 | |
0242f74d AD |
3099 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
3100 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); | |
3101 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); | |
3102 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); | |
3103 | return 0; | |
3104 | } | |
c93bb85b | 3105 | |
0242f74d AD |
3106 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
3107 | { | |
3108 | int surf_index = reg * 16; | |
3109 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); | |
3110 | } | |
c93bb85b | 3111 | |
0242f74d AD |
3112 | void r100_bandwidth_update(struct radeon_device *rdev) |
3113 | { | |
3114 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; | |
3115 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; | |
3116 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | |
3117 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | |
3118 | fixed20_12 memtcas_ff[8] = { | |
3119 | dfixed_init(1), | |
3120 | dfixed_init(2), | |
3121 | dfixed_init(3), | |
3122 | dfixed_init(0), | |
3123 | dfixed_init_half(1), | |
3124 | dfixed_init_half(2), | |
3125 | dfixed_init(0), | |
3126 | }; | |
3127 | fixed20_12 memtcas_rs480_ff[8] = { | |
3128 | dfixed_init(0), | |
3129 | dfixed_init(1), | |
3130 | dfixed_init(2), | |
3131 | dfixed_init(3), | |
3132 | dfixed_init(0), | |
3133 | dfixed_init_half(1), | |
3134 | dfixed_init_half(2), | |
3135 | dfixed_init_half(3), | |
3136 | }; | |
3137 | fixed20_12 memtcas2_ff[8] = { | |
3138 | dfixed_init(0), | |
3139 | dfixed_init(1), | |
3140 | dfixed_init(2), | |
3141 | dfixed_init(3), | |
3142 | dfixed_init(4), | |
3143 | dfixed_init(5), | |
3144 | dfixed_init(6), | |
3145 | dfixed_init(7), | |
3146 | }; | |
3147 | fixed20_12 memtrbs[8] = { | |
3148 | dfixed_init(1), | |
3149 | dfixed_init_half(1), | |
3150 | dfixed_init(2), | |
3151 | dfixed_init_half(2), | |
3152 | dfixed_init(3), | |
3153 | dfixed_init_half(3), | |
3154 | dfixed_init(4), | |
3155 | dfixed_init_half(4) | |
3156 | }; | |
3157 | fixed20_12 memtrbs_r4xx[8] = { | |
3158 | dfixed_init(4), | |
3159 | dfixed_init(5), | |
3160 | dfixed_init(6), | |
3161 | dfixed_init(7), | |
3162 | dfixed_init(8), | |
3163 | dfixed_init(9), | |
3164 | dfixed_init(10), | |
3165 | dfixed_init(11) | |
3166 | }; | |
3167 | fixed20_12 min_mem_eff; | |
3168 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | |
3169 | fixed20_12 cur_latency_mclk, cur_latency_sclk; | |
3170 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, | |
3171 | disp_drain_rate2, read_return_rate; | |
3172 | fixed20_12 time_disp1_drop_priority; | |
3173 | int c; | |
3174 | int cur_size = 16; /* in octawords */ | |
3175 | int critical_point = 0, critical_point2; | |
3176 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ | |
3177 | int stop_req, max_stop_req; | |
3178 | struct drm_display_mode *mode1 = NULL; | |
3179 | struct drm_display_mode *mode2 = NULL; | |
3180 | uint32_t pixel_bytes1 = 0; | |
3181 | uint32_t pixel_bytes2 = 0; | |
c93bb85b | 3182 | |
0242f74d | 3183 | radeon_update_display_priority(rdev); |
c93bb85b | 3184 | |
0242f74d AD |
3185 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
3186 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; | |
3187 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; | |
3188 | } | |
3189 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3190 | if (rdev->mode_info.crtcs[1]->base.enabled) { | |
3191 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; | |
3192 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; | |
3193 | } | |
3194 | } | |
c93bb85b | 3195 | |
0242f74d AD |
3196 | min_mem_eff.full = dfixed_const_8(0); |
3197 | /* get modes */ | |
3198 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | |
3199 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | |
3200 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
3201 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
3202 | /* check crtc enables */ | |
3203 | if (mode2) | |
3204 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
3205 | if (mode1) | |
3206 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
3207 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); | |
3208 | } | |
c93bb85b | 3209 | |
0242f74d AD |
3210 | /* |
3211 | * determine is there is enough bw for current mode | |
3212 | */ | |
3213 | sclk_ff = rdev->pm.sclk; | |
3214 | mclk_ff = rdev->pm.mclk; | |
c93bb85b | 3215 | |
0242f74d AD |
3216 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
3217 | temp_ff.full = dfixed_const(temp); | |
3218 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); | |
c93bb85b | 3219 | |
0242f74d AD |
3220 | pix_clk.full = 0; |
3221 | pix_clk2.full = 0; | |
3222 | peak_disp_bw.full = 0; | |
3223 | if (mode1) { | |
3224 | temp_ff.full = dfixed_const(1000); | |
3225 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ | |
3226 | pix_clk.full = dfixed_div(pix_clk, temp_ff); | |
3227 | temp_ff.full = dfixed_const(pixel_bytes1); | |
3228 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); | |
3229 | } | |
3230 | if (mode2) { | |
3231 | temp_ff.full = dfixed_const(1000); | |
3232 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ | |
3233 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); | |
3234 | temp_ff.full = dfixed_const(pixel_bytes2); | |
3235 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); | |
3236 | } | |
c93bb85b | 3237 | |
0242f74d AD |
3238 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
3239 | if (peak_disp_bw.full >= mem_bw.full) { | |
3240 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | |
3241 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | |
3242 | } | |
c93bb85b | 3243 | |
0242f74d AD |
3244 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
3245 | temp = RREG32(RADEON_MEM_TIMING_CNTL); | |
3246 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ | |
3247 | mem_trcd = ((temp >> 2) & 0x3) + 1; | |
3248 | mem_trp = ((temp & 0x3)) + 1; | |
3249 | mem_tras = ((temp & 0x70) >> 4) + 1; | |
3250 | } else if (rdev->family == CHIP_R300 || | |
3251 | rdev->family == CHIP_R350) { /* r300, r350 */ | |
3252 | mem_trcd = (temp & 0x7) + 1; | |
3253 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
3254 | mem_tras = ((temp >> 11) & 0xf) + 4; | |
3255 | } else if (rdev->family == CHIP_RV350 || | |
3256 | rdev->family <= CHIP_RV380) { | |
3257 | /* rv3x0 */ | |
3258 | mem_trcd = (temp & 0x7) + 3; | |
3259 | mem_trp = ((temp >> 8) & 0x7) + 3; | |
3260 | mem_tras = ((temp >> 11) & 0xf) + 6; | |
3261 | } else if (rdev->family == CHIP_R420 || | |
3262 | rdev->family == CHIP_R423 || | |
3263 | rdev->family == CHIP_RV410) { | |
3264 | /* r4xx */ | |
3265 | mem_trcd = (temp & 0xf) + 3; | |
3266 | if (mem_trcd > 15) | |
3267 | mem_trcd = 15; | |
3268 | mem_trp = ((temp >> 8) & 0xf) + 3; | |
3269 | if (mem_trp > 15) | |
3270 | mem_trp = 15; | |
3271 | mem_tras = ((temp >> 12) & 0x1f) + 6; | |
3272 | if (mem_tras > 31) | |
3273 | mem_tras = 31; | |
3274 | } else { /* RV200, R200 */ | |
3275 | mem_trcd = (temp & 0x7) + 1; | |
3276 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
3277 | mem_tras = ((temp >> 12) & 0xf) + 4; | |
3278 | } | |
3279 | /* convert to FF */ | |
3280 | trcd_ff.full = dfixed_const(mem_trcd); | |
3281 | trp_ff.full = dfixed_const(mem_trp); | |
3282 | tras_ff.full = dfixed_const(mem_tras); | |
c93bb85b | 3283 | |
0242f74d AD |
3284 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
3285 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | |
3286 | data = (temp & (7 << 20)) >> 20; | |
3287 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { | |
3288 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ | |
3289 | tcas_ff = memtcas_rs480_ff[data]; | |
3290 | else | |
3291 | tcas_ff = memtcas_ff[data]; | |
3292 | } else | |
3293 | tcas_ff = memtcas2_ff[data]; | |
c93bb85b | 3294 | |
0242f74d AD |
3295 | if (rdev->family == CHIP_RS400 || |
3296 | rdev->family == CHIP_RS480) { | |
3297 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | |
3298 | data = (temp >> 23) & 0x7; | |
3299 | if (data < 5) | |
3300 | tcas_ff.full += dfixed_const(data); | |
c93bb85b | 3301 | } |
551ebd83 | 3302 | |
0242f74d AD |
3303 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
3304 | /* on the R300, Tcas is included in Trbs. | |
3305 | */ | |
3306 | temp = RREG32(RADEON_MEM_CNTL); | |
3307 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); | |
3308 | if (data == 1) { | |
3309 | if (R300_MEM_USE_CD_CH_ONLY & temp) { | |
3310 | temp = RREG32(R300_MC_IND_INDEX); | |
3311 | temp &= ~R300_MC_IND_ADDR_MASK; | |
3312 | temp |= R300_MC_READ_CNTL_CD_mcind; | |
3313 | WREG32(R300_MC_IND_INDEX, temp); | |
3314 | temp = RREG32(R300_MC_IND_DATA); | |
3315 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); | |
3316 | } else { | |
3317 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
3318 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
3319 | } | |
3320 | } else { | |
3321 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
3322 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
3323 | } | |
3324 | if (rdev->family == CHIP_RV410 || | |
3325 | rdev->family == CHIP_R420 || | |
3326 | rdev->family == CHIP_R423) | |
3327 | trbs_ff = memtrbs_r4xx[data]; | |
3328 | else | |
3329 | trbs_ff = memtrbs[data]; | |
3330 | tcas_ff.full += trbs_ff.full; | |
3331 | } | |
551ebd83 | 3332 | |
0242f74d | 3333 | sclk_eff_ff.full = sclk_ff.full; |
d785d78b | 3334 | |
0242f74d AD |
3335 | if (rdev->flags & RADEON_IS_AGP) { |
3336 | fixed20_12 agpmode_ff; | |
3337 | agpmode_ff.full = dfixed_const(radeon_agpmode); | |
3338 | temp_ff.full = dfixed_const_666(16); | |
3339 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); | |
3340 | } | |
3341 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | |
d785d78b | 3342 | |
0242f74d AD |
3343 | if (ASIC_IS_R300(rdev)) { |
3344 | sclk_delay_ff.full = dfixed_const(250); | |
3345 | } else { | |
3346 | if ((rdev->family == CHIP_RV100) || | |
3347 | rdev->flags & RADEON_IS_IGP) { | |
3348 | if (rdev->mc.vram_is_ddr) | |
3349 | sclk_delay_ff.full = dfixed_const(41); | |
3350 | else | |
3351 | sclk_delay_ff.full = dfixed_const(33); | |
3352 | } else { | |
3353 | if (rdev->mc.vram_width == 128) | |
3354 | sclk_delay_ff.full = dfixed_const(57); | |
3355 | else | |
3356 | sclk_delay_ff.full = dfixed_const(41); | |
3357 | } | |
d785d78b DA |
3358 | } |
3359 | ||
0242f74d | 3360 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
d785d78b | 3361 | |
0242f74d AD |
3362 | if (rdev->mc.vram_is_ddr) { |
3363 | if (rdev->mc.vram_width == 32) { | |
3364 | k1.full = dfixed_const(40); | |
3365 | c = 3; | |
3366 | } else { | |
3367 | k1.full = dfixed_const(20); | |
3368 | c = 1; | |
3369 | } | |
3370 | } else { | |
3371 | k1.full = dfixed_const(40); | |
3372 | c = 3; | |
3373 | } | |
37cf6b03 | 3374 | |
0242f74d AD |
3375 | temp_ff.full = dfixed_const(2); |
3376 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); | |
3377 | temp_ff.full = dfixed_const(c); | |
3378 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); | |
3379 | temp_ff.full = dfixed_const(4); | |
3380 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); | |
3381 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); | |
3382 | mc_latency_mclk.full += k1.full; | |
37cf6b03 | 3383 | |
0242f74d AD |
3384 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
3385 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); | |
37cf6b03 | 3386 | |
0242f74d AD |
3387 | /* |
3388 | HW cursor time assuming worst case of full size colour cursor. | |
3389 | */ | |
3390 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | |
3391 | temp_ff.full += trcd_ff.full; | |
3392 | if (temp_ff.full < tras_ff.full) | |
3393 | temp_ff.full = tras_ff.full; | |
3394 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); | |
37cf6b03 | 3395 | |
0242f74d AD |
3396 | temp_ff.full = dfixed_const(cur_size); |
3397 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); | |
3398 | /* | |
3399 | Find the total latency for the display data. | |
3400 | */ | |
3401 | disp_latency_overhead.full = dfixed_const(8); | |
3402 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); | |
3403 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; | |
3404 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | |
37cf6b03 | 3405 | |
0242f74d AD |
3406 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
3407 | disp_latency.full = mc_latency_mclk.full; | |
3408 | else | |
3409 | disp_latency.full = mc_latency_sclk.full; | |
551ebd83 | 3410 | |
0242f74d AD |
3411 | /* setup Max GRPH_STOP_REQ default value */ |
3412 | if (ASIC_IS_RV100(rdev)) | |
3413 | max_stop_req = 0x5c; | |
3414 | else | |
3415 | max_stop_req = 0x7c; | |
d785d78b | 3416 | |
0242f74d AD |
3417 | if (mode1) { |
3418 | /* CRTC1 | |
3419 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. | |
3420 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] | |
3421 | */ | |
3422 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; | |
d785d78b | 3423 | |
0242f74d AD |
3424 | if (stop_req > max_stop_req) |
3425 | stop_req = max_stop_req; | |
551ebd83 | 3426 | |
0242f74d AD |
3427 | /* |
3428 | Find the drain rate of the display buffer. | |
3429 | */ | |
3430 | temp_ff.full = dfixed_const((16/pixel_bytes1)); | |
3431 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); | |
551ebd83 | 3432 | |
0242f74d AD |
3433 | /* |
3434 | Find the critical point of the display buffer. | |
3435 | */ | |
3436 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); | |
3437 | crit_point_ff.full += dfixed_const_half(0); | |
a41ceb1c | 3438 | |
0242f74d AD |
3439 | critical_point = dfixed_trunc(crit_point_ff); |
3440 | ||
3441 | if (rdev->disp_priority == 2) { | |
3442 | critical_point = 0; | |
551ebd83 | 3443 | } |
40b4a759 | 3444 | |
0242f74d AD |
3445 | /* |
3446 | The critical point should never be above max_stop_req-4. Setting | |
3447 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. | |
3448 | */ | |
3449 | if (max_stop_req - critical_point < 4) | |
3450 | critical_point = 0; | |
3451 | ||
3452 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { | |
3453 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ | |
3454 | critical_point = 0x10; | |
551ebd83 | 3455 | } |
0242f74d AD |
3456 | |
3457 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); | |
3458 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
3459 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
3460 | temp &= ~(RADEON_GRPH_START_REQ_MASK); | |
3461 | if ((rdev->family == CHIP_R350) && | |
3462 | (stop_req > 0x15)) { | |
3463 | stop_req -= 0x10; | |
551ebd83 | 3464 | } |
0242f74d AD |
3465 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3466 | temp |= RADEON_GRPH_BUFFER_SIZE; | |
3467 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
3468 | RADEON_GRPH_CRITICAL_AT_SOF | | |
3469 | RADEON_GRPH_STOP_CNTL); | |
3470 | /* | |
3471 | Write the result into the register. | |
3472 | */ | |
3473 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | |
3474 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
40b4a759 | 3475 | |
0242f74d AD |
3476 | #if 0 |
3477 | if ((rdev->family == CHIP_RS400) || | |
3478 | (rdev->family == CHIP_RS480)) { | |
3479 | /* attempt to program RS400 disp regs correctly ??? */ | |
3480 | temp = RREG32(RS400_DISP1_REG_CNTL); | |
3481 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | | |
3482 | RS400_DISP1_STOP_REQ_LEVEL_MASK); | |
3483 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | | |
3484 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
3485 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
3486 | temp = RREG32(RS400_DMIF_MEM_CNTL1); | |
3487 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | | |
3488 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); | |
3489 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | | |
3490 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | | |
3491 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); | |
fff1ce4d | 3492 | } |
0242f74d | 3493 | #endif |
fff1ce4d | 3494 | |
0242f74d AD |
3495 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
3496 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | |
3497 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | |
cae94b0a | 3498 | } |
0242f74d AD |
3499 | |
3500 | if (mode2) { | |
3501 | u32 grph2_cntl; | |
3502 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; | |
3503 | ||
3504 | if (stop_req > max_stop_req) | |
3505 | stop_req = max_stop_req; | |
3506 | ||
3507 | /* | |
3508 | Find the drain rate of the display buffer. | |
3509 | */ | |
3510 | temp_ff.full = dfixed_const((16/pixel_bytes2)); | |
3511 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); | |
3512 | ||
3513 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | |
3514 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
3515 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
3516 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); | |
3517 | if ((rdev->family == CHIP_R350) && | |
3518 | (stop_req > 0x15)) { | |
3519 | stop_req -= 0x10; | |
551ebd83 | 3520 | } |
0242f74d AD |
3521 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
3522 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; | |
3523 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
3524 | RADEON_GRPH_CRITICAL_AT_SOF | | |
3525 | RADEON_GRPH_STOP_CNTL); | |
3526 | ||
3527 | if ((rdev->family == CHIP_RS100) || | |
3528 | (rdev->family == CHIP_RS200)) | |
3529 | critical_point2 = 0; | |
3530 | else { | |
3531 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | |
3532 | temp_ff.full = dfixed_const(temp); | |
3533 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); | |
3534 | if (sclk_ff.full < temp_ff.full) | |
3535 | temp_ff.full = sclk_ff.full; | |
3536 | ||
3537 | read_return_rate.full = temp_ff.full; | |
3538 | ||
3539 | if (mode1) { | |
3540 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | |
3541 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); | |
3542 | } else { | |
3543 | time_disp1_drop_priority.full = 0; | |
551ebd83 | 3544 | } |
0242f74d AD |
3545 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
3546 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); | |
3547 | crit_point_ff.full += dfixed_const_half(0); | |
3548 | ||
3549 | critical_point2 = dfixed_trunc(crit_point_ff); | |
3550 | ||
3551 | if (rdev->disp_priority == 2) { | |
3552 | critical_point2 = 0; | |
551ebd83 | 3553 | } |
40b4a759 | 3554 | |
0242f74d AD |
3555 | if (max_stop_req - critical_point2 < 4) |
3556 | critical_point2 = 0; | |
551ebd83 | 3557 | |
0242f74d | 3558 | } |
551ebd83 | 3559 | |
0242f74d AD |
3560 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
3561 | /* some R300 cards have problem with this set to 0 */ | |
3562 | critical_point2 = 0x10; | |
3563 | } | |
40b4a759 | 3564 | |
0242f74d AD |
3565 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
3566 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
551ebd83 | 3567 | |
0242f74d AD |
3568 | if ((rdev->family == CHIP_RS400) || |
3569 | (rdev->family == CHIP_RS480)) { | |
3570 | #if 0 | |
3571 | /* attempt to program RS400 disp2 regs correctly ??? */ | |
3572 | temp = RREG32(RS400_DISP2_REQ_CNTL1); | |
3573 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | | |
3574 | RS400_DISP2_STOP_REQ_LEVEL_MASK); | |
3575 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | | |
3576 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
3577 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
3578 | temp = RREG32(RS400_DISP2_REQ_CNTL2); | |
3579 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | | |
3580 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); | |
3581 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | | |
3582 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | | |
3583 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); | |
3584 | #endif | |
3585 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); | |
3586 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); | |
3587 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); | |
3588 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | |
551ebd83 | 3589 | } |
0242f74d AD |
3590 | |
3591 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", | |
3592 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | |
551ebd83 DA |
3593 | } |
3594 | } | |
3ce0a23d | 3595 | |
e32eb50d | 3596 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d JG |
3597 | { |
3598 | uint32_t scratch; | |
3599 | uint32_t tmp = 0; | |
3600 | unsigned i; | |
3601 | int r; | |
3602 | ||
3603 | r = radeon_scratch_get(rdev, &scratch); | |
3604 | if (r) { | |
3605 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
3606 | return r; | |
3607 | } | |
3608 | WREG32(scratch, 0xCAFEDEAD); | |
e32eb50d | 3609 | r = radeon_ring_lock(rdev, ring, 2); |
3ce0a23d JG |
3610 | if (r) { |
3611 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
3612 | radeon_scratch_free(rdev, scratch); | |
3613 | return r; | |
3614 | } | |
e32eb50d CK |
3615 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
3616 | radeon_ring_write(ring, 0xDEADBEEF); | |
3617 | radeon_ring_unlock_commit(rdev, ring); | |
3ce0a23d JG |
3618 | for (i = 0; i < rdev->usec_timeout; i++) { |
3619 | tmp = RREG32(scratch); | |
3620 | if (tmp == 0xDEADBEEF) { | |
3621 | break; | |
3622 | } | |
3623 | DRM_UDELAY(1); | |
3624 | } | |
3625 | if (i < rdev->usec_timeout) { | |
3626 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
3627 | } else { | |
369d7ec1 | 3628 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
3629 | scratch, tmp); |
3630 | r = -EINVAL; | |
3631 | } | |
3632 | radeon_scratch_free(rdev, scratch); | |
3633 | return r; | |
3634 | } | |
3635 | ||
3636 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
3637 | { | |
e32eb50d | 3638 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
7b1f2485 | 3639 | |
c7eff978 AD |
3640 | if (ring->rptr_save_reg) { |
3641 | u32 next_rptr = ring->wptr + 2 + 3; | |
3642 | radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); | |
3643 | radeon_ring_write(ring, next_rptr); | |
3644 | } | |
3645 | ||
e32eb50d CK |
3646 | radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); |
3647 | radeon_ring_write(ring, ib->gpu_addr); | |
3648 | radeon_ring_write(ring, ib->length_dw); | |
3ce0a23d JG |
3649 | } |
3650 | ||
f712812e | 3651 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d | 3652 | { |
f2e39221 | 3653 | struct radeon_ib ib; |
3ce0a23d JG |
3654 | uint32_t scratch; |
3655 | uint32_t tmp = 0; | |
3656 | unsigned i; | |
3657 | int r; | |
3658 | ||
3659 | r = radeon_scratch_get(rdev, &scratch); | |
3660 | if (r) { | |
3661 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
3662 | return r; | |
3663 | } | |
3664 | WREG32(scratch, 0xCAFEDEAD); | |
4bf3dd92 | 3665 | r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); |
3ce0a23d | 3666 | if (r) { |
af026c5b MD |
3667 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
3668 | goto free_scratch; | |
3ce0a23d | 3669 | } |
f2e39221 JG |
3670 | ib.ptr[0] = PACKET0(scratch, 0); |
3671 | ib.ptr[1] = 0xDEADBEEF; | |
3672 | ib.ptr[2] = PACKET2(0); | |
3673 | ib.ptr[3] = PACKET2(0); | |
3674 | ib.ptr[4] = PACKET2(0); | |
3675 | ib.ptr[5] = PACKET2(0); | |
3676 | ib.ptr[6] = PACKET2(0); | |
3677 | ib.ptr[7] = PACKET2(0); | |
3678 | ib.length_dw = 8; | |
4ef72566 | 3679 | r = radeon_ib_schedule(rdev, &ib, NULL); |
3ce0a23d | 3680 | if (r) { |
af026c5b MD |
3681 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3682 | goto free_ib; | |
3ce0a23d | 3683 | } |
f2e39221 | 3684 | r = radeon_fence_wait(ib.fence, false); |
3ce0a23d | 3685 | if (r) { |
af026c5b MD |
3686 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
3687 | goto free_ib; | |
3ce0a23d JG |
3688 | } |
3689 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3690 | tmp = RREG32(scratch); | |
3691 | if (tmp == 0xDEADBEEF) { | |
3692 | break; | |
3693 | } | |
3694 | DRM_UDELAY(1); | |
3695 | } | |
3696 | if (i < rdev->usec_timeout) { | |
3697 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
3698 | } else { | |
62f288cf | 3699 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
3700 | scratch, tmp); |
3701 | r = -EINVAL; | |
3702 | } | |
af026c5b | 3703 | free_ib: |
3ce0a23d | 3704 | radeon_ib_free(rdev, &ib); |
af026c5b MD |
3705 | free_scratch: |
3706 | radeon_scratch_free(rdev, scratch); | |
3ce0a23d JG |
3707 | return r; |
3708 | } | |
9f022ddf | 3709 | |
9f022ddf JG |
3710 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3711 | { | |
3712 | /* Shutdown CP we shouldn't need to do that but better be safe than | |
3713 | * sorry | |
3714 | */ | |
e32eb50d | 3715 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
9f022ddf JG |
3716 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
3717 | ||
3718 | /* Save few CRTC registers */ | |
ca6ffc64 | 3719 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
9f022ddf JG |
3720 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3721 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); | |
3722 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); | |
3723 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3724 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); | |
3725 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); | |
3726 | } | |
3727 | ||
3728 | /* Disable VGA aperture access */ | |
ca6ffc64 | 3729 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
9f022ddf JG |
3730 | /* Disable cursor, overlay, crtc */ |
3731 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); | |
3732 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | | |
3733 | S_000054_CRTC_DISPLAY_DIS(1)); | |
3734 | WREG32(R_000050_CRTC_GEN_CNTL, | |
3735 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | | |
3736 | S_000050_CRTC_DISP_REQ_EN_B(1)); | |
3737 | WREG32(R_000420_OV0_SCALE_CNTL, | |
3738 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); | |
3739 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); | |
3740 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3741 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | | |
3742 | S_000360_CUR2_LOCK(1)); | |
3743 | WREG32(R_0003F8_CRTC2_GEN_CNTL, | |
3744 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | | |
3745 | S_0003F8_CRTC2_DISPLAY_DIS(1) | | |
3746 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); | |
3747 | WREG32(R_000360_CUR2_OFFSET, | |
3748 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); | |
3749 | } | |
3750 | } | |
3751 | ||
3752 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) | |
3753 | { | |
3754 | /* Update base address for crtc */ | |
d594e46a | 3755 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf | 3756 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
d594e46a | 3757 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf JG |
3758 | } |
3759 | /* Restore CRTC registers */ | |
ca6ffc64 | 3760 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
9f022ddf JG |
3761 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3762 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); | |
3763 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3764 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); | |
3765 | } | |
3766 | } | |
ca6ffc64 JG |
3767 | |
3768 | void r100_vga_render_disable(struct radeon_device *rdev) | |
3769 | { | |
d4550907 | 3770 | u32 tmp; |
ca6ffc64 | 3771 | |
d4550907 | 3772 | tmp = RREG8(R_0003C2_GENMO_WT); |
ca6ffc64 JG |
3773 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
3774 | } | |
d4550907 JG |
3775 | |
3776 | static void r100_debugfs(struct radeon_device *rdev) | |
3777 | { | |
3778 | int r; | |
3779 | ||
3780 | r = r100_debugfs_mc_info_init(rdev); | |
3781 | if (r) | |
3782 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
3783 | } | |
3784 | ||
3785 | static void r100_mc_program(struct radeon_device *rdev) | |
3786 | { | |
3787 | struct r100_mc_save save; | |
3788 | ||
3789 | /* Stops all mc clients */ | |
3790 | r100_mc_stop(rdev, &save); | |
3791 | if (rdev->flags & RADEON_IS_AGP) { | |
3792 | WREG32(R_00014C_MC_AGP_LOCATION, | |
3793 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
3794 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
3795 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
3796 | if (rdev->family > CHIP_RV200) | |
3797 | WREG32(R_00015C_AGP_BASE_2, | |
3798 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
3799 | } else { | |
3800 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
3801 | WREG32(R_000170_AGP_BASE, 0); | |
3802 | if (rdev->family > CHIP_RV200) | |
3803 | WREG32(R_00015C_AGP_BASE_2, 0); | |
3804 | } | |
3805 | /* Wait for mc idle */ | |
3806 | if (r100_mc_wait_for_idle(rdev)) | |
3807 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); | |
3808 | /* Program MC, should be a 32bits limited address space */ | |
3809 | WREG32(R_000148_MC_FB_LOCATION, | |
3810 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
3811 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
3812 | r100_mc_resume(rdev, &save); | |
3813 | } | |
3814 | ||
1109ca09 | 3815 | static void r100_clock_startup(struct radeon_device *rdev) |
d4550907 JG |
3816 | { |
3817 | u32 tmp; | |
3818 | ||
3819 | if (radeon_dynclks != -1 && radeon_dynclks) | |
3820 | radeon_legacy_set_clock_gating(rdev, 1); | |
3821 | /* We need to force on some of the block */ | |
3822 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
3823 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
3824 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) | |
3825 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); | |
3826 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
3827 | } | |
3828 | ||
3829 | static int r100_startup(struct radeon_device *rdev) | |
3830 | { | |
3831 | int r; | |
3832 | ||
92cde00c AD |
3833 | /* set common regs */ |
3834 | r100_set_common_regs(rdev); | |
3835 | /* program mc */ | |
d4550907 JG |
3836 | r100_mc_program(rdev); |
3837 | /* Resume clock */ | |
3838 | r100_clock_startup(rdev); | |
d4550907 JG |
3839 | /* Initialize GART (initialize after TTM so we can allocate |
3840 | * memory through TTM but finalize after TTM) */ | |
17e15b0c | 3841 | r100_enable_bm(rdev); |
d4550907 JG |
3842 | if (rdev->flags & RADEON_IS_PCI) { |
3843 | r = r100_pci_gart_enable(rdev); | |
3844 | if (r) | |
3845 | return r; | |
3846 | } | |
724c80e1 AD |
3847 | |
3848 | /* allocate wb buffer */ | |
3849 | r = radeon_wb_init(rdev); | |
3850 | if (r) | |
3851 | return r; | |
3852 | ||
30eb77f4 JG |
3853 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3854 | if (r) { | |
3855 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3856 | return r; | |
3857 | } | |
3858 | ||
d4550907 | 3859 | /* Enable IRQ */ |
e49f3959 AH |
3860 | if (!rdev->irq.installed) { |
3861 | r = radeon_irq_kms_init(rdev); | |
3862 | if (r) | |
3863 | return r; | |
3864 | } | |
3865 | ||
d4550907 | 3866 | r100_irq_set(rdev); |
cafe6609 | 3867 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
d4550907 JG |
3868 | /* 1M ring buffer */ |
3869 | r = r100_cp_init(rdev, 1024 * 1024); | |
3870 | if (r) { | |
ec4f2ac4 | 3871 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
d4550907 JG |
3872 | return r; |
3873 | } | |
b15ba512 | 3874 | |
2898c348 CK |
3875 | r = radeon_ib_pool_init(rdev); |
3876 | if (r) { | |
3877 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 3878 | return r; |
2898c348 | 3879 | } |
b15ba512 | 3880 | |
d4550907 JG |
3881 | return 0; |
3882 | } | |
3883 | ||
3884 | int r100_resume(struct radeon_device *rdev) | |
3885 | { | |
6b7746e8 JG |
3886 | int r; |
3887 | ||
d4550907 JG |
3888 | /* Make sur GART are not working */ |
3889 | if (rdev->flags & RADEON_IS_PCI) | |
3890 | r100_pci_gart_disable(rdev); | |
3891 | /* Resume clock before doing reset */ | |
3892 | r100_clock_startup(rdev); | |
3893 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3894 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3895 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
3896 | RREG32(R_000E40_RBBM_STATUS), | |
3897 | RREG32(R_0007C0_CP_STAT)); | |
3898 | } | |
3899 | /* post */ | |
3900 | radeon_combios_asic_init(rdev->ddev); | |
3901 | /* Resume clock after posting */ | |
3902 | r100_clock_startup(rdev); | |
550e2d92 DA |
3903 | /* Initialize surface registers */ |
3904 | radeon_surface_init(rdev); | |
b15ba512 JG |
3905 | |
3906 | rdev->accel_working = true; | |
6b7746e8 JG |
3907 | r = r100_startup(rdev); |
3908 | if (r) { | |
3909 | rdev->accel_working = false; | |
3910 | } | |
3911 | return r; | |
d4550907 JG |
3912 | } |
3913 | ||
3914 | int r100_suspend(struct radeon_device *rdev) | |
3915 | { | |
3916 | r100_cp_disable(rdev); | |
724c80e1 | 3917 | radeon_wb_disable(rdev); |
d4550907 JG |
3918 | r100_irq_disable(rdev); |
3919 | if (rdev->flags & RADEON_IS_PCI) | |
3920 | r100_pci_gart_disable(rdev); | |
3921 | return 0; | |
3922 | } | |
3923 | ||
3924 | void r100_fini(struct radeon_device *rdev) | |
3925 | { | |
d4550907 | 3926 | r100_cp_fini(rdev); |
724c80e1 | 3927 | radeon_wb_fini(rdev); |
2898c348 | 3928 | radeon_ib_pool_fini(rdev); |
d4550907 JG |
3929 | radeon_gem_fini(rdev); |
3930 | if (rdev->flags & RADEON_IS_PCI) | |
3931 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 3932 | radeon_agp_fini(rdev); |
d4550907 JG |
3933 | radeon_irq_kms_fini(rdev); |
3934 | radeon_fence_driver_fini(rdev); | |
4c788679 | 3935 | radeon_bo_fini(rdev); |
d4550907 JG |
3936 | radeon_atombios_fini(rdev); |
3937 | kfree(rdev->bios); | |
3938 | rdev->bios = NULL; | |
3939 | } | |
3940 | ||
4c712e6c DA |
3941 | /* |
3942 | * Due to how kexec works, it can leave the hw fully initialised when it | |
3943 | * boots the new kernel. However doing our init sequence with the CP and | |
3944 | * WB stuff setup causes GPU hangs on the RN50 at least. So at startup | |
3945 | * do some quick sanity checks and restore sane values to avoid this | |
3946 | * problem. | |
3947 | */ | |
3948 | void r100_restore_sanity(struct radeon_device *rdev) | |
3949 | { | |
3950 | u32 tmp; | |
3951 | ||
3952 | tmp = RREG32(RADEON_CP_CSQ_CNTL); | |
3953 | if (tmp) { | |
3954 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
3955 | } | |
3956 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
3957 | if (tmp) { | |
3958 | WREG32(RADEON_CP_RB_CNTL, 0); | |
3959 | } | |
3960 | tmp = RREG32(RADEON_SCRATCH_UMSK); | |
3961 | if (tmp) { | |
3962 | WREG32(RADEON_SCRATCH_UMSK, 0); | |
3963 | } | |
3964 | } | |
3965 | ||
d4550907 JG |
3966 | int r100_init(struct radeon_device *rdev) |
3967 | { | |
3968 | int r; | |
3969 | ||
d4550907 JG |
3970 | /* Register debugfs file specific to this group of asics */ |
3971 | r100_debugfs(rdev); | |
3972 | /* Disable VGA */ | |
3973 | r100_vga_render_disable(rdev); | |
3974 | /* Initialize scratch registers */ | |
3975 | radeon_scratch_init(rdev); | |
3976 | /* Initialize surface registers */ | |
3977 | radeon_surface_init(rdev); | |
4c712e6c DA |
3978 | /* sanity check some register to avoid hangs like after kexec */ |
3979 | r100_restore_sanity(rdev); | |
d4550907 JG |
3980 | /* TODO: disable VGA need to use VGA request */ |
3981 | /* BIOS*/ | |
3982 | if (!radeon_get_bios(rdev)) { | |
3983 | if (ASIC_IS_AVIVO(rdev)) | |
3984 | return -EINVAL; | |
3985 | } | |
3986 | if (rdev->is_atom_bios) { | |
3987 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
3988 | return -EINVAL; | |
3989 | } else { | |
3990 | r = radeon_combios_init(rdev); | |
3991 | if (r) | |
3992 | return r; | |
3993 | } | |
3994 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3995 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3996 | dev_warn(rdev->dev, |
3997 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
3998 | RREG32(R_000E40_RBBM_STATUS), | |
3999 | RREG32(R_0007C0_CP_STAT)); | |
4000 | } | |
4001 | /* check if cards are posted or not */ | |
72542d77 DA |
4002 | if (radeon_boot_test_post_card(rdev) == false) |
4003 | return -EINVAL; | |
d4550907 JG |
4004 | /* Set asic errata */ |
4005 | r100_errata(rdev); | |
4006 | /* Initialize clocks */ | |
4007 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
4008 | /* initialize AGP */ |
4009 | if (rdev->flags & RADEON_IS_AGP) { | |
4010 | r = radeon_agp_init(rdev); | |
4011 | if (r) { | |
4012 | radeon_agp_disable(rdev); | |
4013 | } | |
4014 | } | |
4015 | /* initialize VRAM */ | |
4016 | r100_mc_init(rdev); | |
d4550907 | 4017 | /* Fence driver */ |
30eb77f4 | 4018 | r = radeon_fence_driver_init(rdev); |
d4550907 JG |
4019 | if (r) |
4020 | return r; | |
d4550907 | 4021 | /* Memory manager */ |
4c788679 | 4022 | r = radeon_bo_init(rdev); |
d4550907 JG |
4023 | if (r) |
4024 | return r; | |
4025 | if (rdev->flags & RADEON_IS_PCI) { | |
4026 | r = r100_pci_gart_init(rdev); | |
4027 | if (r) | |
4028 | return r; | |
4029 | } | |
4030 | r100_set_safe_registers(rdev); | |
b15ba512 | 4031 | |
d4550907 JG |
4032 | rdev->accel_working = true; |
4033 | r = r100_startup(rdev); | |
4034 | if (r) { | |
4035 | /* Somethings want wront with the accel init stop accel */ | |
4036 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
d4550907 | 4037 | r100_cp_fini(rdev); |
724c80e1 | 4038 | radeon_wb_fini(rdev); |
2898c348 | 4039 | radeon_ib_pool_fini(rdev); |
655efd3d | 4040 | radeon_irq_kms_fini(rdev); |
d4550907 JG |
4041 | if (rdev->flags & RADEON_IS_PCI) |
4042 | r100_pci_gart_fini(rdev); | |
d4550907 JG |
4043 | rdev->accel_working = false; |
4044 | } | |
4045 | return 0; | |
4046 | } | |
6fcbef7a | 4047 | |
2ef9bdfe DV |
4048 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
4049 | bool always_indirect) | |
6fcbef7a | 4050 | { |
2ef9bdfe | 4051 | if (reg < rdev->rmmio_size && !always_indirect) |
6fcbef7a AK |
4052 | return readl(((void __iomem *)rdev->rmmio) + reg); |
4053 | else { | |
2c385151 DV |
4054 | unsigned long flags; |
4055 | uint32_t ret; | |
4056 | ||
4057 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
6fcbef7a | 4058 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
2c385151 DV |
4059 | ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
4060 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
4061 | ||
4062 | return ret; | |
6fcbef7a AK |
4063 | } |
4064 | } | |
4065 | ||
2ef9bdfe DV |
4066 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
4067 | bool always_indirect) | |
6fcbef7a | 4068 | { |
2ef9bdfe | 4069 | if (reg < rdev->rmmio_size && !always_indirect) |
6fcbef7a AK |
4070 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
4071 | else { | |
2c385151 DV |
4072 | unsigned long flags; |
4073 | ||
4074 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
6fcbef7a AK |
4075 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
4076 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
2c385151 | 4077 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
6fcbef7a AK |
4078 | } |
4079 | } | |
4080 | ||
4081 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) | |
4082 | { | |
4083 | if (reg < rdev->rio_mem_size) | |
4084 | return ioread32(rdev->rio_mem + reg); | |
4085 | else { | |
4086 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
4087 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); | |
4088 | } | |
4089 | } | |
4090 | ||
4091 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
4092 | { | |
4093 | if (reg < rdev->rio_mem_size) | |
4094 | iowrite32(v, rdev->rio_mem + reg); | |
4095 | else { | |
4096 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
4097 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); | |
4098 | } | |
4099 | } |