[deliverable/linux.git] / drivers / gpu / drm / radeon / r100_track.h


#define R100_TRACK_MAX_TEXTURE 3
#define R200_TRACK_MAX_TEXTURE 6
#define R300_TRACK_MAX_TEXTURE 16

#define R100_MAX_CB 1
#define R300_MAX_CB 4

/*
 * CS functions
 */
struct r100_cs_track_cb {
	struct radeon_bo	*robj;
	unsigned		pitch;
	unsigned		cpp;
	unsigned		offset;
};

struct r100_cs_track_array {
	struct radeon_bo	*robj;
	unsigned		esize;
};

struct r100_cs_cube_info {
	struct radeon_bo	*robj;
	unsigned		offset;
	unsigned		width;
	unsigned		height;
};

#define R100_TRACK_COMP_NONE   0
#define R100_TRACK_COMP_DXT1   1
#define R100_TRACK_COMP_DXT35  2

struct r100_cs_track_texture {
	struct radeon_bo	*robj;
	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
	unsigned		pitch;
	unsigned		width;
	unsigned		height;
	unsigned		num_levels;
	unsigned		cpp;
	unsigned		tex_coord_type;
	unsigned		txdepth;
	unsigned		width_11;
	unsigned		height_11;
	bool			use_pitch;
	bool			enabled;
	bool                    lookup_disable;
	bool			roundup_w;
	bool			roundup_h;
	unsigned                compress_format;
};

struct r100_cs_track {
	unsigned			num_cb;
	unsigned                        num_texture;
	unsigned			maxy;
	unsigned			vtx_size;
	unsigned			vap_vf_cntl;
	unsigned			vap_alt_nverts;
	unsigned			immd_dwords;
	unsigned			num_arrays;
	unsigned			max_indx;
	unsigned			color_channel_mask;
	struct r100_cs_track_array	arrays[16];
	struct r100_cs_track_cb 	cb[R300_MAX_CB];
	struct r100_cs_track_cb 	zb;
	struct r100_cs_track_cb 	aa;
	struct r100_cs_track_texture	textures[R300_TRACK_MAX_TEXTURE];
	bool				z_enabled;
	bool                            separate_cube;
	bool				zb_cb_clear;
	bool				blend_read_enable;
	bool				cb_dirty;
	bool				zb_dirty;
	bool				tex_dirty;
	bool				aa_dirty;
	bool				aaresolve;
};

int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);

int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);

int r200_packet0_check(struct radeon_cs_parser *p,
		       struct radeon_cs_packet *pkt,
		       unsigned idx, unsigned reg);

int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
			    struct radeon_cs_packet *pkt,
			    unsigned idx,
			    unsigned reg);
int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
			     struct radeon_cs_packet *pkt,
			     int idx);
Commit	Line	Data
551ebd83 DA	1
	2	#define R100_TRACK_MAX_TEXTURE 3
	3	#define R200_TRACK_MAX_TEXTURE 6
	4	#define R300_TRACK_MAX_TEXTURE 16
	5
	6	#define R100_MAX_CB 1
	7	#define R300_MAX_CB 4
	8
	9	/*
	10	* CS functions
	11	*/
	12	struct r100_cs_track_cb {
4c788679	13	struct radeon_bo *robj;
551ebd83 DA	14	unsigned pitch;
	15	unsigned cpp;
	16	unsigned offset;
	17	};
	18
	19	struct r100_cs_track_array {
4c788679	20	struct radeon_bo *robj;
551ebd83 DA	21	unsigned esize;
	22	};
	23
	24	struct r100_cs_cube_info {
4c788679 JG	25	struct radeon_bo *robj;
4c788679 JG	26	unsigned offset;
551ebd83 DA	27	unsigned width;
	28	unsigned height;
	29	};
	30
d785d78b DA	31	#define R100_TRACK_COMP_NONE 0
	32	#define R100_TRACK_COMP_DXT1 1
	33	#define R100_TRACK_COMP_DXT35 2
	34
551ebd83	35	struct r100_cs_track_texture {
4c788679	36	struct radeon_bo *robj;
551ebd83 DA	37	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
	38	unsigned pitch;
	39	unsigned width;
	40	unsigned height;
	41	unsigned num_levels;
	42	unsigned cpp;
	43	unsigned tex_coord_type;
	44	unsigned txdepth;
	45	unsigned width_11;
	46	unsigned height_11;
	47	bool use_pitch;
	48	bool enabled;
43b93fbf	49	bool lookup_disable;
551ebd83 DA	50	bool roundup_w;
551ebd83 DA	51	bool roundup_h;
d785d78b	52	unsigned compress_format;
551ebd83 DA	53	};
551ebd83 DA	54
551ebd83	55	struct r100_cs_track {
551ebd83 DA	56	unsigned num_cb;
	57	unsigned num_texture;
	58	unsigned maxy;
	59	unsigned vtx_size;
	60	unsigned vap_vf_cntl;
cae94b0a	61	unsigned vap_alt_nverts;
551ebd83 DA	62	unsigned immd_dwords;
	63	unsigned num_arrays;
	64	unsigned max_indx;
46c64d4b	65	unsigned color_channel_mask;
a27bb4b2	66	struct r100_cs_track_array arrays[16];
551ebd83 DA	67	struct r100_cs_track_cb cb[R300_MAX_CB];
551ebd83 DA	68	struct r100_cs_track_cb zb;
fff1ce4d	69	struct r100_cs_track_cb aa;
551ebd83 DA	70	struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
	71	bool z_enabled;
	72	bool separate_cube;
797fd5b9	73	bool zb_cb_clear;
46c64d4b	74	bool blend_read_enable;
40b4a759 MO	75	bool cb_dirty;
	76	bool zb_dirty;
	77	bool tex_dirty;
fff1ce4d MO	78	bool aa_dirty;
fff1ce4d MO	79	bool aaresolve;
551ebd83 DA	80	};
	81
	82	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track);
	83	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track);
551ebd83 DA	84
	85	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
	86
	87	int r200_packet0_check(struct radeon_cs_parser *p,
	88	struct radeon_cs_packet *pkt,
	89	unsigned idx, unsigned reg);
	90
cbdd4501 AK	91	int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
	92	struct radeon_cs_packet *pkt,
	93	unsigned idx,
	94	unsigned reg);
	95	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
	96	struct radeon_cs_packet *pkt,
	97	int idx);