Commit | Line | Data |
---|---|---|
551ebd83 DA |
1 | |
2 | #define R100_TRACK_MAX_TEXTURE 3 | |
3 | #define R200_TRACK_MAX_TEXTURE 6 | |
4 | #define R300_TRACK_MAX_TEXTURE 16 | |
5 | ||
6 | #define R100_MAX_CB 1 | |
7 | #define R300_MAX_CB 4 | |
8 | ||
9 | /* | |
10 | * CS functions | |
11 | */ | |
12 | struct r100_cs_track_cb { | |
4c788679 | 13 | struct radeon_bo *robj; |
551ebd83 DA |
14 | unsigned pitch; |
15 | unsigned cpp; | |
16 | unsigned offset; | |
17 | }; | |
18 | ||
19 | struct r100_cs_track_array { | |
4c788679 | 20 | struct radeon_bo *robj; |
551ebd83 DA |
21 | unsigned esize; |
22 | }; | |
23 | ||
24 | struct r100_cs_cube_info { | |
4c788679 JG |
25 | struct radeon_bo *robj; |
26 | unsigned offset; | |
551ebd83 DA |
27 | unsigned width; |
28 | unsigned height; | |
29 | }; | |
30 | ||
d785d78b DA |
31 | #define R100_TRACK_COMP_NONE 0 |
32 | #define R100_TRACK_COMP_DXT1 1 | |
33 | #define R100_TRACK_COMP_DXT35 2 | |
34 | ||
551ebd83 | 35 | struct r100_cs_track_texture { |
4c788679 | 36 | struct radeon_bo *robj; |
551ebd83 DA |
37 | struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ |
38 | unsigned pitch; | |
39 | unsigned width; | |
40 | unsigned height; | |
41 | unsigned num_levels; | |
42 | unsigned cpp; | |
43 | unsigned tex_coord_type; | |
44 | unsigned txdepth; | |
45 | unsigned width_11; | |
46 | unsigned height_11; | |
47 | bool use_pitch; | |
48 | bool enabled; | |
49 | bool roundup_w; | |
50 | bool roundup_h; | |
d785d78b | 51 | unsigned compress_format; |
551ebd83 DA |
52 | }; |
53 | ||
54 | struct r100_cs_track_limits { | |
55 | unsigned num_cb; | |
56 | unsigned num_texture; | |
57 | unsigned max_levels; | |
58 | }; | |
59 | ||
60 | struct r100_cs_track { | |
61 | struct radeon_device *rdev; | |
62 | unsigned num_cb; | |
63 | unsigned num_texture; | |
64 | unsigned maxy; | |
65 | unsigned vtx_size; | |
66 | unsigned vap_vf_cntl; | |
cae94b0a | 67 | unsigned vap_alt_nverts; |
551ebd83 DA |
68 | unsigned immd_dwords; |
69 | unsigned num_arrays; | |
70 | unsigned max_indx; | |
46c64d4b | 71 | unsigned color_channel_mask; |
551ebd83 DA |
72 | struct r100_cs_track_array arrays[11]; |
73 | struct r100_cs_track_cb cb[R300_MAX_CB]; | |
74 | struct r100_cs_track_cb zb; | |
75 | struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; | |
76 | bool z_enabled; | |
77 | bool separate_cube; | |
797fd5b9 | 78 | bool zb_cb_clear; |
46c64d4b | 79 | bool blend_read_enable; |
551ebd83 DA |
80 | }; |
81 | ||
82 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); | |
83 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); | |
84 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
85 | struct radeon_cs_reloc **cs_reloc); | |
86 | void r100_cs_dump_packet(struct radeon_cs_parser *p, | |
87 | struct radeon_cs_packet *pkt); | |
88 | ||
89 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); | |
90 | ||
91 | int r200_packet0_check(struct radeon_cs_parser *p, | |
92 | struct radeon_cs_packet *pkt, | |
93 | unsigned idx, unsigned reg); | |
94 | ||
513bcb46 DA |
95 | |
96 | ||
551ebd83 DA |
97 | static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
98 | struct radeon_cs_packet *pkt, | |
99 | unsigned idx, | |
100 | unsigned reg) | |
101 | { | |
102 | int r; | |
103 | u32 tile_flags = 0; | |
104 | u32 tmp; | |
105 | struct radeon_cs_reloc *reloc; | |
513bcb46 | 106 | u32 value; |
551ebd83 DA |
107 | |
108 | r = r100_cs_packet_next_reloc(p, &reloc); | |
109 | if (r) { | |
110 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
111 | idx, reg); | |
112 | r100_cs_dump_packet(p, pkt); | |
113 | return r; | |
114 | } | |
513bcb46 DA |
115 | value = radeon_get_ib_value(p, idx); |
116 | tmp = value & 0x003fffff; | |
551ebd83 DA |
117 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
118 | ||
119 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
120 | tile_flags |= RADEON_DST_TILE_MACRO; | |
121 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | |
122 | if (reg == RADEON_SRC_PITCH_OFFSET) { | |
123 | DRM_ERROR("Cannot src blit from microtiled surface\n"); | |
124 | r100_cs_dump_packet(p, pkt); | |
125 | return -EINVAL; | |
126 | } | |
127 | tile_flags |= RADEON_DST_TILE_MICRO; | |
128 | } | |
129 | ||
130 | tmp |= tile_flags; | |
513bcb46 | 131 | p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; |
551ebd83 DA |
132 | return 0; |
133 | } | |
513bcb46 DA |
134 | |
135 | static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |
136 | struct radeon_cs_packet *pkt, | |
137 | int idx) | |
138 | { | |
139 | unsigned c, i; | |
140 | struct radeon_cs_reloc *reloc; | |
141 | struct r100_cs_track *track; | |
142 | int r = 0; | |
143 | volatile uint32_t *ib; | |
144 | u32 idx_value; | |
145 | ||
146 | ib = p->ib->ptr; | |
147 | track = (struct r100_cs_track *)p->track; | |
148 | c = radeon_get_ib_value(p, idx++) & 0x1F; | |
149 | track->num_arrays = c; | |
150 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | |
151 | r = r100_cs_packet_next_reloc(p, &reloc); | |
152 | if (r) { | |
153 | DRM_ERROR("No reloc for packet3 %d\n", | |
154 | pkt->opcode); | |
155 | r100_cs_dump_packet(p, pkt); | |
156 | return r; | |
157 | } | |
158 | idx_value = radeon_get_ib_value(p, idx); | |
159 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | |
160 | ||
161 | track->arrays[i + 0].esize = idx_value >> 8; | |
162 | track->arrays[i + 0].robj = reloc->robj; | |
163 | track->arrays[i + 0].esize &= 0x7F; | |
164 | r = r100_cs_packet_next_reloc(p, &reloc); | |
165 | if (r) { | |
166 | DRM_ERROR("No reloc for packet3 %d\n", | |
167 | pkt->opcode); | |
168 | r100_cs_dump_packet(p, pkt); | |
169 | return r; | |
170 | } | |
171 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); | |
172 | track->arrays[i + 1].robj = reloc->robj; | |
173 | track->arrays[i + 1].esize = idx_value >> 24; | |
174 | track->arrays[i + 1].esize &= 0x7F; | |
175 | } | |
176 | if (c & 1) { | |
177 | r = r100_cs_packet_next_reloc(p, &reloc); | |
178 | if (r) { | |
179 | DRM_ERROR("No reloc for packet3 %d\n", | |
180 | pkt->opcode); | |
181 | r100_cs_dump_packet(p, pkt); | |
182 | return r; | |
183 | } | |
184 | idx_value = radeon_get_ib_value(p, idx); | |
185 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | |
186 | track->arrays[i + 0].robj = reloc->robj; | |
187 | track->arrays[i + 0].esize = idx_value >> 8; | |
188 | track->arrays[i + 0].esize &= 0x7F; | |
189 | } | |
190 | return r; | |
191 | } |