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drm/radeon: use status regs to determine what to reset (si)
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
e0cd3608 32#include <linux/module.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/radeon_drm.h>
771fe6b9 35#include "radeon.h"
e6990375 36#include "radeon_asic.h"
3ce0a23d 37#include "radeon_mode.h"
3ce0a23d 38#include "r600d.h"
3ce0a23d 39#include "atom.h"
d39c3b89 40#include "avivod.h"
771fe6b9 41
3ce0a23d
JG		 42#define PFP_UCODE_SIZE 576
43#define PM4_UCODE_SIZE 1792
d8f60cfc 44#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 45#define R700_PFP_UCODE_SIZE 848
46#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 47#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 50#define EVERGREEN_RLC_UCODE_SIZE 768
12727809 51#define CAYMAN_RLC_UCODE_SIZE 1024
c420c745 52#define ARUBA_RLC_UCODE_SIZE 1536
3ce0a23d
JG		 53
54/* Firmware Names */
55MODULE_FIRMWARE("radeon/R600_pfp.bin");
56MODULE_FIRMWARE("radeon/R600_me.bin");
57MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58MODULE_FIRMWARE("radeon/RV610_me.bin");
59MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60MODULE_FIRMWARE("radeon/RV630_me.bin");
61MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62MODULE_FIRMWARE("radeon/RV620_me.bin");
63MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64MODULE_FIRMWARE("radeon/RV635_me.bin");
65MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66MODULE_FIRMWARE("radeon/RV670_me.bin");
67MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68MODULE_FIRMWARE("radeon/RS780_me.bin");
69MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70MODULE_FIRMWARE("radeon/RV770_me.bin");
71MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72MODULE_FIRMWARE("radeon/RV730_me.bin");
73MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 75MODULE_FIRMWARE("radeon/R600_rlc.bin");
76MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 83MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 86MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 87MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 88MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 89MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90MODULE_FIRMWARE("radeon/PALM_me.bin");
91MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 92MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93MODULE_FIRMWARE("radeon/SUMO_me.bin");
94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d 96
f13f7731
AD		 97static const u32 crtc_offsets[2] =
98{
99 0,
100 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
101};
102
3ce0a23d 103int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 104
1a029b76 105/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9 106int r600_mc_wait_for_idle(struct radeon_device *rdev);
1109ca09 107static void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 108void r600_fini(struct radeon_device *rdev);
45f9a39b 109void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 110static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 111
21a8122a 112/* get temperature in millidegrees */
20d391d7 113int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 114{
115 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
116 ASIC_T_SHIFT;
20d391d7 117 int actual_temp = temp & 0xff;
21a8122a 118
20d391d7
AD		 119 if (temp & 0x100)
120 actual_temp -= 256;
121
122 return actual_temp * 1000;
21a8122a
AD		 123}
124
ce8f5370 125void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 126{
127 int i;
128
ce8f5370
AD		 129 rdev->pm.dynpm_can_upclock = true;
130 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 131
132 /* power state array is low to high, default is first */
133 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
134 int min_power_state_index = 0;
135
136 if (rdev->pm.num_power_states > 2)
137 min_power_state_index = 1;
138
ce8f5370
AD		 139 switch (rdev->pm.dynpm_planned_action) {
140 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 141 rdev->pm.requested_power_state_index = min_power_state_index;
142 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 143 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 144 break;
ce8f5370 145 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 146 if (rdev->pm.current_power_state_index == min_power_state_index) {
147 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 148 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 149 } else {
150 if (rdev->pm.active_crtc_count > 1) {
151 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 152 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 153 continue;
154 else if (i >= rdev->pm.current_power_state_index) {
155 rdev->pm.requested_power_state_index =
156 rdev->pm.current_power_state_index;
157 break;
158 } else {
159 rdev->pm.requested_power_state_index = i;
160 break;
161 }
162 }
773c3fa3
AD		 163 } else {
164 if (rdev->pm.current_power_state_index == 0)
165 rdev->pm.requested_power_state_index =
166 rdev->pm.num_power_states - 1;
167 else
168 rdev->pm.requested_power_state_index =
169 rdev->pm.current_power_state_index - 1;
170 }
a48b9b4e
AD		 171 }
172 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 173 /* don't use the power state if crtcs are active and no display flag is set */
174 if ((rdev->pm.active_crtc_count > 0) &&
175 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
176 clock_info[rdev->pm.requested_clock_mode_index].flags &
177 RADEON_PM_MODE_NO_DISPLAY)) {
178 rdev->pm.requested_power_state_index++;
179 }
a48b9b4e 180 break;
ce8f5370 181 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 182 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
183 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 184 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 185 } else {
186 if (rdev->pm.active_crtc_count > 1) {
187 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 188 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 189 continue;
190 else if (i <= rdev->pm.current_power_state_index) {
191 rdev->pm.requested_power_state_index =
192 rdev->pm.current_power_state_index;
193 break;
194 } else {
195 rdev->pm.requested_power_state_index = i;
196 break;
197 }
198 }
199 } else
200 rdev->pm.requested_power_state_index =
201 rdev->pm.current_power_state_index + 1;
202 }
203 rdev->pm.requested_clock_mode_index = 0;
204 break;
ce8f5370 205 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 206 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
207 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 208 rdev->pm.dynpm_can_upclock = false;
58e21dff 209 break;
ce8f5370 210 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 211 default:
212 DRM_ERROR("Requested mode for not defined action\n");
213 return;
214 }
215 } else {
216 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
217 /* for now just select the first power state and switch between clock modes */
218 /* power state array is low to high, default is first (0) */
219 if (rdev->pm.active_crtc_count > 1) {
220 rdev->pm.requested_power_state_index = -1;
221 /* start at 1 as we don't want the default mode */
222 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 223 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 224 continue;
225 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
226 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
227 rdev->pm.requested_power_state_index = i;
228 break;
229 }
230 }
231 /* if nothing selected, grab the default state. */
232 if (rdev->pm.requested_power_state_index == -1)
233 rdev->pm.requested_power_state_index = 0;
234 } else
235 rdev->pm.requested_power_state_index = 1;
236
ce8f5370
AD		 237 switch (rdev->pm.dynpm_planned_action) {
238 case DYNPM_ACTION_MINIMUM:
a48b9b4e 239 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 240 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 241 break;
ce8f5370 242 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 243 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
244 if (rdev->pm.current_clock_mode_index == 0) {
245 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 246 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 247 } else
248 rdev->pm.requested_clock_mode_index =
249 rdev->pm.current_clock_mode_index - 1;
250 } else {
251 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 252 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 253 }
d7311171
AD		 254 /* don't use the power state if crtcs are active and no display flag is set */
255 if ((rdev->pm.active_crtc_count > 0) &&
256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
257 clock_info[rdev->pm.requested_clock_mode_index].flags &
258 RADEON_PM_MODE_NO_DISPLAY)) {
259 rdev->pm.requested_clock_mode_index++;
260 }
a48b9b4e 261 break;
ce8f5370 262 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 263 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
264 if (rdev->pm.current_clock_mode_index ==
265 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
266 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 267 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 268 } else
269 rdev->pm.requested_clock_mode_index =
270 rdev->pm.current_clock_mode_index + 1;
271 } else {
272 rdev->pm.requested_clock_mode_index =
273 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 274 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 275 }
276 break;
ce8f5370 277 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 278 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
279 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 280 rdev->pm.dynpm_can_upclock = false;
58e21dff 281 break;
ce8f5370 282 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 283 default:
284 DRM_ERROR("Requested mode for not defined action\n");
285 return;
286 }
287 }
288
d9fdaafb 289 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 290 rdev->pm.power_state[rdev->pm.requested_power_state_index].
291 clock_info[rdev->pm.requested_clock_mode_index].sclk,
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].mclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
295 pcie_lanes);
a48b9b4e
AD		 296}
297
ce8f5370
AD		 298void rs780_pm_init_profile(struct radeon_device *rdev)
299{
300 if (rdev->pm.num_power_states == 2) {
301 /* default */
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
306 /* low sh */
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 311 /* mid sh */
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 316 /* high sh */
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
321 /* low mh */
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 326 /* mid mh */
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 331 /* high mh */
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
336 } else if (rdev->pm.num_power_states == 3) {
337 /* default */
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
342 /* low sh */
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
345 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 347 /* mid sh */
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
349 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
350 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 352 /* high sh */
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
355 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
357 /* low mh */
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 362 /* mid mh */
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
364 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
365 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 367 /* high mh */
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
369 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
370 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
372 } else {
373 /* default */
374 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
375 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
376 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
377 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
378 /* low sh */
379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
381 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 383 /* mid sh */
384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
385 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
386 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 388 /* high sh */
389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
390 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
391 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
393 /* low mh */
394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
395 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 398 /* mid mh */
399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
400 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 403 /* high mh */
404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
405 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
406 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
408 }
409}
bae6b562 410
ce8f5370
AD		 411void r600_pm_init_profile(struct radeon_device *rdev)
412{
bbe26ffe
AD		 413 int idx;
414
ce8f5370
AD		 415 if (rdev->family == CHIP_R600) {
416 /* XXX */
417 /* default */
418 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 421 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 422 /* low sh */
423 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 426 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 427 /* mid sh */
428 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
431 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 432 /* high sh */
433 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 436 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 437 /* low mh */
438 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 441 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 442 /* mid mh */
443 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
446 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 447 /* high mh */
448 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
449 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 451 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 452 } else {
453 if (rdev->pm.num_power_states < 4) {
454 /* default */
455 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
458 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
459 /* low sh */
4bff5171
AD		 460 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 463 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
464 /* mid sh */
465 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
468 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 469 /* high sh */
4bff5171
AD		 470 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
473 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
474 /* low mh */
4bff5171
AD		 475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 478 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
479 /* low mh */
480 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 484 /* high mh */
4bff5171
AD		 485 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
489 } else {
490 /* default */
491 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
492 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
494 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
495 /* low sh */
bbe26ffe
AD		 496 if (rdev->flags & RADEON_IS_MOBILITY)
497 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 else
499 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 504 /* mid sh */
bbe26ffe
AD		 505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
507 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 509 /* high sh */
bbe26ffe
AD		 510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
512 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
514 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
515 /* low mh */
bbe26ffe
AD		 516 if (rdev->flags & RADEON_IS_MOBILITY)
517 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
518 else
519 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
520 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
523 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 524 /* mid mh */
bbe26ffe
AD		 525 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
527 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 529 /* high mh */
bbe26ffe
AD		 530 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
531 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
532 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 533 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
534 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
535 }
536 }
bae6b562
AD		 537}
538
49e02b73
AD		 539void r600_pm_misc(struct radeon_device *rdev)
540{
a081a9d6
RM		 541 int req_ps_idx = rdev->pm.requested_power_state_index;
542 int req_cm_idx = rdev->pm.requested_clock_mode_index;
543 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
544 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 545
4d60173f 546 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 547 /* 0xff01 is a flag rather then an actual voltage */
548 if (voltage->voltage == 0xff01)
549 return;
4d60173f 550 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 551 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 552 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 553 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 554 }
555 }
49e02b73
AD		 556}
557
def9ba9c
AD		 558bool r600_gui_idle(struct radeon_device *rdev)
559{
560 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
561 return false;
562 else
563 return true;
564}
565
e0df1ac5
AD		 566/* hpd for digital panel detect/disconnect */
567bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
568{
569 bool connected = false;
570
571 if (ASIC_IS_DCE3(rdev)) {
572 switch (hpd) {
573 case RADEON_HPD_1:
574 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
575 connected = true;
576 break;
577 case RADEON_HPD_2:
578 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
579 connected = true;
580 break;
581 case RADEON_HPD_3:
582 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
583 connected = true;
584 break;
585 case RADEON_HPD_4:
586 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
587 connected = true;
588 break;
589 /* DCE 3.2 */
590 case RADEON_HPD_5:
591 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
592 connected = true;
593 break;
594 case RADEON_HPD_6:
595 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
596 connected = true;
597 break;
598 default:
599 break;
600 }
601 } else {
602 switch (hpd) {
603 case RADEON_HPD_1:
604 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
605 connected = true;
606 break;
607 case RADEON_HPD_2:
608 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
609 connected = true;
610 break;
611 case RADEON_HPD_3:
612 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
613 connected = true;
614 break;
615 default:
616 break;
617 }
618 }
619 return connected;
620}
621
622void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 623 enum radeon_hpd_id hpd)
e0df1ac5
AD		 624{
625 u32 tmp;
626 bool connected = r600_hpd_sense(rdev, hpd);
627
628 if (ASIC_IS_DCE3(rdev)) {
629 switch (hpd) {
630 case RADEON_HPD_1:
631 tmp = RREG32(DC_HPD1_INT_CONTROL);
632 if (connected)
633 tmp &= ~DC_HPDx_INT_POLARITY;
634 else
635 tmp |= DC_HPDx_INT_POLARITY;
636 WREG32(DC_HPD1_INT_CONTROL, tmp);
637 break;
638 case RADEON_HPD_2:
639 tmp = RREG32(DC_HPD2_INT_CONTROL);
640 if (connected)
641 tmp &= ~DC_HPDx_INT_POLARITY;
642 else
643 tmp |= DC_HPDx_INT_POLARITY;
644 WREG32(DC_HPD2_INT_CONTROL, tmp);
645 break;
646 case RADEON_HPD_3:
647 tmp = RREG32(DC_HPD3_INT_CONTROL);
648 if (connected)
649 tmp &= ~DC_HPDx_INT_POLARITY;
650 else
651 tmp |= DC_HPDx_INT_POLARITY;
652 WREG32(DC_HPD3_INT_CONTROL, tmp);
653 break;
654 case RADEON_HPD_4:
655 tmp = RREG32(DC_HPD4_INT_CONTROL);
656 if (connected)
657 tmp &= ~DC_HPDx_INT_POLARITY;
658 else
659 tmp |= DC_HPDx_INT_POLARITY;
660 WREG32(DC_HPD4_INT_CONTROL, tmp);
661 break;
662 case RADEON_HPD_5:
663 tmp = RREG32(DC_HPD5_INT_CONTROL);
664 if (connected)
665 tmp &= ~DC_HPDx_INT_POLARITY;
666 else
667 tmp |= DC_HPDx_INT_POLARITY;
668 WREG32(DC_HPD5_INT_CONTROL, tmp);
669 break;
670 /* DCE 3.2 */
671 case RADEON_HPD_6:
672 tmp = RREG32(DC_HPD6_INT_CONTROL);
673 if (connected)
674 tmp &= ~DC_HPDx_INT_POLARITY;
675 else
676 tmp |= DC_HPDx_INT_POLARITY;
677 WREG32(DC_HPD6_INT_CONTROL, tmp);
678 break;
679 default:
680 break;
681 }
682 } else {
683 switch (hpd) {
684 case RADEON_HPD_1:
685 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
686 if (connected)
687 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
688 else
689 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
691 break;
692 case RADEON_HPD_2:
693 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
694 if (connected)
695 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
696 else
697 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
699 break;
700 case RADEON_HPD_3:
701 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
702 if (connected)
703 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
704 else
705 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
706 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
707 break;
708 default:
709 break;
710 }
711 }
712}
713
714void r600_hpd_init(struct radeon_device *rdev)
715{
716 struct drm_device *dev = rdev->ddev;
717 struct drm_connector *connector;
fb98257a 718 unsigned enable = 0;
e0df1ac5 719
64912e99
AD		 720 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
721 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
722
455c89b9
JG		 723 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
724 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
725 /* don't try to enable hpd on eDP or LVDS avoid breaking the
726 * aux dp channel on imac and help (but not completely fix)
727 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
728 */
729 continue;
730 }
64912e99
AD		 731 if (ASIC_IS_DCE3(rdev)) {
732 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
733 if (ASIC_IS_DCE32(rdev))
734 tmp |= DC_HPDx_EN;
e0df1ac5 735
e0df1ac5
AD		 736 switch (radeon_connector->hpd.hpd) {
737 case RADEON_HPD_1:
738 WREG32(DC_HPD1_CONTROL, tmp);
e0df1ac5
AD		 739 break;
740 case RADEON_HPD_2:
741 WREG32(DC_HPD2_CONTROL, tmp);
e0df1ac5
AD		 742 break;
743 case RADEON_HPD_3:
744 WREG32(DC_HPD3_CONTROL, tmp);
e0df1ac5
AD		 745 break;
746 case RADEON_HPD_4:
747 WREG32(DC_HPD4_CONTROL, tmp);
e0df1ac5
AD		 748 break;
749 /* DCE 3.2 */
750 case RADEON_HPD_5:
751 WREG32(DC_HPD5_CONTROL, tmp);
e0df1ac5
AD		 752 break;
753 case RADEON_HPD_6:
754 WREG32(DC_HPD6_CONTROL, tmp);
e0df1ac5
AD		 755 break;
756 default:
757 break;
758 }
64912e99 759 } else {
e0df1ac5
AD		 760 switch (radeon_connector->hpd.hpd) {
761 case RADEON_HPD_1:
762 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 763 break;
764 case RADEON_HPD_2:
765 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 766 break;
767 case RADEON_HPD_3:
768 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 769 break;
770 default:
771 break;
772 }
773 }
fb98257a 774 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 775 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 776 }
fb98257a 777 radeon_irq_kms_enable_hpd(rdev, enable);
e0df1ac5
AD		 778}
779
780void r600_hpd_fini(struct radeon_device *rdev)
781{
782 struct drm_device *dev = rdev->ddev;
783 struct drm_connector *connector;
fb98257a 784 unsigned disable = 0;
e0df1ac5 785
fb98257a
CK		 786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
787 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
788 if (ASIC_IS_DCE3(rdev)) {
e0df1ac5
AD		 789 switch (radeon_connector->hpd.hpd) {
790 case RADEON_HPD_1:
791 WREG32(DC_HPD1_CONTROL, 0);
e0df1ac5
AD		 792 break;
793 case RADEON_HPD_2:
794 WREG32(DC_HPD2_CONTROL, 0);
e0df1ac5
AD		 795 break;
796 case RADEON_HPD_3:
797 WREG32(DC_HPD3_CONTROL, 0);
e0df1ac5
AD		 798 break;
799 case RADEON_HPD_4:
800 WREG32(DC_HPD4_CONTROL, 0);
e0df1ac5
AD		 801 break;
802 /* DCE 3.2 */
803 case RADEON_HPD_5:
804 WREG32(DC_HPD5_CONTROL, 0);
e0df1ac5
AD		 805 break;
806 case RADEON_HPD_6:
807 WREG32(DC_HPD6_CONTROL, 0);
e0df1ac5
AD		 808 break;
809 default:
810 break;
811 }
fb98257a 812 } else {
e0df1ac5
AD		 813 switch (radeon_connector->hpd.hpd) {
814 case RADEON_HPD_1:
815 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
e0df1ac5
AD		 816 break;
817 case RADEON_HPD_2:
818 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
e0df1ac5
AD		 819 break;
820 case RADEON_HPD_3:
821 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
e0df1ac5
AD		 822 break;
823 default:
824 break;
825 }
826 }
fb98257a 827 disable |= 1 << radeon_connector->hpd.hpd;
e0df1ac5 828 }
fb98257a 829 radeon_irq_kms_disable_hpd(rdev, disable);
e0df1ac5
AD		 830}
831
771fe6b9 832/*
3ce0a23d 833 * R600 PCIE GART
771fe6b9 834 */
3ce0a23d
JG		 835void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
836{
837 unsigned i;
838 u32 tmp;
839
2e98f10a 840 /* flush hdp cache so updates hit vram */
f3886f85
AD		 841 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
842 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 843 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 844 u32 tmp;
845
846 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
847 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 848 * This seems to cause problems on some AGP cards. Just use the old
849 * method for them.
812d0469
AD		 850 */
851 WREG32(HDP_DEBUG1, 0);
852 tmp = readl((void __iomem *)ptr);
853 } else
854 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 855
3ce0a23d
JG		 856 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
857 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
858 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
859 for (i = 0; i < rdev->usec_timeout; i++) {
860 /* read MC_STATUS */
861 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
862 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
863 if (tmp == 2) {
864 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
865 return;
866 }
867 if (tmp) {
868 return;
869 }
870 udelay(1);
871 }
872}
873
4aac0473 874int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 875{
4aac0473 876 int r;
3ce0a23d 877
c9a1be96 878 if (rdev->gart.robj) {
fce7d61b 879 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 880 return 0;
881 }
3ce0a23d
JG		 882 /* Initialize common gart structure */
883 r = radeon_gart_init(rdev);
4aac0473 884 if (r)
3ce0a23d 885 return r;
3ce0a23d 886 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 887 return radeon_gart_table_vram_alloc(rdev);
888}
889
1109ca09 890static int r600_pcie_gart_enable(struct radeon_device *rdev)
4aac0473
JG		 891{
892 u32 tmp;
893 int r, i;
894
c9a1be96 895 if (rdev->gart.robj == NULL) {
4aac0473
JG		 896 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
897 return -EINVAL;
771fe6b9 898 }
4aac0473
JG		 899 r = radeon_gart_table_vram_pin(rdev);
900 if (r)
901 return r;
82568565 902 radeon_gart_restore(rdev);
bc1a631e 903
3ce0a23d
JG		 904 /* Setup L2 cache */
905 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
906 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
907 EFFECTIVE_L2_QUEUE_SIZE(7));
908 WREG32(VM_L2_CNTL2, 0);
909 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
910 /* Setup TLB control */
911 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
912 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
913 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
914 ENABLE_WAIT_L2_QUERY;
915 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
916 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
917 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
918 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
922 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
923 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
924 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
925 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
926 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
928 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
929 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 930 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 931 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
932 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
933 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
934 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
935 (u32)(rdev->dummy_page.addr >> 12));
936 for (i = 1; i < 7; i++)
937 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 938
3ce0a23d 939 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 940 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
941 (unsigned)(rdev->mc.gtt_size >> 20),
942 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 943 rdev->gart.ready = true;
771fe6b9
JG		 944 return 0;
945}
946
1109ca09 947static void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 948{
3ce0a23d 949 u32 tmp;
c9a1be96 950 int i;
771fe6b9 951
3ce0a23d
JG		 952 /* Disable all tables */
953 for (i = 0; i < 7; i++)
954 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 955
3ce0a23d
JG		 956 /* Disable L2 cache */
957 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
958 EFFECTIVE_L2_QUEUE_SIZE(7));
959 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
960 /* Setup L1 TLB control */
961 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
962 ENABLE_WAIT_L2_QUERY;
963 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
c9a1be96 977 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 978}
979
1109ca09 980static void r600_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 981{
f9274562 982 radeon_gart_fini(rdev);
4aac0473
JG		 983 r600_pcie_gart_disable(rdev);
984 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 985}
986
1109ca09 987static void r600_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 988{
989 u32 tmp;
990 int i;
991
992 /* Setup L2 cache */
993 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
994 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
995 EFFECTIVE_L2_QUEUE_SIZE(7));
996 WREG32(VM_L2_CNTL2, 0);
997 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
998 /* Setup TLB control */
999 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1000 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1001 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1002 ENABLE_WAIT_L2_QUERY;
1003 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1016 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1017 for (i = 0; i < 7; i++)
1018 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1019}
1020
771fe6b9
JG		 1021int r600_mc_wait_for_idle(struct radeon_device *rdev)
1022{
3ce0a23d
JG		 1023 unsigned i;
1024 u32 tmp;
1025
1026 for (i = 0; i < rdev->usec_timeout; i++) {
1027 /* read MC_STATUS */
1028 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1029 if (!tmp)
1030 return 0;
1031 udelay(1);
1032 }
1033 return -1;
771fe6b9
JG		 1034}
1035
a3c1945a 1036static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1037{
a3c1945a 1038 struct rv515_mc_save save;
3ce0a23d
JG		 1039 u32 tmp;
1040 int i, j;
771fe6b9 1041
3ce0a23d
JG		 1042 /* Initialize HDP */
1043 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1044 WREG32((0x2c14 + j), 0x00000000);
1045 WREG32((0x2c18 + j), 0x00000000);
1046 WREG32((0x2c1c + j), 0x00000000);
1047 WREG32((0x2c20 + j), 0x00000000);
1048 WREG32((0x2c24 + j), 0x00000000);
1049 }
1050 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1051
a3c1945a 1052 rv515_mc_stop(rdev, &save);
3ce0a23d 1053 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1054 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1055 }
a3c1945a 1056 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1057 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1058 /* Update configuration */
1a029b76
JG		 1059 if (rdev->flags & RADEON_IS_AGP) {
1060 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1061 /* VRAM before AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063 rdev->mc.vram_start >> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065 rdev->mc.gtt_end >> 12);
1066 } else {
1067 /* VRAM after AGP */
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1069 rdev->mc.gtt_start >> 12);
1070 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1071 rdev->mc.vram_end >> 12);
1072 }
1073 } else {
1074 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1075 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1076 }
16cdf04d 1077 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1078 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1079 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1080 WREG32(MC_VM_FB_LOCATION, tmp);
1081 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1082 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1083 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1084 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1085 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1086 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1087 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1088 } else {
1089 WREG32(MC_VM_AGP_BASE, 0);
1090 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1091 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1092 }
3ce0a23d 1093 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1094 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1095 }
a3c1945a 1096 rv515_mc_resume(rdev, &save);
698443d9
DA		 1097 /* we need to own VRAM, so turn off the VGA renderer here
1098 * to stop it overwriting our objects */
d39c3b89 1099 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1100}
1101
d594e46a
JG		 1102/**
1103 * r600_vram_gtt_location - try to find VRAM & GTT location
1104 * @rdev: radeon device structure holding all necessary informations
1105 * @mc: memory controller structure holding memory informations
1106 *
1107 * Function will place try to place VRAM at same place as in CPU (PCI)
1108 * address space as some GPU seems to have issue when we reprogram at
1109 * different address space.
1110 *
1111 * If there is not enough space to fit the unvisible VRAM after the
1112 * aperture then we limit the VRAM size to the aperture.
1113 *
1114 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1115 * them to be in one from GPU point of view so that we can program GPU to
1116 * catch access outside them (weird GPU policy see ??).
1117 *
1118 * This function will never fails, worst case are limiting VRAM or GTT.
1119 *
1120 * Note: GTT start, end, size should be initialized before calling this
1121 * function on AGP platform.
1122 */
0ef0c1f7 1123static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1124{
1125 u64 size_bf, size_af;
1126
1127 if (mc->mc_vram_size > 0xE0000000) {
1128 /* leave room for at least 512M GTT */
1129 dev_warn(rdev->dev, "limiting VRAM\n");
1130 mc->real_vram_size = 0xE0000000;
1131 mc->mc_vram_size = 0xE0000000;
1132 }
1133 if (rdev->flags & RADEON_IS_AGP) {
1134 size_bf = mc->gtt_start;
dfc6ae5b 1135 size_af = 0xFFFFFFFF - mc->gtt_end;
d594e46a
JG		 1136 if (size_bf > size_af) {
1137 if (mc->mc_vram_size > size_bf) {
1138 dev_warn(rdev->dev, "limiting VRAM\n");
1139 mc->real_vram_size = size_bf;
1140 mc->mc_vram_size = size_bf;
1141 }
1142 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1143 } else {
1144 if (mc->mc_vram_size > size_af) {
1145 dev_warn(rdev->dev, "limiting VRAM\n");
1146 mc->real_vram_size = size_af;
1147 mc->mc_vram_size = size_af;
1148 }
dfc6ae5b 1149 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1150 }
1151 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1152 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1153 mc->mc_vram_size >> 20, mc->vram_start,
1154 mc->vram_end, mc->real_vram_size >> 20);
1155 } else {
1156 u64 base = 0;
8961d52d
AD		 1157 if (rdev->flags & RADEON_IS_IGP) {
1158 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1159 base <<= 24;
1160 }
d594e46a 1161 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1162 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1163 radeon_gtt_location(rdev, mc);
1164 }
1165}
1166
1109ca09 1167static int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1168{
3ce0a23d 1169 u32 tmp;
5885b7a9 1170 int chansize, numchan;
771fe6b9 1171
3ce0a23d 1172 /* Get VRAM informations */
771fe6b9 1173 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1174 tmp = RREG32(RAMCFG);
1175 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1176 chansize = 16;
3ce0a23d 1177 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1178 chansize = 64;
1179 } else {
1180 chansize = 32;
1181 }
5885b7a9
AD		 1182 tmp = RREG32(CHMAP);
1183 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1184 case 0:
1185 default:
1186 numchan = 1;
1187 break;
1188 case 1:
1189 numchan = 2;
1190 break;
1191 case 2:
1192 numchan = 4;
1193 break;
1194 case 3:
1195 numchan = 8;
1196 break;
771fe6b9 1197 }
5885b7a9 1198 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1199 /* Could aper size report 0 ? */
01d73a69
JC		 1200 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1201 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1202 /* Setup GPU memory space */
1203 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1204 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1205 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1206 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1207
f892034a
AD		 1208 if (rdev->flags & RADEON_IS_IGP) {
1209 rs690_pm_info(rdev);
06b6476d 1210 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1211 }
f47299c5 1212 radeon_update_bandwidth_info(rdev);
3ce0a23d 1213 return 0;
771fe6b9
JG		 1214}
1215
16cdf04d
AD		 1216int r600_vram_scratch_init(struct radeon_device *rdev)
1217{
1218 int r;
1219
1220 if (rdev->vram_scratch.robj == NULL) {
1221 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1222 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
40f5cf99 1223 NULL, &rdev->vram_scratch.robj);
16cdf04d
AD		 1224 if (r) {
1225 return r;
1226 }
1227 }
1228
1229 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1230 if (unlikely(r != 0))
1231 return r;
1232 r = radeon_bo_pin(rdev->vram_scratch.robj,
1233 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1234 if (r) {
1235 radeon_bo_unreserve(rdev->vram_scratch.robj);
1236 return r;
1237 }
1238 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1239 (void **)&rdev->vram_scratch.ptr);
1240 if (r)
1241 radeon_bo_unpin(rdev->vram_scratch.robj);
1242 radeon_bo_unreserve(rdev->vram_scratch.robj);
1243
1244 return r;
1245}
1246
1247void r600_vram_scratch_fini(struct radeon_device *rdev)
1248{
1249 int r;
1250
1251 if (rdev->vram_scratch.robj == NULL) {
1252 return;
1253 }
1254 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1255 if (likely(r == 0)) {
1256 radeon_bo_kunmap(rdev->vram_scratch.robj);
1257 radeon_bo_unpin(rdev->vram_scratch.robj);
1258 radeon_bo_unreserve(rdev->vram_scratch.robj);
1259 }
1260 radeon_bo_unref(&rdev->vram_scratch.robj);
1261}
1262
410a3418
AD		 1263void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1264{
1265 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1266
1267 if (hung)
1268 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1269 else
1270 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1271
1272 WREG32(R600_BIOS_3_SCRATCH, tmp);
1273}
1274
d3cb781e 1275static void r600_print_gpu_status_regs(struct radeon_device *rdev)
771fe6b9 1276{
64c56e8c 1277 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
d3cb781e 1278 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1279 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
d3cb781e 1280 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1281 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
d3cb781e 1282 RREG32(R_000E50_SRBM_STATUS));
440a7cd8 1283 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
d3cb781e 1284 RREG32(CP_STALLED_STAT1));
440a7cd8 1285 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
d3cb781e 1286 RREG32(CP_STALLED_STAT2));
440a7cd8 1287 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
d3cb781e 1288 RREG32(CP_BUSY_STAT));
440a7cd8 1289 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
d3cb781e 1290 RREG32(CP_STAT));
71e3d157
AD		 1291 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1292 RREG32(DMA_STATUS_REG));
1293}
1294
f13f7731 1295static bool r600_is_display_hung(struct radeon_device *rdev)
71e3d157 1296{
f13f7731
AD		 1297 u32 crtc_hung = 0;
1298 u32 crtc_status[2];
1299 u32 i, j, tmp;
1300
1301 for (i = 0; i < rdev->num_crtc; i++) {
1302 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1303 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1304 crtc_hung |= (1 << i);
1305 }
1306 }
1307
1308 for (j = 0; j < 10; j++) {
1309 for (i = 0; i < rdev->num_crtc; i++) {
1310 if (crtc_hung & (1 << i)) {
1311 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1312 if (tmp != crtc_status[i])
1313 crtc_hung &= ~(1 << i);
1314 }
1315 }
1316 if (crtc_hung == 0)
1317 return false;
1318 udelay(100);
1319 }
1320
1321 return true;
1322}
1323
1324static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1325{
1326 u32 reset_mask = 0;
d3cb781e 1327 u32 tmp;
71e3d157 1328
f13f7731
AD		 1329 /* GRBM_STATUS */
1330 tmp = RREG32(R_008010_GRBM_STATUS);
1331 if (rdev->family >= CHIP_RV770) {
1332 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1333 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1334 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1335 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1336 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1337 reset_mask |= RADEON_RESET_GFX;
1338 } else {
1339 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1340 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1341 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1342 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1343 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1344 reset_mask |= RADEON_RESET_GFX;
1345 }
1346
1347 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1348 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1349 reset_mask |= RADEON_RESET_CP;
1350
1351 if (G_008010_GRBM_EE_BUSY(tmp))
1352 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1353
1354 /* DMA_STATUS_REG */
1355 tmp = RREG32(DMA_STATUS_REG);
1356 if (!(tmp & DMA_IDLE))
1357 reset_mask |= RADEON_RESET_DMA;
1358
1359 /* SRBM_STATUS */
1360 tmp = RREG32(R_000E50_SRBM_STATUS);
1361 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1362 reset_mask |= RADEON_RESET_RLC;
1363
1364 if (G_000E50_IH_BUSY(tmp))
1365 reset_mask |= RADEON_RESET_IH;
1366
1367 if (G_000E50_SEM_BUSY(tmp))
1368 reset_mask |= RADEON_RESET_SEM;
19fc42ed 1369
f13f7731
AD		 1370 if (G_000E50_GRBM_RQ_PENDING(tmp))
1371 reset_mask |= RADEON_RESET_GRBM;
1372
1373 if (G_000E50_VMC_BUSY(tmp))
1374 reset_mask |= RADEON_RESET_VMC;
1375
1376 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1377 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1378 G_000E50_MCDW_BUSY(tmp))
1379 reset_mask |= RADEON_RESET_MC;
1380
1381 if (r600_is_display_hung(rdev))
1382 reset_mask |= RADEON_RESET_DISPLAY;
1383
1384 return reset_mask;
1385}
1386
1387static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1388{
1389 struct rv515_mc_save save;
1390 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1391 u32 tmp;
19fc42ed 1392
71e3d157 1393 if (reset_mask == 0)
f13f7731 1394 return;
71e3d157
AD		 1395
1396 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1397
d3cb781e
AD		 1398 r600_print_gpu_status_regs(rdev);
1399
71e3d157
AD		 1400 rv515_mc_stop(rdev, &save);
1401 if (r600_mc_wait_for_idle(rdev)) {
1402 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1403 }
1404
d3cb781e
AD		 1405 /* Disable CP parsing/prefetching */
1406 if (rdev->family >= CHIP_RV770)
1407 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1408 else
1409 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1410
1411 /* disable the RLC */
1412 WREG32(RLC_CNTL, 0);
1413
1414 if (reset_mask & RADEON_RESET_DMA) {
1415 /* Disable DMA */
1416 tmp = RREG32(DMA_RB_CNTL);
1417 tmp &= ~DMA_RB_ENABLE;
1418 WREG32(DMA_RB_CNTL, tmp);
1419 }
1420
1421 mdelay(50);
1422
1423 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1424 if (rdev->family >= CHIP_RV770)
1425 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1426 S_008020_SOFT_RESET_CB(1) |
1427 S_008020_SOFT_RESET_PA(1) |
1428 S_008020_SOFT_RESET_SC(1) |
1429 S_008020_SOFT_RESET_SPI(1) |
1430 S_008020_SOFT_RESET_SX(1) |
1431 S_008020_SOFT_RESET_SH(1) |
1432 S_008020_SOFT_RESET_TC(1) |
1433 S_008020_SOFT_RESET_TA(1) |
1434 S_008020_SOFT_RESET_VC(1) |
1435 S_008020_SOFT_RESET_VGT(1);
1436 else
1437 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1438 S_008020_SOFT_RESET_DB(1) |
1439 S_008020_SOFT_RESET_CB(1) |
1440 S_008020_SOFT_RESET_PA(1) |
1441 S_008020_SOFT_RESET_SC(1) |
1442 S_008020_SOFT_RESET_SMX(1) |
1443 S_008020_SOFT_RESET_SPI(1) |
1444 S_008020_SOFT_RESET_SX(1) |
1445 S_008020_SOFT_RESET_SH(1) |
1446 S_008020_SOFT_RESET_TC(1) |
1447 S_008020_SOFT_RESET_TA(1) |
1448 S_008020_SOFT_RESET_VC(1) |
1449 S_008020_SOFT_RESET_VGT(1);
1450 }
1451
1452 if (reset_mask & RADEON_RESET_CP) {
1453 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1454 S_008020_SOFT_RESET_VGT(1);
1455
1456 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1457 }
1458
1459 if (reset_mask & RADEON_RESET_DMA) {
1460 if (rdev->family >= CHIP_RV770)
1461 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1462 else
1463 srbm_soft_reset |= SOFT_RESET_DMA;
1464 }
1465
f13f7731
AD		 1466 if (reset_mask & RADEON_RESET_RLC)
1467 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1468
1469 if (reset_mask & RADEON_RESET_SEM)
1470 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1471
1472 if (reset_mask & RADEON_RESET_IH)
1473 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1474
1475 if (reset_mask & RADEON_RESET_GRBM)
1476 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1477
1478 if (reset_mask & RADEON_RESET_MC)
1479 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1480
1481 if (reset_mask & RADEON_RESET_VMC)
1482 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1483
d3cb781e
AD		 1484 if (grbm_soft_reset) {
1485 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1486 tmp |= grbm_soft_reset;
1487 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1488 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1489 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1490
1491 udelay(50);
1492
1493 tmp &= ~grbm_soft_reset;
1494 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1495 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1496 }
1497
1498 if (srbm_soft_reset) {
1499 tmp = RREG32(SRBM_SOFT_RESET);
1500 tmp |= srbm_soft_reset;
1501 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1502 WREG32(SRBM_SOFT_RESET, tmp);
1503 tmp = RREG32(SRBM_SOFT_RESET);
1504
1505 udelay(50);
71e3d157 1506
d3cb781e
AD		 1507 tmp &= ~srbm_soft_reset;
1508 WREG32(SRBM_SOFT_RESET, tmp);
1509 tmp = RREG32(SRBM_SOFT_RESET);
1510 }
71e3d157
AD		 1511
1512 /* Wait a little for things to settle down */
1513 mdelay(1);
1514
a3c1945a 1515 rv515_mc_resume(rdev, &save);
d3cb781e 1516 udelay(50);
410a3418 1517
d3cb781e 1518 r600_print_gpu_status_regs(rdev);
d3cb781e
AD		 1519}
1520
1521int r600_asic_reset(struct radeon_device *rdev)
1522{
f13f7731
AD		 1523 u32 reset_mask;
1524
1525 reset_mask = r600_gpu_check_soft_reset(rdev);
1526
1527 if (reset_mask)
1528 r600_set_bios_scratch_engine_hung(rdev, true);
1529
1530 r600_gpu_soft_reset(rdev, reset_mask);
1531
1532 reset_mask = r600_gpu_check_soft_reset(rdev);
1533
1534 if (!reset_mask)
1535 r600_set_bios_scratch_engine_hung(rdev, false);
1536
1537 return 0;
3ce0a23d
JG		 1538}
1539
e32eb50d 1540bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8
JG		 1541{
1542 u32 srbm_status;
1543 u32 grbm_status;
1544 u32 grbm_status2;
225758d8
JG		 1545
1546 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1547 grbm_status = RREG32(R_008010_GRBM_STATUS);
1548 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1549 if (!G_008010_GUI_ACTIVE(grbm_status)) {
069211e5 1550 radeon_ring_lockup_update(ring);
225758d8
JG		 1551 return false;
1552 }
1553 /* force CP activities */
7b9ef16b 1554 radeon_ring_force_activity(rdev, ring);
069211e5 1555 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1556}
1557
4d75658b
AD		 1558/**
1559 * r600_dma_is_lockup - Check if the DMA engine is locked up
1560 *
1561 * @rdev: radeon_device pointer
1562 * @ring: radeon_ring structure holding ring information
1563 *
1564 * Check if the async DMA engine is locked up (r6xx-evergreen).
1565 * Returns true if the engine appears to be locked up, false if not.
1566 */
1567bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1568{
1569 u32 dma_status_reg;
1570
1571 dma_status_reg = RREG32(DMA_STATUS_REG);
1572 if (dma_status_reg & DMA_IDLE) {
1573 radeon_ring_lockup_update(ring);
1574 return false;
1575 }
1576 /* force ring activities */
1577 radeon_ring_force_activity(rdev, ring);
1578 return radeon_ring_test_lockup(rdev, ring);
1579}
1580
416a2bd2
AD		 1581u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1582 u32 tiling_pipe_num,
1583 u32 max_rb_num,
1584 u32 total_max_rb_num,
1585 u32 disabled_rb_mask)
3ce0a23d 1586{
416a2bd2 1587 u32 rendering_pipe_num, rb_num_width, req_rb_num;
f689e3ac 1588 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
416a2bd2
AD		 1589 u32 data = 0, mask = 1 << (max_rb_num - 1);
1590 unsigned i, j;
3ce0a23d 1591
416a2bd2 1592 /* mask out the RBs that don't exist on that asic */
f689e3ac
MT		 1593 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1594 /* make sure at least one RB is available */
1595 if ((tmp & 0xff) != 0xff)
1596 disabled_rb_mask = tmp;
3ce0a23d 1597
416a2bd2
AD		 1598 rendering_pipe_num = 1 << tiling_pipe_num;
1599 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1600 BUG_ON(rendering_pipe_num < req_rb_num);
3ce0a23d 1601
416a2bd2
AD		 1602 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1603 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
3ce0a23d 1604
416a2bd2
AD		 1605 if (rdev->family <= CHIP_RV740) {
1606 /* r6xx/r7xx */
1607 rb_num_width = 2;
1608 } else {
1609 /* eg+ */
1610 rb_num_width = 4;
1611 }
3ce0a23d 1612
416a2bd2
AD		 1613 for (i = 0; i < max_rb_num; i++) {
1614 if (!(mask & disabled_rb_mask)) {
1615 for (j = 0; j < pipe_rb_ratio; j++) {
1616 data <<= rb_num_width;
1617 data |= max_rb_num - i - 1;
1618 }
1619 if (pipe_rb_remain) {
1620 data <<= rb_num_width;
1621 data |= max_rb_num - i - 1;
1622 pipe_rb_remain--;
1623 }
1624 }
1625 mask >>= 1;
3ce0a23d
JG		 1626 }
1627
416a2bd2 1628 return data;
3ce0a23d
JG		 1629}
1630
1631int r600_count_pipe_bits(uint32_t val)
1632{
ef8cf3a1 1633 return hweight32(val);
771fe6b9
JG		 1634}
1635
1109ca09 1636static void r600_gpu_init(struct radeon_device *rdev)
3ce0a23d
JG		 1637{
1638 u32 tiling_config;
1639 u32 ramcfg;
d03f5d59
AD		 1640 u32 cc_rb_backend_disable;
1641 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1642 u32 tmp;
1643 int i, j;
1644 u32 sq_config;
1645 u32 sq_gpr_resource_mgmt_1 = 0;
1646 u32 sq_gpr_resource_mgmt_2 = 0;
1647 u32 sq_thread_resource_mgmt = 0;
1648 u32 sq_stack_resource_mgmt_1 = 0;
1649 u32 sq_stack_resource_mgmt_2 = 0;
416a2bd2 1650 u32 disabled_rb_mask;
3ce0a23d 1651
416a2bd2 1652 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1653 switch (rdev->family) {
1654 case CHIP_R600:
1655 rdev->config.r600.max_pipes = 4;
1656 rdev->config.r600.max_tile_pipes = 8;
1657 rdev->config.r600.max_simds = 4;
1658 rdev->config.r600.max_backends = 4;
1659 rdev->config.r600.max_gprs = 256;
1660 rdev->config.r600.max_threads = 192;
1661 rdev->config.r600.max_stack_entries = 256;
1662 rdev->config.r600.max_hw_contexts = 8;
1663 rdev->config.r600.max_gs_threads = 16;
1664 rdev->config.r600.sx_max_export_size = 128;
1665 rdev->config.r600.sx_max_export_pos_size = 16;
1666 rdev->config.r600.sx_max_export_smx_size = 128;
1667 rdev->config.r600.sq_num_cf_insts = 2;
1668 break;
1669 case CHIP_RV630:
1670 case CHIP_RV635:
1671 rdev->config.r600.max_pipes = 2;
1672 rdev->config.r600.max_tile_pipes = 2;
1673 rdev->config.r600.max_simds = 3;
1674 rdev->config.r600.max_backends = 1;
1675 rdev->config.r600.max_gprs = 128;
1676 rdev->config.r600.max_threads = 192;
1677 rdev->config.r600.max_stack_entries = 128;
1678 rdev->config.r600.max_hw_contexts = 8;
1679 rdev->config.r600.max_gs_threads = 4;
1680 rdev->config.r600.sx_max_export_size = 128;
1681 rdev->config.r600.sx_max_export_pos_size = 16;
1682 rdev->config.r600.sx_max_export_smx_size = 128;
1683 rdev->config.r600.sq_num_cf_insts = 2;
1684 break;
1685 case CHIP_RV610:
1686 case CHIP_RV620:
1687 case CHIP_RS780:
1688 case CHIP_RS880:
1689 rdev->config.r600.max_pipes = 1;
1690 rdev->config.r600.max_tile_pipes = 1;
1691 rdev->config.r600.max_simds = 2;
1692 rdev->config.r600.max_backends = 1;
1693 rdev->config.r600.max_gprs = 128;
1694 rdev->config.r600.max_threads = 192;
1695 rdev->config.r600.max_stack_entries = 128;
1696 rdev->config.r600.max_hw_contexts = 4;
1697 rdev->config.r600.max_gs_threads = 4;
1698 rdev->config.r600.sx_max_export_size = 128;
1699 rdev->config.r600.sx_max_export_pos_size = 16;
1700 rdev->config.r600.sx_max_export_smx_size = 128;
1701 rdev->config.r600.sq_num_cf_insts = 1;
1702 break;
1703 case CHIP_RV670:
1704 rdev->config.r600.max_pipes = 4;
1705 rdev->config.r600.max_tile_pipes = 4;
1706 rdev->config.r600.max_simds = 4;
1707 rdev->config.r600.max_backends = 4;
1708 rdev->config.r600.max_gprs = 192;
1709 rdev->config.r600.max_threads = 192;
1710 rdev->config.r600.max_stack_entries = 256;
1711 rdev->config.r600.max_hw_contexts = 8;
1712 rdev->config.r600.max_gs_threads = 16;
1713 rdev->config.r600.sx_max_export_size = 128;
1714 rdev->config.r600.sx_max_export_pos_size = 16;
1715 rdev->config.r600.sx_max_export_smx_size = 128;
1716 rdev->config.r600.sq_num_cf_insts = 2;
1717 break;
1718 default:
1719 break;
1720 }
1721
1722 /* Initialize HDP */
1723 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1724 WREG32((0x2c14 + j), 0x00000000);
1725 WREG32((0x2c18 + j), 0x00000000);
1726 WREG32((0x2c1c + j), 0x00000000);
1727 WREG32((0x2c20 + j), 0x00000000);
1728 WREG32((0x2c24 + j), 0x00000000);
1729 }
1730
1731 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1732
1733 /* Setup tiling */
1734 tiling_config = 0;
1735 ramcfg = RREG32(RAMCFG);
1736 switch (rdev->config.r600.max_tile_pipes) {
1737 case 1:
1738 tiling_config |= PIPE_TILING(0);
1739 break;
1740 case 2:
1741 tiling_config |= PIPE_TILING(1);
1742 break;
1743 case 4:
1744 tiling_config |= PIPE_TILING(2);
1745 break;
1746 case 8:
1747 tiling_config |= PIPE_TILING(3);
1748 break;
1749 default:
1750 break;
1751 }
d03f5d59 1752 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1753 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1754 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1 1755 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
416a2bd2 1756
3ce0a23d
JG		 1757 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1758 if (tmp > 3) {
1759 tiling_config |= ROW_TILING(3);
1760 tiling_config |= SAMPLE_SPLIT(3);
1761 } else {
1762 tiling_config |= ROW_TILING(tmp);
1763 tiling_config |= SAMPLE_SPLIT(tmp);
1764 }
1765 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1766
1767 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
416a2bd2
AD		 1768 tmp = R6XX_MAX_BACKENDS -
1769 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1770 if (tmp < rdev->config.r600.max_backends) {
1771 rdev->config.r600.max_backends = tmp;
1772 }
1773
1774 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1775 tmp = R6XX_MAX_PIPES -
1776 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1777 if (tmp < rdev->config.r600.max_pipes) {
1778 rdev->config.r600.max_pipes = tmp;
1779 }
1780 tmp = R6XX_MAX_SIMDS -
1781 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1782 if (tmp < rdev->config.r600.max_simds) {
1783 rdev->config.r600.max_simds = tmp;
1784 }
1785
1786 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1787 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1788 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1789 R6XX_MAX_BACKENDS, disabled_rb_mask);
1790 tiling_config |= tmp << 16;
1791 rdev->config.r600.backend_map = tmp;
1792
e7aeeba6 1793 rdev->config.r600.tile_config = tiling_config;
3ce0a23d
JG		 1794 WREG32(GB_TILING_CONFIG, tiling_config);
1795 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1796 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
4d75658b 1797 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
3ce0a23d 1798
d03f5d59 1799 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1800 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1801 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1802
1803 /* Setup some CP states */
1804 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1805 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1806
1807 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1808 SYNC_WALKER | SYNC_ALIGNER));
1809 /* Setup various GPU states */
1810 if (rdev->family == CHIP_RV670)
1811 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1812
1813 tmp = RREG32(SX_DEBUG_1);
1814 tmp |= SMX_EVENT_RELEASE;
1815 if ((rdev->family > CHIP_R600))
1816 tmp |= ENABLE_NEW_SMX_ADDRESS;
1817 WREG32(SX_DEBUG_1, tmp);
1818
1819 if (((rdev->family) == CHIP_R600) ||
1820 ((rdev->family) == CHIP_RV630) ||
1821 ((rdev->family) == CHIP_RV610) ||
1822 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1823 ((rdev->family) == CHIP_RS780) ||
1824 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1825 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1826 } else {
1827 WREG32(DB_DEBUG, 0);
1828 }
1829 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1830 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1831
1832 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1833 WREG32(VGT_NUM_INSTANCES, 0);
1834
1835 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1836 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1837
1838 tmp = RREG32(SQ_MS_FIFO_SIZES);
1839 if (((rdev->family) == CHIP_RV610) ||
1840 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1841 ((rdev->family) == CHIP_RS780) ||
1842 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1843 tmp = (CACHE_FIFO_SIZE(0xa) |
1844 FETCH_FIFO_HIWATER(0xa) |
1845 DONE_FIFO_HIWATER(0xe0) |
1846 ALU_UPDATE_FIFO_HIWATER(0x8));
1847 } else if (((rdev->family) == CHIP_R600) ||
1848 ((rdev->family) == CHIP_RV630)) {
1849 tmp &= ~DONE_FIFO_HIWATER(0xff);
1850 tmp |= DONE_FIFO_HIWATER(0x4);
1851 }
1852 WREG32(SQ_MS_FIFO_SIZES, tmp);
1853
1854 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1855 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1856 */
1857 sq_config = RREG32(SQ_CONFIG);
1858 sq_config &= ~(PS_PRIO(3) |
1859 VS_PRIO(3) |
1860 GS_PRIO(3) |
1861 ES_PRIO(3));
1862 sq_config |= (DX9_CONSTS |
1863 VC_ENABLE |
1864 PS_PRIO(0) |
1865 VS_PRIO(1) |
1866 GS_PRIO(2) |
1867 ES_PRIO(3));
1868
1869 if ((rdev->family) == CHIP_R600) {
1870 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1871 NUM_VS_GPRS(124) |
1872 NUM_CLAUSE_TEMP_GPRS(4));
1873 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1874 NUM_ES_GPRS(0));
1875 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1876 NUM_VS_THREADS(48) |
1877 NUM_GS_THREADS(4) |
1878 NUM_ES_THREADS(4));
1879 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1880 NUM_VS_STACK_ENTRIES(128));
1881 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1882 NUM_ES_STACK_ENTRIES(0));
1883 } else if (((rdev->family) == CHIP_RV610) ||
1884 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1885 ((rdev->family) == CHIP_RS780) ||
1886 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1887 /* no vertex cache */
1888 sq_config &= ~VC_ENABLE;
1889
1890 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1891 NUM_VS_GPRS(44) |
1892 NUM_CLAUSE_TEMP_GPRS(2));
1893 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1894 NUM_ES_GPRS(17));
1895 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1896 NUM_VS_THREADS(78) |
1897 NUM_GS_THREADS(4) |
1898 NUM_ES_THREADS(31));
1899 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1900 NUM_VS_STACK_ENTRIES(40));
1901 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1902 NUM_ES_STACK_ENTRIES(16));
1903 } else if (((rdev->family) == CHIP_RV630) ||
1904 ((rdev->family) == CHIP_RV635)) {
1905 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1906 NUM_VS_GPRS(44) |
1907 NUM_CLAUSE_TEMP_GPRS(2));
1908 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1909 NUM_ES_GPRS(18));
1910 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1911 NUM_VS_THREADS(78) |
1912 NUM_GS_THREADS(4) |
1913 NUM_ES_THREADS(31));
1914 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1915 NUM_VS_STACK_ENTRIES(40));
1916 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1917 NUM_ES_STACK_ENTRIES(16));
1918 } else if ((rdev->family) == CHIP_RV670) {
1919 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1920 NUM_VS_GPRS(44) |
1921 NUM_CLAUSE_TEMP_GPRS(2));
1922 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1923 NUM_ES_GPRS(17));
1924 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1925 NUM_VS_THREADS(78) |
1926 NUM_GS_THREADS(4) |
1927 NUM_ES_THREADS(31));
1928 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1929 NUM_VS_STACK_ENTRIES(64));
1930 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1931 NUM_ES_STACK_ENTRIES(64));
1932 }
1933
1934 WREG32(SQ_CONFIG, sq_config);
1935 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1936 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1937 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1938 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1939 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1940
1941 if (((rdev->family) == CHIP_RV610) ||
1942 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1943 ((rdev->family) == CHIP_RS780) ||
1944 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1945 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1946 } else {
1947 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1948 }
1949
1950 /* More default values. 2D/3D driver should adjust as needed */
1951 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1952 S1_X(0x4) | S1_Y(0xc)));
1953 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1954 S1_X(0x2) | S1_Y(0x2) |
1955 S2_X(0xa) | S2_Y(0x6) |
1956 S3_X(0x6) | S3_Y(0xa)));
1957 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1958 S1_X(0x4) | S1_Y(0xc) |
1959 S2_X(0x1) | S2_Y(0x6) |
1960 S3_X(0xa) | S3_Y(0xe)));
1961 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1962 S5_X(0x0) | S5_Y(0x0) |
1963 S6_X(0xb) | S6_Y(0x4) |
1964 S7_X(0x7) | S7_Y(0x8)));
1965
1966 WREG32(VGT_STRMOUT_EN, 0);
1967 tmp = rdev->config.r600.max_pipes * 16;
1968 switch (rdev->family) {
1969 case CHIP_RV610:
3ce0a23d 1970 case CHIP_RV620:
ee59f2b4
AD		 1971 case CHIP_RS780:
1972 case CHIP_RS880:
3ce0a23d
JG		 1973 tmp += 32;
1974 break;
1975 case CHIP_RV670:
1976 tmp += 128;
1977 break;
1978 default:
1979 break;
1980 }
1981 if (tmp > 256) {
1982 tmp = 256;
1983 }
1984 WREG32(VGT_ES_PER_GS, 128);
1985 WREG32(VGT_GS_PER_ES, tmp);
1986 WREG32(VGT_GS_PER_VS, 2);
1987 WREG32(VGT_GS_VERTEX_REUSE, 16);
1988
1989 /* more default values. 2D/3D driver should adjust as needed */
1990 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1991 WREG32(VGT_STRMOUT_EN, 0);
1992 WREG32(SX_MISC, 0);
1993 WREG32(PA_SC_MODE_CNTL, 0);
1994 WREG32(PA_SC_AA_CONFIG, 0);
1995 WREG32(PA_SC_LINE_STIPPLE, 0);
1996 WREG32(SPI_INPUT_Z, 0);
1997 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1998 WREG32(CB_COLOR7_FRAG, 0);
1999
2000 /* Clear render buffer base addresses */
2001 WREG32(CB_COLOR0_BASE, 0);
2002 WREG32(CB_COLOR1_BASE, 0);
2003 WREG32(CB_COLOR2_BASE, 0);
2004 WREG32(CB_COLOR3_BASE, 0);
2005 WREG32(CB_COLOR4_BASE, 0);
2006 WREG32(CB_COLOR5_BASE, 0);
2007 WREG32(CB_COLOR6_BASE, 0);
2008 WREG32(CB_COLOR7_BASE, 0);
2009 WREG32(CB_COLOR7_FRAG, 0);
2010
2011 switch (rdev->family) {
2012 case CHIP_RV610:
3ce0a23d 2013 case CHIP_RV620:
ee59f2b4
AD		 2014 case CHIP_RS780:
2015 case CHIP_RS880:
3ce0a23d
JG		 2016 tmp = TC_L2_SIZE(8);
2017 break;
2018 case CHIP_RV630:
2019 case CHIP_RV635:
2020 tmp = TC_L2_SIZE(4);
2021 break;
2022 case CHIP_R600:
2023 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2024 break;
2025 default:
2026 tmp = TC_L2_SIZE(0);
2027 break;
2028 }
2029 WREG32(TC_CNTL, tmp);
2030
2031 tmp = RREG32(HDP_HOST_PATH_CNTL);
2032 WREG32(HDP_HOST_PATH_CNTL, tmp);
2033
2034 tmp = RREG32(ARB_POP);
2035 tmp |= ENABLE_TC128;
2036 WREG32(ARB_POP, tmp);
2037
2038 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2039 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2040 NUM_CLIP_SEQ(3)));
2041 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
b866d133 2042 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 2043}
2044
2045
771fe6b9
JG		 2046/*
2047 * Indirect registers accessor
2048 */
3ce0a23d
JG		 2049u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2050{
2051 u32 r;
2052
2053 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2054 (void)RREG32(PCIE_PORT_INDEX);
2055 r = RREG32(PCIE_PORT_DATA);
2056 return r;
2057}
2058
2059void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2060{
2061 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2062 (void)RREG32(PCIE_PORT_INDEX);
2063 WREG32(PCIE_PORT_DATA, (v));
2064 (void)RREG32(PCIE_PORT_DATA);
2065}
2066
3ce0a23d
JG		 2067/*
2068 * CP & Ring
2069 */
2070void r600_cp_stop(struct radeon_device *rdev)
2071{
53595338 2072 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 2073 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 2074 WREG32(SCRATCH_UMSK, 0);
4d75658b 2075 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3ce0a23d
JG		 2076}
2077
d8f60cfc 2078int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 2079{
2080 struct platform_device *pdev;
2081 const char *chip_name;
d8f60cfc
AD		 2082 const char *rlc_chip_name;
2083 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 2084 char fw_name[30];
2085 int err;
2086
2087 DRM_DEBUG("\n");
2088
2089 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
2090 err = IS_ERR(pdev);
2091 if (err) {
2092 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
2093 return -EINVAL;
2094 }
2095
2096 switch (rdev->family) {
d8f60cfc
AD		 2097 case CHIP_R600:
2098 chip_name = "R600";
2099 rlc_chip_name = "R600";
2100 break;
2101 case CHIP_RV610:
2102 chip_name = "RV610";
2103 rlc_chip_name = "R600";
2104 break;
2105 case CHIP_RV630:
2106 chip_name = "RV630";
2107 rlc_chip_name = "R600";
2108 break;
2109 case CHIP_RV620:
2110 chip_name = "RV620";
2111 rlc_chip_name = "R600";
2112 break;
2113 case CHIP_RV635:
2114 chip_name = "RV635";
2115 rlc_chip_name = "R600";
2116 break;
2117 case CHIP_RV670:
2118 chip_name = "RV670";
2119 rlc_chip_name = "R600";
2120 break;
3ce0a23d 2121 case CHIP_RS780:
d8f60cfc
AD		 2122 case CHIP_RS880:
2123 chip_name = "RS780";
2124 rlc_chip_name = "R600";
2125 break;
2126 case CHIP_RV770:
2127 chip_name = "RV770";
2128 rlc_chip_name = "R700";
2129 break;
3ce0a23d 2130 case CHIP_RV730:
d8f60cfc
AD		 2131 case CHIP_RV740:
2132 chip_name = "RV730";
2133 rlc_chip_name = "R700";
2134 break;
2135 case CHIP_RV710:
2136 chip_name = "RV710";
2137 rlc_chip_name = "R700";
2138 break;
fe251e2f
AD		 2139 case CHIP_CEDAR:
2140 chip_name = "CEDAR";
45f9a39b 2141 rlc_chip_name = "CEDAR";
fe251e2f
AD		 2142 break;
2143 case CHIP_REDWOOD:
2144 chip_name = "REDWOOD";
45f9a39b 2145 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2146 break;
2147 case CHIP_JUNIPER:
2148 chip_name = "JUNIPER";
45f9a39b 2149 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2150 break;
2151 case CHIP_CYPRESS:
2152 case CHIP_HEMLOCK:
2153 chip_name = "CYPRESS";
45f9a39b 2154 rlc_chip_name = "CYPRESS";
fe251e2f 2155 break;
439bd6cd
AD		 2156 case CHIP_PALM:
2157 chip_name = "PALM";
2158 rlc_chip_name = "SUMO";
2159 break;
d5c5a72f
AD		 2160 case CHIP_SUMO:
2161 chip_name = "SUMO";
2162 rlc_chip_name = "SUMO";
2163 break;
2164 case CHIP_SUMO2:
2165 chip_name = "SUMO2";
2166 rlc_chip_name = "SUMO";
2167 break;
3ce0a23d
JG		 2168 default: BUG();
2169 }
2170
fe251e2f
AD		 2171 if (rdev->family >= CHIP_CEDAR) {
2172 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2173 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2174 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2175 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2176 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2177 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2178 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2179 } else {
2180 pfp_req_size = PFP_UCODE_SIZE * 4;
2181 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2182 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2183 }
2184
d8f60cfc 2185 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2186
2187 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2188 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2189 if (err)
2190 goto out;
2191 if (rdev->pfp_fw->size != pfp_req_size) {
2192 printk(KERN_ERR
2193 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2194 rdev->pfp_fw->size, fw_name);
2195 err = -EINVAL;
2196 goto out;
2197 }
2198
2199 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2200 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2201 if (err)
2202 goto out;
2203 if (rdev->me_fw->size != me_req_size) {
2204 printk(KERN_ERR
2205 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2206 rdev->me_fw->size, fw_name);
2207 err = -EINVAL;
2208 }
d8f60cfc
AD		 2209
2210 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2211 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2212 if (err)
2213 goto out;
2214 if (rdev->rlc_fw->size != rlc_req_size) {
2215 printk(KERN_ERR
2216 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2217 rdev->rlc_fw->size, fw_name);
2218 err = -EINVAL;
2219 }
2220
3ce0a23d
JG		 2221out:
2222 platform_device_unregister(pdev);
2223
2224 if (err) {
2225 if (err != -EINVAL)
2226 printk(KERN_ERR
2227 "r600_cp: Failed to load firmware \"%s\"\n",
2228 fw_name);
2229 release_firmware(rdev->pfp_fw);
2230 rdev->pfp_fw = NULL;
2231 release_firmware(rdev->me_fw);
2232 rdev->me_fw = NULL;
d8f60cfc
AD		 2233 release_firmware(rdev->rlc_fw);
2234 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2235 }
2236 return err;
2237}
2238
2239static int r600_cp_load_microcode(struct radeon_device *rdev)
2240{
2241 const __be32 *fw_data;
2242 int i;
2243
2244 if (!rdev->me_fw || !rdev->pfp_fw)
2245 return -EINVAL;
2246
2247 r600_cp_stop(rdev);
2248
4eace7fd
CC		 2249 WREG32(CP_RB_CNTL,
2250#ifdef __BIG_ENDIAN
2251 BUF_SWAP_32BIT |
2252#endif
2253 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2254
2255 /* Reset cp */
2256 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2257 RREG32(GRBM_SOFT_RESET);
2258 mdelay(15);
2259 WREG32(GRBM_SOFT_RESET, 0);
2260
2261 WREG32(CP_ME_RAM_WADDR, 0);
2262
2263 fw_data = (const __be32 *)rdev->me_fw->data;
2264 WREG32(CP_ME_RAM_WADDR, 0);
2265 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2266 WREG32(CP_ME_RAM_DATA,
2267 be32_to_cpup(fw_data++));
2268
2269 fw_data = (const __be32 *)rdev->pfp_fw->data;
2270 WREG32(CP_PFP_UCODE_ADDR, 0);
2271 for (i = 0; i < PFP_UCODE_SIZE; i++)
2272 WREG32(CP_PFP_UCODE_DATA,
2273 be32_to_cpup(fw_data++));
2274
2275 WREG32(CP_PFP_UCODE_ADDR, 0);
2276 WREG32(CP_ME_RAM_WADDR, 0);
2277 WREG32(CP_ME_RAM_RADDR, 0);
2278 return 0;
2279}
2280
2281int r600_cp_start(struct radeon_device *rdev)
2282{
e32eb50d 2283 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2284 int r;
2285 uint32_t cp_me;
2286
e32eb50d 2287 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2288 if (r) {
2289 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2290 return r;
2291 }
e32eb50d
CK		 2292 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2293 radeon_ring_write(ring, 0x1);
7e7b41d2 2294 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2295 radeon_ring_write(ring, 0x0);
2296 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2297 } else {
e32eb50d
CK		 2298 radeon_ring_write(ring, 0x3);
2299 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2300 }
e32eb50d
CK		 2301 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2302 radeon_ring_write(ring, 0);
2303 radeon_ring_write(ring, 0);
2304 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2305
2306 cp_me = 0xff;
2307 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2308 return 0;
2309}
2310
2311int r600_cp_resume(struct radeon_device *rdev)
2312{
e32eb50d 2313 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2314 u32 tmp;
2315 u32 rb_bufsz;
2316 int r;
2317
2318 /* Reset cp */
2319 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2320 RREG32(GRBM_SOFT_RESET);
2321 mdelay(15);
2322 WREG32(GRBM_SOFT_RESET, 0);
2323
2324 /* Set ring buffer size */
e32eb50d 2325 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 2326 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2327#ifdef __BIG_ENDIAN
d6f28938 2328 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2329#endif
d6f28938 2330 WREG32(CP_RB_CNTL, tmp);
15d3332f 2331 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2332
2333 /* Set the write pointer delay */
2334 WREG32(CP_RB_WPTR_DELAY, 0);
2335
2336 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2337 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2338 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2339 ring->wptr = 0;
2340 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2341
2342 /* set the wb address whether it's enabled or not */
4eace7fd 2343 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2344 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2345 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2346 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2347
2348 if (rdev->wb.enabled)
2349 WREG32(SCRATCH_UMSK, 0xff);
2350 else {
2351 tmp |= RB_NO_UPDATE;
2352 WREG32(SCRATCH_UMSK, 0);
2353 }
2354
3ce0a23d
JG		 2355 mdelay(1);
2356 WREG32(CP_RB_CNTL, tmp);
2357
e32eb50d 2358 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2359 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2360
e32eb50d 2361 ring->rptr = RREG32(CP_RB_RPTR);
3ce0a23d
JG		 2362
2363 r600_cp_start(rdev);
e32eb50d 2364 ring->ready = true;
f712812e 2365 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2366 if (r) {
e32eb50d 2367 ring->ready = false;
3ce0a23d
JG		 2368 return r;
2369 }
2370 return 0;
2371}
2372
e32eb50d 2373void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2374{
2375 u32 rb_bufsz;
45df6803 2376 int r;
3ce0a23d
JG		 2377
2378 /* Align ring size */
2379 rb_bufsz = drm_order(ring_size / 8);
2380 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2381 ring->ring_size = ring_size;
2382 ring->align_mask = 16 - 1;
45df6803 2383
89d35807
AD		 2384 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2385 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2386 if (r) {
2387 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2388 ring->rptr_save_reg = 0;
2389 }
45df6803 2390 }
3ce0a23d
JG		 2391}
2392
655efd3d
JG		 2393void r600_cp_fini(struct radeon_device *rdev)
2394{
45df6803 2395 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
655efd3d 2396 r600_cp_stop(rdev);
45df6803
CK		 2397 radeon_ring_fini(rdev, ring);
2398 radeon_scratch_free(rdev, ring->rptr_save_reg);
655efd3d
JG		 2399}
2400
4d75658b
AD		 2401/*
2402 * DMA
2403 * Starting with R600, the GPU has an asynchronous
2404 * DMA engine. The programming model is very similar
2405 * to the 3D engine (ring buffer, IBs, etc.), but the
2406 * DMA controller has it's own packet format that is
2407 * different form the PM4 format used by the 3D engine.
2408 * It supports copying data, writing embedded data,
2409 * solid fills, and a number of other things. It also
2410 * has support for tiling/detiling of buffers.
2411 */
2412/**
2413 * r600_dma_stop - stop the async dma engine
2414 *
2415 * @rdev: radeon_device pointer
2416 *
2417 * Stop the async dma engine (r6xx-evergreen).
2418 */
2419void r600_dma_stop(struct radeon_device *rdev)
2420{
2421 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2422
2423 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2424
2425 rb_cntl &= ~DMA_RB_ENABLE;
2426 WREG32(DMA_RB_CNTL, rb_cntl);
2427
2428 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2429}
2430
2431/**
2432 * r600_dma_resume - setup and start the async dma engine
2433 *
2434 * @rdev: radeon_device pointer
2435 *
2436 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2437 * Returns 0 for success, error for failure.
2438 */
2439int r600_dma_resume(struct radeon_device *rdev)
2440{
2441 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
b3dfcb20 2442 u32 rb_cntl, dma_cntl, ib_cntl;
4d75658b
AD		 2443 u32 rb_bufsz;
2444 int r;
2445
2446 /* Reset dma */
2447 if (rdev->family >= CHIP_RV770)
2448 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2449 else
2450 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2451 RREG32(SRBM_SOFT_RESET);
2452 udelay(50);
2453 WREG32(SRBM_SOFT_RESET, 0);
2454
2455 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2456 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2457
2458 /* Set ring buffer size in dwords */
2459 rb_bufsz = drm_order(ring->ring_size / 4);
2460 rb_cntl = rb_bufsz << 1;
2461#ifdef __BIG_ENDIAN
2462 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2463#endif
2464 WREG32(DMA_RB_CNTL, rb_cntl);
2465
2466 /* Initialize the ring buffer's read and write pointers */
2467 WREG32(DMA_RB_RPTR, 0);
2468 WREG32(DMA_RB_WPTR, 0);
2469
2470 /* set the wb address whether it's enabled or not */
2471 WREG32(DMA_RB_RPTR_ADDR_HI,
2472 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2473 WREG32(DMA_RB_RPTR_ADDR_LO,
2474 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2475
2476 if (rdev->wb.enabled)
2477 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2478
2479 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2480
2481 /* enable DMA IBs */
b3dfcb20
MD		 2482 ib_cntl = DMA_IB_ENABLE;
2483#ifdef __BIG_ENDIAN
2484 ib_cntl |= DMA_IB_SWAP_ENABLE;
2485#endif
2486 WREG32(DMA_IB_CNTL, ib_cntl);
4d75658b
AD		 2487
2488 dma_cntl = RREG32(DMA_CNTL);
2489 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2490 WREG32(DMA_CNTL, dma_cntl);
2491
2492 if (rdev->family >= CHIP_RV770)
2493 WREG32(DMA_MODE, 1);
2494
2495 ring->wptr = 0;
2496 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2497
2498 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2499
2500 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2501
2502 ring->ready = true;
2503
2504 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2505 if (r) {
2506 ring->ready = false;
2507 return r;
2508 }
2509
2510 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2511
2512 return 0;
2513}
2514
2515/**
2516 * r600_dma_fini - tear down the async dma engine
2517 *
2518 * @rdev: radeon_device pointer
2519 *
2520 * Stop the async dma engine and free the ring (r6xx-evergreen).
2521 */
2522void r600_dma_fini(struct radeon_device *rdev)
2523{
2524 r600_dma_stop(rdev);
2525 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2526}
3ce0a23d
JG		 2527
2528/*
2529 * GPU scratch registers helpers function.
2530 */
2531void r600_scratch_init(struct radeon_device *rdev)
2532{
2533 int i;
2534
2535 rdev->scratch.num_reg = 7;
724c80e1 2536 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2537 for (i = 0; i < rdev->scratch.num_reg; i++) {
2538 rdev->scratch.free[i] = true;
724c80e1 2539 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2540 }
2541}
2542
e32eb50d 2543int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2544{
2545 uint32_t scratch;
2546 uint32_t tmp = 0;
8b25ed34 2547 unsigned i;
3ce0a23d
JG		 2548 int r;
2549
2550 r = radeon_scratch_get(rdev, &scratch);
2551 if (r) {
2552 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2553 return r;
2554 }
2555 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2556 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2557 if (r) {
8b25ed34 2558 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3ce0a23d
JG		 2559 radeon_scratch_free(rdev, scratch);
2560 return r;
2561 }
e32eb50d
CK		 2562 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2563 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2564 radeon_ring_write(ring, 0xDEADBEEF);
2565 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2566 for (i = 0; i < rdev->usec_timeout; i++) {
2567 tmp = RREG32(scratch);
2568 if (tmp == 0xDEADBEEF)
2569 break;
2570 DRM_UDELAY(1);
2571 }
2572 if (i < rdev->usec_timeout) {
8b25ed34 2573 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3ce0a23d 2574 } else {
bf852799 2575 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
8b25ed34 2576 ring->idx, scratch, tmp);
3ce0a23d
JG		 2577 r = -EINVAL;
2578 }
2579 radeon_scratch_free(rdev, scratch);
2580 return r;
2581}
2582
4d75658b
AD		 2583/**
2584 * r600_dma_ring_test - simple async dma engine test
2585 *
2586 * @rdev: radeon_device pointer
2587 * @ring: radeon_ring structure holding ring information
2588 *
2589 * Test the DMA engine by writing using it to write an
2590 * value to memory. (r6xx-SI).
2591 * Returns 0 for success, error for failure.
2592 */
2593int r600_dma_ring_test(struct radeon_device *rdev,
2594 struct radeon_ring *ring)
2595{
2596 unsigned i;
2597 int r;
2598 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2599 u32 tmp;
2600
2601 if (!ptr) {
2602 DRM_ERROR("invalid vram scratch pointer\n");
2603 return -EINVAL;
2604 }
2605
2606 tmp = 0xCAFEDEAD;
2607 writel(tmp, ptr);
2608
2609 r = radeon_ring_lock(rdev, ring, 4);
2610 if (r) {
2611 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2612 return r;
2613 }
2614 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2615 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2616 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2617 radeon_ring_write(ring, 0xDEADBEEF);
2618 radeon_ring_unlock_commit(rdev, ring);
2619
2620 for (i = 0; i < rdev->usec_timeout; i++) {
2621 tmp = readl(ptr);
2622 if (tmp == 0xDEADBEEF)
2623 break;
2624 DRM_UDELAY(1);
2625 }
2626
2627 if (i < rdev->usec_timeout) {
2628 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2629 } else {
2630 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2631 ring->idx, tmp);
2632 r = -EINVAL;
2633 }
2634 return r;
2635}
2636
2637/*
2638 * CP fences/semaphores
2639 */
2640
3ce0a23d
JG		 2641void r600_fence_ring_emit(struct radeon_device *rdev,
2642 struct radeon_fence *fence)
2643{
e32eb50d 2644 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 2645
d0f8a854 2646 if (rdev->wb.use_event) {
30eb77f4 2647 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2648 /* flush read cache over gart */
e32eb50d
CK		 2649 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2650 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2651 PACKET3_VC_ACTION_ENA |
2652 PACKET3_SH_ACTION_ENA);
2653 radeon_ring_write(ring, 0xFFFFFFFF);
2654 radeon_ring_write(ring, 0);
2655 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2656 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2657 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2658 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2659 radeon_ring_write(ring, addr & 0xffffffff);
2660 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2661 radeon_ring_write(ring, fence->seq);
2662 radeon_ring_write(ring, 0);
d0f8a854 2663 } else {
77b1bad4 2664 /* flush read cache over gart */
e32eb50d
CK		 2665 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2666 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2667 PACKET3_VC_ACTION_ENA |
2668 PACKET3_SH_ACTION_ENA);
2669 radeon_ring_write(ring, 0xFFFFFFFF);
2670 radeon_ring_write(ring, 0);
2671 radeon_ring_write(ring, 10); /* poll interval */
2672 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2673 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2674 /* wait for 3D idle clean */
e32eb50d
CK		 2675 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2676 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2677 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2678 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2679 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2680 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2681 radeon_ring_write(ring, fence->seq);
d0f8a854 2682 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2683 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2684 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2685 }
3ce0a23d
JG		 2686}
2687
15d3332f 2688void r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2689 struct radeon_ring *ring,
15d3332f 2690 struct radeon_semaphore *semaphore,
7b1f2485 2691 bool emit_wait)
15d3332f
CK		 2692{
2693 uint64_t addr = semaphore->gpu_addr;
2694 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2695
0be70439
CK		 2696 if (rdev->family < CHIP_CAYMAN)
2697 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2698
e32eb50d
CK		 2699 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2700 radeon_ring_write(ring, addr & 0xffffffff);
2701 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
15d3332f
CK		 2702}
2703
4d75658b
AD		 2704/*
2705 * DMA fences/semaphores
2706 */
2707
2708/**
2709 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2710 *
2711 * @rdev: radeon_device pointer
2712 * @fence: radeon fence object
2713 *
2714 * Add a DMA fence packet to the ring to write
2715 * the fence seq number and DMA trap packet to generate
2716 * an interrupt if needed (r6xx-r7xx).
2717 */
2718void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2719 struct radeon_fence *fence)
2720{
2721 struct radeon_ring *ring = &rdev->ring[fence->ring];
2722 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
86a1881d 2723
4d75658b
AD		 2724 /* write the fence */
2725 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2726 radeon_ring_write(ring, addr & 0xfffffffc);
2727 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
86a1881d 2728 radeon_ring_write(ring, lower_32_bits(fence->seq));
4d75658b
AD		 2729 /* generate an interrupt */
2730 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2731}
2732
2733/**
2734 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2735 *
2736 * @rdev: radeon_device pointer
2737 * @ring: radeon_ring structure holding ring information
2738 * @semaphore: radeon semaphore object
2739 * @emit_wait: wait or signal semaphore
2740 *
2741 * Add a DMA semaphore packet to the ring wait on or signal
2742 * other rings (r6xx-SI).
2743 */
2744void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2745 struct radeon_ring *ring,
2746 struct radeon_semaphore *semaphore,
2747 bool emit_wait)
2748{
2749 u64 addr = semaphore->gpu_addr;
2750 u32 s = emit_wait ? 0 : 1;
2751
2752 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2753 radeon_ring_write(ring, addr & 0xfffffffc);
2754 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2755}
2756
3ce0a23d 2757int r600_copy_blit(struct radeon_device *rdev,
003cefe0
AD		 2758 uint64_t src_offset,
2759 uint64_t dst_offset,
2760 unsigned num_gpu_pages,
876dc9f3 2761 struct radeon_fence **fence)
3ce0a23d 2762{
220907d9 2763 struct radeon_semaphore *sem = NULL;
f237750f 2764 struct radeon_sa_bo *vb = NULL;
ff82f052
JG		 2765 int r;
2766
220907d9 2767 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
ff82f052 2768 if (r) {
ff82f052
JG		 2769 return r;
2770 }
f237750f 2771 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
220907d9 2772 r600_blit_done_copy(rdev, fence, vb, sem);
3ce0a23d
JG		 2773 return 0;
2774}
2775
4d75658b
AD		 2776/**
2777 * r600_copy_dma - copy pages using the DMA engine
2778 *
2779 * @rdev: radeon_device pointer
2780 * @src_offset: src GPU address
2781 * @dst_offset: dst GPU address
2782 * @num_gpu_pages: number of GPU pages to xfer
2783 * @fence: radeon fence object
2784 *
43fb7787 2785 * Copy GPU paging using the DMA engine (r6xx).
4d75658b
AD		 2786 * Used by the radeon ttm implementation to move pages if
2787 * registered as the asic copy callback.
2788 */
2789int r600_copy_dma(struct radeon_device *rdev,
2790 uint64_t src_offset, uint64_t dst_offset,
2791 unsigned num_gpu_pages,
2792 struct radeon_fence **fence)
2793{
2794 struct radeon_semaphore *sem = NULL;
2795 int ring_index = rdev->asic->copy.dma_ring_index;
2796 struct radeon_ring *ring = &rdev->ring[ring_index];
2797 u32 size_in_dw, cur_size_in_dw;
2798 int i, num_loops;
2799 int r = 0;
2800
2801 r = radeon_semaphore_create(rdev, &sem);
2802 if (r) {
2803 DRM_ERROR("radeon: moving bo (%d).\n", r);
2804 return r;
2805 }
2806
2807 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
43fb7787
AD		 2808 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
2809 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
4d75658b
AD		 2810 if (r) {
2811 DRM_ERROR("radeon: moving bo (%d).\n", r);
2812 radeon_semaphore_free(rdev, &sem, NULL);
2813 return r;
2814 }
2815
2816 if (radeon_fence_need_sync(*fence, ring->idx)) {
2817 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2818 ring->idx);
2819 radeon_fence_note_sync(*fence, ring->idx);
2820 } else {
2821 radeon_semaphore_free(rdev, &sem, NULL);
2822 }
2823
2824 for (i = 0; i < num_loops; i++) {
2825 cur_size_in_dw = size_in_dw;
909d9eb6
AD		 2826 if (cur_size_in_dw > 0xFFFE)
2827 cur_size_in_dw = 0xFFFE;
4d75658b
AD		 2828 size_in_dw -= cur_size_in_dw;
2829 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2830 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2831 radeon_ring_write(ring, src_offset & 0xfffffffc);
43fb7787
AD		 2832 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2833 (upper_32_bits(src_offset) & 0xff)));
4d75658b
AD		 2834 src_offset += cur_size_in_dw * 4;
2835 dst_offset += cur_size_in_dw * 4;
2836 }
2837
2838 r = radeon_fence_emit(rdev, fence, ring->idx);
2839 if (r) {
2840 radeon_ring_unlock_undo(rdev, ring);
2841 return r;
2842 }
2843
2844 radeon_ring_unlock_commit(rdev, ring);
2845 radeon_semaphore_free(rdev, &sem, *fence);
2846
2847 return r;
2848}
2849
3ce0a23d
JG		 2850int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2851 uint32_t tiling_flags, uint32_t pitch,
2852 uint32_t offset, uint32_t obj_size)
2853{
2854 /* FIXME: implement */
2855 return 0;
2856}
2857
2858void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2859{
2860 /* FIXME: implement */
2861}
2862
1109ca09 2863static int r600_startup(struct radeon_device *rdev)
3ce0a23d 2864{
4d75658b 2865 struct radeon_ring *ring;
3ce0a23d
JG		 2866 int r;
2867
9e46a48d
AD		 2868 /* enable pcie gen2 link */
2869 r600_pcie_gen2_enable(rdev);
2870
779720a3
AD		 2871 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2872 r = r600_init_microcode(rdev);
2873 if (r) {
2874 DRM_ERROR("Failed to load firmware!\n");
2875 return r;
2876 }
2877 }
2878
16cdf04d
AD		 2879 r = r600_vram_scratch_init(rdev);
2880 if (r)
2881 return r;
2882
a3c1945a 2883 r600_mc_program(rdev);
1a029b76
JG		 2884 if (rdev->flags & RADEON_IS_AGP) {
2885 r600_agp_enable(rdev);
2886 } else {
2887 r = r600_pcie_gart_enable(rdev);
2888 if (r)
2889 return r;
2890 }
3ce0a23d 2891 r600_gpu_init(rdev);
c38c7b64
JG		 2892 r = r600_blit_init(rdev);
2893 if (r) {
2894 r600_blit_fini(rdev);
27cd7769 2895 rdev->asic->copy.copy = NULL;
c38c7b64
JG		 2896 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2897 }
b70d6bb3 2898
724c80e1
AD		 2899 /* allocate wb buffer */
2900 r = radeon_wb_init(rdev);
2901 if (r)
2902 return r;
2903
30eb77f4
JG		 2904 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2905 if (r) {
2906 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2907 return r;
2908 }
2909
4d75658b
AD		 2910 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2911 if (r) {
2912 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2913 return r;
2914 }
2915
d8f60cfc 2916 /* Enable IRQ */
d8f60cfc
AD		 2917 r = r600_irq_init(rdev);
2918 if (r) {
2919 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2920 radeon_irq_kms_fini(rdev);
2921 return r;
2922 }
2923 r600_irq_set(rdev);
2924
4d75658b 2925 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 2926 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 2927 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2928 0, 0xfffff, RADEON_CP_PACKET2);
4d75658b
AD		 2929 if (r)
2930 return r;
5596a9db 2931
4d75658b
AD		 2932 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2933 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2934 DMA_RB_RPTR, DMA_RB_WPTR,
2935 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3ce0a23d
JG		 2936 if (r)
2937 return r;
4d75658b 2938
3ce0a23d
JG		 2939 r = r600_cp_load_microcode(rdev);
2940 if (r)
2941 return r;
2942 r = r600_cp_resume(rdev);
2943 if (r)
2944 return r;
724c80e1 2945
4d75658b
AD		 2946 r = r600_dma_resume(rdev);
2947 if (r)
2948 return r;
2949
2898c348
CK		 2950 r = radeon_ib_pool_init(rdev);
2951 if (r) {
2952 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 2953 return r;
2898c348 2954 }
b15ba512 2955
d4e30ef0
AD		 2956 r = r600_audio_init(rdev);
2957 if (r) {
2958 DRM_ERROR("radeon: audio init failed\n");
2959 return r;
2960 }
2961
3ce0a23d
JG		 2962 return 0;
2963}
2964
28d52043
DA		 2965void r600_vga_set_state(struct radeon_device *rdev, bool state)
2966{
2967 uint32_t temp;
2968
2969 temp = RREG32(CONFIG_CNTL);
2970 if (state == false) {
2971 temp &= ~(1<<0);
2972 temp |= (1<<1);
2973 } else {
2974 temp &= ~(1<<1);
2975 }
2976 WREG32(CONFIG_CNTL, temp);
2977}
2978
fc30b8ef
DA		 2979int r600_resume(struct radeon_device *rdev)
2980{
2981 int r;
2982
1a029b76
JG		 2983 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2984 * posting will perform necessary task to bring back GPU into good
2985 * shape.
2986 */
fc30b8ef 2987 /* post card */
e7d40b9a 2988 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 2989
b15ba512 2990 rdev->accel_working = true;
fc30b8ef
DA		 2991 r = r600_startup(rdev);
2992 if (r) {
2993 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 2994 rdev->accel_working = false;
fc30b8ef
DA		 2995 return r;
2996 }
2997
fc30b8ef
DA		 2998 return r;
2999}
3000
3ce0a23d
JG		 3001int r600_suspend(struct radeon_device *rdev)
3002{
38fd2c6f 3003 r600_audio_fini(rdev);
3ce0a23d 3004 r600_cp_stop(rdev);
4d75658b 3005 r600_dma_stop(rdev);
0c45249f 3006 r600_irq_suspend(rdev);
724c80e1 3007 radeon_wb_disable(rdev);
4aac0473 3008 r600_pcie_gart_disable(rdev);
6ddddfe7 3009
3ce0a23d
JG		 3010 return 0;
3011}
3012
3013/* Plan is to move initialization in that function and use
3014 * helper function so that radeon_device_init pretty much
3015 * do nothing more than calling asic specific function. This
3016 * should also allow to remove a bunch of callback function
3017 * like vram_info.
3018 */
3019int r600_init(struct radeon_device *rdev)
771fe6b9 3020{
3ce0a23d 3021 int r;
771fe6b9 3022
3ce0a23d
JG		 3023 if (r600_debugfs_mc_info_init(rdev)) {
3024 DRM_ERROR("Failed to register debugfs file for mc !\n");
3025 }
3ce0a23d
JG		 3026 /* Read BIOS */
3027 if (!radeon_get_bios(rdev)) {
3028 if (ASIC_IS_AVIVO(rdev))
3029 return -EINVAL;
3030 }
3031 /* Must be an ATOMBIOS */
e7d40b9a
JG		 3032 if (!rdev->is_atom_bios) {
3033 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 3034 return -EINVAL;
e7d40b9a 3035 }
3ce0a23d
JG		 3036 r = radeon_atombios_init(rdev);
3037 if (r)
3038 return r;
3039 /* Post card if necessary */
fd909c37 3040 if (!radeon_card_posted(rdev)) {
72542d77
DA		 3041 if (!rdev->bios) {
3042 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3043 return -EINVAL;
3044 }
3ce0a23d
JG		 3045 DRM_INFO("GPU not posted. posting now...\n");
3046 atom_asic_init(rdev->mode_info.atom_context);
3047 }
3048 /* Initialize scratch registers */
3049 r600_scratch_init(rdev);
3050 /* Initialize surface registers */
3051 radeon_surface_init(rdev);
7433874e 3052 /* Initialize clocks */
5e6dde7e 3053 radeon_get_clock_info(rdev->ddev);
3ce0a23d 3054 /* Fence driver */
30eb77f4 3055 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 3056 if (r)
3057 return r;
700a0cc0
JG		 3058 if (rdev->flags & RADEON_IS_AGP) {
3059 r = radeon_agp_init(rdev);
3060 if (r)
3061 radeon_agp_disable(rdev);
3062 }
3ce0a23d 3063 r = r600_mc_init(rdev);
b574f251 3064 if (r)
3ce0a23d 3065 return r;
3ce0a23d 3066 /* Memory manager */
4c788679 3067 r = radeon_bo_init(rdev);
3ce0a23d
JG		 3068 if (r)
3069 return r;
d8f60cfc
AD		 3070
3071 r = radeon_irq_kms_init(rdev);
3072 if (r)
3073 return r;
3074
e32eb50d
CK		 3075 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3076 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 3077
4d75658b
AD		 3078 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3079 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3080
d8f60cfc
AD		 3081 rdev->ih.ring_obj = NULL;
3082 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 3083
4aac0473
JG		 3084 r = r600_pcie_gart_init(rdev);
3085 if (r)
3086 return r;
3087
779720a3 3088 rdev->accel_working = true;
fc30b8ef 3089 r = r600_startup(rdev);
3ce0a23d 3090 if (r) {
655efd3d
JG		 3091 dev_err(rdev->dev, "disabling GPU acceleration\n");
3092 r600_cp_fini(rdev);
4d75658b 3093 r600_dma_fini(rdev);
655efd3d 3094 r600_irq_fini(rdev);
724c80e1 3095 radeon_wb_fini(rdev);
2898c348 3096 radeon_ib_pool_fini(rdev);
655efd3d 3097 radeon_irq_kms_fini(rdev);
75c81298 3098 r600_pcie_gart_fini(rdev);
733289c2 3099 rdev->accel_working = false;
3ce0a23d 3100 }
dafc3bd5 3101
3ce0a23d
JG		 3102 return 0;
3103}
3104
3105void r600_fini(struct radeon_device *rdev)
3106{
dafc3bd5 3107 r600_audio_fini(rdev);
3ce0a23d 3108 r600_blit_fini(rdev);
655efd3d 3109 r600_cp_fini(rdev);
4d75658b 3110 r600_dma_fini(rdev);
d8f60cfc 3111 r600_irq_fini(rdev);
724c80e1 3112 radeon_wb_fini(rdev);
2898c348 3113 radeon_ib_pool_fini(rdev);
d8f60cfc 3114 radeon_irq_kms_fini(rdev);
4aac0473 3115 r600_pcie_gart_fini(rdev);
16cdf04d 3116 r600_vram_scratch_fini(rdev);
655efd3d 3117 radeon_agp_fini(rdev);
3ce0a23d
JG		 3118 radeon_gem_fini(rdev);
3119 radeon_fence_driver_fini(rdev);
4c788679 3120 radeon_bo_fini(rdev);
e7d40b9a 3121 radeon_atombios_fini(rdev);
3ce0a23d
JG		 3122 kfree(rdev->bios);
3123 rdev->bios = NULL;
3ce0a23d
JG		 3124}
3125
3126
3127/*
3128 * CS stuff
3129 */
3130void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3131{
876dc9f3 3132 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 3133 u32 next_rptr;
7b1f2485 3134
45df6803 3135 if (ring->rptr_save_reg) {
89d35807 3136 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 3137 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3138 radeon_ring_write(ring, ((ring->rptr_save_reg -
3139 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3140 radeon_ring_write(ring, next_rptr);
89d35807
AD		 3141 } else if (rdev->wb.enabled) {
3142 next_rptr = ring->wptr + 5 + 4;
3143 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3145 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3146 radeon_ring_write(ring, next_rptr);
3147 radeon_ring_write(ring, 0);
45df6803
CK		 3148 }
3149
e32eb50d
CK		 3150 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3151 radeon_ring_write(ring,
4eace7fd
CC		 3152#ifdef __BIG_ENDIAN
3153 (2 << 0) |
3154#endif
3155 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 3156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3157 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3158}
3159
f712812e 3160int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3161{
f2e39221 3162 struct radeon_ib ib;
3ce0a23d
JG		 3163 uint32_t scratch;
3164 uint32_t tmp = 0;
3165 unsigned i;
3166 int r;
3167
3168 r = radeon_scratch_get(rdev, &scratch);
3169 if (r) {
3170 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3171 return r;
3172 }
3173 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3174 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3ce0a23d
JG		 3175 if (r) {
3176 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
af026c5b 3177 goto free_scratch;
3ce0a23d 3178 }
f2e39221
JG		 3179 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3180 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3181 ib.ptr[2] = 0xDEADBEEF;
3182 ib.length_dw = 3;
4ef72566 3183 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3184 if (r) {
3ce0a23d 3185 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
af026c5b 3186 goto free_ib;
3ce0a23d 3187 }
f2e39221 3188 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3189 if (r) {
3190 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
af026c5b 3191 goto free_ib;
3ce0a23d
JG		 3192 }
3193 for (i = 0; i < rdev->usec_timeout; i++) {
3194 tmp = RREG32(scratch);
3195 if (tmp == 0xDEADBEEF)
3196 break;
3197 DRM_UDELAY(1);
3198 }
3199 if (i < rdev->usec_timeout) {
f2e39221 3200 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3ce0a23d 3201 } else {
4417d7f6 3202 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3203 scratch, tmp);
3204 r = -EINVAL;
3205 }
af026c5b 3206free_ib:
3ce0a23d 3207 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3208free_scratch:
3209 radeon_scratch_free(rdev, scratch);
771fe6b9
JG		 3210 return r;
3211}
3212
4d75658b
AD		 3213/**
3214 * r600_dma_ib_test - test an IB on the DMA engine
3215 *
3216 * @rdev: radeon_device pointer
3217 * @ring: radeon_ring structure holding ring information
3218 *
3219 * Test a simple IB in the DMA ring (r6xx-SI).
3220 * Returns 0 on success, error on failure.
3221 */
3222int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3223{
3224 struct radeon_ib ib;
3225 unsigned i;
3226 int r;
3227 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3228 u32 tmp = 0;
3229
3230 if (!ptr) {
3231 DRM_ERROR("invalid vram scratch pointer\n");
3232 return -EINVAL;
3233 }
3234
3235 tmp = 0xCAFEDEAD;
3236 writel(tmp, ptr);
3237
3238 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3239 if (r) {
3240 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3241 return r;
3242 }
3243
3244 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3245 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3246 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3247 ib.ptr[3] = 0xDEADBEEF;
3248 ib.length_dw = 4;
3249
3250 r = radeon_ib_schedule(rdev, &ib, NULL);
3251 if (r) {
3252 radeon_ib_free(rdev, &ib);
3253 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3254 return r;
3255 }
3256 r = radeon_fence_wait(ib.fence, false);
3257 if (r) {
3258 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3259 return r;
3260 }
3261 for (i = 0; i < rdev->usec_timeout; i++) {
3262 tmp = readl(ptr);
3263 if (tmp == 0xDEADBEEF)
3264 break;
3265 DRM_UDELAY(1);
3266 }
3267 if (i < rdev->usec_timeout) {
3268 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3269 } else {
3270 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3271 r = -EINVAL;
3272 }
3273 radeon_ib_free(rdev, &ib);
3274 return r;
3275}
3276
3277/**
3278 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3279 *
3280 * @rdev: radeon_device pointer
3281 * @ib: IB object to schedule
3282 *
3283 * Schedule an IB in the DMA ring (r6xx-r7xx).
3284 */
3285void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3286{
3287 struct radeon_ring *ring = &rdev->ring[ib->ring];
3288
3289 if (rdev->wb.enabled) {
3290 u32 next_rptr = ring->wptr + 4;
3291 while ((next_rptr & 7) != 5)
3292 next_rptr++;
3293 next_rptr += 3;
3294 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3295 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3296 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3297 radeon_ring_write(ring, next_rptr);
3298 }
3299
3300 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3301 * Pad as necessary with NOPs.
3302 */
3303 while ((ring->wptr & 7) != 5)
3304 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3305 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3306 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3307 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3308
3309}
3310
d8f60cfc
AD		 3311/*
3312 * Interrupts
3313 *
3314 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3315 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3316 * writing to the ring and the GPU consuming, the GPU writes to the ring
3317 * and host consumes. As the host irq handler processes interrupts, it
3318 * increments the rptr. When the rptr catches up with the wptr, all the
3319 * current interrupts have been processed.
3320 */
3321
3322void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3323{
3324 u32 rb_bufsz;
3325
3326 /* Align ring size */
3327 rb_bufsz = drm_order(ring_size / 4);
3328 ring_size = (1 << rb_bufsz) * 4;
3329 rdev->ih.ring_size = ring_size;
0c45249f
JG		 3330 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3331 rdev->ih.rptr = 0;
d8f60cfc
AD		 3332}
3333
25a857fb 3334int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 3335{
3336 int r;
3337
d8f60cfc
AD		 3338 /* Allocate ring buffer */
3339 if (rdev->ih.ring_obj == NULL) {
441921d5 3340 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 3341 PAGE_SIZE, true,
4c788679 3342 RADEON_GEM_DOMAIN_GTT,
40f5cf99 3343 NULL, &rdev->ih.ring_obj);
d8f60cfc
AD		 3344 if (r) {
3345 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3346 return r;
3347 }
4c788679
JG		 3348 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3349 if (unlikely(r != 0))
3350 return r;
3351 r = radeon_bo_pin(rdev->ih.ring_obj,
3352 RADEON_GEM_DOMAIN_GTT,
3353 &rdev->ih.gpu_addr);
d8f60cfc 3354 if (r) {
4c788679 3355 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3356 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3357 return r;
3358 }
4c788679
JG		 3359 r = radeon_bo_kmap(rdev->ih.ring_obj,
3360 (void **)&rdev->ih.ring);
3361 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3362 if (r) {
3363 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3364 return r;
3365 }
3366 }
d8f60cfc
AD		 3367 return 0;
3368}
3369
25a857fb 3370void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 3371{
4c788679 3372 int r;
d8f60cfc 3373 if (rdev->ih.ring_obj) {
4c788679
JG		 3374 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3375 if (likely(r == 0)) {
3376 radeon_bo_kunmap(rdev->ih.ring_obj);
3377 radeon_bo_unpin(rdev->ih.ring_obj);
3378 radeon_bo_unreserve(rdev->ih.ring_obj);
3379 }
3380 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 3381 rdev->ih.ring = NULL;
3382 rdev->ih.ring_obj = NULL;
3383 }
3384}
3385
45f9a39b 3386void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 3387{
3388
45f9a39b
AD		 3389 if ((rdev->family >= CHIP_RV770) &&
3390 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 3391 /* r7xx asics need to soft reset RLC before halting */
3392 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3393 RREG32(SRBM_SOFT_RESET);
4de833c3 3394 mdelay(15);
d8f60cfc
AD		 3395 WREG32(SRBM_SOFT_RESET, 0);
3396 RREG32(SRBM_SOFT_RESET);
3397 }
3398
3399 WREG32(RLC_CNTL, 0);
3400}
3401
3402static void r600_rlc_start(struct radeon_device *rdev)
3403{
3404 WREG32(RLC_CNTL, RLC_ENABLE);
3405}
3406
3407static int r600_rlc_init(struct radeon_device *rdev)
3408{
3409 u32 i;
3410 const __be32 *fw_data;
3411
3412 if (!rdev->rlc_fw)
3413 return -EINVAL;
3414
3415 r600_rlc_stop(rdev);
3416
d8f60cfc 3417 WREG32(RLC_HB_CNTL, 0);
c420c745
AD		 3418
3419 if (rdev->family == CHIP_ARUBA) {
3420 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3421 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3422 }
3423 if (rdev->family <= CHIP_CAYMAN) {
3424 WREG32(RLC_HB_BASE, 0);
3425 WREG32(RLC_HB_RPTR, 0);
3426 WREG32(RLC_HB_WPTR, 0);
3427 }
12727809
AD		 3428 if (rdev->family <= CHIP_CAICOS) {
3429 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3430 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3431 }
d8f60cfc
AD		 3432 WREG32(RLC_MC_CNTL, 0);
3433 WREG32(RLC_UCODE_CNTL, 0);
3434
3435 fw_data = (const __be32 *)rdev->rlc_fw->data;
c420c745
AD		 3436 if (rdev->family >= CHIP_ARUBA) {
3437 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3438 WREG32(RLC_UCODE_ADDR, i);
3439 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3440 }
3441 } else if (rdev->family >= CHIP_CAYMAN) {
12727809
AD		 3442 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3443 WREG32(RLC_UCODE_ADDR, i);
3444 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3445 }
3446 } else if (rdev->family >= CHIP_CEDAR) {
45f9a39b
AD		 3447 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3448 WREG32(RLC_UCODE_ADDR, i);
3449 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3450 }
3451 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 3452 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3453 WREG32(RLC_UCODE_ADDR, i);
3454 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3455 }
3456 } else {
3457 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3458 WREG32(RLC_UCODE_ADDR, i);
3459 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3460 }
3461 }
3462 WREG32(RLC_UCODE_ADDR, 0);
3463
3464 r600_rlc_start(rdev);
3465
3466 return 0;
3467}
3468
3469static void r600_enable_interrupts(struct radeon_device *rdev)
3470{
3471 u32 ih_cntl = RREG32(IH_CNTL);
3472 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3473
3474 ih_cntl |= ENABLE_INTR;
3475 ih_rb_cntl |= IH_RB_ENABLE;
3476 WREG32(IH_CNTL, ih_cntl);
3477 WREG32(IH_RB_CNTL, ih_rb_cntl);
3478 rdev->ih.enabled = true;
3479}
3480
45f9a39b 3481void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 3482{
3483 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3484 u32 ih_cntl = RREG32(IH_CNTL);
3485
3486 ih_rb_cntl &= ~IH_RB_ENABLE;
3487 ih_cntl &= ~ENABLE_INTR;
3488 WREG32(IH_RB_CNTL, ih_rb_cntl);
3489 WREG32(IH_CNTL, ih_cntl);
3490 /* set rptr, wptr to 0 */
3491 WREG32(IH_RB_RPTR, 0);
3492 WREG32(IH_RB_WPTR, 0);
3493 rdev->ih.enabled = false;
d8f60cfc
AD		 3494 rdev->ih.rptr = 0;
3495}
3496
e0df1ac5
AD		 3497static void r600_disable_interrupt_state(struct radeon_device *rdev)
3498{
3499 u32 tmp;
3500
3555e53b 3501 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4d75658b
AD		 3502 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3503 WREG32(DMA_CNTL, tmp);
e0df1ac5
AD		 3504 WREG32(GRBM_INT_CNTL, 0);
3505 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 3506 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3507 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 3508 if (ASIC_IS_DCE3(rdev)) {
3509 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3510 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3511 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3512 WREG32(DC_HPD1_INT_CONTROL, tmp);
3513 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3514 WREG32(DC_HPD2_INT_CONTROL, tmp);
3515 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3516 WREG32(DC_HPD3_INT_CONTROL, tmp);
3517 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3518 WREG32(DC_HPD4_INT_CONTROL, tmp);
3519 if (ASIC_IS_DCE32(rdev)) {
3520 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3521 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 3522 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3523 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 3524 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3525 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3526 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3527 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 3528 } else {
3529 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3530 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3531 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3532 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3533 }
3534 } else {
3535 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3536 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3537 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3538 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 3539 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3540 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 3541 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3542 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 3543 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3544 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3545 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3546 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3547 }
3548}
3549
d8f60cfc
AD		 3550int r600_irq_init(struct radeon_device *rdev)
3551{
3552 int ret = 0;
3553 int rb_bufsz;
3554 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3555
3556 /* allocate ring */
0c45249f 3557 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 3558 if (ret)
3559 return ret;
3560
3561 /* disable irqs */
3562 r600_disable_interrupts(rdev);
3563
3564 /* init rlc */
3565 ret = r600_rlc_init(rdev);
3566 if (ret) {
3567 r600_ih_ring_fini(rdev);
3568 return ret;
3569 }
3570
3571 /* setup interrupt control */
3572 /* set dummy read address to ring address */
3573 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3574 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3575 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3576 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3577 */
3578 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3579 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3580 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3581 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3582
3583 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3584 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3585
3586 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3587 IH_WPTR_OVERFLOW_CLEAR |
3588 (rb_bufsz << 1));
724c80e1
AD		 3589
3590 if (rdev->wb.enabled)
3591 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3592
3593 /* set the writeback address whether it's enabled or not */
3594 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3595 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3596
3597 WREG32(IH_RB_CNTL, ih_rb_cntl);
3598
3599 /* set rptr, wptr to 0 */
3600 WREG32(IH_RB_RPTR, 0);
3601 WREG32(IH_RB_WPTR, 0);
3602
3603 /* Default settings for IH_CNTL (disabled at first) */
3604 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3605 /* RPTR_REARM only works if msi's are enabled */
3606 if (rdev->msi_enabled)
3607 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3608 WREG32(IH_CNTL, ih_cntl);
3609
3610 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3611 if (rdev->family >= CHIP_CEDAR)
3612 evergreen_disable_interrupt_state(rdev);
3613 else
3614 r600_disable_interrupt_state(rdev);
d8f60cfc 3615
2099810f
DA		 3616 /* at this point everything should be setup correctly to enable master */
3617 pci_set_master(rdev->pdev);
3618
d8f60cfc
AD		 3619 /* enable irqs */
3620 r600_enable_interrupts(rdev);
3621
3622 return ret;
3623}
3624
0c45249f 3625void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3626{
45f9a39b 3627 r600_irq_disable(rdev);
d8f60cfc 3628 r600_rlc_stop(rdev);
0c45249f
JG		 3629}
3630
3631void r600_irq_fini(struct radeon_device *rdev)
3632{
3633 r600_irq_suspend(rdev);
d8f60cfc
AD		 3634 r600_ih_ring_fini(rdev);
3635}
3636
3637int r600_irq_set(struct radeon_device *rdev)
3638{
e0df1ac5
AD		 3639 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3640 u32 mode_int = 0;
3641 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3642 u32 grbm_int_cntl = 0;
f122c610 3643 u32 hdmi0, hdmi1;
6f34be50 3644 u32 d1grph = 0, d2grph = 0;
4d75658b 3645 u32 dma_cntl;
d8f60cfc 3646
003e69f9 3647 if (!rdev->irq.installed) {
fce7d61b 3648 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3649 return -EINVAL;
3650 }
d8f60cfc 3651 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3652 if (!rdev->ih.enabled) {
3653 r600_disable_interrupts(rdev);
3654 /* force the active interrupt state to all disabled */
3655 r600_disable_interrupt_state(rdev);
d8f60cfc 3656 return 0;
79c2bbc5 3657 }
d8f60cfc 3658
e0df1ac5
AD		 3659 if (ASIC_IS_DCE3(rdev)) {
3660 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3661 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3662 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3663 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3664 if (ASIC_IS_DCE32(rdev)) {
3665 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3666 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3667 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3668 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3669 } else {
3670 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3671 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3672 }
3673 } else {
3674 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3675 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3676 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3677 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3678 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5 3679 }
4d75658b 3680 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
e0df1ac5 3681
736fc37f 3682 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
d8f60cfc
AD		 3683 DRM_DEBUG("r600_irq_set: sw int\n");
3684 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3685 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3686 }
4d75658b
AD		 3687
3688 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3689 DRM_DEBUG("r600_irq_set: sw int dma\n");
3690 dma_cntl |= TRAP_ENABLE;
3691 }
3692
6f34be50 3693 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3694 atomic_read(&rdev->irq.pflip[0])) {
d8f60cfc
AD		 3695 DRM_DEBUG("r600_irq_set: vblank 0\n");
3696 mode_int |= D1MODE_VBLANK_INT_MASK;
3697 }
6f34be50 3698 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3699 atomic_read(&rdev->irq.pflip[1])) {
d8f60cfc
AD		 3700 DRM_DEBUG("r600_irq_set: vblank 1\n");
3701 mode_int |= D2MODE_VBLANK_INT_MASK;
3702 }
e0df1ac5
AD		 3703 if (rdev->irq.hpd[0]) {
3704 DRM_DEBUG("r600_irq_set: hpd 1\n");
3705 hpd1 |= DC_HPDx_INT_EN;
3706 }
3707 if (rdev->irq.hpd[1]) {
3708 DRM_DEBUG("r600_irq_set: hpd 2\n");
3709 hpd2 |= DC_HPDx_INT_EN;
3710 }
3711 if (rdev->irq.hpd[2]) {
3712 DRM_DEBUG("r600_irq_set: hpd 3\n");
3713 hpd3 |= DC_HPDx_INT_EN;
3714 }
3715 if (rdev->irq.hpd[3]) {
3716 DRM_DEBUG("r600_irq_set: hpd 4\n");
3717 hpd4 |= DC_HPDx_INT_EN;
3718 }
3719 if (rdev->irq.hpd[4]) {
3720 DRM_DEBUG("r600_irq_set: hpd 5\n");
3721 hpd5 |= DC_HPDx_INT_EN;
3722 }
3723 if (rdev->irq.hpd[5]) {
3724 DRM_DEBUG("r600_irq_set: hpd 6\n");
3725 hpd6 |= DC_HPDx_INT_EN;
3726 }
f122c610
AD		 3727 if (rdev->irq.afmt[0]) {
3728 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3729 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3730 }
f122c610
AD		 3731 if (rdev->irq.afmt[1]) {
3732 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3733 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3734 }
d8f60cfc
AD		 3735
3736 WREG32(CP_INT_CNTL, cp_int_cntl);
4d75658b 3737 WREG32(DMA_CNTL, dma_cntl);
d8f60cfc 3738 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3739 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3740 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3741 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3742 if (ASIC_IS_DCE3(rdev)) {
3743 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3744 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3745 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3746 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3747 if (ASIC_IS_DCE32(rdev)) {
3748 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3749 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3750 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3751 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3752 } else {
3753 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3754 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3755 }
3756 } else {
3757 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3758 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3759 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3760 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3761 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3762 }
d8f60cfc
AD		 3763
3764 return 0;
3765}
3766
ce580fab 3767static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3768{
e0df1ac5
AD		 3769 u32 tmp;
3770
3771 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3772 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3773 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3774 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3775 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3776 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3777 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3778 } else {
3779 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3780 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3781 }
e0df1ac5 3782 } else {
6f34be50
AD		 3783 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3784 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3785 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3786 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3787 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3788 }
3789 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3790 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3791
3792 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3793 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3794 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3795 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3796 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3797 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3798 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3799 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3800 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3801 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3802 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3803 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3804 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3805 if (ASIC_IS_DCE3(rdev)) {
3806 tmp = RREG32(DC_HPD1_INT_CONTROL);
3807 tmp |= DC_HPDx_INT_ACK;
3808 WREG32(DC_HPD1_INT_CONTROL, tmp);
3809 } else {
3810 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3811 tmp |= DC_HPDx_INT_ACK;
3812 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3813 }
3814 }
6f34be50 3815 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3816 if (ASIC_IS_DCE3(rdev)) {
3817 tmp = RREG32(DC_HPD2_INT_CONTROL);
3818 tmp |= DC_HPDx_INT_ACK;
3819 WREG32(DC_HPD2_INT_CONTROL, tmp);
3820 } else {
3821 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3822 tmp |= DC_HPDx_INT_ACK;
3823 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3824 }
3825 }
6f34be50 3826 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3827 if (ASIC_IS_DCE3(rdev)) {
3828 tmp = RREG32(DC_HPD3_INT_CONTROL);
3829 tmp |= DC_HPDx_INT_ACK;
3830 WREG32(DC_HPD3_INT_CONTROL, tmp);
3831 } else {
3832 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3833 tmp |= DC_HPDx_INT_ACK;
3834 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3835 }
3836 }
6f34be50 3837 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3838 tmp = RREG32(DC_HPD4_INT_CONTROL);
3839 tmp |= DC_HPDx_INT_ACK;
3840 WREG32(DC_HPD4_INT_CONTROL, tmp);
3841 }
3842 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3843 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3844 tmp = RREG32(DC_HPD5_INT_CONTROL);
3845 tmp |= DC_HPDx_INT_ACK;
3846 WREG32(DC_HPD5_INT_CONTROL, tmp);
3847 }
6f34be50 3848 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3849 tmp = RREG32(DC_HPD5_INT_CONTROL);
3850 tmp |= DC_HPDx_INT_ACK;
3851 WREG32(DC_HPD6_INT_CONTROL, tmp);
3852 }
f122c610 3853 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3854 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 3855 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3856 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 3857 }
3858 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3859 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 3860 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3861 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 3862 }
3863 } else {
f122c610
AD		 3864 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3865 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3866 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3867 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3868 }
3869 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3870 if (ASIC_IS_DCE3(rdev)) {
3871 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3872 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3873 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3874 } else {
3875 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3876 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3877 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3878 }
f2594933
CK		 3879 }
3880 }
d8f60cfc
AD		 3881}
3882
3883void r600_irq_disable(struct radeon_device *rdev)
3884{
d8f60cfc
AD		 3885 r600_disable_interrupts(rdev);
3886 /* Wait and acknowledge irq */
3887 mdelay(1);
6f34be50 3888 r600_irq_ack(rdev);
e0df1ac5 3889 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3890}
3891
ce580fab 3892static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3893{
3894 u32 wptr, tmp;
3ce0a23d 3895
724c80e1 3896 if (rdev->wb.enabled)
204ae24d 3897 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3898 else
3899 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3900
d8f60cfc 3901 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3902 /* When a ring buffer overflow happen start parsing interrupt
3903 * from the last not overwritten vector (wptr + 16). Hopefully
3904 * this should allow us to catchup.
3905 */
3906 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3907 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3908 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3909 tmp = RREG32(IH_RB_CNTL);
3910 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3911 WREG32(IH_RB_CNTL, tmp);
3912 }
0c45249f 3913 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3914}
3ce0a23d 3915
d8f60cfc
AD		 3916/* r600 IV Ring
3917 * Each IV ring entry is 128 bits:
3918 * [7:0] - interrupt source id
3919 * [31:8] - reserved
3920 * [59:32] - interrupt source data
3921 * [127:60] - reserved
3922 *
3923 * The basic interrupt vector entries
3924 * are decoded as follows:
3925 * src_id src_data description
3926 * 1 0 D1 Vblank
3927 * 1 1 D1 Vline
3928 * 5 0 D2 Vblank
3929 * 5 1 D2 Vline
3930 * 19 0 FP Hot plug detection A
3931 * 19 1 FP Hot plug detection B
3932 * 19 2 DAC A auto-detection
3933 * 19 3 DAC B auto-detection
f2594933
CK		 3934 * 21 4 HDMI block A
3935 * 21 5 HDMI block B
d8f60cfc
AD		 3936 * 176 - CP_INT RB
3937 * 177 - CP_INT IB1
3938 * 178 - CP_INT IB2
3939 * 181 - EOP Interrupt
3940 * 233 - GUI Idle
3941 *
3942 * Note, these are based on r600 and may need to be
3943 * adjusted or added to on newer asics
3944 */
3945
3946int r600_irq_process(struct radeon_device *rdev)
3947{
682f1a54
DA		 3948 u32 wptr;
3949 u32 rptr;
d8f60cfc 3950 u32 src_id, src_data;
6f34be50 3951 u32 ring_index;
d4877cf2 3952 bool queue_hotplug = false;
f122c610 3953 bool queue_hdmi = false;
d8f60cfc 3954
682f1a54 3955 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3956 return IRQ_NONE;
d8f60cfc 3957
f6a56939
BH		 3958 /* No MSIs, need a dummy read to flush PCI DMAs */
3959 if (!rdev->msi_enabled)
3960 RREG32(IH_RB_WPTR);
3961
682f1a54 3962 wptr = r600_get_ih_wptr(rdev);
d8f60cfc 3963
c20dc369
CK		 3964restart_ih:
3965 /* is somebody else already processing irqs? */
3966 if (atomic_xchg(&rdev->ih.lock, 1))
d8f60cfc 3967 return IRQ_NONE;
d8f60cfc 3968
c20dc369
CK		 3969 rptr = rdev->ih.rptr;
3970 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3971
964f6645
BH		 3972 /* Order reading of wptr vs. reading of IH ring data */
3973 rmb();
3974
d8f60cfc 3975 /* display interrupts */
6f34be50 3976 r600_irq_ack(rdev);
d8f60cfc 3977
d8f60cfc
AD		 3978 while (rptr != wptr) {
3979 /* wptr/rptr are in bytes! */
3980 ring_index = rptr / 4;
4eace7fd
CC		 3981 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3982 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3983
3984 switch (src_id) {
3985 case 1: /* D1 vblank/vline */
3986 switch (src_data) {
3987 case 0: /* D1 vblank */
6f34be50 3988 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3989 if (rdev->irq.crtc_vblank_int[0]) {
3990 drm_handle_vblank(rdev->ddev, 0);
3991 rdev->pm.vblank_sync = true;
3992 wake_up(&rdev->irq.vblank_queue);
3993 }
736fc37f 3994 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3995 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3996 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3997 DRM_DEBUG("IH: D1 vblank\n");
3998 }
3999 break;
4000 case 1: /* D1 vline */
6f34be50
AD		 4001 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4002 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 4003 DRM_DEBUG("IH: D1 vline\n");
4004 }
4005 break;
4006 default:
b042589c 4007 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4008 break;
4009 }
4010 break;
4011 case 5: /* D2 vblank/vline */
4012 switch (src_data) {
4013 case 0: /* D2 vblank */
6f34be50 4014 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 4015 if (rdev->irq.crtc_vblank_int[1]) {
4016 drm_handle_vblank(rdev->ddev, 1);
4017 rdev->pm.vblank_sync = true;
4018 wake_up(&rdev->irq.vblank_queue);
4019 }
736fc37f 4020 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 4021 radeon_crtc_handle_flip(rdev, 1);
6f34be50 4022 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 4023 DRM_DEBUG("IH: D2 vblank\n");
4024 }
4025 break;
4026 case 1: /* D1 vline */
6f34be50
AD		 4027 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4028 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 4029 DRM_DEBUG("IH: D2 vline\n");
4030 }
4031 break;
4032 default:
b042589c 4033 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4034 break;
4035 }
4036 break;
e0df1ac5
AD		 4037 case 19: /* HPD/DAC hotplug */
4038 switch (src_data) {
4039 case 0:
6f34be50
AD		 4040 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4041 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 4042 queue_hotplug = true;
4043 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 4044 }
4045 break;
4046 case 1:
6f34be50
AD		 4047 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4048 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 4049 queue_hotplug = true;
4050 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 4051 }
4052 break;
4053 case 4:
6f34be50
AD		 4054 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4055 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 4056 queue_hotplug = true;
4057 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 4058 }
4059 break;
4060 case 5:
6f34be50
AD		 4061 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4062 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 4063 queue_hotplug = true;
4064 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 4065 }
4066 break;
4067 case 10:
6f34be50
AD		 4068 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4069 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 4070 queue_hotplug = true;
4071 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 4072 }
4073 break;
4074 case 12:
6f34be50
AD		 4075 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4076 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 4077 queue_hotplug = true;
4078 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 4079 }
4080 break;
4081 default:
b042589c 4082 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 4083 break;
4084 }
4085 break;
f122c610
AD		 4086 case 21: /* hdmi */
4087 switch (src_data) {
4088 case 4:
4089 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4090 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4091 queue_hdmi = true;
4092 DRM_DEBUG("IH: HDMI0\n");
4093 }
4094 break;
4095 case 5:
4096 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4097 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4098 queue_hdmi = true;
4099 DRM_DEBUG("IH: HDMI1\n");
4100 }
4101 break;
4102 default:
4103 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4104 break;
4105 }
f2594933 4106 break;
d8f60cfc
AD		 4107 case 176: /* CP_INT in ring buffer */
4108 case 177: /* CP_INT in IB1 */
4109 case 178: /* CP_INT in IB2 */
4110 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 4111 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 4112 break;
4113 case 181: /* CP EOP event */
4114 DRM_DEBUG("IH: CP EOP\n");
7465280c 4115 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 4116 break;
4d75658b
AD		 4117 case 224: /* DMA trap event */
4118 DRM_DEBUG("IH: DMA trap\n");
4119 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4120 break;
2031f77c 4121 case 233: /* GUI IDLE */
303c805c 4122 DRM_DEBUG("IH: GUI idle\n");
2031f77c 4123 break;
d8f60cfc 4124 default:
b042589c 4125 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4126 break;
4127 }
4128
4129 /* wptr/rptr are in bytes! */
0c45249f
JG		 4130 rptr += 16;
4131 rptr &= rdev->ih.ptr_mask;
d8f60cfc 4132 }
d4877cf2 4133 if (queue_hotplug)
32c87fca 4134 schedule_work(&rdev->hotplug_work);
f122c610
AD		 4135 if (queue_hdmi)
4136 schedule_work(&rdev->audio_work);
d8f60cfc
AD		 4137 rdev->ih.rptr = rptr;
4138 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4139 atomic_set(&rdev->ih.lock, 0);
4140
4141 /* make sure wptr hasn't changed while processing */
4142 wptr = r600_get_ih_wptr(rdev);
4143 if (wptr != rptr)
4144 goto restart_ih;
4145
d8f60cfc
AD		 4146 return IRQ_HANDLED;
4147}
3ce0a23d
JG		 4148
4149/*
4150 * Debugfs info
4151 */
4152#if defined(CONFIG_DEBUG_FS)
4153
3ce0a23d
JG		 4154static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4155{
4156 struct drm_info_node *node = (struct drm_info_node *) m->private;
4157 struct drm_device *dev = node->minor->dev;
4158 struct radeon_device *rdev = dev->dev_private;
4159
4160 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4161 DREG32_SYS(m, rdev, VM_L2_STATUS);
4162 return 0;
4163}
4164
4165static struct drm_info_list r600_mc_info_list[] = {
4166 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 4167};
4168#endif
4169
4170int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4171{
4172#if defined(CONFIG_DEBUG_FS)
4173 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4174#else
4175 return 0;
4176#endif
771fe6b9 4177}
062b389c
JG		 4178
4179/**
4180 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4181 * rdev: radeon device structure
4182 * bo: buffer object struct which userspace is waiting for idle
4183 *
4184 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4185 * through ring buffer, this leads to corruption in rendering, see
4186 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4187 * directly perform HDP flush by writing register through MMIO.
4188 */
4189void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4190{
812d0469 4191 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 4192 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4193 * This seems to cause problems on some AGP cards. Just use the old
4194 * method for them.
812d0469 4195 */
e488459a 4196 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 4197 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 4198 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 4199 u32 tmp;
4200
4201 WREG32(HDP_DEBUG1, 0);
4202 tmp = readl((void __iomem *)ptr);
4203 } else
4204 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 4205}
3313e3d4
AD		 4206
4207void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4208{
4209 u32 link_width_cntl, mask, target_reg;
4210
4211 if (rdev->flags & RADEON_IS_IGP)
4212 return;
4213
4214 if (!(rdev->flags & RADEON_IS_PCIE))
4215 return;
4216
4217 /* x2 cards have a special sequence */
4218 if (ASIC_IS_X2(rdev))
4219 return;
4220
4221 /* FIXME wait for idle */
4222
4223 switch (lanes) {
4224 case 0:
4225 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4226 break;
4227 case 1:
4228 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4229 break;
4230 case 2:
4231 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4232 break;
4233 case 4:
4234 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4235 break;
4236 case 8:
4237 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4238 break;
4239 case 12:
4240 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4241 break;
4242 case 16:
4243 default:
4244 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4245 break;
4246 }
4247
4248 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4249
4250 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4251 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4252 return;
4253
4254 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4255 return;
4256
4257 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4258 RADEON_PCIE_LC_RECONFIG_NOW |
4259 R600_PCIE_LC_RENEGOTIATE_EN |
4260 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4261 link_width_cntl |= mask;
4262
4263 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4264
4265 /* some northbridges can renegotiate the link rather than requiring
4266 * a complete re-config.
4267 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4268 */
4269 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4270 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4271 else
4272 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4273
4274 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4275 RADEON_PCIE_LC_RECONFIG_NOW));
4276
4277 if (rdev->family >= CHIP_RV770)
4278 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4279 else
4280 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4281
4282 /* wait for lane set to complete */
4283 link_width_cntl = RREG32(target_reg);
4284 while (link_width_cntl == 0xffffffff)
4285 link_width_cntl = RREG32(target_reg);
4286
4287}
4288
4289int r600_get_pcie_lanes(struct radeon_device *rdev)
4290{
4291 u32 link_width_cntl;
4292
4293 if (rdev->flags & RADEON_IS_IGP)
4294 return 0;
4295
4296 if (!(rdev->flags & RADEON_IS_PCIE))
4297 return 0;
4298
4299 /* x2 cards have a special sequence */
4300 if (ASIC_IS_X2(rdev))
4301 return 0;
4302
4303 /* FIXME wait for idle */
4304
4305 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4306
4307 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4308 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4309 return 0;
4310 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4311 return 1;
4312 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4313 return 2;
4314 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4315 return 4;
4316 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4317 return 8;
4318 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4319 default:
4320 return 16;
4321 }
4322}
4323
9e46a48d
AD		 4324static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4325{
4326 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4327 u16 link_cntl2;
197bbb3d
DA		 4328 u32 mask;
4329 int ret;
9e46a48d 4330
d42dd579
AD		 4331 if (radeon_pcie_gen2 == 0)
4332 return;
4333
9e46a48d
AD		 4334 if (rdev->flags & RADEON_IS_IGP)
4335 return;
4336
4337 if (!(rdev->flags & RADEON_IS_PCIE))
4338 return;
4339
4340 /* x2 cards have a special sequence */
4341 if (ASIC_IS_X2(rdev))
4342 return;
4343
4344 /* only RV6xx+ chips are supported */
4345 if (rdev->family <= CHIP_R600)
4346 return;
4347
197bbb3d
DA		 4348 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4349 if (ret != 0)
4350 return;
4351
4352 if (!(mask & DRM_PCIE_SPEED_50))
4353 return;
4354
3691feea
AD		 4355 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4356 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4357 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4358 return;
4359 }
4360
197bbb3d
DA		 4361 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4362
9e46a48d
AD		 4363 /* 55 nm r6xx asics */
4364 if ((rdev->family == CHIP_RV670) ||
4365 (rdev->family == CHIP_RV620) ||
4366 (rdev->family == CHIP_RV635)) {
4367 /* advertise upconfig capability */
4368 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4369 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4370 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4371 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4372 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4373 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4374 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4375 LC_RECONFIG_ARC_MISSING_ESCAPE);
4376 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4377 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4378 } else {
4379 link_width_cntl |= LC_UPCONFIGURE_DIS;
4380 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4381 }
4382 }
4383
4384 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4385 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4386 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4387
4388 /* 55 nm r6xx asics */
4389 if ((rdev->family == CHIP_RV670) ||
4390 (rdev->family == CHIP_RV620) ||
4391 (rdev->family == CHIP_RV635)) {
4392 WREG32(MM_CFGREGS_CNTL, 0x8);
4393 link_cntl2 = RREG32(0x4088);
4394 WREG32(MM_CFGREGS_CNTL, 0);
4395 /* not supported yet */
4396 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4397 return;
4398 }
4399
4400 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4401 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4402 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4403 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4404 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4405 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4406
4407 tmp = RREG32(0x541c);
4408 WREG32(0x541c, tmp | 0x8);
4409 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4410 link_cntl2 = RREG16(0x4088);
4411 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4412 link_cntl2 |= 0x2;
4413 WREG16(0x4088, link_cntl2);
4414 WREG32(MM_CFGREGS_CNTL, 0);
4415
4416 if ((rdev->family == CHIP_RV670) ||
4417 (rdev->family == CHIP_RV620) ||
4418 (rdev->family == CHIP_RV635)) {
4419 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4420 training_cntl &= ~LC_POINT_7_PLUS_EN;
4421 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4422 } else {
4423 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4424 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4425 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4426 }
4427
4428 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4429 speed_cntl |= LC_GEN2_EN_STRAP;
4430 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4431
4432 } else {
4433 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4434 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4435 if (1)
4436 link_width_cntl |= LC_UPCONFIGURE_DIS;
4437 else
4438 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4439 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4440 }
4441}
6759a0a7
MO		 4442
4443/**
4444 * r600_get_gpu_clock - return GPU clock counter snapshot
4445 *
4446 * @rdev: radeon_device pointer
4447 *
4448 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4449 * Returns the 64 bit clock counter snapshot.
4450 */
4451uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4452{
4453 uint64_t clock;
4454
4455 mutex_lock(&rdev->gpu_clock_mutex);
4456 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4457 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4458 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4459 mutex_unlock(&rdev->gpu_clock_mutex);
4460 return clock;
4461}
Linux kernel - Deliverables
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