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drm/radeon/kms: remove duplicate card_posted() functions
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 86MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87MODULE_FIRMWARE("radeon/PALM_me.bin");
88MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
3ce0a23d
JG		 89
90int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 91
1a029b76 92/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 93int r600_mc_wait_for_idle(struct radeon_device *rdev);
94void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 95void r600_fini(struct radeon_device *rdev);
45f9a39b 96void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 97static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 98
21a8122a
AD		 99/* get temperature in millidegrees */
100u32 rv6xx_get_temp(struct radeon_device *rdev)
101{
102 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
103 ASIC_T_SHIFT;
21a8122a 104
b2298fd2 105 return temp * 1000;
21a8122a
AD		 106}
107
ce8f5370 108void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 109{
110 int i;
111
ce8f5370
AD		 112 rdev->pm.dynpm_can_upclock = true;
113 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 114
115 /* power state array is low to high, default is first */
116 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
117 int min_power_state_index = 0;
118
119 if (rdev->pm.num_power_states > 2)
120 min_power_state_index = 1;
121
ce8f5370
AD		 122 switch (rdev->pm.dynpm_planned_action) {
123 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 124 rdev->pm.requested_power_state_index = min_power_state_index;
125 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 126 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 127 break;
ce8f5370 128 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 129 if (rdev->pm.current_power_state_index == min_power_state_index) {
130 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 131 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 132 } else {
133 if (rdev->pm.active_crtc_count > 1) {
134 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 135 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 136 continue;
137 else if (i >= rdev->pm.current_power_state_index) {
138 rdev->pm.requested_power_state_index =
139 rdev->pm.current_power_state_index;
140 break;
141 } else {
142 rdev->pm.requested_power_state_index = i;
143 break;
144 }
145 }
773c3fa3
AD		 146 } else {
147 if (rdev->pm.current_power_state_index == 0)
148 rdev->pm.requested_power_state_index =
149 rdev->pm.num_power_states - 1;
150 else
151 rdev->pm.requested_power_state_index =
152 rdev->pm.current_power_state_index - 1;
153 }
a48b9b4e
AD		 154 }
155 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 156 /* don't use the power state if crtcs are active and no display flag is set */
157 if ((rdev->pm.active_crtc_count > 0) &&
158 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
159 clock_info[rdev->pm.requested_clock_mode_index].flags &
160 RADEON_PM_MODE_NO_DISPLAY)) {
161 rdev->pm.requested_power_state_index++;
162 }
a48b9b4e 163 break;
ce8f5370 164 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 165 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
166 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 167 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 168 } else {
169 if (rdev->pm.active_crtc_count > 1) {
170 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 171 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 172 continue;
173 else if (i <= rdev->pm.current_power_state_index) {
174 rdev->pm.requested_power_state_index =
175 rdev->pm.current_power_state_index;
176 break;
177 } else {
178 rdev->pm.requested_power_state_index = i;
179 break;
180 }
181 }
182 } else
183 rdev->pm.requested_power_state_index =
184 rdev->pm.current_power_state_index + 1;
185 }
186 rdev->pm.requested_clock_mode_index = 0;
187 break;
ce8f5370 188 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 189 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
190 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 191 rdev->pm.dynpm_can_upclock = false;
58e21dff 192 break;
ce8f5370 193 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 194 default:
195 DRM_ERROR("Requested mode for not defined action\n");
196 return;
197 }
198 } else {
199 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
200 /* for now just select the first power state and switch between clock modes */
201 /* power state array is low to high, default is first (0) */
202 if (rdev->pm.active_crtc_count > 1) {
203 rdev->pm.requested_power_state_index = -1;
204 /* start at 1 as we don't want the default mode */
205 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 206 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 207 continue;
208 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
209 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
210 rdev->pm.requested_power_state_index = i;
211 break;
212 }
213 }
214 /* if nothing selected, grab the default state. */
215 if (rdev->pm.requested_power_state_index == -1)
216 rdev->pm.requested_power_state_index = 0;
217 } else
218 rdev->pm.requested_power_state_index = 1;
219
ce8f5370
AD		 220 switch (rdev->pm.dynpm_planned_action) {
221 case DYNPM_ACTION_MINIMUM:
a48b9b4e 222 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 223 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 224 break;
ce8f5370 225 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 226 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
227 if (rdev->pm.current_clock_mode_index == 0) {
228 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 229 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 230 } else
231 rdev->pm.requested_clock_mode_index =
232 rdev->pm.current_clock_mode_index - 1;
233 } else {
234 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 235 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 236 }
d7311171
AD		 237 /* don't use the power state if crtcs are active and no display flag is set */
238 if ((rdev->pm.active_crtc_count > 0) &&
239 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
240 clock_info[rdev->pm.requested_clock_mode_index].flags &
241 RADEON_PM_MODE_NO_DISPLAY)) {
242 rdev->pm.requested_clock_mode_index++;
243 }
a48b9b4e 244 break;
ce8f5370 245 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 246 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
247 if (rdev->pm.current_clock_mode_index ==
248 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
249 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 250 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 251 } else
252 rdev->pm.requested_clock_mode_index =
253 rdev->pm.current_clock_mode_index + 1;
254 } else {
255 rdev->pm.requested_clock_mode_index =
256 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 257 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 258 }
259 break;
ce8f5370 260 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 261 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
262 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 263 rdev->pm.dynpm_can_upclock = false;
58e21dff 264 break;
ce8f5370 265 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 266 default:
267 DRM_ERROR("Requested mode for not defined action\n");
268 return;
269 }
270 }
271
d9fdaafb 272 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 273 rdev->pm.power_state[rdev->pm.requested_power_state_index].
274 clock_info[rdev->pm.requested_clock_mode_index].sclk,
275 rdev->pm.power_state[rdev->pm.requested_power_state_index].
276 clock_info[rdev->pm.requested_clock_mode_index].mclk,
277 rdev->pm.power_state[rdev->pm.requested_power_state_index].
278 pcie_lanes);
a48b9b4e
AD		 279}
280
ce8f5370
AD		 281static int r600_pm_get_type_index(struct radeon_device *rdev,
282 enum radeon_pm_state_type ps_type,
283 int instance)
bae6b562 284{
ce8f5370
AD		 285 int i;
286 int found_instance = -1;
bae6b562 287
ce8f5370
AD		 288 for (i = 0; i < rdev->pm.num_power_states; i++) {
289 if (rdev->pm.power_state[i].type == ps_type) {
290 found_instance++;
291 if (found_instance == instance)
292 return i;
a424816f 293 }
ce8f5370
AD		 294 }
295 /* return default if no match */
296 return rdev->pm.default_power_state_index;
297}
298
299void rs780_pm_init_profile(struct radeon_device *rdev)
300{
301 if (rdev->pm.num_power_states == 2) {
302 /* default */
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
305 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
307 /* low sh */
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 312 /* mid sh */
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 317 /* high sh */
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
320 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
322 /* low mh */
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 327 /* mid mh */
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 332 /* high mh */
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
335 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
337 } else if (rdev->pm.num_power_states == 3) {
338 /* default */
339 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
343 /* low sh */
344 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
345 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
346 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 348 /* mid sh */
349 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
350 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
351 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
352 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 353 /* high sh */
354 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
355 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
356 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
357 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
358 /* low mh */
359 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
361 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
362 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 363 /* mid mh */
364 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
365 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
366 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
367 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 368 /* high mh */
369 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
370 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
371 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
372 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
373 } else {
374 /* default */
375 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
376 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
377 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
378 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
379 /* low sh */
380 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
381 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
383 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 384 /* mid sh */
385 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
386 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
388 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 389 /* high sh */
390 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
391 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
394 /* low mh */
395 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
396 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 399 /* mid mh */
400 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
401 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
403 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 404 /* high mh */
405 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
406 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
408 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
409 }
410}
bae6b562 411
ce8f5370
AD		 412void r600_pm_init_profile(struct radeon_device *rdev)
413{
414 if (rdev->family == CHIP_R600) {
415 /* XXX */
416 /* default */
417 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 421 /* low sh */
422 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 426 /* mid sh */
427 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 431 /* high sh */
432 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 436 /* low mh */
437 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 441 /* mid mh */
442 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 446 /* high mh */
447 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
449 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 451 } else {
452 if (rdev->pm.num_power_states < 4) {
453 /* default */
454 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
455 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
458 /* low sh */
4bff5171
AD		 459 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
463 /* mid sh */
464 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 468 /* high sh */
4bff5171
AD		 469 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
470 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
473 /* low mh */
4bff5171
AD		 474 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
478 /* low mh */
479 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 483 /* high mh */
4bff5171
AD		 484 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
485 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
488 } else {
489 /* default */
490 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
491 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
492 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
494 /* low sh */
4bff5171
AD		 495 if (rdev->flags & RADEON_IS_MOBILITY) {
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
497 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
499 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 502 } else {
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
504 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 508 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
509 }
510 /* mid sh */
511 if (rdev->flags & RADEON_IS_MOBILITY) {
512 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
513 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
514 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
516 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
518 } else {
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
520 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
524 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 525 }
ce8f5370 526 /* high sh */
4bff5171
AD		 527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
528 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
529 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
530 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 531 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
532 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
533 /* low mh */
4bff5171
AD		 534 if (rdev->flags & RADEON_IS_MOBILITY) {
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
536 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
537 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
538 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
539 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 540 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 541 } else {
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
543 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
548 }
549 /* mid mh */
550 if (rdev->flags & RADEON_IS_MOBILITY) {
551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
552 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
553 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
555 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
557 } else {
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
559 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
563 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 564 }
ce8f5370 565 /* high mh */
4bff5171
AD		 566 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
567 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
568 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
569 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
572 }
573 }
bae6b562
AD		 574}
575
49e02b73
AD		 576void r600_pm_misc(struct radeon_device *rdev)
577{
a081a9d6
RM		 578 int req_ps_idx = rdev->pm.requested_power_state_index;
579 int req_cm_idx = rdev->pm.requested_clock_mode_index;
580 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
581 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 582
4d60173f
AD		 583 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
584 if (voltage->voltage != rdev->pm.current_vddc) {
585 radeon_atom_set_voltage(rdev, voltage->voltage);
586 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 587 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 588 }
589 }
49e02b73
AD		 590}
591
def9ba9c
AD		 592bool r600_gui_idle(struct radeon_device *rdev)
593{
594 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
595 return false;
596 else
597 return true;
598}
599
e0df1ac5
AD		 600/* hpd for digital panel detect/disconnect */
601bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
602{
603 bool connected = false;
604
605 if (ASIC_IS_DCE3(rdev)) {
606 switch (hpd) {
607 case RADEON_HPD_1:
608 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
609 connected = true;
610 break;
611 case RADEON_HPD_2:
612 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
613 connected = true;
614 break;
615 case RADEON_HPD_3:
616 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
617 connected = true;
618 break;
619 case RADEON_HPD_4:
620 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
621 connected = true;
622 break;
623 /* DCE 3.2 */
624 case RADEON_HPD_5:
625 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
626 connected = true;
627 break;
628 case RADEON_HPD_6:
629 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
630 connected = true;
631 break;
632 default:
633 break;
634 }
635 } else {
636 switch (hpd) {
637 case RADEON_HPD_1:
638 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
639 connected = true;
640 break;
641 case RADEON_HPD_2:
642 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
643 connected = true;
644 break;
645 case RADEON_HPD_3:
646 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
647 connected = true;
648 break;
649 default:
650 break;
651 }
652 }
653 return connected;
654}
655
656void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 657 enum radeon_hpd_id hpd)
e0df1ac5
AD		 658{
659 u32 tmp;
660 bool connected = r600_hpd_sense(rdev, hpd);
661
662 if (ASIC_IS_DCE3(rdev)) {
663 switch (hpd) {
664 case RADEON_HPD_1:
665 tmp = RREG32(DC_HPD1_INT_CONTROL);
666 if (connected)
667 tmp &= ~DC_HPDx_INT_POLARITY;
668 else
669 tmp |= DC_HPDx_INT_POLARITY;
670 WREG32(DC_HPD1_INT_CONTROL, tmp);
671 break;
672 case RADEON_HPD_2:
673 tmp = RREG32(DC_HPD2_INT_CONTROL);
674 if (connected)
675 tmp &= ~DC_HPDx_INT_POLARITY;
676 else
677 tmp |= DC_HPDx_INT_POLARITY;
678 WREG32(DC_HPD2_INT_CONTROL, tmp);
679 break;
680 case RADEON_HPD_3:
681 tmp = RREG32(DC_HPD3_INT_CONTROL);
682 if (connected)
683 tmp &= ~DC_HPDx_INT_POLARITY;
684 else
685 tmp |= DC_HPDx_INT_POLARITY;
686 WREG32(DC_HPD3_INT_CONTROL, tmp);
687 break;
688 case RADEON_HPD_4:
689 tmp = RREG32(DC_HPD4_INT_CONTROL);
690 if (connected)
691 tmp &= ~DC_HPDx_INT_POLARITY;
692 else
693 tmp |= DC_HPDx_INT_POLARITY;
694 WREG32(DC_HPD4_INT_CONTROL, tmp);
695 break;
696 case RADEON_HPD_5:
697 tmp = RREG32(DC_HPD5_INT_CONTROL);
698 if (connected)
699 tmp &= ~DC_HPDx_INT_POLARITY;
700 else
701 tmp |= DC_HPDx_INT_POLARITY;
702 WREG32(DC_HPD5_INT_CONTROL, tmp);
703 break;
704 /* DCE 3.2 */
705 case RADEON_HPD_6:
706 tmp = RREG32(DC_HPD6_INT_CONTROL);
707 if (connected)
708 tmp &= ~DC_HPDx_INT_POLARITY;
709 else
710 tmp |= DC_HPDx_INT_POLARITY;
711 WREG32(DC_HPD6_INT_CONTROL, tmp);
712 break;
713 default:
714 break;
715 }
716 } else {
717 switch (hpd) {
718 case RADEON_HPD_1:
719 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
720 if (connected)
721 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
722 else
723 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
724 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
725 break;
726 case RADEON_HPD_2:
727 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
728 if (connected)
729 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
730 else
731 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
732 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
733 break;
734 case RADEON_HPD_3:
735 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
736 if (connected)
737 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
738 else
739 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
740 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
741 break;
742 default:
743 break;
744 }
745 }
746}
747
748void r600_hpd_init(struct radeon_device *rdev)
749{
750 struct drm_device *dev = rdev->ddev;
751 struct drm_connector *connector;
752
753 if (ASIC_IS_DCE3(rdev)) {
754 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
755 if (ASIC_IS_DCE32(rdev))
756 tmp |= DC_HPDx_EN;
757
758 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
759 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
760 switch (radeon_connector->hpd.hpd) {
761 case RADEON_HPD_1:
762 WREG32(DC_HPD1_CONTROL, tmp);
763 rdev->irq.hpd[0] = true;
764 break;
765 case RADEON_HPD_2:
766 WREG32(DC_HPD2_CONTROL, tmp);
767 rdev->irq.hpd[1] = true;
768 break;
769 case RADEON_HPD_3:
770 WREG32(DC_HPD3_CONTROL, tmp);
771 rdev->irq.hpd[2] = true;
772 break;
773 case RADEON_HPD_4:
774 WREG32(DC_HPD4_CONTROL, tmp);
775 rdev->irq.hpd[3] = true;
776 break;
777 /* DCE 3.2 */
778 case RADEON_HPD_5:
779 WREG32(DC_HPD5_CONTROL, tmp);
780 rdev->irq.hpd[4] = true;
781 break;
782 case RADEON_HPD_6:
783 WREG32(DC_HPD6_CONTROL, tmp);
784 rdev->irq.hpd[5] = true;
785 break;
786 default:
787 break;
788 }
789 }
790 } else {
791 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
792 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
793 switch (radeon_connector->hpd.hpd) {
794 case RADEON_HPD_1:
795 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
796 rdev->irq.hpd[0] = true;
797 break;
798 case RADEON_HPD_2:
799 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
800 rdev->irq.hpd[1] = true;
801 break;
802 case RADEON_HPD_3:
803 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
804 rdev->irq.hpd[2] = true;
805 break;
806 default:
807 break;
808 }
809 }
810 }
003e69f9
JG		 811 if (rdev->irq.installed)
812 r600_irq_set(rdev);
e0df1ac5
AD		 813}
814
815void r600_hpd_fini(struct radeon_device *rdev)
816{
817 struct drm_device *dev = rdev->ddev;
818 struct drm_connector *connector;
819
820 if (ASIC_IS_DCE3(rdev)) {
821 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
822 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
823 switch (radeon_connector->hpd.hpd) {
824 case RADEON_HPD_1:
825 WREG32(DC_HPD1_CONTROL, 0);
826 rdev->irq.hpd[0] = false;
827 break;
828 case RADEON_HPD_2:
829 WREG32(DC_HPD2_CONTROL, 0);
830 rdev->irq.hpd[1] = false;
831 break;
832 case RADEON_HPD_3:
833 WREG32(DC_HPD3_CONTROL, 0);
834 rdev->irq.hpd[2] = false;
835 break;
836 case RADEON_HPD_4:
837 WREG32(DC_HPD4_CONTROL, 0);
838 rdev->irq.hpd[3] = false;
839 break;
840 /* DCE 3.2 */
841 case RADEON_HPD_5:
842 WREG32(DC_HPD5_CONTROL, 0);
843 rdev->irq.hpd[4] = false;
844 break;
845 case RADEON_HPD_6:
846 WREG32(DC_HPD6_CONTROL, 0);
847 rdev->irq.hpd[5] = false;
848 break;
849 default:
850 break;
851 }
852 }
853 } else {
854 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
855 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
856 switch (radeon_connector->hpd.hpd) {
857 case RADEON_HPD_1:
858 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
859 rdev->irq.hpd[0] = false;
860 break;
861 case RADEON_HPD_2:
862 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
863 rdev->irq.hpd[1] = false;
864 break;
865 case RADEON_HPD_3:
866 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
867 rdev->irq.hpd[2] = false;
868 break;
869 default:
870 break;
871 }
872 }
873 }
874}
875
771fe6b9 876/*
3ce0a23d 877 * R600 PCIE GART
771fe6b9 878 */
3ce0a23d
JG		 879void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
880{
881 unsigned i;
882 u32 tmp;
883
2e98f10a 884 /* flush hdp cache so updates hit vram */
f3886f85
AD		 885 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
886 !(rdev->flags & RADEON_IS_AGP)) {
812d0469
AD		 887 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
888 u32 tmp;
889
890 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
891 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 892 * This seems to cause problems on some AGP cards. Just use the old
893 * method for them.
812d0469
AD		 894 */
895 WREG32(HDP_DEBUG1, 0);
896 tmp = readl((void __iomem *)ptr);
897 } else
898 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 899
3ce0a23d
JG		 900 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
901 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
902 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
903 for (i = 0; i < rdev->usec_timeout; i++) {
904 /* read MC_STATUS */
905 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
906 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
907 if (tmp == 2) {
908 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
909 return;
910 }
911 if (tmp) {
912 return;
913 }
914 udelay(1);
915 }
916}
917
4aac0473 918int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 919{
4aac0473 920 int r;
3ce0a23d 921
4aac0473 922 if (rdev->gart.table.vram.robj) {
fce7d61b 923 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 924 return 0;
925 }
3ce0a23d
JG		 926 /* Initialize common gart structure */
927 r = radeon_gart_init(rdev);
4aac0473 928 if (r)
3ce0a23d 929 return r;
3ce0a23d 930 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 931 return radeon_gart_table_vram_alloc(rdev);
932}
933
934int r600_pcie_gart_enable(struct radeon_device *rdev)
935{
936 u32 tmp;
937 int r, i;
938
939 if (rdev->gart.table.vram.robj == NULL) {
940 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
941 return -EINVAL;
771fe6b9 942 }
4aac0473
JG		 943 r = radeon_gart_table_vram_pin(rdev);
944 if (r)
945 return r;
82568565 946 radeon_gart_restore(rdev);
bc1a631e 947
3ce0a23d
JG		 948 /* Setup L2 cache */
949 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
950 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
951 EFFECTIVE_L2_QUEUE_SIZE(7));
952 WREG32(VM_L2_CNTL2, 0);
953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup TLB control */
955 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
956 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
957 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
958 ENABLE_WAIT_L2_QUERY;
959 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
962 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
972 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
973 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 974 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 975 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
976 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
977 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
978 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
979 (u32)(rdev->dummy_page.addr >> 12));
980 for (i = 1; i < 7; i++)
981 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 982
3ce0a23d
JG		 983 r600_pcie_gart_tlb_flush(rdev);
984 rdev->gart.ready = true;
771fe6b9
JG		 985 return 0;
986}
987
3ce0a23d 988void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 989{
3ce0a23d 990 u32 tmp;
4c788679 991 int i, r;
771fe6b9 992
3ce0a23d
JG		 993 /* Disable all tables */
994 for (i = 0; i < 7; i++)
995 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 996
3ce0a23d
JG		 997 /* Disable L2 cache */
998 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
999 EFFECTIVE_L2_QUEUE_SIZE(7));
1000 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1001 /* Setup L1 TLB control */
1002 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1003 ENABLE_WAIT_L2_QUERY;
1004 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 1018 if (rdev->gart.table.vram.robj) {
4c788679
JG		 1019 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1020 if (likely(r == 0)) {
1021 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1022 radeon_bo_unpin(rdev->gart.table.vram.robj);
1023 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1024 }
4aac0473
JG		 1025 }
1026}
1027
1028void r600_pcie_gart_fini(struct radeon_device *rdev)
1029{
f9274562 1030 radeon_gart_fini(rdev);
4aac0473
JG		 1031 r600_pcie_gart_disable(rdev);
1032 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1033}
1034
1a029b76
JG		 1035void r600_agp_enable(struct radeon_device *rdev)
1036{
1037 u32 tmp;
1038 int i;
1039
1040 /* Setup L2 cache */
1041 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1042 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1043 EFFECTIVE_L2_QUEUE_SIZE(7));
1044 WREG32(VM_L2_CNTL2, 0);
1045 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1046 /* Setup TLB control */
1047 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1048 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1049 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1050 ENABLE_WAIT_L2_QUERY;
1051 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1052 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1053 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1054 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1055 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1056 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1057 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1058 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1059 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1060 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1061 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1062 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1063 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1065 for (i = 0; i < 7; i++)
1066 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1067}
1068
771fe6b9
JG		 1069int r600_mc_wait_for_idle(struct radeon_device *rdev)
1070{
3ce0a23d
JG		 1071 unsigned i;
1072 u32 tmp;
1073
1074 for (i = 0; i < rdev->usec_timeout; i++) {
1075 /* read MC_STATUS */
1076 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1077 if (!tmp)
1078 return 0;
1079 udelay(1);
1080 }
1081 return -1;
771fe6b9
JG		 1082}
1083
a3c1945a 1084static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1085{
a3c1945a 1086 struct rv515_mc_save save;
3ce0a23d
JG		 1087 u32 tmp;
1088 int i, j;
771fe6b9 1089
3ce0a23d
JG		 1090 /* Initialize HDP */
1091 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1092 WREG32((0x2c14 + j), 0x00000000);
1093 WREG32((0x2c18 + j), 0x00000000);
1094 WREG32((0x2c1c + j), 0x00000000);
1095 WREG32((0x2c20 + j), 0x00000000);
1096 WREG32((0x2c24 + j), 0x00000000);
1097 }
1098 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1099
a3c1945a 1100 rv515_mc_stop(rdev, &save);
3ce0a23d 1101 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1102 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1103 }
a3c1945a 1104 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1105 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1106 /* Update configuration */
1a029b76
JG		 1107 if (rdev->flags & RADEON_IS_AGP) {
1108 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1109 /* VRAM before AGP */
1110 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1111 rdev->mc.vram_start >> 12);
1112 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1113 rdev->mc.gtt_end >> 12);
1114 } else {
1115 /* VRAM after AGP */
1116 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1117 rdev->mc.gtt_start >> 12);
1118 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1119 rdev->mc.vram_end >> 12);
1120 }
1121 } else {
1122 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1123 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1124 }
3ce0a23d 1125 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1126 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1127 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1128 WREG32(MC_VM_FB_LOCATION, tmp);
1129 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1130 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1131 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1132 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1133 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1134 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1135 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1136 } else {
1137 WREG32(MC_VM_AGP_BASE, 0);
1138 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1139 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1140 }
3ce0a23d 1141 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1142 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1143 }
a3c1945a 1144 rv515_mc_resume(rdev, &save);
698443d9
DA		 1145 /* we need to own VRAM, so turn off the VGA renderer here
1146 * to stop it overwriting our objects */
d39c3b89 1147 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1148}
1149
d594e46a
JG		 1150/**
1151 * r600_vram_gtt_location - try to find VRAM & GTT location
1152 * @rdev: radeon device structure holding all necessary informations
1153 * @mc: memory controller structure holding memory informations
1154 *
1155 * Function will place try to place VRAM at same place as in CPU (PCI)
1156 * address space as some GPU seems to have issue when we reprogram at
1157 * different address space.
1158 *
1159 * If there is not enough space to fit the unvisible VRAM after the
1160 * aperture then we limit the VRAM size to the aperture.
1161 *
1162 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1163 * them to be in one from GPU point of view so that we can program GPU to
1164 * catch access outside them (weird GPU policy see ??).
1165 *
1166 * This function will never fails, worst case are limiting VRAM or GTT.
1167 *
1168 * Note: GTT start, end, size should be initialized before calling this
1169 * function on AGP platform.
1170 */
0ef0c1f7 1171static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1172{
1173 u64 size_bf, size_af;
1174
1175 if (mc->mc_vram_size > 0xE0000000) {
1176 /* leave room for at least 512M GTT */
1177 dev_warn(rdev->dev, "limiting VRAM\n");
1178 mc->real_vram_size = 0xE0000000;
1179 mc->mc_vram_size = 0xE0000000;
1180 }
1181 if (rdev->flags & RADEON_IS_AGP) {
1182 size_bf = mc->gtt_start;
1183 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1184 if (size_bf > size_af) {
1185 if (mc->mc_vram_size > size_bf) {
1186 dev_warn(rdev->dev, "limiting VRAM\n");
1187 mc->real_vram_size = size_bf;
1188 mc->mc_vram_size = size_bf;
1189 }
1190 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1191 } else {
1192 if (mc->mc_vram_size > size_af) {
1193 dev_warn(rdev->dev, "limiting VRAM\n");
1194 mc->real_vram_size = size_af;
1195 mc->mc_vram_size = size_af;
1196 }
1197 mc->vram_start = mc->gtt_end;
1198 }
1199 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1200 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1201 mc->mc_vram_size >> 20, mc->vram_start,
1202 mc->vram_end, mc->real_vram_size >> 20);
1203 } else {
1204 u64 base = 0;
8961d52d
AD		 1205 if (rdev->flags & RADEON_IS_IGP) {
1206 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1207 base <<= 24;
1208 }
d594e46a 1209 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1210 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1211 radeon_gtt_location(rdev, mc);
1212 }
1213}
1214
3ce0a23d 1215int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1216{
3ce0a23d 1217 u32 tmp;
5885b7a9 1218 int chansize, numchan;
771fe6b9 1219
3ce0a23d 1220 /* Get VRAM informations */
771fe6b9 1221 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1222 tmp = RREG32(RAMCFG);
1223 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1224 chansize = 16;
3ce0a23d 1225 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1226 chansize = 64;
1227 } else {
1228 chansize = 32;
1229 }
5885b7a9
AD		 1230 tmp = RREG32(CHMAP);
1231 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1232 case 0:
1233 default:
1234 numchan = 1;
1235 break;
1236 case 1:
1237 numchan = 2;
1238 break;
1239 case 2:
1240 numchan = 4;
1241 break;
1242 case 3:
1243 numchan = 8;
1244 break;
771fe6b9 1245 }
5885b7a9 1246 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1247 /* Could aper size report 0 ? */
01d73a69
JC		 1248 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1249 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1250 /* Setup GPU memory space */
1251 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1252 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1253 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 1254 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d594e46a 1255 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1256
f892034a
AD		 1257 if (rdev->flags & RADEON_IS_IGP) {
1258 rs690_pm_info(rdev);
06b6476d 1259 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1260 }
f47299c5 1261 radeon_update_bandwidth_info(rdev);
3ce0a23d 1262 return 0;
771fe6b9
JG		 1263}
1264
3ce0a23d
JG		 1265/* We doesn't check that the GPU really needs a reset we simply do the
1266 * reset, it's up to the caller to determine if the GPU needs one. We
1267 * might add an helper function to check that.
1268 */
1269int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1270{
a3c1945a 1271 struct rv515_mc_save save;
3ce0a23d
JG		 1272 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1273 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1274 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1275 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1276 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1277 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1278 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1279 S_008010_GUI_ACTIVE(1);
1280 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1281 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1282 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1283 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1284 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1285 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1286 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1287 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1288 u32 tmp;
771fe6b9 1289
1a029b76
JG		 1290 dev_info(rdev->dev, "GPU softreset \n");
1291 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1292 RREG32(R_008010_GRBM_STATUS));
1293 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1294 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1295 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1296 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1297 rv515_mc_stop(rdev, &save);
1298 if (r600_mc_wait_for_idle(rdev)) {
1299 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1300 }
3ce0a23d 1301 /* Disable CP parsing/prefetching */
90aca4d2 1302 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1303 /* Check if any of the rendering block is busy and reset it */
1304 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1305 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1306 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1307 S_008020_SOFT_RESET_DB(1) |
1308 S_008020_SOFT_RESET_CB(1) |
1309 S_008020_SOFT_RESET_PA(1) |
1310 S_008020_SOFT_RESET_SC(1) |
1311 S_008020_SOFT_RESET_SMX(1) |
1312 S_008020_SOFT_RESET_SPI(1) |
1313 S_008020_SOFT_RESET_SX(1) |
1314 S_008020_SOFT_RESET_SH(1) |
1315 S_008020_SOFT_RESET_TC(1) |
1316 S_008020_SOFT_RESET_TA(1) |
1317 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1318 S_008020_SOFT_RESET_VGT(1);
1a029b76 1319 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1320 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1321 RREG32(R_008020_GRBM_SOFT_RESET);
1322 mdelay(15);
3ce0a23d 1323 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1324 }
1325 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1326 tmp = S_008020_SOFT_RESET_CP(1);
1327 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1328 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1329 RREG32(R_008020_GRBM_SOFT_RESET);
1330 mdelay(15);
3ce0a23d 1331 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1332 /* Wait a little for things to settle down */
225758d8 1333 mdelay(1);
1a029b76
JG		 1334 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1335 RREG32(R_008010_GRBM_STATUS));
1336 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1337 RREG32(R_008014_GRBM_STATUS2));
1338 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1339 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1340 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1341 return 0;
1342}
1343
225758d8
JG		 1344bool r600_gpu_is_lockup(struct radeon_device *rdev)
1345{
1346 u32 srbm_status;
1347 u32 grbm_status;
1348 u32 grbm_status2;
e29ff729 1349 struct r100_gpu_lockup *lockup;
225758d8
JG		 1350 int r;
1351
e29ff729
AD		 1352 if (rdev->family >= CHIP_RV770)
1353 lockup = &rdev->config.rv770.lockup;
1354 else
1355 lockup = &rdev->config.r600.lockup;
1356
225758d8
JG		 1357 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1358 grbm_status = RREG32(R_008010_GRBM_STATUS);
1359 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1360 if (!G_008010_GUI_ACTIVE(grbm_status)) {
e29ff729 1361 r100_gpu_lockup_update(lockup, &rdev->cp);
225758d8
JG		 1362 return false;
1363 }
1364 /* force CP activities */
1365 r = radeon_ring_lock(rdev, 2);
1366 if (!r) {
1367 /* PACKET2 NOP */
1368 radeon_ring_write(rdev, 0x80000000);
1369 radeon_ring_write(rdev, 0x80000000);
1370 radeon_ring_unlock_commit(rdev);
1371 }
1372 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
e29ff729 1373 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
225758d8
JG		 1374}
1375
a2d07b74 1376int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1377{
1378 return r600_gpu_soft_reset(rdev);
1379}
1380
1381static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1382 u32 num_backends,
1383 u32 backend_disable_mask)
1384{
1385 u32 backend_map = 0;
1386 u32 enabled_backends_mask;
1387 u32 enabled_backends_count;
1388 u32 cur_pipe;
1389 u32 swizzle_pipe[R6XX_MAX_PIPES];
1390 u32 cur_backend;
1391 u32 i;
1392
1393 if (num_tile_pipes > R6XX_MAX_PIPES)
1394 num_tile_pipes = R6XX_MAX_PIPES;
1395 if (num_tile_pipes < 1)
1396 num_tile_pipes = 1;
1397 if (num_backends > R6XX_MAX_BACKENDS)
1398 num_backends = R6XX_MAX_BACKENDS;
1399 if (num_backends < 1)
1400 num_backends = 1;
1401
1402 enabled_backends_mask = 0;
1403 enabled_backends_count = 0;
1404 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1405 if (((backend_disable_mask >> i) & 1) == 0) {
1406 enabled_backends_mask |= (1 << i);
1407 ++enabled_backends_count;
1408 }
1409 if (enabled_backends_count == num_backends)
1410 break;
1411 }
1412
1413 if (enabled_backends_count == 0) {
1414 enabled_backends_mask = 1;
1415 enabled_backends_count = 1;
1416 }
1417
1418 if (enabled_backends_count != num_backends)
1419 num_backends = enabled_backends_count;
1420
1421 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1422 switch (num_tile_pipes) {
1423 case 1:
1424 swizzle_pipe[0] = 0;
1425 break;
1426 case 2:
1427 swizzle_pipe[0] = 0;
1428 swizzle_pipe[1] = 1;
1429 break;
1430 case 3:
1431 swizzle_pipe[0] = 0;
1432 swizzle_pipe[1] = 1;
1433 swizzle_pipe[2] = 2;
1434 break;
1435 case 4:
1436 swizzle_pipe[0] = 0;
1437 swizzle_pipe[1] = 1;
1438 swizzle_pipe[2] = 2;
1439 swizzle_pipe[3] = 3;
1440 break;
1441 case 5:
1442 swizzle_pipe[0] = 0;
1443 swizzle_pipe[1] = 1;
1444 swizzle_pipe[2] = 2;
1445 swizzle_pipe[3] = 3;
1446 swizzle_pipe[4] = 4;
1447 break;
1448 case 6:
1449 swizzle_pipe[0] = 0;
1450 swizzle_pipe[1] = 2;
1451 swizzle_pipe[2] = 4;
1452 swizzle_pipe[3] = 5;
1453 swizzle_pipe[4] = 1;
1454 swizzle_pipe[5] = 3;
1455 break;
1456 case 7:
1457 swizzle_pipe[0] = 0;
1458 swizzle_pipe[1] = 2;
1459 swizzle_pipe[2] = 4;
1460 swizzle_pipe[3] = 6;
1461 swizzle_pipe[4] = 1;
1462 swizzle_pipe[5] = 3;
1463 swizzle_pipe[6] = 5;
1464 break;
1465 case 8:
1466 swizzle_pipe[0] = 0;
1467 swizzle_pipe[1] = 2;
1468 swizzle_pipe[2] = 4;
1469 swizzle_pipe[3] = 6;
1470 swizzle_pipe[4] = 1;
1471 swizzle_pipe[5] = 3;
1472 swizzle_pipe[6] = 5;
1473 swizzle_pipe[7] = 7;
1474 break;
1475 }
1476
1477 cur_backend = 0;
1478 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1479 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1480 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1481
1482 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1483
1484 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1485 }
1486
1487 return backend_map;
1488}
1489
1490int r600_count_pipe_bits(uint32_t val)
1491{
1492 int i, ret = 0;
1493
1494 for (i = 0; i < 32; i++) {
1495 ret += val & 1;
1496 val >>= 1;
1497 }
1498 return ret;
771fe6b9
JG		 1499}
1500
3ce0a23d
JG		 1501void r600_gpu_init(struct radeon_device *rdev)
1502{
1503 u32 tiling_config;
1504 u32 ramcfg;
d03f5d59
AD		 1505 u32 backend_map;
1506 u32 cc_rb_backend_disable;
1507 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1508 u32 tmp;
1509 int i, j;
1510 u32 sq_config;
1511 u32 sq_gpr_resource_mgmt_1 = 0;
1512 u32 sq_gpr_resource_mgmt_2 = 0;
1513 u32 sq_thread_resource_mgmt = 0;
1514 u32 sq_stack_resource_mgmt_1 = 0;
1515 u32 sq_stack_resource_mgmt_2 = 0;
1516
1517 /* FIXME: implement */
1518 switch (rdev->family) {
1519 case CHIP_R600:
1520 rdev->config.r600.max_pipes = 4;
1521 rdev->config.r600.max_tile_pipes = 8;
1522 rdev->config.r600.max_simds = 4;
1523 rdev->config.r600.max_backends = 4;
1524 rdev->config.r600.max_gprs = 256;
1525 rdev->config.r600.max_threads = 192;
1526 rdev->config.r600.max_stack_entries = 256;
1527 rdev->config.r600.max_hw_contexts = 8;
1528 rdev->config.r600.max_gs_threads = 16;
1529 rdev->config.r600.sx_max_export_size = 128;
1530 rdev->config.r600.sx_max_export_pos_size = 16;
1531 rdev->config.r600.sx_max_export_smx_size = 128;
1532 rdev->config.r600.sq_num_cf_insts = 2;
1533 break;
1534 case CHIP_RV630:
1535 case CHIP_RV635:
1536 rdev->config.r600.max_pipes = 2;
1537 rdev->config.r600.max_tile_pipes = 2;
1538 rdev->config.r600.max_simds = 3;
1539 rdev->config.r600.max_backends = 1;
1540 rdev->config.r600.max_gprs = 128;
1541 rdev->config.r600.max_threads = 192;
1542 rdev->config.r600.max_stack_entries = 128;
1543 rdev->config.r600.max_hw_contexts = 8;
1544 rdev->config.r600.max_gs_threads = 4;
1545 rdev->config.r600.sx_max_export_size = 128;
1546 rdev->config.r600.sx_max_export_pos_size = 16;
1547 rdev->config.r600.sx_max_export_smx_size = 128;
1548 rdev->config.r600.sq_num_cf_insts = 2;
1549 break;
1550 case CHIP_RV610:
1551 case CHIP_RV620:
1552 case CHIP_RS780:
1553 case CHIP_RS880:
1554 rdev->config.r600.max_pipes = 1;
1555 rdev->config.r600.max_tile_pipes = 1;
1556 rdev->config.r600.max_simds = 2;
1557 rdev->config.r600.max_backends = 1;
1558 rdev->config.r600.max_gprs = 128;
1559 rdev->config.r600.max_threads = 192;
1560 rdev->config.r600.max_stack_entries = 128;
1561 rdev->config.r600.max_hw_contexts = 4;
1562 rdev->config.r600.max_gs_threads = 4;
1563 rdev->config.r600.sx_max_export_size = 128;
1564 rdev->config.r600.sx_max_export_pos_size = 16;
1565 rdev->config.r600.sx_max_export_smx_size = 128;
1566 rdev->config.r600.sq_num_cf_insts = 1;
1567 break;
1568 case CHIP_RV670:
1569 rdev->config.r600.max_pipes = 4;
1570 rdev->config.r600.max_tile_pipes = 4;
1571 rdev->config.r600.max_simds = 4;
1572 rdev->config.r600.max_backends = 4;
1573 rdev->config.r600.max_gprs = 192;
1574 rdev->config.r600.max_threads = 192;
1575 rdev->config.r600.max_stack_entries = 256;
1576 rdev->config.r600.max_hw_contexts = 8;
1577 rdev->config.r600.max_gs_threads = 16;
1578 rdev->config.r600.sx_max_export_size = 128;
1579 rdev->config.r600.sx_max_export_pos_size = 16;
1580 rdev->config.r600.sx_max_export_smx_size = 128;
1581 rdev->config.r600.sq_num_cf_insts = 2;
1582 break;
1583 default:
1584 break;
1585 }
1586
1587 /* Initialize HDP */
1588 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1589 WREG32((0x2c14 + j), 0x00000000);
1590 WREG32((0x2c18 + j), 0x00000000);
1591 WREG32((0x2c1c + j), 0x00000000);
1592 WREG32((0x2c20 + j), 0x00000000);
1593 WREG32((0x2c24 + j), 0x00000000);
1594 }
1595
1596 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1597
1598 /* Setup tiling */
1599 tiling_config = 0;
1600 ramcfg = RREG32(RAMCFG);
1601 switch (rdev->config.r600.max_tile_pipes) {
1602 case 1:
1603 tiling_config |= PIPE_TILING(0);
1604 break;
1605 case 2:
1606 tiling_config |= PIPE_TILING(1);
1607 break;
1608 case 4:
1609 tiling_config |= PIPE_TILING(2);
1610 break;
1611 case 8:
1612 tiling_config |= PIPE_TILING(3);
1613 break;
1614 default:
1615 break;
1616 }
d03f5d59 1617 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1618 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1619 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1
AD		 1620 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1621 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1622 rdev->config.r600.tiling_group_size = 512;
1623 else
1624 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1625 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1626 if (tmp > 3) {
1627 tiling_config |= ROW_TILING(3);
1628 tiling_config |= SAMPLE_SPLIT(3);
1629 } else {
1630 tiling_config |= ROW_TILING(tmp);
1631 tiling_config |= SAMPLE_SPLIT(tmp);
1632 }
1633 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1634
1635 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1636 cc_rb_backend_disable |=
1637 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1638
1639 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1640 cc_gc_shader_pipe_config |=
1641 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1642 cc_gc_shader_pipe_config |=
1643 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1644
1645 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1646 (R6XX_MAX_BACKENDS -
1647 r600_count_pipe_bits((cc_rb_backend_disable &
1648 R6XX_MAX_BACKENDS_MASK) >> 16)),
1649 (cc_rb_backend_disable >> 16));
e7aeeba6 1650 rdev->config.r600.tile_config = tiling_config;
d03f5d59 1651 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1652 WREG32(GB_TILING_CONFIG, tiling_config);
1653 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1654 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1655
3ce0a23d 1656 /* Setup pipes */
d03f5d59
AD		 1657 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1658 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1659 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1660
d03f5d59 1661 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1662 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1663 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1664
1665 /* Setup some CP states */
1666 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1667 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1668
1669 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1670 SYNC_WALKER | SYNC_ALIGNER));
1671 /* Setup various GPU states */
1672 if (rdev->family == CHIP_RV670)
1673 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1674
1675 tmp = RREG32(SX_DEBUG_1);
1676 tmp |= SMX_EVENT_RELEASE;
1677 if ((rdev->family > CHIP_R600))
1678 tmp |= ENABLE_NEW_SMX_ADDRESS;
1679 WREG32(SX_DEBUG_1, tmp);
1680
1681 if (((rdev->family) == CHIP_R600) ||
1682 ((rdev->family) == CHIP_RV630) ||
1683 ((rdev->family) == CHIP_RV610) ||
1684 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1685 ((rdev->family) == CHIP_RS780) ||
1686 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1687 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1688 } else {
1689 WREG32(DB_DEBUG, 0);
1690 }
1691 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1692 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1693
1694 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1695 WREG32(VGT_NUM_INSTANCES, 0);
1696
1697 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1698 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1699
1700 tmp = RREG32(SQ_MS_FIFO_SIZES);
1701 if (((rdev->family) == CHIP_RV610) ||
1702 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1703 ((rdev->family) == CHIP_RS780) ||
1704 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1705 tmp = (CACHE_FIFO_SIZE(0xa) |
1706 FETCH_FIFO_HIWATER(0xa) |
1707 DONE_FIFO_HIWATER(0xe0) |
1708 ALU_UPDATE_FIFO_HIWATER(0x8));
1709 } else if (((rdev->family) == CHIP_R600) ||
1710 ((rdev->family) == CHIP_RV630)) {
1711 tmp &= ~DONE_FIFO_HIWATER(0xff);
1712 tmp |= DONE_FIFO_HIWATER(0x4);
1713 }
1714 WREG32(SQ_MS_FIFO_SIZES, tmp);
1715
1716 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1717 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1718 */
1719 sq_config = RREG32(SQ_CONFIG);
1720 sq_config &= ~(PS_PRIO(3) |
1721 VS_PRIO(3) |
1722 GS_PRIO(3) |
1723 ES_PRIO(3));
1724 sq_config |= (DX9_CONSTS |
1725 VC_ENABLE |
1726 PS_PRIO(0) |
1727 VS_PRIO(1) |
1728 GS_PRIO(2) |
1729 ES_PRIO(3));
1730
1731 if ((rdev->family) == CHIP_R600) {
1732 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1733 NUM_VS_GPRS(124) |
1734 NUM_CLAUSE_TEMP_GPRS(4));
1735 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1736 NUM_ES_GPRS(0));
1737 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1738 NUM_VS_THREADS(48) |
1739 NUM_GS_THREADS(4) |
1740 NUM_ES_THREADS(4));
1741 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1742 NUM_VS_STACK_ENTRIES(128));
1743 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1744 NUM_ES_STACK_ENTRIES(0));
1745 } else if (((rdev->family) == CHIP_RV610) ||
1746 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1747 ((rdev->family) == CHIP_RS780) ||
1748 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1749 /* no vertex cache */
1750 sq_config &= ~VC_ENABLE;
1751
1752 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1753 NUM_VS_GPRS(44) |
1754 NUM_CLAUSE_TEMP_GPRS(2));
1755 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1756 NUM_ES_GPRS(17));
1757 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1758 NUM_VS_THREADS(78) |
1759 NUM_GS_THREADS(4) |
1760 NUM_ES_THREADS(31));
1761 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1762 NUM_VS_STACK_ENTRIES(40));
1763 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1764 NUM_ES_STACK_ENTRIES(16));
1765 } else if (((rdev->family) == CHIP_RV630) ||
1766 ((rdev->family) == CHIP_RV635)) {
1767 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1768 NUM_VS_GPRS(44) |
1769 NUM_CLAUSE_TEMP_GPRS(2));
1770 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1771 NUM_ES_GPRS(18));
1772 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1773 NUM_VS_THREADS(78) |
1774 NUM_GS_THREADS(4) |
1775 NUM_ES_THREADS(31));
1776 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1777 NUM_VS_STACK_ENTRIES(40));
1778 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1779 NUM_ES_STACK_ENTRIES(16));
1780 } else if ((rdev->family) == CHIP_RV670) {
1781 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1782 NUM_VS_GPRS(44) |
1783 NUM_CLAUSE_TEMP_GPRS(2));
1784 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1785 NUM_ES_GPRS(17));
1786 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1787 NUM_VS_THREADS(78) |
1788 NUM_GS_THREADS(4) |
1789 NUM_ES_THREADS(31));
1790 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1791 NUM_VS_STACK_ENTRIES(64));
1792 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1793 NUM_ES_STACK_ENTRIES(64));
1794 }
1795
1796 WREG32(SQ_CONFIG, sq_config);
1797 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1798 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1799 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1800 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1801 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1802
1803 if (((rdev->family) == CHIP_RV610) ||
1804 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1805 ((rdev->family) == CHIP_RS780) ||
1806 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1807 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1808 } else {
1809 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1810 }
1811
1812 /* More default values. 2D/3D driver should adjust as needed */
1813 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1814 S1_X(0x4) | S1_Y(0xc)));
1815 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1816 S1_X(0x2) | S1_Y(0x2) |
1817 S2_X(0xa) | S2_Y(0x6) |
1818 S3_X(0x6) | S3_Y(0xa)));
1819 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1820 S1_X(0x4) | S1_Y(0xc) |
1821 S2_X(0x1) | S2_Y(0x6) |
1822 S3_X(0xa) | S3_Y(0xe)));
1823 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1824 S5_X(0x0) | S5_Y(0x0) |
1825 S6_X(0xb) | S6_Y(0x4) |
1826 S7_X(0x7) | S7_Y(0x8)));
1827
1828 WREG32(VGT_STRMOUT_EN, 0);
1829 tmp = rdev->config.r600.max_pipes * 16;
1830 switch (rdev->family) {
1831 case CHIP_RV610:
3ce0a23d 1832 case CHIP_RV620:
ee59f2b4
AD		 1833 case CHIP_RS780:
1834 case CHIP_RS880:
3ce0a23d
JG		 1835 tmp += 32;
1836 break;
1837 case CHIP_RV670:
1838 tmp += 128;
1839 break;
1840 default:
1841 break;
1842 }
1843 if (tmp > 256) {
1844 tmp = 256;
1845 }
1846 WREG32(VGT_ES_PER_GS, 128);
1847 WREG32(VGT_GS_PER_ES, tmp);
1848 WREG32(VGT_GS_PER_VS, 2);
1849 WREG32(VGT_GS_VERTEX_REUSE, 16);
1850
1851 /* more default values. 2D/3D driver should adjust as needed */
1852 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1853 WREG32(VGT_STRMOUT_EN, 0);
1854 WREG32(SX_MISC, 0);
1855 WREG32(PA_SC_MODE_CNTL, 0);
1856 WREG32(PA_SC_AA_CONFIG, 0);
1857 WREG32(PA_SC_LINE_STIPPLE, 0);
1858 WREG32(SPI_INPUT_Z, 0);
1859 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1860 WREG32(CB_COLOR7_FRAG, 0);
1861
1862 /* Clear render buffer base addresses */
1863 WREG32(CB_COLOR0_BASE, 0);
1864 WREG32(CB_COLOR1_BASE, 0);
1865 WREG32(CB_COLOR2_BASE, 0);
1866 WREG32(CB_COLOR3_BASE, 0);
1867 WREG32(CB_COLOR4_BASE, 0);
1868 WREG32(CB_COLOR5_BASE, 0);
1869 WREG32(CB_COLOR6_BASE, 0);
1870 WREG32(CB_COLOR7_BASE, 0);
1871 WREG32(CB_COLOR7_FRAG, 0);
1872
1873 switch (rdev->family) {
1874 case CHIP_RV610:
3ce0a23d 1875 case CHIP_RV620:
ee59f2b4
AD		 1876 case CHIP_RS780:
1877 case CHIP_RS880:
3ce0a23d
JG		 1878 tmp = TC_L2_SIZE(8);
1879 break;
1880 case CHIP_RV630:
1881 case CHIP_RV635:
1882 tmp = TC_L2_SIZE(4);
1883 break;
1884 case CHIP_R600:
1885 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1886 break;
1887 default:
1888 tmp = TC_L2_SIZE(0);
1889 break;
1890 }
1891 WREG32(TC_CNTL, tmp);
1892
1893 tmp = RREG32(HDP_HOST_PATH_CNTL);
1894 WREG32(HDP_HOST_PATH_CNTL, tmp);
1895
1896 tmp = RREG32(ARB_POP);
1897 tmp |= ENABLE_TC128;
1898 WREG32(ARB_POP, tmp);
1899
1900 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1901 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1902 NUM_CLIP_SEQ(3)));
1903 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1904}
1905
1906
771fe6b9
JG		 1907/*
1908 * Indirect registers accessor
1909 */
3ce0a23d
JG		 1910u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1911{
1912 u32 r;
1913
1914 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1915 (void)RREG32(PCIE_PORT_INDEX);
1916 r = RREG32(PCIE_PORT_DATA);
1917 return r;
1918}
1919
1920void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1921{
1922 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1923 (void)RREG32(PCIE_PORT_INDEX);
1924 WREG32(PCIE_PORT_DATA, (v));
1925 (void)RREG32(PCIE_PORT_DATA);
1926}
1927
3ce0a23d
JG		 1928/*
1929 * CP & Ring
1930 */
1931void r600_cp_stop(struct radeon_device *rdev)
1932{
c919b371 1933 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
3ce0a23d 1934 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1935 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1936}
1937
d8f60cfc 1938int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1939{
1940 struct platform_device *pdev;
1941 const char *chip_name;
d8f60cfc
AD		 1942 const char *rlc_chip_name;
1943 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1944 char fw_name[30];
1945 int err;
1946
1947 DRM_DEBUG("\n");
1948
1949 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1950 err = IS_ERR(pdev);
1951 if (err) {
1952 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1953 return -EINVAL;
1954 }
1955
1956 switch (rdev->family) {
d8f60cfc
AD		 1957 case CHIP_R600:
1958 chip_name = "R600";
1959 rlc_chip_name = "R600";
1960 break;
1961 case CHIP_RV610:
1962 chip_name = "RV610";
1963 rlc_chip_name = "R600";
1964 break;
1965 case CHIP_RV630:
1966 chip_name = "RV630";
1967 rlc_chip_name = "R600";
1968 break;
1969 case CHIP_RV620:
1970 chip_name = "RV620";
1971 rlc_chip_name = "R600";
1972 break;
1973 case CHIP_RV635:
1974 chip_name = "RV635";
1975 rlc_chip_name = "R600";
1976 break;
1977 case CHIP_RV670:
1978 chip_name = "RV670";
1979 rlc_chip_name = "R600";
1980 break;
3ce0a23d 1981 case CHIP_RS780:
d8f60cfc
AD		 1982 case CHIP_RS880:
1983 chip_name = "RS780";
1984 rlc_chip_name = "R600";
1985 break;
1986 case CHIP_RV770:
1987 chip_name = "RV770";
1988 rlc_chip_name = "R700";
1989 break;
3ce0a23d 1990 case CHIP_RV730:
d8f60cfc
AD		 1991 case CHIP_RV740:
1992 chip_name = "RV730";
1993 rlc_chip_name = "R700";
1994 break;
1995 case CHIP_RV710:
1996 chip_name = "RV710";
1997 rlc_chip_name = "R700";
1998 break;
fe251e2f
AD		 1999 case CHIP_CEDAR:
2000 chip_name = "CEDAR";
45f9a39b 2001 rlc_chip_name = "CEDAR";
fe251e2f
AD		 2002 break;
2003 case CHIP_REDWOOD:
2004 chip_name = "REDWOOD";
45f9a39b 2005 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2006 break;
2007 case CHIP_JUNIPER:
2008 chip_name = "JUNIPER";
45f9a39b 2009 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2010 break;
2011 case CHIP_CYPRESS:
2012 case CHIP_HEMLOCK:
2013 chip_name = "CYPRESS";
45f9a39b 2014 rlc_chip_name = "CYPRESS";
fe251e2f 2015 break;
439bd6cd
AD		 2016 case CHIP_PALM:
2017 chip_name = "PALM";
2018 rlc_chip_name = "SUMO";
2019 break;
3ce0a23d
JG		 2020 default: BUG();
2021 }
2022
fe251e2f
AD		 2023 if (rdev->family >= CHIP_CEDAR) {
2024 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2025 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2026 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2027 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2028 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2029 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2030 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2031 } else {
2032 pfp_req_size = PFP_UCODE_SIZE * 4;
2033 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2034 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2035 }
2036
d8f60cfc 2037 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2038
2039 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2040 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2041 if (err)
2042 goto out;
2043 if (rdev->pfp_fw->size != pfp_req_size) {
2044 printk(KERN_ERR
2045 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2046 rdev->pfp_fw->size, fw_name);
2047 err = -EINVAL;
2048 goto out;
2049 }
2050
2051 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2052 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2053 if (err)
2054 goto out;
2055 if (rdev->me_fw->size != me_req_size) {
2056 printk(KERN_ERR
2057 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2058 rdev->me_fw->size, fw_name);
2059 err = -EINVAL;
2060 }
d8f60cfc
AD		 2061
2062 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2063 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2064 if (err)
2065 goto out;
2066 if (rdev->rlc_fw->size != rlc_req_size) {
2067 printk(KERN_ERR
2068 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2069 rdev->rlc_fw->size, fw_name);
2070 err = -EINVAL;
2071 }
2072
3ce0a23d
JG		 2073out:
2074 platform_device_unregister(pdev);
2075
2076 if (err) {
2077 if (err != -EINVAL)
2078 printk(KERN_ERR
2079 "r600_cp: Failed to load firmware \"%s\"\n",
2080 fw_name);
2081 release_firmware(rdev->pfp_fw);
2082 rdev->pfp_fw = NULL;
2083 release_firmware(rdev->me_fw);
2084 rdev->me_fw = NULL;
d8f60cfc
AD		 2085 release_firmware(rdev->rlc_fw);
2086 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2087 }
2088 return err;
2089}
2090
2091static int r600_cp_load_microcode(struct radeon_device *rdev)
2092{
2093 const __be32 *fw_data;
2094 int i;
2095
2096 if (!rdev->me_fw || !rdev->pfp_fw)
2097 return -EINVAL;
2098
2099 r600_cp_stop(rdev);
2100
2101 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2102
2103 /* Reset cp */
2104 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2105 RREG32(GRBM_SOFT_RESET);
2106 mdelay(15);
2107 WREG32(GRBM_SOFT_RESET, 0);
2108
2109 WREG32(CP_ME_RAM_WADDR, 0);
2110
2111 fw_data = (const __be32 *)rdev->me_fw->data;
2112 WREG32(CP_ME_RAM_WADDR, 0);
2113 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2114 WREG32(CP_ME_RAM_DATA,
2115 be32_to_cpup(fw_data++));
2116
2117 fw_data = (const __be32 *)rdev->pfp_fw->data;
2118 WREG32(CP_PFP_UCODE_ADDR, 0);
2119 for (i = 0; i < PFP_UCODE_SIZE; i++)
2120 WREG32(CP_PFP_UCODE_DATA,
2121 be32_to_cpup(fw_data++));
2122
2123 WREG32(CP_PFP_UCODE_ADDR, 0);
2124 WREG32(CP_ME_RAM_WADDR, 0);
2125 WREG32(CP_ME_RAM_RADDR, 0);
2126 return 0;
2127}
2128
2129int r600_cp_start(struct radeon_device *rdev)
2130{
2131 int r;
2132 uint32_t cp_me;
2133
2134 r = radeon_ring_lock(rdev, 7);
2135 if (r) {
2136 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2137 return r;
2138 }
2139 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2140 radeon_ring_write(rdev, 0x1);
7e7b41d2 2141 if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2142 radeon_ring_write(rdev, 0x0);
2143 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2144 } else {
2145 radeon_ring_write(rdev, 0x3);
2146 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2147 }
2148 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2149 radeon_ring_write(rdev, 0);
2150 radeon_ring_write(rdev, 0);
2151 radeon_ring_unlock_commit(rdev);
2152
2153 cp_me = 0xff;
2154 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2155 return 0;
2156}
2157
2158int r600_cp_resume(struct radeon_device *rdev)
2159{
2160 u32 tmp;
2161 u32 rb_bufsz;
2162 int r;
2163
2164 /* Reset cp */
2165 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2166 RREG32(GRBM_SOFT_RESET);
2167 mdelay(15);
2168 WREG32(GRBM_SOFT_RESET, 0);
2169
2170 /* Set ring buffer size */
2171 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 2172 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2173#ifdef __BIG_ENDIAN
d6f28938 2174 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2175#endif
d6f28938 2176 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2177 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2178
2179 /* Set the write pointer delay */
2180 WREG32(CP_RB_WPTR_DELAY, 0);
2181
2182 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2183 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2184 WREG32(CP_RB_RPTR_WR, 0);
2185 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 2186
2187 /* set the wb address whether it's enabled or not */
2188 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2189 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2190 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2191
2192 if (rdev->wb.enabled)
2193 WREG32(SCRATCH_UMSK, 0xff);
2194 else {
2195 tmp |= RB_NO_UPDATE;
2196 WREG32(SCRATCH_UMSK, 0);
2197 }
2198
3ce0a23d
JG		 2199 mdelay(1);
2200 WREG32(CP_RB_CNTL, tmp);
2201
2202 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2203 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2204
2205 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2206 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2207
2208 r600_cp_start(rdev);
2209 rdev->cp.ready = true;
2210 r = radeon_ring_test(rdev);
2211 if (r) {
2212 rdev->cp.ready = false;
2213 return r;
2214 }
2215 return 0;
2216}
2217
2218void r600_cp_commit(struct radeon_device *rdev)
2219{
2220 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2221 (void)RREG32(CP_RB_WPTR);
2222}
2223
2224void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2225{
2226 u32 rb_bufsz;
2227
2228 /* Align ring size */
2229 rb_bufsz = drm_order(ring_size / 8);
2230 ring_size = (1 << (rb_bufsz + 1)) * 4;
2231 rdev->cp.ring_size = ring_size;
2232 rdev->cp.align_mask = 16 - 1;
2233}
2234
655efd3d
JG		 2235void r600_cp_fini(struct radeon_device *rdev)
2236{
2237 r600_cp_stop(rdev);
2238 radeon_ring_fini(rdev);
2239}
2240
3ce0a23d
JG		 2241
2242/*
2243 * GPU scratch registers helpers function.
2244 */
2245void r600_scratch_init(struct radeon_device *rdev)
2246{
2247 int i;
2248
2249 rdev->scratch.num_reg = 7;
724c80e1 2250 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2251 for (i = 0; i < rdev->scratch.num_reg; i++) {
2252 rdev->scratch.free[i] = true;
724c80e1 2253 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2254 }
2255}
2256
2257int r600_ring_test(struct radeon_device *rdev)
2258{
2259 uint32_t scratch;
2260 uint32_t tmp = 0;
2261 unsigned i;
2262 int r;
2263
2264 r = radeon_scratch_get(rdev, &scratch);
2265 if (r) {
2266 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2267 return r;
2268 }
2269 WREG32(scratch, 0xCAFEDEAD);
2270 r = radeon_ring_lock(rdev, 3);
2271 if (r) {
2272 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2273 radeon_scratch_free(rdev, scratch);
2274 return r;
2275 }
2276 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2277 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2278 radeon_ring_write(rdev, 0xDEADBEEF);
2279 radeon_ring_unlock_commit(rdev);
2280 for (i = 0; i < rdev->usec_timeout; i++) {
2281 tmp = RREG32(scratch);
2282 if (tmp == 0xDEADBEEF)
2283 break;
2284 DRM_UDELAY(1);
2285 }
2286 if (i < rdev->usec_timeout) {
2287 DRM_INFO("ring test succeeded in %d usecs\n", i);
2288 } else {
2289 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2290 scratch, tmp);
2291 r = -EINVAL;
2292 }
2293 radeon_scratch_free(rdev, scratch);
2294 return r;
2295}
2296
3ce0a23d
JG		 2297void r600_fence_ring_emit(struct radeon_device *rdev,
2298 struct radeon_fence *fence)
2299{
d0f8a854
AD		 2300 if (rdev->wb.use_event) {
2301 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2302 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2303 /* EVENT_WRITE_EOP - flush caches, send int */
2304 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2305 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2306 radeon_ring_write(rdev, addr & 0xffffffff);
2307 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2308 radeon_ring_write(rdev, fence->seq);
2309 radeon_ring_write(rdev, 0);
2310 } else {
2311 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2312 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2313 /* wait for 3D idle clean */
2314 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2315 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2316 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2317 /* Emit fence sequence & fire IRQ */
2318 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2319 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2320 radeon_ring_write(rdev, fence->seq);
2321 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2322 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2323 radeon_ring_write(rdev, RB_INT_STAT);
2324 }
3ce0a23d
JG		 2325}
2326
3ce0a23d
JG		 2327int r600_copy_blit(struct radeon_device *rdev,
2328 uint64_t src_offset, uint64_t dst_offset,
2329 unsigned num_pages, struct radeon_fence *fence)
2330{
ff82f052
JG		 2331 int r;
2332
2333 mutex_lock(&rdev->r600_blit.mutex);
2334 rdev->r600_blit.vb_ib = NULL;
2335 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2336 if (r) {
2337 if (rdev->r600_blit.vb_ib)
2338 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2339 mutex_unlock(&rdev->r600_blit.mutex);
2340 return r;
2341 }
a77f1718 2342 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2343 r600_blit_done_copy(rdev, fence);
ff82f052 2344 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2345 return 0;
2346}
2347
3ce0a23d
JG		 2348int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2349 uint32_t tiling_flags, uint32_t pitch,
2350 uint32_t offset, uint32_t obj_size)
2351{
2352 /* FIXME: implement */
2353 return 0;
2354}
2355
2356void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2357{
2358 /* FIXME: implement */
2359}
2360
fc30b8ef 2361int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2362{
2363 int r;
2364
9e46a48d
AD		 2365 /* enable pcie gen2 link */
2366 r600_pcie_gen2_enable(rdev);
2367
779720a3
AD		 2368 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2369 r = r600_init_microcode(rdev);
2370 if (r) {
2371 DRM_ERROR("Failed to load firmware!\n");
2372 return r;
2373 }
2374 }
2375
a3c1945a 2376 r600_mc_program(rdev);
1a029b76
JG		 2377 if (rdev->flags & RADEON_IS_AGP) {
2378 r600_agp_enable(rdev);
2379 } else {
2380 r = r600_pcie_gart_enable(rdev);
2381 if (r)
2382 return r;
2383 }
3ce0a23d 2384 r600_gpu_init(rdev);
c38c7b64
JG		 2385 r = r600_blit_init(rdev);
2386 if (r) {
2387 r600_blit_fini(rdev);
2388 rdev->asic->copy = NULL;
2389 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2390 }
b70d6bb3 2391
724c80e1
AD		 2392 /* allocate wb buffer */
2393 r = radeon_wb_init(rdev);
2394 if (r)
2395 return r;
2396
d8f60cfc 2397 /* Enable IRQ */
d8f60cfc
AD		 2398 r = r600_irq_init(rdev);
2399 if (r) {
2400 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2401 radeon_irq_kms_fini(rdev);
2402 return r;
2403 }
2404 r600_irq_set(rdev);
2405
3ce0a23d
JG		 2406 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2407 if (r)
2408 return r;
2409 r = r600_cp_load_microcode(rdev);
2410 if (r)
2411 return r;
2412 r = r600_cp_resume(rdev);
2413 if (r)
2414 return r;
724c80e1 2415
3ce0a23d
JG		 2416 return 0;
2417}
2418
28d52043
DA		 2419void r600_vga_set_state(struct radeon_device *rdev, bool state)
2420{
2421 uint32_t temp;
2422
2423 temp = RREG32(CONFIG_CNTL);
2424 if (state == false) {
2425 temp &= ~(1<<0);
2426 temp |= (1<<1);
2427 } else {
2428 temp &= ~(1<<1);
2429 }
2430 WREG32(CONFIG_CNTL, temp);
2431}
2432
fc30b8ef
DA		 2433int r600_resume(struct radeon_device *rdev)
2434{
2435 int r;
2436
1a029b76
JG		 2437 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2438 * posting will perform necessary task to bring back GPU into good
2439 * shape.
2440 */
fc30b8ef 2441 /* post card */
e7d40b9a 2442 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2443
2444 r = r600_startup(rdev);
2445 if (r) {
2446 DRM_ERROR("r600 startup failed on resume\n");
2447 return r;
2448 }
2449
62a8ea3f 2450 r = r600_ib_test(rdev);
fc30b8ef
DA		 2451 if (r) {
2452 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2453 return r;
2454 }
38fd2c6f
RM		 2455
2456 r = r600_audio_init(rdev);
2457 if (r) {
2458 DRM_ERROR("radeon: audio resume failed\n");
2459 return r;
2460 }
2461
fc30b8ef
DA		 2462 return r;
2463}
2464
3ce0a23d
JG		 2465int r600_suspend(struct radeon_device *rdev)
2466{
4c788679
JG		 2467 int r;
2468
38fd2c6f 2469 r600_audio_fini(rdev);
3ce0a23d
JG		 2470 /* FIXME: we should wait for ring to be empty */
2471 r600_cp_stop(rdev);
bc1a631e 2472 rdev->cp.ready = false;
0c45249f 2473 r600_irq_suspend(rdev);
724c80e1 2474 radeon_wb_disable(rdev);
4aac0473 2475 r600_pcie_gart_disable(rdev);
bc1a631e 2476 /* unpin shaders bo */
30d2d9a5
JG		 2477 if (rdev->r600_blit.shader_obj) {
2478 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2479 if (!r) {
2480 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2481 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2482 }
2483 }
3ce0a23d
JG		 2484 return 0;
2485}
2486
2487/* Plan is to move initialization in that function and use
2488 * helper function so that radeon_device_init pretty much
2489 * do nothing more than calling asic specific function. This
2490 * should also allow to remove a bunch of callback function
2491 * like vram_info.
2492 */
2493int r600_init(struct radeon_device *rdev)
771fe6b9 2494{
3ce0a23d 2495 int r;
771fe6b9 2496
3ce0a23d
JG		 2497 r = radeon_dummy_page_init(rdev);
2498 if (r)
2499 return r;
2500 if (r600_debugfs_mc_info_init(rdev)) {
2501 DRM_ERROR("Failed to register debugfs file for mc !\n");
2502 }
2503 /* This don't do much */
2504 r = radeon_gem_init(rdev);
2505 if (r)
2506 return r;
2507 /* Read BIOS */
2508 if (!radeon_get_bios(rdev)) {
2509 if (ASIC_IS_AVIVO(rdev))
2510 return -EINVAL;
2511 }
2512 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2513 if (!rdev->is_atom_bios) {
2514 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2515 return -EINVAL;
e7d40b9a 2516 }
3ce0a23d
JG		 2517 r = radeon_atombios_init(rdev);
2518 if (r)
2519 return r;
2520 /* Post card if necessary */
fd909c37 2521 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2522 if (!rdev->bios) {
2523 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2524 return -EINVAL;
2525 }
3ce0a23d
JG		 2526 DRM_INFO("GPU not posted. posting now...\n");
2527 atom_asic_init(rdev->mode_info.atom_context);
2528 }
2529 /* Initialize scratch registers */
2530 r600_scratch_init(rdev);
2531 /* Initialize surface registers */
2532 radeon_surface_init(rdev);
7433874e 2533 /* Initialize clocks */
5e6dde7e 2534 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2535 /* Fence driver */
2536 r = radeon_fence_driver_init(rdev);
2537 if (r)
2538 return r;
700a0cc0
JG		 2539 if (rdev->flags & RADEON_IS_AGP) {
2540 r = radeon_agp_init(rdev);
2541 if (r)
2542 radeon_agp_disable(rdev);
2543 }
3ce0a23d 2544 r = r600_mc_init(rdev);
b574f251 2545 if (r)
3ce0a23d 2546 return r;
3ce0a23d 2547 /* Memory manager */
4c788679 2548 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2549 if (r)
2550 return r;
d8f60cfc
AD		 2551
2552 r = radeon_irq_kms_init(rdev);
2553 if (r)
2554 return r;
2555
3ce0a23d
JG		 2556 rdev->cp.ring_obj = NULL;
2557 r600_ring_init(rdev, 1024 * 1024);
2558
d8f60cfc
AD		 2559 rdev->ih.ring_obj = NULL;
2560 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2561
4aac0473
JG		 2562 r = r600_pcie_gart_init(rdev);
2563 if (r)
2564 return r;
2565
779720a3 2566 rdev->accel_working = true;
fc30b8ef 2567 r = r600_startup(rdev);
3ce0a23d 2568 if (r) {
655efd3d
JG		 2569 dev_err(rdev->dev, "disabling GPU acceleration\n");
2570 r600_cp_fini(rdev);
655efd3d 2571 r600_irq_fini(rdev);
724c80e1 2572 radeon_wb_fini(rdev);
655efd3d 2573 radeon_irq_kms_fini(rdev);
75c81298 2574 r600_pcie_gart_fini(rdev);
733289c2 2575 rdev->accel_working = false;
3ce0a23d 2576 }
733289c2
JG		 2577 if (rdev->accel_working) {
2578 r = radeon_ib_pool_init(rdev);
2579 if (r) {
db96380e 2580 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2581 rdev->accel_working = false;
db96380e
JG		 2582 } else {
2583 r = r600_ib_test(rdev);
2584 if (r) {
2585 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2586 rdev->accel_working = false;
2587 }
733289c2 2588 }
3ce0a23d 2589 }
dafc3bd5
CK		 2590
2591 r = r600_audio_init(rdev);
2592 if (r)
2593 return r; /* TODO error handling */
3ce0a23d
JG		 2594 return 0;
2595}
2596
2597void r600_fini(struct radeon_device *rdev)
2598{
dafc3bd5 2599 r600_audio_fini(rdev);
3ce0a23d 2600 r600_blit_fini(rdev);
655efd3d 2601 r600_cp_fini(rdev);
d8f60cfc 2602 r600_irq_fini(rdev);
724c80e1 2603 radeon_wb_fini(rdev);
d8f60cfc 2604 radeon_irq_kms_fini(rdev);
4aac0473 2605 r600_pcie_gart_fini(rdev);
655efd3d 2606 radeon_agp_fini(rdev);
3ce0a23d
JG		 2607 radeon_gem_fini(rdev);
2608 radeon_fence_driver_fini(rdev);
4c788679 2609 radeon_bo_fini(rdev);
e7d40b9a 2610 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2611 kfree(rdev->bios);
2612 rdev->bios = NULL;
2613 radeon_dummy_page_fini(rdev);
2614}
2615
2616
2617/*
2618 * CS stuff
2619 */
2620void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2621{
2622 /* FIXME: implement */
2623 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2624 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2625 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2626 radeon_ring_write(rdev, ib->length_dw);
2627}
2628
2629int r600_ib_test(struct radeon_device *rdev)
2630{
2631 struct radeon_ib *ib;
2632 uint32_t scratch;
2633 uint32_t tmp = 0;
2634 unsigned i;
2635 int r;
2636
2637 r = radeon_scratch_get(rdev, &scratch);
2638 if (r) {
2639 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2640 return r;
2641 }
2642 WREG32(scratch, 0xCAFEDEAD);
2643 r = radeon_ib_get(rdev, &ib);
2644 if (r) {
2645 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2646 return r;
2647 }
2648 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2649 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2650 ib->ptr[2] = 0xDEADBEEF;
2651 ib->ptr[3] = PACKET2(0);
2652 ib->ptr[4] = PACKET2(0);
2653 ib->ptr[5] = PACKET2(0);
2654 ib->ptr[6] = PACKET2(0);
2655 ib->ptr[7] = PACKET2(0);
2656 ib->ptr[8] = PACKET2(0);
2657 ib->ptr[9] = PACKET2(0);
2658 ib->ptr[10] = PACKET2(0);
2659 ib->ptr[11] = PACKET2(0);
2660 ib->ptr[12] = PACKET2(0);
2661 ib->ptr[13] = PACKET2(0);
2662 ib->ptr[14] = PACKET2(0);
2663 ib->ptr[15] = PACKET2(0);
2664 ib->length_dw = 16;
2665 r = radeon_ib_schedule(rdev, ib);
2666 if (r) {
2667 radeon_scratch_free(rdev, scratch);
2668 radeon_ib_free(rdev, &ib);
2669 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2670 return r;
2671 }
2672 r = radeon_fence_wait(ib->fence, false);
2673 if (r) {
2674 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2675 return r;
2676 }
2677 for (i = 0; i < rdev->usec_timeout; i++) {
2678 tmp = RREG32(scratch);
2679 if (tmp == 0xDEADBEEF)
2680 break;
2681 DRM_UDELAY(1);
2682 }
2683 if (i < rdev->usec_timeout) {
2684 DRM_INFO("ib test succeeded in %u usecs\n", i);
2685 } else {
4417d7f6 2686 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2687 scratch, tmp);
2688 r = -EINVAL;
2689 }
2690 radeon_scratch_free(rdev, scratch);
2691 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2692 return r;
2693}
2694
d8f60cfc
AD		 2695/*
2696 * Interrupts
2697 *
2698 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2699 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2700 * writing to the ring and the GPU consuming, the GPU writes to the ring
2701 * and host consumes. As the host irq handler processes interrupts, it
2702 * increments the rptr. When the rptr catches up with the wptr, all the
2703 * current interrupts have been processed.
2704 */
2705
2706void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2707{
2708 u32 rb_bufsz;
2709
2710 /* Align ring size */
2711 rb_bufsz = drm_order(ring_size / 4);
2712 ring_size = (1 << rb_bufsz) * 4;
2713 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2714 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2715 rdev->ih.rptr = 0;
d8f60cfc
AD		 2716}
2717
0c45249f 2718static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2719{
2720 int r;
2721
d8f60cfc
AD		 2722 /* Allocate ring buffer */
2723 if (rdev->ih.ring_obj == NULL) {
4c788679 2724 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
268b2510 2725 PAGE_SIZE, true,
4c788679
JG		 2726 RADEON_GEM_DOMAIN_GTT,
2727 &rdev->ih.ring_obj);
d8f60cfc
AD		 2728 if (r) {
2729 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2730 return r;
2731 }
4c788679
JG		 2732 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2733 if (unlikely(r != 0))
2734 return r;
2735 r = radeon_bo_pin(rdev->ih.ring_obj,
2736 RADEON_GEM_DOMAIN_GTT,
2737 &rdev->ih.gpu_addr);
d8f60cfc 2738 if (r) {
4c788679 2739 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2740 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2741 return r;
2742 }
4c788679
JG		 2743 r = radeon_bo_kmap(rdev->ih.ring_obj,
2744 (void **)&rdev->ih.ring);
2745 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2746 if (r) {
2747 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2748 return r;
2749 }
2750 }
d8f60cfc
AD		 2751 return 0;
2752}
2753
2754static void r600_ih_ring_fini(struct radeon_device *rdev)
2755{
4c788679 2756 int r;
d8f60cfc 2757 if (rdev->ih.ring_obj) {
4c788679
JG		 2758 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2759 if (likely(r == 0)) {
2760 radeon_bo_kunmap(rdev->ih.ring_obj);
2761 radeon_bo_unpin(rdev->ih.ring_obj);
2762 radeon_bo_unreserve(rdev->ih.ring_obj);
2763 }
2764 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2765 rdev->ih.ring = NULL;
2766 rdev->ih.ring_obj = NULL;
2767 }
2768}
2769
45f9a39b 2770void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2771{
2772
45f9a39b
AD		 2773 if ((rdev->family >= CHIP_RV770) &&
2774 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2775 /* r7xx asics need to soft reset RLC before halting */
2776 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2777 RREG32(SRBM_SOFT_RESET);
2778 udelay(15000);
2779 WREG32(SRBM_SOFT_RESET, 0);
2780 RREG32(SRBM_SOFT_RESET);
2781 }
2782
2783 WREG32(RLC_CNTL, 0);
2784}
2785
2786static void r600_rlc_start(struct radeon_device *rdev)
2787{
2788 WREG32(RLC_CNTL, RLC_ENABLE);
2789}
2790
2791static int r600_rlc_init(struct radeon_device *rdev)
2792{
2793 u32 i;
2794 const __be32 *fw_data;
2795
2796 if (!rdev->rlc_fw)
2797 return -EINVAL;
2798
2799 r600_rlc_stop(rdev);
2800
2801 WREG32(RLC_HB_BASE, 0);
2802 WREG32(RLC_HB_CNTL, 0);
2803 WREG32(RLC_HB_RPTR, 0);
2804 WREG32(RLC_HB_WPTR, 0);
2805 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2806 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2807 WREG32(RLC_MC_CNTL, 0);
2808 WREG32(RLC_UCODE_CNTL, 0);
2809
2810 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2811 if (rdev->family >= CHIP_CEDAR) {
2812 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2813 WREG32(RLC_UCODE_ADDR, i);
2814 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2815 }
2816 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2817 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2818 WREG32(RLC_UCODE_ADDR, i);
2819 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2820 }
2821 } else {
2822 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2823 WREG32(RLC_UCODE_ADDR, i);
2824 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2825 }
2826 }
2827 WREG32(RLC_UCODE_ADDR, 0);
2828
2829 r600_rlc_start(rdev);
2830
2831 return 0;
2832}
2833
2834static void r600_enable_interrupts(struct radeon_device *rdev)
2835{
2836 u32 ih_cntl = RREG32(IH_CNTL);
2837 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2838
2839 ih_cntl |= ENABLE_INTR;
2840 ih_rb_cntl |= IH_RB_ENABLE;
2841 WREG32(IH_CNTL, ih_cntl);
2842 WREG32(IH_RB_CNTL, ih_rb_cntl);
2843 rdev->ih.enabled = true;
2844}
2845
45f9a39b 2846void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2847{
2848 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2849 u32 ih_cntl = RREG32(IH_CNTL);
2850
2851 ih_rb_cntl &= ~IH_RB_ENABLE;
2852 ih_cntl &= ~ENABLE_INTR;
2853 WREG32(IH_RB_CNTL, ih_rb_cntl);
2854 WREG32(IH_CNTL, ih_cntl);
2855 /* set rptr, wptr to 0 */
2856 WREG32(IH_RB_RPTR, 0);
2857 WREG32(IH_RB_WPTR, 0);
2858 rdev->ih.enabled = false;
2859 rdev->ih.wptr = 0;
2860 rdev->ih.rptr = 0;
2861}
2862
e0df1ac5
AD		 2863static void r600_disable_interrupt_state(struct radeon_device *rdev)
2864{
2865 u32 tmp;
2866
3555e53b 2867 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
e0df1ac5
AD		 2868 WREG32(GRBM_INT_CNTL, 0);
2869 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 2870 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2871 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 2872 if (ASIC_IS_DCE3(rdev)) {
2873 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2874 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2875 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2876 WREG32(DC_HPD1_INT_CONTROL, tmp);
2877 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2878 WREG32(DC_HPD2_INT_CONTROL, tmp);
2879 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2880 WREG32(DC_HPD3_INT_CONTROL, tmp);
2881 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2882 WREG32(DC_HPD4_INT_CONTROL, tmp);
2883 if (ASIC_IS_DCE32(rdev)) {
2884 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2885 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2886 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2887 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2888 }
2889 } else {
2890 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2891 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2892 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2893 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2894 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2895 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2896 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2897 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2898 }
2899}
2900
d8f60cfc
AD		 2901int r600_irq_init(struct radeon_device *rdev)
2902{
2903 int ret = 0;
2904 int rb_bufsz;
2905 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2906
2907 /* allocate ring */
0c45249f 2908 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2909 if (ret)
2910 return ret;
2911
2912 /* disable irqs */
2913 r600_disable_interrupts(rdev);
2914
2915 /* init rlc */
2916 ret = r600_rlc_init(rdev);
2917 if (ret) {
2918 r600_ih_ring_fini(rdev);
2919 return ret;
2920 }
2921
2922 /* setup interrupt control */
2923 /* set dummy read address to ring address */
2924 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2925 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2926 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2927 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2928 */
2929 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2930 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2931 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2932 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2933
2934 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2935 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2936
2937 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2938 IH_WPTR_OVERFLOW_CLEAR |
2939 (rb_bufsz << 1));
724c80e1
AD		 2940
2941 if (rdev->wb.enabled)
2942 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2943
2944 /* set the writeback address whether it's enabled or not */
2945 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2946 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 2947
2948 WREG32(IH_RB_CNTL, ih_rb_cntl);
2949
2950 /* set rptr, wptr to 0 */
2951 WREG32(IH_RB_RPTR, 0);
2952 WREG32(IH_RB_WPTR, 0);
2953
2954 /* Default settings for IH_CNTL (disabled at first) */
2955 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2956 /* RPTR_REARM only works if msi's are enabled */
2957 if (rdev->msi_enabled)
2958 ih_cntl |= RPTR_REARM;
2959
2960#ifdef __BIG_ENDIAN
2961 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2962#endif
2963 WREG32(IH_CNTL, ih_cntl);
2964
2965 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2966 if (rdev->family >= CHIP_CEDAR)
2967 evergreen_disable_interrupt_state(rdev);
2968 else
2969 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2970
2971 /* enable irqs */
2972 r600_enable_interrupts(rdev);
2973
2974 return ret;
2975}
2976
0c45249f 2977void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2978{
45f9a39b 2979 r600_irq_disable(rdev);
d8f60cfc 2980 r600_rlc_stop(rdev);
0c45249f
JG		 2981}
2982
2983void r600_irq_fini(struct radeon_device *rdev)
2984{
2985 r600_irq_suspend(rdev);
d8f60cfc
AD		 2986 r600_ih_ring_fini(rdev);
2987}
2988
2989int r600_irq_set(struct radeon_device *rdev)
2990{
e0df1ac5
AD		 2991 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2992 u32 mode_int = 0;
2993 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 2994 u32 grbm_int_cntl = 0;
f2594933 2995 u32 hdmi1, hdmi2;
6f34be50 2996 u32 d1grph = 0, d2grph = 0;
d8f60cfc 2997
003e69f9 2998 if (!rdev->irq.installed) {
fce7d61b 2999 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3000 return -EINVAL;
3001 }
d8f60cfc 3002 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3003 if (!rdev->ih.enabled) {
3004 r600_disable_interrupts(rdev);
3005 /* force the active interrupt state to all disabled */
3006 r600_disable_interrupt_state(rdev);
d8f60cfc 3007 return 0;
79c2bbc5 3008 }
d8f60cfc 3009
f2594933 3010 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3011 if (ASIC_IS_DCE3(rdev)) {
f2594933 3012 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3013 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3014 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3015 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3016 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3017 if (ASIC_IS_DCE32(rdev)) {
3018 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3019 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3020 }
3021 } else {
f2594933 3022 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3023 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3024 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3025 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3026 }
3027
d8f60cfc
AD		 3028 if (rdev->irq.sw_int) {
3029 DRM_DEBUG("r600_irq_set: sw int\n");
3030 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3031 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3032 }
6f34be50
AD		 3033 if (rdev->irq.crtc_vblank_int[0] ||
3034 rdev->irq.pflip[0]) {
d8f60cfc
AD		 3035 DRM_DEBUG("r600_irq_set: vblank 0\n");
3036 mode_int |= D1MODE_VBLANK_INT_MASK;
3037 }
6f34be50
AD		 3038 if (rdev->irq.crtc_vblank_int[1] ||
3039 rdev->irq.pflip[1]) {
d8f60cfc
AD		 3040 DRM_DEBUG("r600_irq_set: vblank 1\n");
3041 mode_int |= D2MODE_VBLANK_INT_MASK;
3042 }
e0df1ac5
AD		 3043 if (rdev->irq.hpd[0]) {
3044 DRM_DEBUG("r600_irq_set: hpd 1\n");
3045 hpd1 |= DC_HPDx_INT_EN;
3046 }
3047 if (rdev->irq.hpd[1]) {
3048 DRM_DEBUG("r600_irq_set: hpd 2\n");
3049 hpd2 |= DC_HPDx_INT_EN;
3050 }
3051 if (rdev->irq.hpd[2]) {
3052 DRM_DEBUG("r600_irq_set: hpd 3\n");
3053 hpd3 |= DC_HPDx_INT_EN;
3054 }
3055 if (rdev->irq.hpd[3]) {
3056 DRM_DEBUG("r600_irq_set: hpd 4\n");
3057 hpd4 |= DC_HPDx_INT_EN;
3058 }
3059 if (rdev->irq.hpd[4]) {
3060 DRM_DEBUG("r600_irq_set: hpd 5\n");
3061 hpd5 |= DC_HPDx_INT_EN;
3062 }
3063 if (rdev->irq.hpd[5]) {
3064 DRM_DEBUG("r600_irq_set: hpd 6\n");
3065 hpd6 |= DC_HPDx_INT_EN;
3066 }
f2594933
CK		 3067 if (rdev->irq.hdmi[0]) {
3068 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3069 hdmi1 |= R600_HDMI_INT_EN;
3070 }
3071 if (rdev->irq.hdmi[1]) {
3072 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3073 hdmi2 |= R600_HDMI_INT_EN;
3074 }
2031f77c
AD		 3075 if (rdev->irq.gui_idle) {
3076 DRM_DEBUG("gui idle\n");
3077 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3078 }
d8f60cfc
AD		 3079
3080 WREG32(CP_INT_CNTL, cp_int_cntl);
3081 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3082 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3083 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3084 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3085 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3086 if (ASIC_IS_DCE3(rdev)) {
f2594933 3087 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3088 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3089 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3090 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3091 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3092 if (ASIC_IS_DCE32(rdev)) {
3093 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3094 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3095 }
3096 } else {
f2594933 3097 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3098 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3099 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3100 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3101 }
d8f60cfc
AD		 3102
3103 return 0;
3104}
3105
6f34be50 3106static inline void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3107{
e0df1ac5
AD		 3108 u32 tmp;
3109
3110 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3111 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3112 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3113 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
e0df1ac5 3114 } else {
6f34be50
AD		 3115 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3116 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3117 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3118 }
3119 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3120 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3121
3122 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3123 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3124 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3125 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3126 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3127 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3128 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3129 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3130 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3131 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3132 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3133 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3134 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3135 if (ASIC_IS_DCE3(rdev)) {
3136 tmp = RREG32(DC_HPD1_INT_CONTROL);
3137 tmp |= DC_HPDx_INT_ACK;
3138 WREG32(DC_HPD1_INT_CONTROL, tmp);
3139 } else {
3140 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3141 tmp |= DC_HPDx_INT_ACK;
3142 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3143 }
3144 }
6f34be50 3145 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3146 if (ASIC_IS_DCE3(rdev)) {
3147 tmp = RREG32(DC_HPD2_INT_CONTROL);
3148 tmp |= DC_HPDx_INT_ACK;
3149 WREG32(DC_HPD2_INT_CONTROL, tmp);
3150 } else {
3151 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3152 tmp |= DC_HPDx_INT_ACK;
3153 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3154 }
3155 }
6f34be50 3156 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3157 if (ASIC_IS_DCE3(rdev)) {
3158 tmp = RREG32(DC_HPD3_INT_CONTROL);
3159 tmp |= DC_HPDx_INT_ACK;
3160 WREG32(DC_HPD3_INT_CONTROL, tmp);
3161 } else {
3162 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3163 tmp |= DC_HPDx_INT_ACK;
3164 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3165 }
3166 }
6f34be50 3167 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3168 tmp = RREG32(DC_HPD4_INT_CONTROL);
3169 tmp |= DC_HPDx_INT_ACK;
3170 WREG32(DC_HPD4_INT_CONTROL, tmp);
3171 }
3172 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3173 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3174 tmp = RREG32(DC_HPD5_INT_CONTROL);
3175 tmp |= DC_HPDx_INT_ACK;
3176 WREG32(DC_HPD5_INT_CONTROL, tmp);
3177 }
6f34be50 3178 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3179 tmp = RREG32(DC_HPD5_INT_CONTROL);
3180 tmp |= DC_HPDx_INT_ACK;
3181 WREG32(DC_HPD6_INT_CONTROL, tmp);
3182 }
3183 }
f2594933
CK		 3184 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3185 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3186 }
3187 if (ASIC_IS_DCE3(rdev)) {
3188 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3189 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3190 }
3191 } else {
3192 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3193 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3194 }
3195 }
d8f60cfc
AD		 3196}
3197
3198void r600_irq_disable(struct radeon_device *rdev)
3199{
d8f60cfc
AD		 3200 r600_disable_interrupts(rdev);
3201 /* Wait and acknowledge irq */
3202 mdelay(1);
6f34be50 3203 r600_irq_ack(rdev);
e0df1ac5 3204 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3205}
3206
3207static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3208{
3209 u32 wptr, tmp;
3ce0a23d 3210
724c80e1
AD		 3211 if (rdev->wb.enabled)
3212 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3213 else
3214 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3215
d8f60cfc 3216 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3217 /* When a ring buffer overflow happen start parsing interrupt
3218 * from the last not overwritten vector (wptr + 16). Hopefully
3219 * this should allow us to catchup.
3220 */
3221 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3222 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3223 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3224 tmp = RREG32(IH_RB_CNTL);
3225 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3226 WREG32(IH_RB_CNTL, tmp);
3227 }
0c45249f 3228 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3229}
3ce0a23d 3230
d8f60cfc
AD		 3231/* r600 IV Ring
3232 * Each IV ring entry is 128 bits:
3233 * [7:0] - interrupt source id
3234 * [31:8] - reserved
3235 * [59:32] - interrupt source data
3236 * [127:60] - reserved
3237 *
3238 * The basic interrupt vector entries
3239 * are decoded as follows:
3240 * src_id src_data description
3241 * 1 0 D1 Vblank
3242 * 1 1 D1 Vline
3243 * 5 0 D2 Vblank
3244 * 5 1 D2 Vline
3245 * 19 0 FP Hot plug detection A
3246 * 19 1 FP Hot plug detection B
3247 * 19 2 DAC A auto-detection
3248 * 19 3 DAC B auto-detection
f2594933
CK		 3249 * 21 4 HDMI block A
3250 * 21 5 HDMI block B
d8f60cfc
AD		 3251 * 176 - CP_INT RB
3252 * 177 - CP_INT IB1
3253 * 178 - CP_INT IB2
3254 * 181 - EOP Interrupt
3255 * 233 - GUI Idle
3256 *
3257 * Note, these are based on r600 and may need to be
3258 * adjusted or added to on newer asics
3259 */
3260
3261int r600_irq_process(struct radeon_device *rdev)
3262{
3263 u32 wptr = r600_get_ih_wptr(rdev);
3264 u32 rptr = rdev->ih.rptr;
3265 u32 src_id, src_data;
6f34be50 3266 u32 ring_index;
d8f60cfc 3267 unsigned long flags;
d4877cf2 3268 bool queue_hotplug = false;
d8f60cfc
AD		 3269
3270 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3271 if (!rdev->ih.enabled)
3272 return IRQ_NONE;
d8f60cfc
AD		 3273
3274 spin_lock_irqsave(&rdev->ih.lock, flags);
3275
3276 if (rptr == wptr) {
3277 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3278 return IRQ_NONE;
3279 }
3280 if (rdev->shutdown) {
3281 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3282 return IRQ_NONE;
3283 }
3284
3285restart_ih:
3286 /* display interrupts */
6f34be50 3287 r600_irq_ack(rdev);
d8f60cfc
AD		 3288
3289 rdev->ih.wptr = wptr;
3290 while (rptr != wptr) {
3291 /* wptr/rptr are in bytes! */
3292 ring_index = rptr / 4;
3293 src_id = rdev->ih.ring[ring_index] & 0xff;
3294 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3295
3296 switch (src_id) {
3297 case 1: /* D1 vblank/vline */
3298 switch (src_data) {
3299 case 0: /* D1 vblank */
6f34be50 3300 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3301 if (rdev->irq.crtc_vblank_int[0]) {
3302 drm_handle_vblank(rdev->ddev, 0);
3303 rdev->pm.vblank_sync = true;
3304 wake_up(&rdev->irq.vblank_queue);
3305 }
3e4ea742
MK		 3306 if (rdev->irq.pflip[0])
3307 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3308 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3309 DRM_DEBUG("IH: D1 vblank\n");
3310 }
3311 break;
3312 case 1: /* D1 vline */
6f34be50
AD		 3313 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3314 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3315 DRM_DEBUG("IH: D1 vline\n");
3316 }
3317 break;
3318 default:
b042589c 3319 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3320 break;
3321 }
3322 break;
3323 case 5: /* D2 vblank/vline */
3324 switch (src_data) {
3325 case 0: /* D2 vblank */
6f34be50 3326 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3327 if (rdev->irq.crtc_vblank_int[1]) {
3328 drm_handle_vblank(rdev->ddev, 1);
3329 rdev->pm.vblank_sync = true;
3330 wake_up(&rdev->irq.vblank_queue);
3331 }
3e4ea742
MK		 3332 if (rdev->irq.pflip[1])
3333 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3334 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3335 DRM_DEBUG("IH: D2 vblank\n");
3336 }
3337 break;
3338 case 1: /* D1 vline */
6f34be50
AD		 3339 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3340 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3341 DRM_DEBUG("IH: D2 vline\n");
3342 }
3343 break;
3344 default:
b042589c 3345 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3346 break;
3347 }
3348 break;
e0df1ac5
AD		 3349 case 19: /* HPD/DAC hotplug */
3350 switch (src_data) {
3351 case 0:
6f34be50
AD		 3352 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3353 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3354 queue_hotplug = true;
3355 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3356 }
3357 break;
3358 case 1:
6f34be50
AD		 3359 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3360 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3361 queue_hotplug = true;
3362 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3363 }
3364 break;
3365 case 4:
6f34be50
AD		 3366 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3367 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3368 queue_hotplug = true;
3369 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3370 }
3371 break;
3372 case 5:
6f34be50
AD		 3373 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3374 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3375 queue_hotplug = true;
3376 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3377 }
3378 break;
3379 case 10:
6f34be50
AD		 3380 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3381 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3382 queue_hotplug = true;
3383 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3384 }
3385 break;
3386 case 12:
6f34be50
AD		 3387 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3388 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3389 queue_hotplug = true;
3390 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3391 }
3392 break;
3393 default:
b042589c 3394 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3395 break;
3396 }
3397 break;
f2594933
CK		 3398 case 21: /* HDMI */
3399 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3400 r600_audio_schedule_polling(rdev);
3401 break;
d8f60cfc
AD		 3402 case 176: /* CP_INT in ring buffer */
3403 case 177: /* CP_INT in IB1 */
3404 case 178: /* CP_INT in IB2 */
3405 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3406 radeon_fence_process(rdev);
3407 break;
3408 case 181: /* CP EOP event */
3409 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 3410 radeon_fence_process(rdev);
d8f60cfc 3411 break;
2031f77c
AD		 3412 case 233: /* GUI IDLE */
3413 DRM_DEBUG("IH: CP EOP\n");
3414 rdev->pm.gui_idle = true;
3415 wake_up(&rdev->irq.idle_queue);
3416 break;
d8f60cfc 3417 default:
b042589c 3418 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3419 break;
3420 }
3421
3422 /* wptr/rptr are in bytes! */
0c45249f
JG		 3423 rptr += 16;
3424 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3425 }
3426 /* make sure wptr hasn't changed while processing */
3427 wptr = r600_get_ih_wptr(rdev);
3428 if (wptr != rdev->ih.wptr)
3429 goto restart_ih;
d4877cf2 3430 if (queue_hotplug)
32c87fca 3431 schedule_work(&rdev->hotplug_work);
d8f60cfc
AD		 3432 rdev->ih.rptr = rptr;
3433 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3434 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3435 return IRQ_HANDLED;
3436}
3ce0a23d
JG		 3437
3438/*
3439 * Debugfs info
3440 */
3441#if defined(CONFIG_DEBUG_FS)
3442
3443static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3444{
3ce0a23d
JG		 3445 struct drm_info_node *node = (struct drm_info_node *) m->private;
3446 struct drm_device *dev = node->minor->dev;
3447 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3448 unsigned count, i, j;
3449
3450 radeon_ring_free_size(rdev);
d6840766 3451 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3452 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3453 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3454 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3455 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3456 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3457 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3458 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3459 i = rdev->cp.rptr;
3ce0a23d 3460 for (j = 0; j <= count; j++) {
3ce0a23d 3461 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3462 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3463 }
3464 return 0;
3465}
3466
3467static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3468{
3469 struct drm_info_node *node = (struct drm_info_node *) m->private;
3470 struct drm_device *dev = node->minor->dev;
3471 struct radeon_device *rdev = dev->dev_private;
3472
3473 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3474 DREG32_SYS(m, rdev, VM_L2_STATUS);
3475 return 0;
3476}
3477
3478static struct drm_info_list r600_mc_info_list[] = {
3479 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3480 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3481};
3482#endif
3483
3484int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3485{
3486#if defined(CONFIG_DEBUG_FS)
3487 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3488#else
3489 return 0;
3490#endif
771fe6b9 3491}
062b389c
JG		 3492
3493/**
3494 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3495 * rdev: radeon device structure
3496 * bo: buffer object struct which userspace is waiting for idle
3497 *
3498 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3499 * through ring buffer, this leads to corruption in rendering, see
3500 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3501 * directly perform HDP flush by writing register through MMIO.
3502 */
3503void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3504{
812d0469 3505 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3506 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3507 * This seems to cause problems on some AGP cards. Just use the old
3508 * method for them.
812d0469 3509 */
e488459a 3510 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3511 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3512 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3513 u32 tmp;
3514
3515 WREG32(HDP_DEBUG1, 0);
3516 tmp = readl((void __iomem *)ptr);
3517 } else
3518 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3519}
3313e3d4
AD		 3520
3521void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3522{
3523 u32 link_width_cntl, mask, target_reg;
3524
3525 if (rdev->flags & RADEON_IS_IGP)
3526 return;
3527
3528 if (!(rdev->flags & RADEON_IS_PCIE))
3529 return;
3530
3531 /* x2 cards have a special sequence */
3532 if (ASIC_IS_X2(rdev))
3533 return;
3534
3535 /* FIXME wait for idle */
3536
3537 switch (lanes) {
3538 case 0:
3539 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3540 break;
3541 case 1:
3542 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3543 break;
3544 case 2:
3545 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3546 break;
3547 case 4:
3548 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3549 break;
3550 case 8:
3551 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3552 break;
3553 case 12:
3554 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3555 break;
3556 case 16:
3557 default:
3558 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3559 break;
3560 }
3561
3562 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3563
3564 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3565 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3566 return;
3567
3568 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3569 return;
3570
3571 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3572 RADEON_PCIE_LC_RECONFIG_NOW |
3573 R600_PCIE_LC_RENEGOTIATE_EN |
3574 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3575 link_width_cntl |= mask;
3576
3577 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3578
3579 /* some northbridges can renegotiate the link rather than requiring
3580 * a complete re-config.
3581 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3582 */
3583 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3584 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3585 else
3586 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3587
3588 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3589 RADEON_PCIE_LC_RECONFIG_NOW));
3590
3591 if (rdev->family >= CHIP_RV770)
3592 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3593 else
3594 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3595
3596 /* wait for lane set to complete */
3597 link_width_cntl = RREG32(target_reg);
3598 while (link_width_cntl == 0xffffffff)
3599 link_width_cntl = RREG32(target_reg);
3600
3601}
3602
3603int r600_get_pcie_lanes(struct radeon_device *rdev)
3604{
3605 u32 link_width_cntl;
3606
3607 if (rdev->flags & RADEON_IS_IGP)
3608 return 0;
3609
3610 if (!(rdev->flags & RADEON_IS_PCIE))
3611 return 0;
3612
3613 /* x2 cards have a special sequence */
3614 if (ASIC_IS_X2(rdev))
3615 return 0;
3616
3617 /* FIXME wait for idle */
3618
3619 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3620
3621 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3622 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3623 return 0;
3624 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3625 return 1;
3626 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3627 return 2;
3628 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3629 return 4;
3630 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3631 return 8;
3632 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3633 default:
3634 return 16;
3635 }
3636}
3637
9e46a48d
AD		 3638static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3639{
3640 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3641 u16 link_cntl2;
3642
d42dd579
AD		 3643 if (radeon_pcie_gen2 == 0)
3644 return;
3645
9e46a48d
AD		 3646 if (rdev->flags & RADEON_IS_IGP)
3647 return;
3648
3649 if (!(rdev->flags & RADEON_IS_PCIE))
3650 return;
3651
3652 /* x2 cards have a special sequence */
3653 if (ASIC_IS_X2(rdev))
3654 return;
3655
3656 /* only RV6xx+ chips are supported */
3657 if (rdev->family <= CHIP_R600)
3658 return;
3659
3660 /* 55 nm r6xx asics */
3661 if ((rdev->family == CHIP_RV670) ||
3662 (rdev->family == CHIP_RV620) ||
3663 (rdev->family == CHIP_RV635)) {
3664 /* advertise upconfig capability */
3665 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3666 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3667 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3668 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3669 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3670 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3671 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3672 LC_RECONFIG_ARC_MISSING_ESCAPE);
3673 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3674 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3675 } else {
3676 link_width_cntl |= LC_UPCONFIGURE_DIS;
3677 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3678 }
3679 }
3680
3681 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3682 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3683 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3684
3685 /* 55 nm r6xx asics */
3686 if ((rdev->family == CHIP_RV670) ||
3687 (rdev->family == CHIP_RV620) ||
3688 (rdev->family == CHIP_RV635)) {
3689 WREG32(MM_CFGREGS_CNTL, 0x8);
3690 link_cntl2 = RREG32(0x4088);
3691 WREG32(MM_CFGREGS_CNTL, 0);
3692 /* not supported yet */
3693 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3694 return;
3695 }
3696
3697 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3698 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3699 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3700 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3701 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3702 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3703
3704 tmp = RREG32(0x541c);
3705 WREG32(0x541c, tmp | 0x8);
3706 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3707 link_cntl2 = RREG16(0x4088);
3708 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3709 link_cntl2 |= 0x2;
3710 WREG16(0x4088, link_cntl2);
3711 WREG32(MM_CFGREGS_CNTL, 0);
3712
3713 if ((rdev->family == CHIP_RV670) ||
3714 (rdev->family == CHIP_RV620) ||
3715 (rdev->family == CHIP_RV635)) {
3716 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3717 training_cntl &= ~LC_POINT_7_PLUS_EN;
3718 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3719 } else {
3720 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3721 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3722 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3723 }
3724
3725 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3726 speed_cntl |= LC_GEN2_EN_STRAP;
3727 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3728
3729 } else {
3730 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3731 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3732 if (1)
3733 link_width_cntl |= LC_UPCONFIGURE_DIS;
3734 else
3735 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3736 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3737 }
3738}
Linux kernel - Deliverables
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