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drm/radeon/kms: add initial radeon tv-out support.
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_cp.c
CommitLineData
c05ce083
AD		 1/*
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
32#include "radeon_drv.h"
33
70967ab9
BH		 34#define PFP_UCODE_SIZE 576
35#define PM4_UCODE_SIZE 1792
36#define R700_PFP_UCODE_SIZE 848
37#define R700_PM4_UCODE_SIZE 1360
38
39/* Firmware Names */
40MODULE_FIRMWARE("radeon/R600_pfp.bin");
41MODULE_FIRMWARE("radeon/R600_me.bin");
42MODULE_FIRMWARE("radeon/RV610_pfp.bin");
43MODULE_FIRMWARE("radeon/RV610_me.bin");
44MODULE_FIRMWARE("radeon/RV630_pfp.bin");
45MODULE_FIRMWARE("radeon/RV630_me.bin");
46MODULE_FIRMWARE("radeon/RV620_pfp.bin");
47MODULE_FIRMWARE("radeon/RV620_me.bin");
48MODULE_FIRMWARE("radeon/RV635_pfp.bin");
49MODULE_FIRMWARE("radeon/RV635_me.bin");
50MODULE_FIRMWARE("radeon/RV670_pfp.bin");
51MODULE_FIRMWARE("radeon/RV670_me.bin");
52MODULE_FIRMWARE("radeon/RS780_pfp.bin");
53MODULE_FIRMWARE("radeon/RS780_me.bin");
54MODULE_FIRMWARE("radeon/RV770_pfp.bin");
55MODULE_FIRMWARE("radeon/RV770_me.bin");
56MODULE_FIRMWARE("radeon/RV730_pfp.bin");
57MODULE_FIRMWARE("radeon/RV730_me.bin");
58MODULE_FIRMWARE("radeon/RV710_pfp.bin");
59MODULE_FIRMWARE("radeon/RV710_me.bin");
c05ce083
AD		 60
61# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
62# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
63
64#define R600_PTE_VALID (1 << 0)
65#define R600_PTE_SYSTEM (1 << 1)
66#define R600_PTE_SNOOPED (1 << 2)
67#define R600_PTE_READABLE (1 << 5)
68#define R600_PTE_WRITEABLE (1 << 6)
69
70/* MAX values used for gfx init */
71#define R6XX_MAX_SH_GPRS 256
72#define R6XX_MAX_TEMP_GPRS 16
73#define R6XX_MAX_SH_THREADS 256
74#define R6XX_MAX_SH_STACK_ENTRIES 4096
75#define R6XX_MAX_BACKENDS 8
76#define R6XX_MAX_BACKENDS_MASK 0xff
77#define R6XX_MAX_SIMDS 8
78#define R6XX_MAX_SIMDS_MASK 0xff
79#define R6XX_MAX_PIPES 8
80#define R6XX_MAX_PIPES_MASK 0xff
81
82#define R7XX_MAX_SH_GPRS 256
83#define R7XX_MAX_TEMP_GPRS 16
84#define R7XX_MAX_SH_THREADS 256
85#define R7XX_MAX_SH_STACK_ENTRIES 4096
86#define R7XX_MAX_BACKENDS 8
87#define R7XX_MAX_BACKENDS_MASK 0xff
88#define R7XX_MAX_SIMDS 16
89#define R7XX_MAX_SIMDS_MASK 0xffff
90#define R7XX_MAX_PIPES 8
91#define R7XX_MAX_PIPES_MASK 0xff
92
93static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
94{
95 int i;
96
97 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
98
99 for (i = 0; i < dev_priv->usec_timeout; i++) {
100 int slots;
101 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
102 slots = (RADEON_READ(R600_GRBM_STATUS)
103 & R700_CMDFIFO_AVAIL_MASK);
104 else
105 slots = (RADEON_READ(R600_GRBM_STATUS)
106 & R600_CMDFIFO_AVAIL_MASK);
107 if (slots >= entries)
108 return 0;
109 DRM_UDELAY(1);
110 }
111 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
112 RADEON_READ(R600_GRBM_STATUS),
113 RADEON_READ(R600_GRBM_STATUS2));
114
115 return -EBUSY;
116}
117
118static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
119{
120 int i, ret;
121
122 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
123
124 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
125 ret = r600_do_wait_for_fifo(dev_priv, 8);
126 else
127 ret = r600_do_wait_for_fifo(dev_priv, 16);
128 if (ret)
129 return ret;
130 for (i = 0; i < dev_priv->usec_timeout; i++) {
131 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
132 return 0;
133 DRM_UDELAY(1);
134 }
135 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
136 RADEON_READ(R600_GRBM_STATUS),
137 RADEON_READ(R600_GRBM_STATUS2));
138
139 return -EBUSY;
140}
141
c1556f71 142void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
c05ce083
AD		 143{
144 struct drm_sg_mem *entry = dev->sg;
145 int max_pages;
146 int pages;
147 int i;
148
08932156
AD		 149 if (!entry)
150 return;
151
c05ce083 152 if (gart_info->bus_addr) {
06f0a488 153 max_pages = (gart_info->table_size / sizeof(u64));
c05ce083
AD		 154 pages = (entry->pages <= max_pages)
155 ? entry->pages : max_pages;
156
157 for (i = 0; i < pages; i++) {
158 if (!entry->busaddr[i])
159 break;
a763d7dc
DA		 160 pci_unmap_page(dev->pdev, entry->busaddr[i],
161 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
c05ce083
AD		 162 }
163 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
164 gart_info->bus_addr = 0;
165 }
166}
167
168/* R600 has page table setup */
169int r600_page_table_init(struct drm_device *dev)
170{
171 drm_radeon_private_t *dev_priv = dev->dev_private;
172 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
eb1d9195 173 struct drm_local_map *map = &gart_info->mapping;
c05ce083
AD		 174 struct drm_sg_mem *entry = dev->sg;
175 int ret = 0;
176 int i, j;
eb1d9195
DA		 177 int pages;
178 u64 page_base;
c05ce083 179 dma_addr_t entry_addr;
eb1d9195 180 int max_ati_pages, max_real_pages, gart_idx;
c05ce083
AD		 181
182 /* okay page table is available - lets rock */
eb1d9195
DA		 183 max_ati_pages = (gart_info->table_size / sizeof(u64));
184 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
c05ce083 185
eb1d9195
DA		 186 pages = (entry->pages <= max_real_pages) ?
187 entry->pages : max_real_pages;
c05ce083 188
eb1d9195 189 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
c05ce083 190
eb1d9195 191 gart_idx = 0;
c05ce083 192 for (i = 0; i < pages; i++) {
a763d7dc
DA		 193 entry->busaddr[i] = pci_map_page(dev->pdev,
194 entry->pagelist[i], 0,
195 PAGE_SIZE,
196 PCI_DMA_BIDIRECTIONAL);
c05ce083
AD		 197 if (entry->busaddr[i] == 0) {
198 DRM_ERROR("unable to map PCIGART pages!\n");
199 r600_page_table_cleanup(dev, gart_info);
c05ce083
AD		 200 goto done;
201 }
202 entry_addr = entry->busaddr[i];
203 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
204 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
205 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
206 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
207
eb1d9195
DA		 208 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
209
210 gart_idx++;
c05ce083
AD		 211
212 if ((i % 128) == 0)
213 DRM_DEBUG("page entry %d: 0x%016llx\n",
214 i, (unsigned long long)page_base);
c05ce083
AD		 215 entry_addr += ATI_PCIGART_PAGE_SIZE;
216 }
217 }
41f13fe8 218 ret = 1;
c05ce083
AD		 219done:
220 return ret;
221}
222
223static void r600_vm_flush_gart_range(struct drm_device *dev)
224{
225 drm_radeon_private_t *dev_priv = dev->dev_private;
226 u32 resp, countdown = 1000;
227 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
228 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
229 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
230
231 do {
232 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
233 countdown--;
234 DRM_UDELAY(1);
235 } while (((resp & 0xf0) == 0) && countdown);
236}
237
238static void r600_vm_init(struct drm_device *dev)
239{
240 drm_radeon_private_t *dev_priv = dev->dev_private;
241 /* initialise the VM to use the page table we constructed up there */
242 u32 vm_c0, i;
243 u32 mc_rd_a;
244 u32 vm_l2_cntl, vm_l2_cntl3;
245 /* okay set up the PCIE aperture type thingo */
246 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
247 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
248 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
249
250 /* setup MC RD a */
251 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
252 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
253 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
254
255 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
256 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
257
258 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
259 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
260
261 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
262 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
263
264 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
265 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
266
267 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
268 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
269
270 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
271 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
272
273 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
274 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
275
276 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
277 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
278 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
279
280 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
281 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
282 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
283 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
284 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
285
286 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
287
288 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
289
290 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
291
292 /* disable all other contexts */
293 for (i = 1; i < 8; i++)
294 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
295
296 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
297 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
298 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
299
300 r600_vm_flush_gart_range(dev);
301}
302
70967ab9
BH		 303static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
304{
305 struct platform_device *pdev;
306 const char *chip_name;
307 size_t pfp_req_size, me_req_size;
308 char fw_name[30];
309 int err;
310
311 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
312 err = IS_ERR(pdev);
313 if (err) {
314 printk(KERN_ERR "r600_cp: Failed to register firmware\n");
315 return -EINVAL;
316 }
317
318 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
319 case CHIP_R600: chip_name = "R600"; break;
320 case CHIP_RV610: chip_name = "RV610"; break;
321 case CHIP_RV630: chip_name = "RV630"; break;
322 case CHIP_RV620: chip_name = "RV620"; break;
323 case CHIP_RV635: chip_name = "RV635"; break;
324 case CHIP_RV670: chip_name = "RV670"; break;
325 case CHIP_RS780:
326 case CHIP_RS880: chip_name = "RS780"; break;
327 case CHIP_RV770: chip_name = "RV770"; break;
328 case CHIP_RV730:
329 case CHIP_RV740: chip_name = "RV730"; break;
330 case CHIP_RV710: chip_name = "RV710"; break;
331 default: BUG();
332 }
333
334 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
335 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
336 me_req_size = R700_PM4_UCODE_SIZE * 4;
337 } else {
338 pfp_req_size = PFP_UCODE_SIZE * 4;
339 me_req_size = PM4_UCODE_SIZE * 12;
340 }
341
342 DRM_INFO("Loading %s CP Microcode\n", chip_name);
343
344 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
345 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
346 if (err)
347 goto out;
348 if (dev_priv->pfp_fw->size != pfp_req_size) {
349 printk(KERN_ERR
350 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
351 dev_priv->pfp_fw->size, fw_name);
352 err = -EINVAL;
353 goto out;
354 }
355
356 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
357 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
358 if (err)
359 goto out;
360 if (dev_priv->me_fw->size != me_req_size) {
361 printk(KERN_ERR
362 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
363 dev_priv->me_fw->size, fw_name);
364 err = -EINVAL;
365 }
366out:
367 platform_device_unregister(pdev);
368
369 if (err) {
370 if (err != -EINVAL)
371 printk(KERN_ERR
372 "r600_cp: Failed to load firmware \"%s\"\n",
373 fw_name);
374 release_firmware(dev_priv->pfp_fw);
375 dev_priv->pfp_fw = NULL;
376 release_firmware(dev_priv->me_fw);
377 dev_priv->me_fw = NULL;
378 }
379 return err;
380}
381
c05ce083
AD		 382static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
383{
70967ab9 384 const __be32 *fw_data;
c05ce083
AD		 385 int i;
386
70967ab9
BH		 387 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
388 return;
389
c05ce083
AD		 390 r600_do_cp_stop(dev_priv);
391
392 RADEON_WRITE(R600_CP_RB_CNTL,
393 R600_RB_NO_UPDATE |
394 R600_RB_BLKSZ(15) |
395 R600_RB_BUFSZ(3));
396
397 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
398 RADEON_READ(R600_GRBM_SOFT_RESET);
399 DRM_UDELAY(15000);
400 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
401
70967ab9 402 fw_data = (const __be32 *)dev_priv->me_fw->data;
c05ce083 403 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
70967ab9
BH		 404 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
405 RADEON_WRITE(R600_CP_ME_RAM_DATA,
406 be32_to_cpup(fw_data++));
c05ce083 407
70967ab9
BH		 408 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
409 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
410 for (i = 0; i < PFP_UCODE_SIZE; i++)
411 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
412 be32_to_cpup(fw_data++));
c05ce083 413
c05ce083
AD		 414 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
415 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
416 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
417
418}
419
420static void r700_vm_init(struct drm_device *dev)
421{
422 drm_radeon_private_t *dev_priv = dev->dev_private;
423 /* initialise the VM to use the page table we constructed up there */
424 u32 vm_c0, i;
425 u32 mc_vm_md_l1;
426 u32 vm_l2_cntl, vm_l2_cntl3;
427 /* okay set up the PCIE aperture type thingo */
428 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
429 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
430 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
431
432 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
433 R700_ENABLE_L1_FRAGMENT_PROCESSING |
434 R700_SYSTEM_ACCESS_MODE_IN_SYS |
435 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
436 R700_EFFECTIVE_L1_TLB_SIZE(5) |
437 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
438
439 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
440 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
441 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
442 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
443 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
444 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
445 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
446
447 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
448 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
449 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
450
451 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
452 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
453 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
454
455 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
456
457 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
458
459 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
460
461 /* disable all other contexts */
462 for (i = 1; i < 8; i++)
463 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
464
465 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
466 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
467 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
468
469 r600_vm_flush_gart_range(dev);
470}
471
c05ce083
AD		 472static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
473{
70967ab9 474 const __be32 *fw_data;
c05ce083
AD		 475 int i;
476
70967ab9
BH		 477 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
478 return;
479
c05ce083
AD		 480 r600_do_cp_stop(dev_priv);
481
482 RADEON_WRITE(R600_CP_RB_CNTL,
483 R600_RB_NO_UPDATE |
484 (15 << 8) |
485 (3 << 0));
486
487 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
488 RADEON_READ(R600_GRBM_SOFT_RESET);
489 DRM_UDELAY(15000);
490 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
491
70967ab9
BH		 492 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
493 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
494 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
495 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
496 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
c05ce083 497
70967ab9
BH		 498 fw_data = (const __be32 *)dev_priv->me_fw->data;
499 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
500 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
501 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
502 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
c05ce083 503
c05ce083
AD		 504 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
506 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
507
508}
509
510static void r600_test_writeback(drm_radeon_private_t *dev_priv)
511{
512 u32 tmp;
513
514 /* Start with assuming that writeback doesn't work */
515 dev_priv->writeback_works = 0;
516
517 /* Writeback doesn't seem to work everywhere, test it here and possibly
518 * enable it if it appears to work
519 */
520 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
521
522 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
523
524 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
525 u32 val;
526
527 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
528 if (val == 0xdeadbeef)
529 break;
530 DRM_UDELAY(1);
531 }
532
533 if (tmp < dev_priv->usec_timeout) {
534 dev_priv->writeback_works = 1;
535 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
536 } else {
537 dev_priv->writeback_works = 0;
538 DRM_INFO("writeback test failed\n");
539 }
540 if (radeon_no_wb == 1) {
541 dev_priv->writeback_works = 0;
542 DRM_INFO("writeback forced off\n");
543 }
544
545 if (!dev_priv->writeback_works) {
546 /* Disable writeback to avoid unnecessary bus master transfer */
547 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
548 RADEON_RB_NO_UPDATE);
549 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
550 }
551}
552
553int r600_do_engine_reset(struct drm_device *dev)
554{
555 drm_radeon_private_t *dev_priv = dev->dev_private;
556 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
557
558 DRM_INFO("Resetting GPU\n");
559
560 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
561 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
562 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
563
564 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
565 RADEON_READ(R600_GRBM_SOFT_RESET);
566 DRM_UDELAY(50);
567 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
568 RADEON_READ(R600_GRBM_SOFT_RESET);
569
570 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
571 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
572 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
573
574 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
575 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
576 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
577 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
578
579 /* Reset the CP ring */
580 r600_do_cp_reset(dev_priv);
581
582 /* The CP is no longer running after an engine reset */
583 dev_priv->cp_running = 0;
584
585 /* Reset any pending vertex, indirect buffers */
586 radeon_freelist_reset(dev);
587
588 return 0;
589
590}
591
592static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
593 u32 num_backends,
594 u32 backend_disable_mask)
595{
596 u32 backend_map = 0;
597 u32 enabled_backends_mask;
598 u32 enabled_backends_count;
599 u32 cur_pipe;
600 u32 swizzle_pipe[R6XX_MAX_PIPES];
601 u32 cur_backend;
602 u32 i;
603
604 if (num_tile_pipes > R6XX_MAX_PIPES)
605 num_tile_pipes = R6XX_MAX_PIPES;
606 if (num_tile_pipes < 1)
607 num_tile_pipes = 1;
608 if (num_backends > R6XX_MAX_BACKENDS)
609 num_backends = R6XX_MAX_BACKENDS;
610 if (num_backends < 1)
611 num_backends = 1;
612
613 enabled_backends_mask = 0;
614 enabled_backends_count = 0;
615 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
616 if (((backend_disable_mask >> i) & 1) == 0) {
617 enabled_backends_mask |= (1 << i);
618 ++enabled_backends_count;
619 }
620 if (enabled_backends_count == num_backends)
621 break;
622 }
623
624 if (enabled_backends_count == 0) {
625 enabled_backends_mask = 1;
626 enabled_backends_count = 1;
627 }
628
629 if (enabled_backends_count != num_backends)
630 num_backends = enabled_backends_count;
631
632 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
633 switch (num_tile_pipes) {
634 case 1:
635 swizzle_pipe[0] = 0;
636 break;
637 case 2:
638 swizzle_pipe[0] = 0;
639 swizzle_pipe[1] = 1;
640 break;
641 case 3:
642 swizzle_pipe[0] = 0;
643 swizzle_pipe[1] = 1;
644 swizzle_pipe[2] = 2;
645 break;
646 case 4:
647 swizzle_pipe[0] = 0;
648 swizzle_pipe[1] = 1;
649 swizzle_pipe[2] = 2;
650 swizzle_pipe[3] = 3;
651 break;
652 case 5:
653 swizzle_pipe[0] = 0;
654 swizzle_pipe[1] = 1;
655 swizzle_pipe[2] = 2;
656 swizzle_pipe[3] = 3;
657 swizzle_pipe[4] = 4;
658 break;
659 case 6:
660 swizzle_pipe[0] = 0;
661 swizzle_pipe[1] = 2;
662 swizzle_pipe[2] = 4;
663 swizzle_pipe[3] = 5;
664 swizzle_pipe[4] = 1;
665 swizzle_pipe[5] = 3;
666 break;
667 case 7:
668 swizzle_pipe[0] = 0;
669 swizzle_pipe[1] = 2;
670 swizzle_pipe[2] = 4;
671 swizzle_pipe[3] = 6;
672 swizzle_pipe[4] = 1;
673 swizzle_pipe[5] = 3;
674 swizzle_pipe[6] = 5;
675 break;
676 case 8:
677 swizzle_pipe[0] = 0;
678 swizzle_pipe[1] = 2;
679 swizzle_pipe[2] = 4;
680 swizzle_pipe[3] = 6;
681 swizzle_pipe[4] = 1;
682 swizzle_pipe[5] = 3;
683 swizzle_pipe[6] = 5;
684 swizzle_pipe[7] = 7;
685 break;
686 }
687
688 cur_backend = 0;
689 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
690 while (((1 << cur_backend) & enabled_backends_mask) == 0)
691 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
692
693 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
694
695 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
696 }
697
698 return backend_map;
699}
700
701static int r600_count_pipe_bits(uint32_t val)
702{
703 int i, ret = 0;
704 for (i = 0; i < 32; i++) {
705 ret += val & 1;
706 val >>= 1;
707 }
708 return ret;
709}
710
711static void r600_gfx_init(struct drm_device *dev,
712 drm_radeon_private_t *dev_priv)
713{
714 int i, j, num_qd_pipes;
715 u32 sx_debug_1;
716 u32 tc_cntl;
717 u32 arb_pop;
718 u32 num_gs_verts_per_thread;
719 u32 vgt_gs_per_es;
720 u32 gs_prim_buffer_depth = 0;
721 u32 sq_ms_fifo_sizes;
722 u32 sq_config;
723 u32 sq_gpr_resource_mgmt_1 = 0;
724 u32 sq_gpr_resource_mgmt_2 = 0;
725 u32 sq_thread_resource_mgmt = 0;
726 u32 sq_stack_resource_mgmt_1 = 0;
727 u32 sq_stack_resource_mgmt_2 = 0;
728 u32 hdp_host_path_cntl;
729 u32 backend_map;
730 u32 gb_tiling_config = 0;
731 u32 cc_rb_backend_disable = 0;
732 u32 cc_gc_shader_pipe_config = 0;
733 u32 ramcfg;
734
735 /* setup chip specs */
736 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
737 case CHIP_R600:
738 dev_priv->r600_max_pipes = 4;
739 dev_priv->r600_max_tile_pipes = 8;
740 dev_priv->r600_max_simds = 4;
741 dev_priv->r600_max_backends = 4;
742 dev_priv->r600_max_gprs = 256;
743 dev_priv->r600_max_threads = 192;
744 dev_priv->r600_max_stack_entries = 256;
745 dev_priv->r600_max_hw_contexts = 8;
746 dev_priv->r600_max_gs_threads = 16;
747 dev_priv->r600_sx_max_export_size = 128;
748 dev_priv->r600_sx_max_export_pos_size = 16;
749 dev_priv->r600_sx_max_export_smx_size = 128;
750 dev_priv->r600_sq_num_cf_insts = 2;
751 break;
752 case CHIP_RV630:
753 case CHIP_RV635:
754 dev_priv->r600_max_pipes = 2;
755 dev_priv->r600_max_tile_pipes = 2;
756 dev_priv->r600_max_simds = 3;
757 dev_priv->r600_max_backends = 1;
758 dev_priv->r600_max_gprs = 128;
759 dev_priv->r600_max_threads = 192;
760 dev_priv->r600_max_stack_entries = 128;
761 dev_priv->r600_max_hw_contexts = 8;
762 dev_priv->r600_max_gs_threads = 4;
763 dev_priv->r600_sx_max_export_size = 128;
764 dev_priv->r600_sx_max_export_pos_size = 16;
765 dev_priv->r600_sx_max_export_smx_size = 128;
766 dev_priv->r600_sq_num_cf_insts = 2;
767 break;
768 case CHIP_RV610:
769 case CHIP_RS780:
6502fbfa 770 case CHIP_RS880:
c05ce083
AD		 771 case CHIP_RV620:
772 dev_priv->r600_max_pipes = 1;
773 dev_priv->r600_max_tile_pipes = 1;
774 dev_priv->r600_max_simds = 2;
775 dev_priv->r600_max_backends = 1;
776 dev_priv->r600_max_gprs = 128;
777 dev_priv->r600_max_threads = 192;
778 dev_priv->r600_max_stack_entries = 128;
779 dev_priv->r600_max_hw_contexts = 4;
780 dev_priv->r600_max_gs_threads = 4;
781 dev_priv->r600_sx_max_export_size = 128;
782 dev_priv->r600_sx_max_export_pos_size = 16;
783 dev_priv->r600_sx_max_export_smx_size = 128;
784 dev_priv->r600_sq_num_cf_insts = 1;
785 break;
786 case CHIP_RV670:
787 dev_priv->r600_max_pipes = 4;
788 dev_priv->r600_max_tile_pipes = 4;
789 dev_priv->r600_max_simds = 4;
790 dev_priv->r600_max_backends = 4;
791 dev_priv->r600_max_gprs = 192;
792 dev_priv->r600_max_threads = 192;
793 dev_priv->r600_max_stack_entries = 256;
794 dev_priv->r600_max_hw_contexts = 8;
795 dev_priv->r600_max_gs_threads = 16;
796 dev_priv->r600_sx_max_export_size = 128;
797 dev_priv->r600_sx_max_export_pos_size = 16;
798 dev_priv->r600_sx_max_export_smx_size = 128;
799 dev_priv->r600_sq_num_cf_insts = 2;
800 break;
801 default:
802 break;
803 }
804
805 /* Initialize HDP */
806 j = 0;
807 for (i = 0; i < 32; i++) {
808 RADEON_WRITE((0x2c14 + j), 0x00000000);
809 RADEON_WRITE((0x2c18 + j), 0x00000000);
810 RADEON_WRITE((0x2c1c + j), 0x00000000);
811 RADEON_WRITE((0x2c20 + j), 0x00000000);
812 RADEON_WRITE((0x2c24 + j), 0x00000000);
813 j += 0x18;
814 }
815
816 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
817
818 /* setup tiling, simd, pipe config */
819 ramcfg = RADEON_READ(R600_RAMCFG);
820
821 switch (dev_priv->r600_max_tile_pipes) {
822 case 1:
823 gb_tiling_config |= R600_PIPE_TILING(0);
824 break;
825 case 2:
826 gb_tiling_config |= R600_PIPE_TILING(1);
827 break;
828 case 4:
829 gb_tiling_config |= R600_PIPE_TILING(2);
830 break;
831 case 8:
832 gb_tiling_config |= R600_PIPE_TILING(3);
833 break;
834 default:
835 break;
836 }
837
838 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
839
840 gb_tiling_config |= R600_GROUP_SIZE(0);
841
842 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
843 gb_tiling_config |= R600_ROW_TILING(3);
844 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
845 } else {
846 gb_tiling_config |=
847 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
848 gb_tiling_config |=
849 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
850 }
851
852 gb_tiling_config |= R600_BANK_SWAPS(1);
853
854 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
855 dev_priv->r600_max_backends,
856 (0xff << dev_priv->r600_max_backends) & 0xff);
857 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
858
859 cc_gc_shader_pipe_config =
860 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
861 cc_gc_shader_pipe_config |=
862 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
863
864 cc_rb_backend_disable =
865 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
866
867 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
868 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
869 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
870
871 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
872 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
873 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
874
875 num_qd_pipes =
876 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
877 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
878 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
879
880 /* set HW defaults for 3D engine */
881 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
882 R600_ROQ_IB2_START(0x2b)));
883
884 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
885 R600_ROQ_END(0x40)));
886
887 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
888 R600_SYNC_GRADIENT |
889 R600_SYNC_WALKER |
890 R600_SYNC_ALIGNER));
891
892 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
893 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
894
895 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
896 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
897 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
898 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
899 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
900
901 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
902 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
903 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
904 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 905 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
906 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
c05ce083
AD		 907 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
908 else
909 RADEON_WRITE(R600_DB_DEBUG, 0);
910
911 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
912 R600_DEPTH_FLUSH(16) |
913 R600_DEPTH_PENDING_FREE(4) |
914 R600_DEPTH_CACHELINE_FREE(16)));
915 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
916 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
917
918 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
919 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
920
921 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
922 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
925 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
c05ce083
AD		 926 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
927 R600_FETCH_FIFO_HIWATER(0xa) |
928 R600_DONE_FIFO_HIWATER(0xe0) |
929 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
930 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
931 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
932 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
933 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
934 }
935 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
936
937 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
938 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
939 */
940 sq_config = RADEON_READ(R600_SQ_CONFIG);
941 sq_config &= ~(R600_PS_PRIO(3) |
942 R600_VS_PRIO(3) |
943 R600_GS_PRIO(3) |
944 R600_ES_PRIO(3));
945 sq_config |= (R600_DX9_CONSTS |
946 R600_VC_ENABLE |
947 R600_PS_PRIO(0) |
948 R600_VS_PRIO(1) |
949 R600_GS_PRIO(2) |
950 R600_ES_PRIO(3));
951
952 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
953 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
954 R600_NUM_VS_GPRS(124) |
955 R600_NUM_CLAUSE_TEMP_GPRS(4));
956 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
957 R600_NUM_ES_GPRS(0));
958 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
959 R600_NUM_VS_THREADS(48) |
960 R600_NUM_GS_THREADS(4) |
961 R600_NUM_ES_THREADS(4));
962 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
963 R600_NUM_VS_STACK_ENTRIES(128));
964 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
965 R600_NUM_ES_STACK_ENTRIES(0));
966 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
967 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 968 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
969 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
c05ce083
AD		 970 /* no vertex cache */
971 sq_config &= ~R600_VC_ENABLE;
972
973 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
974 R600_NUM_VS_GPRS(44) |
975 R600_NUM_CLAUSE_TEMP_GPRS(2));
976 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
977 R600_NUM_ES_GPRS(17));
978 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
979 R600_NUM_VS_THREADS(78) |
980 R600_NUM_GS_THREADS(4) |
981 R600_NUM_ES_THREADS(31));
982 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
983 R600_NUM_VS_STACK_ENTRIES(40));
984 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
985 R600_NUM_ES_STACK_ENTRIES(16));
986 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
987 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
988 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
989 R600_NUM_VS_GPRS(44) |
990 R600_NUM_CLAUSE_TEMP_GPRS(2));
991 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
992 R600_NUM_ES_GPRS(18));
993 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
994 R600_NUM_VS_THREADS(78) |
995 R600_NUM_GS_THREADS(4) |
996 R600_NUM_ES_THREADS(31));
997 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
998 R600_NUM_VS_STACK_ENTRIES(40));
999 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1000 R600_NUM_ES_STACK_ENTRIES(16));
1001 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1002 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1003 R600_NUM_VS_GPRS(44) |
1004 R600_NUM_CLAUSE_TEMP_GPRS(2));
1005 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1006 R600_NUM_ES_GPRS(17));
1007 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1008 R600_NUM_VS_THREADS(78) |
1009 R600_NUM_GS_THREADS(4) |
1010 R600_NUM_ES_THREADS(31));
1011 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1012 R600_NUM_VS_STACK_ENTRIES(64));
1013 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1014 R600_NUM_ES_STACK_ENTRIES(64));
1015 }
1016
1017 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1018 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1019 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1020 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1021 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1022 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1023
1024 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1025 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 1026 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1027 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
c05ce083
AD		 1028 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1029 else
1030 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1031
1032 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1033 R600_S0_Y(0x4) |
1034 R600_S1_X(0x4) |
1035 R600_S1_Y(0xc)));
1036 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1037 R600_S0_Y(0xe) |
1038 R600_S1_X(0x2) |
1039 R600_S1_Y(0x2) |
1040 R600_S2_X(0xa) |
1041 R600_S2_Y(0x6) |
1042 R600_S3_X(0x6) |
1043 R600_S3_Y(0xa)));
1044 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1045 R600_S0_Y(0xb) |
1046 R600_S1_X(0x4) |
1047 R600_S1_Y(0xc) |
1048 R600_S2_X(0x1) |
1049 R600_S2_Y(0x6) |
1050 R600_S3_X(0xa) |
1051 R600_S3_Y(0xe)));
1052 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1053 R600_S4_Y(0x1) |
1054 R600_S5_X(0x0) |
1055 R600_S5_Y(0x0) |
1056 R600_S6_X(0xb) |
1057 R600_S6_Y(0x4) |
1058 R600_S7_X(0x7) |
1059 R600_S7_Y(0x8)));
1060
1061
1062 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1063 case CHIP_R600:
1064 case CHIP_RV630:
1065 case CHIP_RV635:
1066 gs_prim_buffer_depth = 0;
1067 break;
1068 case CHIP_RV610:
1069 case CHIP_RS780:
6502fbfa 1070 case CHIP_RS880:
c05ce083
AD		 1071 case CHIP_RV620:
1072 gs_prim_buffer_depth = 32;
1073 break;
1074 case CHIP_RV670:
1075 gs_prim_buffer_depth = 128;
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1082 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1083 /* Max value for this is 256 */
1084 if (vgt_gs_per_es > 256)
1085 vgt_gs_per_es = 256;
1086
1087 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1088 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1089 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1090 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1091
1092 /* more default values. 2D/3D driver should adjust as needed */
1093 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1094 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1095 RADEON_WRITE(R600_SX_MISC, 0);
1096 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1097 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1098 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1099 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1100 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1101 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1102
1103 /* clear render buffer base addresses */
1104 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1105 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1106 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1107 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1108 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1109 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1110 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1111 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1112
1113 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1114 case CHIP_RV610:
1115 case CHIP_RS780:
6502fbfa 1116 case CHIP_RS880:
c05ce083
AD		 1117 case CHIP_RV620:
1118 tc_cntl = R600_TC_L2_SIZE(8);
1119 break;
1120 case CHIP_RV630:
1121 case CHIP_RV635:
1122 tc_cntl = R600_TC_L2_SIZE(4);
1123 break;
1124 case CHIP_R600:
1125 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1126 break;
1127 default:
1128 tc_cntl = R600_TC_L2_SIZE(0);
1129 break;
1130 }
1131
1132 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1133
1134 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1135 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1136
1137 arb_pop = RADEON_READ(R600_ARB_POP);
1138 arb_pop |= R600_ENABLE_TC128;
1139 RADEON_WRITE(R600_ARB_POP, arb_pop);
1140
1141 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1142 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1143 R600_NUM_CLIP_SEQ(3)));
1144 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1145
1146}
1147
1148static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1149 u32 num_backends,
1150 u32 backend_disable_mask)
1151{
1152 u32 backend_map = 0;
1153 u32 enabled_backends_mask;
1154 u32 enabled_backends_count;
1155 u32 cur_pipe;
1156 u32 swizzle_pipe[R7XX_MAX_PIPES];
1157 u32 cur_backend;
1158 u32 i;
1159
1160 if (num_tile_pipes > R7XX_MAX_PIPES)
1161 num_tile_pipes = R7XX_MAX_PIPES;
1162 if (num_tile_pipes < 1)
1163 num_tile_pipes = 1;
1164 if (num_backends > R7XX_MAX_BACKENDS)
1165 num_backends = R7XX_MAX_BACKENDS;
1166 if (num_backends < 1)
1167 num_backends = 1;
1168
1169 enabled_backends_mask = 0;
1170 enabled_backends_count = 0;
1171 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1172 if (((backend_disable_mask >> i) & 1) == 0) {
1173 enabled_backends_mask |= (1 << i);
1174 ++enabled_backends_count;
1175 }
1176 if (enabled_backends_count == num_backends)
1177 break;
1178 }
1179
1180 if (enabled_backends_count == 0) {
1181 enabled_backends_mask = 1;
1182 enabled_backends_count = 1;
1183 }
1184
1185 if (enabled_backends_count != num_backends)
1186 num_backends = enabled_backends_count;
1187
1188 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1189 switch (num_tile_pipes) {
1190 case 1:
1191 swizzle_pipe[0] = 0;
1192 break;
1193 case 2:
1194 swizzle_pipe[0] = 0;
1195 swizzle_pipe[1] = 1;
1196 break;
1197 case 3:
1198 swizzle_pipe[0] = 0;
1199 swizzle_pipe[1] = 2;
1200 swizzle_pipe[2] = 1;
1201 break;
1202 case 4:
1203 swizzle_pipe[0] = 0;
1204 swizzle_pipe[1] = 2;
1205 swizzle_pipe[2] = 3;
1206 swizzle_pipe[3] = 1;
1207 break;
1208 case 5:
1209 swizzle_pipe[0] = 0;
1210 swizzle_pipe[1] = 2;
1211 swizzle_pipe[2] = 4;
1212 swizzle_pipe[3] = 1;
1213 swizzle_pipe[4] = 3;
1214 break;
1215 case 6:
1216 swizzle_pipe[0] = 0;
1217 swizzle_pipe[1] = 2;
1218 swizzle_pipe[2] = 4;
1219 swizzle_pipe[3] = 5;
1220 swizzle_pipe[4] = 3;
1221 swizzle_pipe[5] = 1;
1222 break;
1223 case 7:
1224 swizzle_pipe[0] = 0;
1225 swizzle_pipe[1] = 2;
1226 swizzle_pipe[2] = 4;
1227 swizzle_pipe[3] = 6;
1228 swizzle_pipe[4] = 3;
1229 swizzle_pipe[5] = 1;
1230 swizzle_pipe[6] = 5;
1231 break;
1232 case 8:
1233 swizzle_pipe[0] = 0;
1234 swizzle_pipe[1] = 2;
1235 swizzle_pipe[2] = 4;
1236 swizzle_pipe[3] = 6;
1237 swizzle_pipe[4] = 3;
1238 swizzle_pipe[5] = 1;
1239 swizzle_pipe[6] = 7;
1240 swizzle_pipe[7] = 5;
1241 break;
1242 }
1243
1244 cur_backend = 0;
1245 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1246 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1247 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1248
1249 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1250
1251 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1252 }
1253
1254 return backend_map;
1255}
1256
1257static void r700_gfx_init(struct drm_device *dev,
1258 drm_radeon_private_t *dev_priv)
1259{
1260 int i, j, num_qd_pipes;
1261 u32 sx_debug_1;
1262 u32 smx_dc_ctl0;
1263 u32 num_gs_verts_per_thread;
1264 u32 vgt_gs_per_es;
1265 u32 gs_prim_buffer_depth = 0;
1266 u32 sq_ms_fifo_sizes;
1267 u32 sq_config;
1268 u32 sq_thread_resource_mgmt;
1269 u32 hdp_host_path_cntl;
1270 u32 sq_dyn_gpr_size_simd_ab_0;
1271 u32 backend_map;
1272 u32 gb_tiling_config = 0;
1273 u32 cc_rb_backend_disable = 0;
1274 u32 cc_gc_shader_pipe_config = 0;
1275 u32 mc_arb_ramcfg;
1276 u32 db_debug4;
1277
1278 /* setup chip specs */
1279 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1280 case CHIP_RV770:
1281 dev_priv->r600_max_pipes = 4;
1282 dev_priv->r600_max_tile_pipes = 8;
1283 dev_priv->r600_max_simds = 10;
1284 dev_priv->r600_max_backends = 4;
1285 dev_priv->r600_max_gprs = 256;
1286 dev_priv->r600_max_threads = 248;
1287 dev_priv->r600_max_stack_entries = 512;
1288 dev_priv->r600_max_hw_contexts = 8;
1289 dev_priv->r600_max_gs_threads = 16 * 2;
1290 dev_priv->r600_sx_max_export_size = 128;
1291 dev_priv->r600_sx_max_export_pos_size = 16;
1292 dev_priv->r600_sx_max_export_smx_size = 112;
1293 dev_priv->r600_sq_num_cf_insts = 2;
1294
1295 dev_priv->r700_sx_num_of_sets = 7;
1296 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1297 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1298 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1299 break;
1300 case CHIP_RV730:
1301 dev_priv->r600_max_pipes = 2;
1302 dev_priv->r600_max_tile_pipes = 4;
1303 dev_priv->r600_max_simds = 8;
1304 dev_priv->r600_max_backends = 2;
1305 dev_priv->r600_max_gprs = 128;
1306 dev_priv->r600_max_threads = 248;
1307 dev_priv->r600_max_stack_entries = 256;
1308 dev_priv->r600_max_hw_contexts = 8;
1309 dev_priv->r600_max_gs_threads = 16 * 2;
1310 dev_priv->r600_sx_max_export_size = 256;
1311 dev_priv->r600_sx_max_export_pos_size = 32;
1312 dev_priv->r600_sx_max_export_smx_size = 224;
1313 dev_priv->r600_sq_num_cf_insts = 2;
1314
1315 dev_priv->r700_sx_num_of_sets = 7;
1316 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1317 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1318 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
2a71ebcd
AD		 1319 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1320 dev_priv->r600_sx_max_export_pos_size -= 16;
1321 dev_priv->r600_sx_max_export_smx_size += 16;
1322 }
c05ce083
AD		 1323 break;
1324 case CHIP_RV710:
1325 dev_priv->r600_max_pipes = 2;
1326 dev_priv->r600_max_tile_pipes = 2;
1327 dev_priv->r600_max_simds = 2;
1328 dev_priv->r600_max_backends = 1;
1329 dev_priv->r600_max_gprs = 256;
1330 dev_priv->r600_max_threads = 192;
1331 dev_priv->r600_max_stack_entries = 256;
1332 dev_priv->r600_max_hw_contexts = 4;
1333 dev_priv->r600_max_gs_threads = 8 * 2;
1334 dev_priv->r600_sx_max_export_size = 128;
1335 dev_priv->r600_sx_max_export_pos_size = 16;
1336 dev_priv->r600_sx_max_export_smx_size = 112;
1337 dev_priv->r600_sq_num_cf_insts = 1;
1338
1339 dev_priv->r700_sx_num_of_sets = 7;
1340 dev_priv->r700_sc_prim_fifo_size = 0x40;
1341 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1342 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1343 break;
2a71ebcd
AD		 1344 case CHIP_RV740:
1345 dev_priv->r600_max_pipes = 4;
1346 dev_priv->r600_max_tile_pipes = 4;
1347 dev_priv->r600_max_simds = 8;
1348 dev_priv->r600_max_backends = 4;
1349 dev_priv->r600_max_gprs = 256;
1350 dev_priv->r600_max_threads = 248;
1351 dev_priv->r600_max_stack_entries = 512;
1352 dev_priv->r600_max_hw_contexts = 8;
1353 dev_priv->r600_max_gs_threads = 16 * 2;
1354 dev_priv->r600_sx_max_export_size = 256;
1355 dev_priv->r600_sx_max_export_pos_size = 32;
1356 dev_priv->r600_sx_max_export_smx_size = 224;
1357 dev_priv->r600_sq_num_cf_insts = 2;
1358
1359 dev_priv->r700_sx_num_of_sets = 7;
1360 dev_priv->r700_sc_prim_fifo_size = 0x100;
1361 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1362 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1363
1364 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1365 dev_priv->r600_sx_max_export_pos_size -= 16;
1366 dev_priv->r600_sx_max_export_smx_size += 16;
1367 }
1368 break;
c05ce083
AD		 1369 default:
1370 break;
1371 }
1372
1373 /* Initialize HDP */
1374 j = 0;
1375 for (i = 0; i < 32; i++) {
1376 RADEON_WRITE((0x2c14 + j), 0x00000000);
1377 RADEON_WRITE((0x2c18 + j), 0x00000000);
1378 RADEON_WRITE((0x2c1c + j), 0x00000000);
1379 RADEON_WRITE((0x2c20 + j), 0x00000000);
1380 RADEON_WRITE((0x2c24 + j), 0x00000000);
1381 j += 0x18;
1382 }
1383
1384 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1385
1386 /* setup tiling, simd, pipe config */
1387 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1388
1389 switch (dev_priv->r600_max_tile_pipes) {
1390 case 1:
1391 gb_tiling_config |= R600_PIPE_TILING(0);
1392 break;
1393 case 2:
1394 gb_tiling_config |= R600_PIPE_TILING(1);
1395 break;
1396 case 4:
1397 gb_tiling_config |= R600_PIPE_TILING(2);
1398 break;
1399 case 8:
1400 gb_tiling_config |= R600_PIPE_TILING(3);
1401 break;
1402 default:
1403 break;
1404 }
1405
1406 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1407 gb_tiling_config |= R600_BANK_TILING(1);
1408 else
1409 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1410
1411 gb_tiling_config |= R600_GROUP_SIZE(0);
1412
1413 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1414 gb_tiling_config |= R600_ROW_TILING(3);
1415 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1416 } else {
1417 gb_tiling_config |=
1418 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1419 gb_tiling_config |=
1420 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1421 }
1422
1423 gb_tiling_config |= R600_BANK_SWAPS(1);
1424
1425 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1426 dev_priv->r600_max_backends,
1427 (0xff << dev_priv->r600_max_backends) & 0xff);
1428 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1429
1430 cc_gc_shader_pipe_config =
1431 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1432 cc_gc_shader_pipe_config |=
1433 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1434
1435 cc_rb_backend_disable =
1436 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1437
1438 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1439 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1440 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1441
1442 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1443 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1444 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1445
1446 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1447 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1448 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1449 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1450 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1451
1452 num_qd_pipes =
1453 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1454 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1455 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1456
1457 /* set HW defaults for 3D engine */
1458 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1459 R600_ROQ_IB2_START(0x2b)));
1460
1461 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1462
1463 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1464 R600_SYNC_GRADIENT |
1465 R600_SYNC_WALKER |
1466 R600_SYNC_ALIGNER));
1467
1468 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1469 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1470 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1471
1472 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1473 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1474 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1475 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1476
1477 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1478 R700_GS_FLUSH_CTL(4) |
1479 R700_ACK_FLUSH_CTL(3) |
1480 R700_SYNC_FLUSH_CTL));
1481
1482 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1483 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1484 else {
1485 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1486 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1487 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1488 }
1489
1490 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1491 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1492 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1493
1494 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1495 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1496 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1497
1498 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1499
1500 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1501
1502 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1503
1504 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1505
1506 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1507
1508 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1509 R600_DONE_FIFO_HIWATER(0xe0) |
1510 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1511 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1512 case CHIP_RV770:
1513 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1514 break;
1515 case CHIP_RV730:
1516 case CHIP_RV710:
2a71ebcd 1517 case CHIP_RV740:
c05ce083
AD		 1518 default:
1519 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1520 break;
1521 }
1522 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1523
1524 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1525 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1526 */
1527 sq_config = RADEON_READ(R600_SQ_CONFIG);
1528 sq_config &= ~(R600_PS_PRIO(3) |
1529 R600_VS_PRIO(3) |
1530 R600_GS_PRIO(3) |
1531 R600_ES_PRIO(3));
1532 sq_config |= (R600_DX9_CONSTS |
1533 R600_VC_ENABLE |
1534 R600_EXPORT_SRC_C |
1535 R600_PS_PRIO(0) |
1536 R600_VS_PRIO(1) |
1537 R600_GS_PRIO(2) |
1538 R600_ES_PRIO(3));
1539 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1540 /* no vertex cache */
1541 sq_config &= ~R600_VC_ENABLE;
1542
1543 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1544
1545 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1546 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1547 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1548
1549 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1550 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1551
1552 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1553 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1554 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1555 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1556 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1557 else
1558 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1559 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1560
1561 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1562 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1563
1564 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1565 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1566
1567 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1568 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1569 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1570 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1571
1572 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1573 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1574 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1575 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1576 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1577 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1578 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1579 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1580
1581 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1582 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1583
1584 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1585 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1586 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1587 else
1588 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1589 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1590
1591 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1592 case CHIP_RV770:
1593 case CHIP_RV730:
2a71ebcd 1594 case CHIP_RV740:
c05ce083
AD		 1595 gs_prim_buffer_depth = 384;
1596 break;
1597 case CHIP_RV710:
1598 gs_prim_buffer_depth = 128;
1599 break;
1600 default:
1601 break;
1602 }
1603
1604 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1605 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1606 /* Max value for this is 256 */
1607 if (vgt_gs_per_es > 256)
1608 vgt_gs_per_es = 256;
1609
1610 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1611 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1612 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1613
1614 /* more default values. 2D/3D driver should adjust as needed */
1615 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1616 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1617 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1618 RADEON_WRITE(R600_SX_MISC, 0);
1619 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1620 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1621 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1622 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1623 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1624 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1625 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1626 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1627
1628 /* clear render buffer base addresses */
1629 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1630 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1631 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1632 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1633 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1634 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1635 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1636 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1637
1638 RADEON_WRITE(R700_TCP_CNTL, 0);
1639
1640 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1641 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1642
1643 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1644
1645 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1646 R600_NUM_CLIP_SEQ(3)));
1647
1648}
1649
1650static void r600_cp_init_ring_buffer(struct drm_device *dev,
1651 drm_radeon_private_t *dev_priv,
1652 struct drm_file *file_priv)
1653{
1654 struct drm_radeon_master_private *master_priv;
1655 u32 ring_start;
6546bf6d 1656 u64 rptr_addr;
c05ce083
AD		 1657
1658 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1659 r700_gfx_init(dev, dev_priv);
1660 else
1661 r600_gfx_init(dev, dev_priv);
1662
1663 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1664 RADEON_READ(R600_GRBM_SOFT_RESET);
1665 DRM_UDELAY(15000);
1666 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1667
1668
1669 /* Set ring buffer size */
1670#ifdef __BIG_ENDIAN
1671 RADEON_WRITE(R600_CP_RB_CNTL,
1672 RADEON_BUF_SWAP_32BIT |
1673 RADEON_RB_NO_UPDATE |
1674 (dev_priv->ring.rptr_update_l2qw << 8) |
1675 dev_priv->ring.size_l2qw);
1676#else
1677 RADEON_WRITE(R600_CP_RB_CNTL,
1678 RADEON_RB_NO_UPDATE |
1679 (dev_priv->ring.rptr_update_l2qw << 8) |
1680 dev_priv->ring.size_l2qw);
1681#endif
1682
1683 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1684
1685 /* Set the write pointer delay */
1686 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1687
1688#ifdef __BIG_ENDIAN
1689 RADEON_WRITE(R600_CP_RB_CNTL,
1690 RADEON_BUF_SWAP_32BIT |
1691 RADEON_RB_NO_UPDATE |
1692 RADEON_RB_RPTR_WR_ENA |
1693 (dev_priv->ring.rptr_update_l2qw << 8) |
1694 dev_priv->ring.size_l2qw);
1695#else
1696 RADEON_WRITE(R600_CP_RB_CNTL,
1697 RADEON_RB_NO_UPDATE |
1698 RADEON_RB_RPTR_WR_ENA |
1699 (dev_priv->ring.rptr_update_l2qw << 8) |
1700 dev_priv->ring.size_l2qw);
1701#endif
1702
1703 /* Initialize the ring buffer's read and write pointers */
1704 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1705 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1706 SET_RING_HEAD(dev_priv, 0);
1707 dev_priv->ring.tail = 0;
1708
1709#if __OS_HAS_AGP
1710 if (dev_priv->flags & RADEON_IS_AGP) {
6546bf6d
DA		 1711 rptr_addr = dev_priv->ring_rptr->offset
1712 - dev->agp->base +
1713 dev_priv->gart_vm_start;
c05ce083
AD		 1714 } else
1715#endif
1716 {
6546bf6d
DA		 1717 rptr_addr = dev_priv->ring_rptr->offset
1718 - ((unsigned long) dev->sg->virtual)
1719 + dev_priv->gart_vm_start;
c05ce083 1720 }
6546bf6d
DA		 1721 RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1722 rptr_addr & 0xffffffff);
1723 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1724 upper_32_bits(rptr_addr));
c05ce083
AD		 1725
1726#ifdef __BIG_ENDIAN
1727 RADEON_WRITE(R600_CP_RB_CNTL,
1728 RADEON_BUF_SWAP_32BIT |
1729 (dev_priv->ring.rptr_update_l2qw << 8) |
1730 dev_priv->ring.size_l2qw);
1731#else
1732 RADEON_WRITE(R600_CP_RB_CNTL,
1733 (dev_priv->ring.rptr_update_l2qw << 8) |
1734 dev_priv->ring.size_l2qw);
1735#endif
1736
1737#if __OS_HAS_AGP
1738 if (dev_priv->flags & RADEON_IS_AGP) {
1739 /* XXX */
1740 radeon_write_agp_base(dev_priv, dev->agp->base);
1741
1742 /* XXX */
1743 radeon_write_agp_location(dev_priv,
1744 (((dev_priv->gart_vm_start - 1 +
1745 dev_priv->gart_size) & 0xffff0000) |
1746 (dev_priv->gart_vm_start >> 16)));
1747
1748 ring_start = (dev_priv->cp_ring->offset
1749 - dev->agp->base
1750 + dev_priv->gart_vm_start);
1751 } else
1752#endif
1753 ring_start = (dev_priv->cp_ring->offset
1754 - (unsigned long)dev->sg->virtual
1755 + dev_priv->gart_vm_start);
1756
1757 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1758
1759 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1760
1761 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1762
c05ce083
AD		 1763 /* Initialize the scratch register pointer. This will cause
1764 * the scratch register values to be written out to memory
1765 * whenever they are updated.
1766 *
1767 * We simply put this behind the ring read pointer, this works
1768 * with PCI GART as well as (whatever kind of) AGP GART
1769 */
6546bf6d
DA		 1770 {
1771 u64 scratch_addr;
1772
1773 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1774 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1775 scratch_addr += R600_SCRATCH_REG_OFFSET;
1776 scratch_addr >>= 8;
1777 scratch_addr &= 0xffffffff;
1778
1779 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1780 }
c05ce083
AD		 1781
1782 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1783
1784 /* Turn on bus mastering */
1785 radeon_enable_bm(dev_priv);
1786
1787 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1788 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1789
1790 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1791 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1792
1793 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1794 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1795
1796 /* reset sarea copies of these */
1797 master_priv = file_priv->master->driver_priv;
1798 if (master_priv->sarea_priv) {
1799 master_priv->sarea_priv->last_frame = 0;
1800 master_priv->sarea_priv->last_dispatch = 0;
1801 master_priv->sarea_priv->last_clear = 0;
1802 }
1803
1804 r600_do_wait_for_idle(dev_priv);
1805
1806}
1807
1808int r600_do_cleanup_cp(struct drm_device *dev)
1809{
1810 drm_radeon_private_t *dev_priv = dev->dev_private;
1811 DRM_DEBUG("\n");
1812
1813 /* Make sure interrupts are disabled here because the uninstall ioctl
1814 * may not have been called from userspace and after dev_private
1815 * is freed, it's too late.
1816 */
1817 if (dev->irq_enabled)
1818 drm_irq_uninstall(dev);
1819
1820#if __OS_HAS_AGP
1821 if (dev_priv->flags & RADEON_IS_AGP) {
1822 if (dev_priv->cp_ring != NULL) {
1823 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1824 dev_priv->cp_ring = NULL;
1825 }
1826 if (dev_priv->ring_rptr != NULL) {
1827 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1828 dev_priv->ring_rptr = NULL;
1829 }
1830 if (dev->agp_buffer_map != NULL) {
1831 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1832 dev->agp_buffer_map = NULL;
1833 }
1834 } else
1835#endif
1836 {
1837
1838 if (dev_priv->gart_info.bus_addr)
1839 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1840
1841 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1842 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
8f497aad 1843 dev_priv->gart_info.addr = NULL;
c05ce083
AD		 1844 }
1845 }
1846 /* only clear to the start of flags */
1847 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1848
1849 return 0;
1850}
1851
1852int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1853 struct drm_file *file_priv)
1854{
1855 drm_radeon_private_t *dev_priv = dev->dev_private;
1856 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1857
1858 DRM_DEBUG("\n");
1859
1860 /* if we require new memory map but we don't have it fail */
1861 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1862 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1863 r600_do_cleanup_cp(dev);
1864 return -EINVAL;
1865 }
1866
1867 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1868 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1869 dev_priv->flags &= ~RADEON_IS_AGP;
1870 /* The writeback test succeeds, but when writeback is enabled,
1871 * the ring buffer read ptr update fails after first 128 bytes.
1872 */
1873 radeon_no_wb = 1;
1874 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1875 && !init->is_pci) {
1876 DRM_DEBUG("Restoring AGP flag\n");
1877 dev_priv->flags |= RADEON_IS_AGP;
1878 }
1879
1880 dev_priv->usec_timeout = init->usec_timeout;
1881 if (dev_priv->usec_timeout < 1 ||
1882 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1883 DRM_DEBUG("TIMEOUT problem!\n");
1884 r600_do_cleanup_cp(dev);
1885 return -EINVAL;
1886 }
1887
1888 /* Enable vblank on CRTC1 for older X servers
1889 */
1890 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1891
1892 dev_priv->cp_mode = init->cp_mode;
1893
1894 /* We don't support anything other than bus-mastering ring mode,
1895 * but the ring can be in either AGP or PCI space for the ring
1896 * read pointer.
1897 */
1898 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1899 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1900 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1901 r600_do_cleanup_cp(dev);
1902 return -EINVAL;
1903 }
1904
1905 switch (init->fb_bpp) {
1906 case 16:
1907 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1908 break;
1909 case 32:
1910 default:
1911 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1912 break;
1913 }
1914 dev_priv->front_offset = init->front_offset;
1915 dev_priv->front_pitch = init->front_pitch;
1916 dev_priv->back_offset = init->back_offset;
1917 dev_priv->back_pitch = init->back_pitch;
1918
1919 dev_priv->ring_offset = init->ring_offset;
1920 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1921 dev_priv->buffers_offset = init->buffers_offset;
1922 dev_priv->gart_textures_offset = init->gart_textures_offset;
1923
1924 master_priv->sarea = drm_getsarea(dev);
1925 if (!master_priv->sarea) {
1926 DRM_ERROR("could not find sarea!\n");
1927 r600_do_cleanup_cp(dev);
1928 return -EINVAL;
1929 }
1930
1931 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1932 if (!dev_priv->cp_ring) {
1933 DRM_ERROR("could not find cp ring region!\n");
1934 r600_do_cleanup_cp(dev);
1935 return -EINVAL;
1936 }
1937 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1938 if (!dev_priv->ring_rptr) {
1939 DRM_ERROR("could not find ring read pointer!\n");
1940 r600_do_cleanup_cp(dev);
1941 return -EINVAL;
1942 }
1943 dev->agp_buffer_token = init->buffers_offset;
1944 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1945 if (!dev->agp_buffer_map) {
1946 DRM_ERROR("could not find dma buffer region!\n");
1947 r600_do_cleanup_cp(dev);
1948 return -EINVAL;
1949 }
1950
1951 if (init->gart_textures_offset) {
1952 dev_priv->gart_textures =
1953 drm_core_findmap(dev, init->gart_textures_offset);
1954 if (!dev_priv->gart_textures) {
1955 DRM_ERROR("could not find GART texture region!\n");
1956 r600_do_cleanup_cp(dev);
1957 return -EINVAL;
1958 }
1959 }
1960
1961#if __OS_HAS_AGP
1962 /* XXX */
1963 if (dev_priv->flags & RADEON_IS_AGP) {
7659e980
AD		 1964 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1965 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1966 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
c05ce083
AD		 1967 if (!dev_priv->cp_ring->handle ||
1968 !dev_priv->ring_rptr->handle ||
1969 !dev->agp_buffer_map->handle) {
1970 DRM_ERROR("could not find ioremap agp regions!\n");
1971 r600_do_cleanup_cp(dev);
1972 return -EINVAL;
1973 }
1974 } else
1975#endif
1976 {
1977 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1978 dev_priv->ring_rptr->handle =
1979 (void *)dev_priv->ring_rptr->offset;
1980 dev->agp_buffer_map->handle =
1981 (void *)dev->agp_buffer_map->offset;
1982
1983 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1984 dev_priv->cp_ring->handle);
1985 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1986 dev_priv->ring_rptr->handle);
1987 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1988 dev->agp_buffer_map->handle);
1989 }
1990
1991 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1992 dev_priv->fb_size =
1993 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1994 - dev_priv->fb_location;
1995
1996 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1997 ((dev_priv->front_offset
1998 + dev_priv->fb_location) >> 10));
1999
2000 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2001 ((dev_priv->back_offset
2002 + dev_priv->fb_location) >> 10));
2003
2004 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2005 ((dev_priv->depth_offset
2006 + dev_priv->fb_location) >> 10));
2007
2008 dev_priv->gart_size = init->gart_size;
2009
2010 /* New let's set the memory map ... */
2011 if (dev_priv->new_memmap) {
2012 u32 base = 0;
2013
2014 DRM_INFO("Setting GART location based on new memory map\n");
2015
2016 /* If using AGP, try to locate the AGP aperture at the same
2017 * location in the card and on the bus, though we have to
2018 * align it down.
2019 */
2020#if __OS_HAS_AGP
2021 /* XXX */
2022 if (dev_priv->flags & RADEON_IS_AGP) {
2023 base = dev->agp->base;
2024 /* Check if valid */
2025 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2026 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2027 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2028 dev->agp->base);
2029 base = 0;
2030 }
2031 }
2032#endif
2033 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2034 if (base == 0) {
2035 base = dev_priv->fb_location + dev_priv->fb_size;
2036 if (base < dev_priv->fb_location ||
2037 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2038 base = dev_priv->fb_location
2039 - dev_priv->gart_size;
2040 }
2041 dev_priv->gart_vm_start = base & 0xffc00000u;
2042 if (dev_priv->gart_vm_start != base)
2043 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2044 base, dev_priv->gart_vm_start);
2045 }
2046
2047#if __OS_HAS_AGP
2048 /* XXX */
2049 if (dev_priv->flags & RADEON_IS_AGP)
2050 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2051 - dev->agp->base
2052 + dev_priv->gart_vm_start);
2053 else
2054#endif
2055 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2056 - (unsigned long)dev->sg->virtual
2057 + dev_priv->gart_vm_start);
2058
2059 DRM_DEBUG("fb 0x%08x size %d\n",
2060 (unsigned int) dev_priv->fb_location,
2061 (unsigned int) dev_priv->fb_size);
2062 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2063 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2064 (unsigned int) dev_priv->gart_vm_start);
2065 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2066 dev_priv->gart_buffers_offset);
2067
2068 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2069 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2070 + init->ring_size / sizeof(u32));
2071 dev_priv->ring.size = init->ring_size;
2072 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2073
2074 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2075 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2076
2077 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2078 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2079
2080 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2081
2082 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2083
2084#if __OS_HAS_AGP
2085 if (dev_priv->flags & RADEON_IS_AGP) {
2086 /* XXX turn off pcie gart */
2087 } else
2088#endif
2089 {
2090 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2091 /* if we have an offset set from userspace */
2092 if (!dev_priv->pcigart_offset_set) {
2093 DRM_ERROR("Need gart offset from userspace\n");
2094 r600_do_cleanup_cp(dev);
2095 return -EINVAL;
2096 }
2097
2098 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2099
2100 dev_priv->gart_info.bus_addr =
2101 dev_priv->pcigart_offset + dev_priv->fb_location;
2102 dev_priv->gart_info.mapping.offset =
2103 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2104 dev_priv->gart_info.mapping.size =
2105 dev_priv->gart_info.table_size;
2106
2107 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2108 if (!dev_priv->gart_info.mapping.handle) {
2109 DRM_ERROR("ioremap failed.\n");
2110 r600_do_cleanup_cp(dev);
2111 return -EINVAL;
2112 }
2113
2114 dev_priv->gart_info.addr =
2115 dev_priv->gart_info.mapping.handle;
2116
2117 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2118 dev_priv->gart_info.addr,
2119 dev_priv->pcigart_offset);
2120
41f13fe8 2121 if (!r600_page_table_init(dev)) {
c05ce083
AD		 2122 DRM_ERROR("Failed to init GART table\n");
2123 r600_do_cleanup_cp(dev);
2124 return -EINVAL;
2125 }
2126
2127 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2128 r700_vm_init(dev);
2129 else
2130 r600_vm_init(dev);
2131 }
2132
70967ab9
BH		 2133 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2134 int err = r600_cp_init_microcode(dev_priv);
2135 if (err) {
2136 DRM_ERROR("Failed to load firmware!\n");
2137 r600_do_cleanup_cp(dev);
2138 return err;
2139 }
2140 }
c05ce083
AD		 2141 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2142 r700_cp_load_microcode(dev_priv);
2143 else
2144 r600_cp_load_microcode(dev_priv);
2145
2146 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2147
2148 dev_priv->last_buf = 0;
2149
2150 r600_do_engine_reset(dev);
2151 r600_test_writeback(dev_priv);
2152
2153 return 0;
2154}
2155
2156int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2157{
2158 drm_radeon_private_t *dev_priv = dev->dev_private;
2159
2160 DRM_DEBUG("\n");
2161 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2162 r700_vm_init(dev);
2163 r700_cp_load_microcode(dev_priv);
2164 } else {
2165 r600_vm_init(dev);
2166 r600_cp_load_microcode(dev_priv);
2167 }
2168 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2169 r600_do_engine_reset(dev);
2170
2171 return 0;
2172}
2173
2174/* Wait for the CP to go idle.
2175 */
2176int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2177{
2178 RING_LOCALS;
2179 DRM_DEBUG("\n");
2180
2181 BEGIN_RING(5);
2182 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2183 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2184 /* wait for 3D idle clean */
2185 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2186 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2187 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2188
2189 ADVANCE_RING();
2190 COMMIT_RING();
2191
2192 return r600_do_wait_for_idle(dev_priv);
2193}
2194
2195/* Start the Command Processor.
2196 */
2197void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2198{
2199 u32 cp_me;
2200 RING_LOCALS;
2201 DRM_DEBUG("\n");
2202
2203 BEGIN_RING(7);
2204 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2205 OUT_RING(0x00000001);
2206 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2207 OUT_RING(0x00000003);
2208 else
2209 OUT_RING(0x00000000);
2210 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2211 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2212 OUT_RING(0x00000000);
2213 OUT_RING(0x00000000);
2214 ADVANCE_RING();
2215 COMMIT_RING();
2216
2217 /* set the mux and reset the halt bit */
2218 cp_me = 0xff;
2219 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2220
2221 dev_priv->cp_running = 1;
2222
2223}
2224
2225void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2226{
2227 u32 cur_read_ptr;
2228 DRM_DEBUG("\n");
2229
2230 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2231 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2232 SET_RING_HEAD(dev_priv, cur_read_ptr);
2233 dev_priv->ring.tail = cur_read_ptr;
2234}
2235
2236void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2237{
2238 uint32_t cp_me;
2239
2240 DRM_DEBUG("\n");
2241
2242 cp_me = 0xff | R600_CP_ME_HALT;
2243
2244 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2245
2246 dev_priv->cp_running = 0;
2247}
2248
2249int r600_cp_dispatch_indirect(struct drm_device *dev,
2250 struct drm_buf *buf, int start, int end)
2251{
2252 drm_radeon_private_t *dev_priv = dev->dev_private;
2253 RING_LOCALS;
2254
2255 if (start != end) {
2256 unsigned long offset = (dev_priv->gart_buffers_offset
2257 + buf->offset + start);
2258 int dwords = (end - start + 3) / sizeof(u32);
2259
2260 DRM_DEBUG("dwords:%d\n", dwords);
2261 DRM_DEBUG("offset 0x%lx\n", offset);
2262
2263
2264 /* Indirect buffer data must be a multiple of 16 dwords.
2265 * pad the data with a Type-2 CP packet.
2266 */
2267 while (dwords & 0xf) {
2268 u32 *data = (u32 *)
2269 ((char *)dev->agp_buffer_map->handle
2270 + buf->offset + start);
2271 data[dwords++] = RADEON_CP_PACKET2;
2272 }
2273
2274 /* Fire off the indirect buffer */
2275 BEGIN_RING(4);
2276 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2277 OUT_RING((offset & 0xfffffffc));
2278 OUT_RING((upper_32_bits(offset) & 0xff));
2279 OUT_RING(dwords);
2280 ADVANCE_RING();
2281 }
2282
2283 return 0;
2284}
Linux kernel - Deliverables
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