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c05ce083 AD |
1 | /* |
2 | * Copyright 2008-2009 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Dave Airlie <airlied@redhat.com> | |
26 | * Alex Deucher <alexander.deucher@amd.com> | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "radeon_drm.h" | |
32 | #include "radeon_drv.h" | |
33 | ||
70967ab9 BH |
34 | #define PFP_UCODE_SIZE 576 |
35 | #define PM4_UCODE_SIZE 1792 | |
36 | #define R700_PFP_UCODE_SIZE 848 | |
37 | #define R700_PM4_UCODE_SIZE 1360 | |
38 | ||
39 | /* Firmware Names */ | |
40 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
41 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
42 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
43 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
44 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
45 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
46 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
47 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
48 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
49 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
50 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
51 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
52 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
53 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
55 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
56 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); | |
59 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
c05ce083 | 60 | |
3ce0a23d JG |
61 | |
62 | int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, | |
63 | unsigned family, u32 *ib, int *l); | |
64 | void r600_cs_legacy_init(void); | |
65 | ||
66 | ||
c05ce083 AD |
67 | # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
68 | # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) | |
69 | ||
70 | #define R600_PTE_VALID (1 << 0) | |
71 | #define R600_PTE_SYSTEM (1 << 1) | |
72 | #define R600_PTE_SNOOPED (1 << 2) | |
73 | #define R600_PTE_READABLE (1 << 5) | |
74 | #define R600_PTE_WRITEABLE (1 << 6) | |
75 | ||
76 | /* MAX values used for gfx init */ | |
77 | #define R6XX_MAX_SH_GPRS 256 | |
78 | #define R6XX_MAX_TEMP_GPRS 16 | |
79 | #define R6XX_MAX_SH_THREADS 256 | |
80 | #define R6XX_MAX_SH_STACK_ENTRIES 4096 | |
81 | #define R6XX_MAX_BACKENDS 8 | |
82 | #define R6XX_MAX_BACKENDS_MASK 0xff | |
83 | #define R6XX_MAX_SIMDS 8 | |
84 | #define R6XX_MAX_SIMDS_MASK 0xff | |
85 | #define R6XX_MAX_PIPES 8 | |
86 | #define R6XX_MAX_PIPES_MASK 0xff | |
87 | ||
88 | #define R7XX_MAX_SH_GPRS 256 | |
89 | #define R7XX_MAX_TEMP_GPRS 16 | |
90 | #define R7XX_MAX_SH_THREADS 256 | |
91 | #define R7XX_MAX_SH_STACK_ENTRIES 4096 | |
92 | #define R7XX_MAX_BACKENDS 8 | |
93 | #define R7XX_MAX_BACKENDS_MASK 0xff | |
94 | #define R7XX_MAX_SIMDS 16 | |
95 | #define R7XX_MAX_SIMDS_MASK 0xffff | |
96 | #define R7XX_MAX_PIPES 8 | |
97 | #define R7XX_MAX_PIPES_MASK 0xff | |
98 | ||
99 | static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) | |
100 | { | |
101 | int i; | |
102 | ||
103 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
104 | ||
105 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
106 | int slots; | |
107 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) | |
108 | slots = (RADEON_READ(R600_GRBM_STATUS) | |
109 | & R700_CMDFIFO_AVAIL_MASK); | |
110 | else | |
111 | slots = (RADEON_READ(R600_GRBM_STATUS) | |
112 | & R600_CMDFIFO_AVAIL_MASK); | |
113 | if (slots >= entries) | |
114 | return 0; | |
115 | DRM_UDELAY(1); | |
116 | } | |
117 | DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", | |
118 | RADEON_READ(R600_GRBM_STATUS), | |
119 | RADEON_READ(R600_GRBM_STATUS2)); | |
120 | ||
121 | return -EBUSY; | |
122 | } | |
123 | ||
124 | static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) | |
125 | { | |
126 | int i, ret; | |
127 | ||
128 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
129 | ||
130 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) | |
131 | ret = r600_do_wait_for_fifo(dev_priv, 8); | |
132 | else | |
133 | ret = r600_do_wait_for_fifo(dev_priv, 16); | |
134 | if (ret) | |
135 | return ret; | |
136 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
137 | if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) | |
138 | return 0; | |
139 | DRM_UDELAY(1); | |
140 | } | |
141 | DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", | |
142 | RADEON_READ(R600_GRBM_STATUS), | |
143 | RADEON_READ(R600_GRBM_STATUS2)); | |
144 | ||
145 | return -EBUSY; | |
146 | } | |
147 | ||
c1556f71 | 148 | void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
c05ce083 AD |
149 | { |
150 | struct drm_sg_mem *entry = dev->sg; | |
151 | int max_pages; | |
152 | int pages; | |
153 | int i; | |
154 | ||
08932156 AD |
155 | if (!entry) |
156 | return; | |
157 | ||
c05ce083 | 158 | if (gart_info->bus_addr) { |
06f0a488 | 159 | max_pages = (gart_info->table_size / sizeof(u64)); |
c05ce083 AD |
160 | pages = (entry->pages <= max_pages) |
161 | ? entry->pages : max_pages; | |
162 | ||
163 | for (i = 0; i < pages; i++) { | |
164 | if (!entry->busaddr[i]) | |
165 | break; | |
a763d7dc DA |
166 | pci_unmap_page(dev->pdev, entry->busaddr[i], |
167 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
c05ce083 AD |
168 | } |
169 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) | |
170 | gart_info->bus_addr = 0; | |
171 | } | |
172 | } | |
173 | ||
174 | /* R600 has page table setup */ | |
175 | int r600_page_table_init(struct drm_device *dev) | |
176 | { | |
177 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
178 | struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; | |
eb1d9195 | 179 | struct drm_local_map *map = &gart_info->mapping; |
c05ce083 AD |
180 | struct drm_sg_mem *entry = dev->sg; |
181 | int ret = 0; | |
182 | int i, j; | |
eb1d9195 DA |
183 | int pages; |
184 | u64 page_base; | |
c05ce083 | 185 | dma_addr_t entry_addr; |
eb1d9195 | 186 | int max_ati_pages, max_real_pages, gart_idx; |
c05ce083 AD |
187 | |
188 | /* okay page table is available - lets rock */ | |
eb1d9195 DA |
189 | max_ati_pages = (gart_info->table_size / sizeof(u64)); |
190 | max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); | |
c05ce083 | 191 | |
eb1d9195 DA |
192 | pages = (entry->pages <= max_real_pages) ? |
193 | entry->pages : max_real_pages; | |
c05ce083 | 194 | |
eb1d9195 | 195 | memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); |
c05ce083 | 196 | |
eb1d9195 | 197 | gart_idx = 0; |
c05ce083 | 198 | for (i = 0; i < pages; i++) { |
a763d7dc DA |
199 | entry->busaddr[i] = pci_map_page(dev->pdev, |
200 | entry->pagelist[i], 0, | |
201 | PAGE_SIZE, | |
202 | PCI_DMA_BIDIRECTIONAL); | |
c05ce083 AD |
203 | if (entry->busaddr[i] == 0) { |
204 | DRM_ERROR("unable to map PCIGART pages!\n"); | |
205 | r600_page_table_cleanup(dev, gart_info); | |
c05ce083 AD |
206 | goto done; |
207 | } | |
208 | entry_addr = entry->busaddr[i]; | |
209 | for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { | |
210 | page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; | |
211 | page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
212 | page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
213 | ||
eb1d9195 DA |
214 | DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); |
215 | ||
216 | gart_idx++; | |
c05ce083 AD |
217 | |
218 | if ((i % 128) == 0) | |
219 | DRM_DEBUG("page entry %d: 0x%016llx\n", | |
220 | i, (unsigned long long)page_base); | |
c05ce083 AD |
221 | entry_addr += ATI_PCIGART_PAGE_SIZE; |
222 | } | |
223 | } | |
41f13fe8 | 224 | ret = 1; |
c05ce083 AD |
225 | done: |
226 | return ret; | |
227 | } | |
228 | ||
229 | static void r600_vm_flush_gart_range(struct drm_device *dev) | |
230 | { | |
231 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
232 | u32 resp, countdown = 1000; | |
233 | RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); | |
234 | RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
235 | RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); | |
236 | ||
237 | do { | |
238 | resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); | |
239 | countdown--; | |
240 | DRM_UDELAY(1); | |
241 | } while (((resp & 0xf0) == 0) && countdown); | |
242 | } | |
243 | ||
244 | static void r600_vm_init(struct drm_device *dev) | |
245 | { | |
246 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
247 | /* initialise the VM to use the page table we constructed up there */ | |
248 | u32 vm_c0, i; | |
249 | u32 mc_rd_a; | |
250 | u32 vm_l2_cntl, vm_l2_cntl3; | |
251 | /* okay set up the PCIE aperture type thingo */ | |
252 | RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); | |
253 | RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
254 | RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); | |
255 | ||
256 | /* setup MC RD a */ | |
257 | mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | | |
258 | R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | | |
259 | R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; | |
260 | ||
261 | RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); | |
262 | RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); | |
263 | ||
264 | RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); | |
265 | RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); | |
266 | ||
267 | RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); | |
268 | RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); | |
269 | ||
270 | RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); | |
271 | RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); | |
272 | ||
273 | RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); | |
274 | RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); | |
275 | ||
276 | RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); | |
277 | RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); | |
278 | ||
279 | RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); | |
280 | RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); | |
281 | ||
282 | vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; | |
283 | vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); | |
284 | RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); | |
285 | ||
286 | RADEON_WRITE(R600_VM_L2_CNTL2, 0); | |
287 | vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | | |
288 | R600_VM_L2_CNTL3_BANK_SELECT_1(1) | | |
289 | R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); | |
290 | RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); | |
291 | ||
292 | vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; | |
293 | ||
294 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); | |
295 | ||
296 | vm_c0 &= ~R600_VM_ENABLE_CONTEXT; | |
297 | ||
298 | /* disable all other contexts */ | |
299 | for (i = 1; i < 8; i++) | |
300 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); | |
301 | ||
302 | RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); | |
303 | RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); | |
304 | RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
305 | ||
306 | r600_vm_flush_gart_range(dev); | |
307 | } | |
308 | ||
70967ab9 BH |
309 | static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) |
310 | { | |
311 | struct platform_device *pdev; | |
312 | const char *chip_name; | |
313 | size_t pfp_req_size, me_req_size; | |
314 | char fw_name[30]; | |
315 | int err; | |
316 | ||
317 | pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); | |
318 | err = IS_ERR(pdev); | |
319 | if (err) { | |
320 | printk(KERN_ERR "r600_cp: Failed to register firmware\n"); | |
321 | return -EINVAL; | |
322 | } | |
323 | ||
324 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
325 | case CHIP_R600: chip_name = "R600"; break; | |
326 | case CHIP_RV610: chip_name = "RV610"; break; | |
327 | case CHIP_RV630: chip_name = "RV630"; break; | |
328 | case CHIP_RV620: chip_name = "RV620"; break; | |
329 | case CHIP_RV635: chip_name = "RV635"; break; | |
330 | case CHIP_RV670: chip_name = "RV670"; break; | |
331 | case CHIP_RS780: | |
332 | case CHIP_RS880: chip_name = "RS780"; break; | |
333 | case CHIP_RV770: chip_name = "RV770"; break; | |
334 | case CHIP_RV730: | |
335 | case CHIP_RV740: chip_name = "RV730"; break; | |
336 | case CHIP_RV710: chip_name = "RV710"; break; | |
337 | default: BUG(); | |
338 | } | |
339 | ||
340 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { | |
341 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; | |
342 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
343 | } else { | |
344 | pfp_req_size = PFP_UCODE_SIZE * 4; | |
345 | me_req_size = PM4_UCODE_SIZE * 12; | |
346 | } | |
347 | ||
348 | DRM_INFO("Loading %s CP Microcode\n", chip_name); | |
349 | ||
350 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
351 | err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); | |
352 | if (err) | |
353 | goto out; | |
354 | if (dev_priv->pfp_fw->size != pfp_req_size) { | |
355 | printk(KERN_ERR | |
356 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
357 | dev_priv->pfp_fw->size, fw_name); | |
358 | err = -EINVAL; | |
359 | goto out; | |
360 | } | |
361 | ||
362 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
363 | err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); | |
364 | if (err) | |
365 | goto out; | |
366 | if (dev_priv->me_fw->size != me_req_size) { | |
367 | printk(KERN_ERR | |
368 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
369 | dev_priv->me_fw->size, fw_name); | |
370 | err = -EINVAL; | |
371 | } | |
372 | out: | |
373 | platform_device_unregister(pdev); | |
374 | ||
375 | if (err) { | |
376 | if (err != -EINVAL) | |
377 | printk(KERN_ERR | |
378 | "r600_cp: Failed to load firmware \"%s\"\n", | |
379 | fw_name); | |
380 | release_firmware(dev_priv->pfp_fw); | |
381 | dev_priv->pfp_fw = NULL; | |
382 | release_firmware(dev_priv->me_fw); | |
383 | dev_priv->me_fw = NULL; | |
384 | } | |
385 | return err; | |
386 | } | |
387 | ||
c05ce083 AD |
388 | static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) |
389 | { | |
70967ab9 | 390 | const __be32 *fw_data; |
c05ce083 AD |
391 | int i; |
392 | ||
70967ab9 BH |
393 | if (!dev_priv->me_fw || !dev_priv->pfp_fw) |
394 | return; | |
395 | ||
c05ce083 AD |
396 | r600_do_cp_stop(dev_priv); |
397 | ||
398 | RADEON_WRITE(R600_CP_RB_CNTL, | |
399 | R600_RB_NO_UPDATE | | |
400 | R600_RB_BLKSZ(15) | | |
401 | R600_RB_BUFSZ(3)); | |
402 | ||
403 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | |
404 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
405 | DRM_UDELAY(15000); | |
406 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
407 | ||
70967ab9 | 408 | fw_data = (const __be32 *)dev_priv->me_fw->data; |
c05ce083 | 409 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); |
70967ab9 BH |
410 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) |
411 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
412 | be32_to_cpup(fw_data++)); | |
c05ce083 | 413 | |
70967ab9 BH |
414 | fw_data = (const __be32 *)dev_priv->pfp_fw->data; |
415 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
416 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
417 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, | |
418 | be32_to_cpup(fw_data++)); | |
c05ce083 | 419 | |
c05ce083 AD |
420 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); |
421 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
422 | RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); | |
423 | ||
424 | } | |
425 | ||
426 | static void r700_vm_init(struct drm_device *dev) | |
427 | { | |
428 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
429 | /* initialise the VM to use the page table we constructed up there */ | |
430 | u32 vm_c0, i; | |
431 | u32 mc_vm_md_l1; | |
432 | u32 vm_l2_cntl, vm_l2_cntl3; | |
433 | /* okay set up the PCIE aperture type thingo */ | |
434 | RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); | |
435 | RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
436 | RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); | |
437 | ||
438 | mc_vm_md_l1 = R700_ENABLE_L1_TLB | | |
439 | R700_ENABLE_L1_FRAGMENT_PROCESSING | | |
440 | R700_SYSTEM_ACCESS_MODE_IN_SYS | | |
441 | R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
442 | R700_EFFECTIVE_L1_TLB_SIZE(5) | | |
443 | R700_EFFECTIVE_L1_QUEUE_SIZE(5); | |
444 | ||
445 | RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); | |
446 | RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); | |
447 | RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); | |
448 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); | |
449 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); | |
450 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); | |
451 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); | |
452 | ||
453 | vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; | |
454 | vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); | |
455 | RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); | |
456 | ||
457 | RADEON_WRITE(R600_VM_L2_CNTL2, 0); | |
458 | vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); | |
459 | RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); | |
460 | ||
461 | vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; | |
462 | ||
463 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); | |
464 | ||
465 | vm_c0 &= ~R600_VM_ENABLE_CONTEXT; | |
466 | ||
467 | /* disable all other contexts */ | |
468 | for (i = 1; i < 8; i++) | |
469 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); | |
470 | ||
471 | RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); | |
472 | RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); | |
473 | RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
474 | ||
475 | r600_vm_flush_gart_range(dev); | |
476 | } | |
477 | ||
c05ce083 AD |
478 | static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) |
479 | { | |
70967ab9 | 480 | const __be32 *fw_data; |
c05ce083 AD |
481 | int i; |
482 | ||
70967ab9 BH |
483 | if (!dev_priv->me_fw || !dev_priv->pfp_fw) |
484 | return; | |
485 | ||
c05ce083 AD |
486 | r600_do_cp_stop(dev_priv); |
487 | ||
488 | RADEON_WRITE(R600_CP_RB_CNTL, | |
489 | R600_RB_NO_UPDATE | | |
490 | (15 << 8) | | |
491 | (3 << 0)); | |
492 | ||
493 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | |
494 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
495 | DRM_UDELAY(15000); | |
496 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
497 | ||
70967ab9 BH |
498 | fw_data = (const __be32 *)dev_priv->pfp_fw->data; |
499 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
500 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) | |
501 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | |
502 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
c05ce083 | 503 | |
70967ab9 BH |
504 | fw_data = (const __be32 *)dev_priv->me_fw->data; |
505 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
506 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) | |
507 | RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | |
508 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
c05ce083 | 509 | |
c05ce083 AD |
510 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); |
511 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
512 | RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); | |
513 | ||
514 | } | |
515 | ||
516 | static void r600_test_writeback(drm_radeon_private_t *dev_priv) | |
517 | { | |
518 | u32 tmp; | |
519 | ||
520 | /* Start with assuming that writeback doesn't work */ | |
521 | dev_priv->writeback_works = 0; | |
522 | ||
523 | /* Writeback doesn't seem to work everywhere, test it here and possibly | |
524 | * enable it if it appears to work | |
525 | */ | |
526 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); | |
527 | ||
528 | RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); | |
529 | ||
530 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
531 | u32 val; | |
532 | ||
533 | val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); | |
534 | if (val == 0xdeadbeef) | |
535 | break; | |
536 | DRM_UDELAY(1); | |
537 | } | |
538 | ||
539 | if (tmp < dev_priv->usec_timeout) { | |
540 | dev_priv->writeback_works = 1; | |
541 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
542 | } else { | |
543 | dev_priv->writeback_works = 0; | |
544 | DRM_INFO("writeback test failed\n"); | |
545 | } | |
546 | if (radeon_no_wb == 1) { | |
547 | dev_priv->writeback_works = 0; | |
548 | DRM_INFO("writeback forced off\n"); | |
549 | } | |
550 | ||
551 | if (!dev_priv->writeback_works) { | |
552 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
553 | RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | | |
554 | RADEON_RB_NO_UPDATE); | |
555 | RADEON_WRITE(R600_SCRATCH_UMSK, 0); | |
556 | } | |
557 | } | |
558 | ||
559 | int r600_do_engine_reset(struct drm_device *dev) | |
560 | { | |
561 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
562 | u32 cp_ptr, cp_me_cntl, cp_rb_cntl; | |
563 | ||
564 | DRM_INFO("Resetting GPU\n"); | |
565 | ||
566 | cp_ptr = RADEON_READ(R600_CP_RB_WPTR); | |
567 | cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); | |
568 | RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); | |
569 | ||
570 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); | |
571 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
572 | DRM_UDELAY(50); | |
573 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
574 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
575 | ||
576 | RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); | |
577 | cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); | |
578 | RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); | |
579 | ||
580 | RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); | |
581 | RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); | |
582 | RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); | |
583 | RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); | |
584 | ||
585 | /* Reset the CP ring */ | |
586 | r600_do_cp_reset(dev_priv); | |
587 | ||
588 | /* The CP is no longer running after an engine reset */ | |
589 | dev_priv->cp_running = 0; | |
590 | ||
591 | /* Reset any pending vertex, indirect buffers */ | |
592 | radeon_freelist_reset(dev); | |
593 | ||
594 | return 0; | |
595 | ||
596 | } | |
597 | ||
598 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
599 | u32 num_backends, | |
600 | u32 backend_disable_mask) | |
601 | { | |
602 | u32 backend_map = 0; | |
603 | u32 enabled_backends_mask; | |
604 | u32 enabled_backends_count; | |
605 | u32 cur_pipe; | |
606 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
607 | u32 cur_backend; | |
608 | u32 i; | |
609 | ||
610 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
611 | num_tile_pipes = R6XX_MAX_PIPES; | |
612 | if (num_tile_pipes < 1) | |
613 | num_tile_pipes = 1; | |
614 | if (num_backends > R6XX_MAX_BACKENDS) | |
615 | num_backends = R6XX_MAX_BACKENDS; | |
616 | if (num_backends < 1) | |
617 | num_backends = 1; | |
618 | ||
619 | enabled_backends_mask = 0; | |
620 | enabled_backends_count = 0; | |
621 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
622 | if (((backend_disable_mask >> i) & 1) == 0) { | |
623 | enabled_backends_mask |= (1 << i); | |
624 | ++enabled_backends_count; | |
625 | } | |
626 | if (enabled_backends_count == num_backends) | |
627 | break; | |
628 | } | |
629 | ||
630 | if (enabled_backends_count == 0) { | |
631 | enabled_backends_mask = 1; | |
632 | enabled_backends_count = 1; | |
633 | } | |
634 | ||
635 | if (enabled_backends_count != num_backends) | |
636 | num_backends = enabled_backends_count; | |
637 | ||
638 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
639 | switch (num_tile_pipes) { | |
640 | case 1: | |
641 | swizzle_pipe[0] = 0; | |
642 | break; | |
643 | case 2: | |
644 | swizzle_pipe[0] = 0; | |
645 | swizzle_pipe[1] = 1; | |
646 | break; | |
647 | case 3: | |
648 | swizzle_pipe[0] = 0; | |
649 | swizzle_pipe[1] = 1; | |
650 | swizzle_pipe[2] = 2; | |
651 | break; | |
652 | case 4: | |
653 | swizzle_pipe[0] = 0; | |
654 | swizzle_pipe[1] = 1; | |
655 | swizzle_pipe[2] = 2; | |
656 | swizzle_pipe[3] = 3; | |
657 | break; | |
658 | case 5: | |
659 | swizzle_pipe[0] = 0; | |
660 | swizzle_pipe[1] = 1; | |
661 | swizzle_pipe[2] = 2; | |
662 | swizzle_pipe[3] = 3; | |
663 | swizzle_pipe[4] = 4; | |
664 | break; | |
665 | case 6: | |
666 | swizzle_pipe[0] = 0; | |
667 | swizzle_pipe[1] = 2; | |
668 | swizzle_pipe[2] = 4; | |
669 | swizzle_pipe[3] = 5; | |
670 | swizzle_pipe[4] = 1; | |
671 | swizzle_pipe[5] = 3; | |
672 | break; | |
673 | case 7: | |
674 | swizzle_pipe[0] = 0; | |
675 | swizzle_pipe[1] = 2; | |
676 | swizzle_pipe[2] = 4; | |
677 | swizzle_pipe[3] = 6; | |
678 | swizzle_pipe[4] = 1; | |
679 | swizzle_pipe[5] = 3; | |
680 | swizzle_pipe[6] = 5; | |
681 | break; | |
682 | case 8: | |
683 | swizzle_pipe[0] = 0; | |
684 | swizzle_pipe[1] = 2; | |
685 | swizzle_pipe[2] = 4; | |
686 | swizzle_pipe[3] = 6; | |
687 | swizzle_pipe[4] = 1; | |
688 | swizzle_pipe[5] = 3; | |
689 | swizzle_pipe[6] = 5; | |
690 | swizzle_pipe[7] = 7; | |
691 | break; | |
692 | } | |
693 | ||
694 | cur_backend = 0; | |
695 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
696 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
697 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
698 | ||
699 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
700 | ||
701 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
702 | } | |
703 | ||
704 | return backend_map; | |
705 | } | |
706 | ||
707 | static int r600_count_pipe_bits(uint32_t val) | |
708 | { | |
709 | int i, ret = 0; | |
710 | for (i = 0; i < 32; i++) { | |
711 | ret += val & 1; | |
712 | val >>= 1; | |
713 | } | |
714 | return ret; | |
715 | } | |
716 | ||
717 | static void r600_gfx_init(struct drm_device *dev, | |
718 | drm_radeon_private_t *dev_priv) | |
719 | { | |
720 | int i, j, num_qd_pipes; | |
721 | u32 sx_debug_1; | |
722 | u32 tc_cntl; | |
723 | u32 arb_pop; | |
724 | u32 num_gs_verts_per_thread; | |
725 | u32 vgt_gs_per_es; | |
726 | u32 gs_prim_buffer_depth = 0; | |
727 | u32 sq_ms_fifo_sizes; | |
728 | u32 sq_config; | |
729 | u32 sq_gpr_resource_mgmt_1 = 0; | |
730 | u32 sq_gpr_resource_mgmt_2 = 0; | |
731 | u32 sq_thread_resource_mgmt = 0; | |
732 | u32 sq_stack_resource_mgmt_1 = 0; | |
733 | u32 sq_stack_resource_mgmt_2 = 0; | |
734 | u32 hdp_host_path_cntl; | |
735 | u32 backend_map; | |
736 | u32 gb_tiling_config = 0; | |
d03f5d59 AD |
737 | u32 cc_rb_backend_disable; |
738 | u32 cc_gc_shader_pipe_config; | |
c05ce083 AD |
739 | u32 ramcfg; |
740 | ||
741 | /* setup chip specs */ | |
742 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
743 | case CHIP_R600: | |
744 | dev_priv->r600_max_pipes = 4; | |
745 | dev_priv->r600_max_tile_pipes = 8; | |
746 | dev_priv->r600_max_simds = 4; | |
747 | dev_priv->r600_max_backends = 4; | |
748 | dev_priv->r600_max_gprs = 256; | |
749 | dev_priv->r600_max_threads = 192; | |
750 | dev_priv->r600_max_stack_entries = 256; | |
751 | dev_priv->r600_max_hw_contexts = 8; | |
752 | dev_priv->r600_max_gs_threads = 16; | |
753 | dev_priv->r600_sx_max_export_size = 128; | |
754 | dev_priv->r600_sx_max_export_pos_size = 16; | |
755 | dev_priv->r600_sx_max_export_smx_size = 128; | |
756 | dev_priv->r600_sq_num_cf_insts = 2; | |
757 | break; | |
758 | case CHIP_RV630: | |
759 | case CHIP_RV635: | |
760 | dev_priv->r600_max_pipes = 2; | |
761 | dev_priv->r600_max_tile_pipes = 2; | |
762 | dev_priv->r600_max_simds = 3; | |
763 | dev_priv->r600_max_backends = 1; | |
764 | dev_priv->r600_max_gprs = 128; | |
765 | dev_priv->r600_max_threads = 192; | |
766 | dev_priv->r600_max_stack_entries = 128; | |
767 | dev_priv->r600_max_hw_contexts = 8; | |
768 | dev_priv->r600_max_gs_threads = 4; | |
769 | dev_priv->r600_sx_max_export_size = 128; | |
770 | dev_priv->r600_sx_max_export_pos_size = 16; | |
771 | dev_priv->r600_sx_max_export_smx_size = 128; | |
772 | dev_priv->r600_sq_num_cf_insts = 2; | |
773 | break; | |
774 | case CHIP_RV610: | |
775 | case CHIP_RS780: | |
6502fbfa | 776 | case CHIP_RS880: |
c05ce083 AD |
777 | case CHIP_RV620: |
778 | dev_priv->r600_max_pipes = 1; | |
779 | dev_priv->r600_max_tile_pipes = 1; | |
780 | dev_priv->r600_max_simds = 2; | |
781 | dev_priv->r600_max_backends = 1; | |
782 | dev_priv->r600_max_gprs = 128; | |
783 | dev_priv->r600_max_threads = 192; | |
784 | dev_priv->r600_max_stack_entries = 128; | |
785 | dev_priv->r600_max_hw_contexts = 4; | |
786 | dev_priv->r600_max_gs_threads = 4; | |
787 | dev_priv->r600_sx_max_export_size = 128; | |
788 | dev_priv->r600_sx_max_export_pos_size = 16; | |
789 | dev_priv->r600_sx_max_export_smx_size = 128; | |
790 | dev_priv->r600_sq_num_cf_insts = 1; | |
791 | break; | |
792 | case CHIP_RV670: | |
793 | dev_priv->r600_max_pipes = 4; | |
794 | dev_priv->r600_max_tile_pipes = 4; | |
795 | dev_priv->r600_max_simds = 4; | |
796 | dev_priv->r600_max_backends = 4; | |
797 | dev_priv->r600_max_gprs = 192; | |
798 | dev_priv->r600_max_threads = 192; | |
799 | dev_priv->r600_max_stack_entries = 256; | |
800 | dev_priv->r600_max_hw_contexts = 8; | |
801 | dev_priv->r600_max_gs_threads = 16; | |
802 | dev_priv->r600_sx_max_export_size = 128; | |
803 | dev_priv->r600_sx_max_export_pos_size = 16; | |
804 | dev_priv->r600_sx_max_export_smx_size = 128; | |
805 | dev_priv->r600_sq_num_cf_insts = 2; | |
806 | break; | |
807 | default: | |
808 | break; | |
809 | } | |
810 | ||
811 | /* Initialize HDP */ | |
812 | j = 0; | |
813 | for (i = 0; i < 32; i++) { | |
814 | RADEON_WRITE((0x2c14 + j), 0x00000000); | |
815 | RADEON_WRITE((0x2c18 + j), 0x00000000); | |
816 | RADEON_WRITE((0x2c1c + j), 0x00000000); | |
817 | RADEON_WRITE((0x2c20 + j), 0x00000000); | |
818 | RADEON_WRITE((0x2c24 + j), 0x00000000); | |
819 | j += 0x18; | |
820 | } | |
821 | ||
822 | RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); | |
823 | ||
824 | /* setup tiling, simd, pipe config */ | |
825 | ramcfg = RADEON_READ(R600_RAMCFG); | |
826 | ||
827 | switch (dev_priv->r600_max_tile_pipes) { | |
828 | case 1: | |
829 | gb_tiling_config |= R600_PIPE_TILING(0); | |
830 | break; | |
831 | case 2: | |
832 | gb_tiling_config |= R600_PIPE_TILING(1); | |
833 | break; | |
834 | case 4: | |
835 | gb_tiling_config |= R600_PIPE_TILING(2); | |
836 | break; | |
837 | case 8: | |
838 | gb_tiling_config |= R600_PIPE_TILING(3); | |
839 | break; | |
840 | default: | |
841 | break; | |
842 | } | |
843 | ||
844 | gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); | |
845 | ||
846 | gb_tiling_config |= R600_GROUP_SIZE(0); | |
847 | ||
848 | if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { | |
849 | gb_tiling_config |= R600_ROW_TILING(3); | |
850 | gb_tiling_config |= R600_SAMPLE_SPLIT(3); | |
851 | } else { | |
852 | gb_tiling_config |= | |
853 | R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); | |
854 | gb_tiling_config |= | |
855 | R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); | |
856 | } | |
857 | ||
858 | gb_tiling_config |= R600_BANK_SWAPS(1); | |
859 | ||
d03f5d59 AD |
860 | cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
861 | cc_rb_backend_disable |= | |
862 | R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); | |
c05ce083 | 863 | |
d03f5d59 AD |
864 | cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
865 | cc_gc_shader_pipe_config |= | |
c05ce083 AD |
866 | R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); |
867 | cc_gc_shader_pipe_config |= | |
868 | R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); | |
869 | ||
d03f5d59 AD |
870 | backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, |
871 | (R6XX_MAX_BACKENDS - | |
872 | r600_count_pipe_bits((cc_rb_backend_disable & | |
873 | R6XX_MAX_BACKENDS_MASK) >> 16)), | |
874 | (cc_rb_backend_disable >> 16)); | |
875 | gb_tiling_config |= R600_BACKEND_MAP(backend_map); | |
c05ce083 AD |
876 | |
877 | RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); | |
878 | RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
879 | RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
961fb597 JG |
880 | if (gb_tiling_config & 0xc0) { |
881 | dev_priv->r600_group_size = 512; | |
882 | } else { | |
883 | dev_priv->r600_group_size = 256; | |
884 | } | |
885 | dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); | |
886 | if (gb_tiling_config & 0x30) { | |
887 | dev_priv->r600_nbanks = 8; | |
888 | } else { | |
889 | dev_priv->r600_nbanks = 4; | |
890 | } | |
c05ce083 AD |
891 | |
892 | RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
893 | RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
894 | RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
895 | ||
896 | num_qd_pipes = | |
d03f5d59 | 897 | R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); |
c05ce083 AD |
898 | RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); |
899 | RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); | |
900 | ||
901 | /* set HW defaults for 3D engine */ | |
902 | RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | | |
903 | R600_ROQ_IB2_START(0x2b))); | |
904 | ||
905 | RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | | |
906 | R600_ROQ_END(0x40))); | |
907 | ||
908 | RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | | |
909 | R600_SYNC_GRADIENT | | |
910 | R600_SYNC_WALKER | | |
911 | R600_SYNC_ALIGNER)); | |
912 | ||
913 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) | |
914 | RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); | |
915 | ||
916 | sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); | |
917 | sx_debug_1 |= R600_SMX_EVENT_RELEASE; | |
918 | if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) | |
919 | sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; | |
920 | RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); | |
921 | ||
922 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || | |
923 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || | |
924 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
925 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
6502fbfa AD |
926 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || |
927 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) | |
c05ce083 AD |
928 | RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
929 | else | |
930 | RADEON_WRITE(R600_DB_DEBUG, 0); | |
931 | ||
932 | RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | | |
933 | R600_DEPTH_FLUSH(16) | | |
934 | R600_DEPTH_PENDING_FREE(4) | | |
935 | R600_DEPTH_CACHELINE_FREE(16))); | |
936 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
937 | RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); | |
938 | ||
939 | RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); | |
940 | RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); | |
941 | ||
942 | sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); | |
943 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
944 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
6502fbfa AD |
945 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || |
946 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { | |
c05ce083 AD |
947 | sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | |
948 | R600_FETCH_FIFO_HIWATER(0xa) | | |
949 | R600_DONE_FIFO_HIWATER(0xe0) | | |
950 | R600_ALU_UPDATE_FIFO_HIWATER(0x8)); | |
951 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || | |
952 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { | |
953 | sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); | |
954 | sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); | |
955 | } | |
956 | RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); | |
957 | ||
958 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
959 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
960 | */ | |
961 | sq_config = RADEON_READ(R600_SQ_CONFIG); | |
962 | sq_config &= ~(R600_PS_PRIO(3) | | |
963 | R600_VS_PRIO(3) | | |
964 | R600_GS_PRIO(3) | | |
965 | R600_ES_PRIO(3)); | |
966 | sq_config |= (R600_DX9_CONSTS | | |
967 | R600_VC_ENABLE | | |
968 | R600_PS_PRIO(0) | | |
969 | R600_VS_PRIO(1) | | |
970 | R600_GS_PRIO(2) | | |
971 | R600_ES_PRIO(3)); | |
972 | ||
973 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { | |
974 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | | |
975 | R600_NUM_VS_GPRS(124) | | |
976 | R600_NUM_CLAUSE_TEMP_GPRS(4)); | |
977 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | | |
978 | R600_NUM_ES_GPRS(0)); | |
979 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | | |
980 | R600_NUM_VS_THREADS(48) | | |
981 | R600_NUM_GS_THREADS(4) | | |
982 | R600_NUM_ES_THREADS(4)); | |
983 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | | |
984 | R600_NUM_VS_STACK_ENTRIES(128)); | |
985 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | | |
986 | R600_NUM_ES_STACK_ENTRIES(0)); | |
987 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
988 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
6502fbfa AD |
989 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || |
990 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { | |
c05ce083 AD |
991 | /* no vertex cache */ |
992 | sq_config &= ~R600_VC_ENABLE; | |
993 | ||
994 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | | |
995 | R600_NUM_VS_GPRS(44) | | |
996 | R600_NUM_CLAUSE_TEMP_GPRS(2)); | |
997 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | | |
998 | R600_NUM_ES_GPRS(17)); | |
999 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | | |
1000 | R600_NUM_VS_THREADS(78) | | |
1001 | R600_NUM_GS_THREADS(4) | | |
1002 | R600_NUM_ES_THREADS(31)); | |
1003 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | | |
1004 | R600_NUM_VS_STACK_ENTRIES(40)); | |
1005 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | | |
1006 | R600_NUM_ES_STACK_ENTRIES(16)); | |
1007 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || | |
1008 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { | |
1009 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | | |
1010 | R600_NUM_VS_GPRS(44) | | |
1011 | R600_NUM_CLAUSE_TEMP_GPRS(2)); | |
1012 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | | |
1013 | R600_NUM_ES_GPRS(18)); | |
1014 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | | |
1015 | R600_NUM_VS_THREADS(78) | | |
1016 | R600_NUM_GS_THREADS(4) | | |
1017 | R600_NUM_ES_THREADS(31)); | |
1018 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | | |
1019 | R600_NUM_VS_STACK_ENTRIES(40)); | |
1020 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | | |
1021 | R600_NUM_ES_STACK_ENTRIES(16)); | |
1022 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { | |
1023 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | | |
1024 | R600_NUM_VS_GPRS(44) | | |
1025 | R600_NUM_CLAUSE_TEMP_GPRS(2)); | |
1026 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | | |
1027 | R600_NUM_ES_GPRS(17)); | |
1028 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | | |
1029 | R600_NUM_VS_THREADS(78) | | |
1030 | R600_NUM_GS_THREADS(4) | | |
1031 | R600_NUM_ES_THREADS(31)); | |
1032 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | | |
1033 | R600_NUM_VS_STACK_ENTRIES(64)); | |
1034 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | | |
1035 | R600_NUM_ES_STACK_ENTRIES(64)); | |
1036 | } | |
1037 | ||
1038 | RADEON_WRITE(R600_SQ_CONFIG, sq_config); | |
1039 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1040 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1041 | RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1042 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1043 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1044 | ||
1045 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
1046 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
6502fbfa AD |
1047 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || |
1048 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) | |
c05ce083 AD |
1049 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); |
1050 | else | |
1051 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); | |
1052 | ||
1053 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | | |
1054 | R600_S0_Y(0x4) | | |
1055 | R600_S1_X(0x4) | | |
1056 | R600_S1_Y(0xc))); | |
1057 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | | |
1058 | R600_S0_Y(0xe) | | |
1059 | R600_S1_X(0x2) | | |
1060 | R600_S1_Y(0x2) | | |
1061 | R600_S2_X(0xa) | | |
1062 | R600_S2_Y(0x6) | | |
1063 | R600_S3_X(0x6) | | |
1064 | R600_S3_Y(0xa))); | |
1065 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | | |
1066 | R600_S0_Y(0xb) | | |
1067 | R600_S1_X(0x4) | | |
1068 | R600_S1_Y(0xc) | | |
1069 | R600_S2_X(0x1) | | |
1070 | R600_S2_Y(0x6) | | |
1071 | R600_S3_X(0xa) | | |
1072 | R600_S3_Y(0xe))); | |
1073 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | | |
1074 | R600_S4_Y(0x1) | | |
1075 | R600_S5_X(0x0) | | |
1076 | R600_S5_Y(0x0) | | |
1077 | R600_S6_X(0xb) | | |
1078 | R600_S6_Y(0x4) | | |
1079 | R600_S7_X(0x7) | | |
1080 | R600_S7_Y(0x8))); | |
1081 | ||
1082 | ||
1083 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1084 | case CHIP_R600: | |
1085 | case CHIP_RV630: | |
1086 | case CHIP_RV635: | |
1087 | gs_prim_buffer_depth = 0; | |
1088 | break; | |
1089 | case CHIP_RV610: | |
1090 | case CHIP_RS780: | |
6502fbfa | 1091 | case CHIP_RS880: |
c05ce083 AD |
1092 | case CHIP_RV620: |
1093 | gs_prim_buffer_depth = 32; | |
1094 | break; | |
1095 | case CHIP_RV670: | |
1096 | gs_prim_buffer_depth = 128; | |
1097 | break; | |
1098 | default: | |
1099 | break; | |
1100 | } | |
1101 | ||
1102 | num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; | |
1103 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; | |
1104 | /* Max value for this is 256 */ | |
1105 | if (vgt_gs_per_es > 256) | |
1106 | vgt_gs_per_es = 256; | |
1107 | ||
1108 | RADEON_WRITE(R600_VGT_ES_PER_GS, 128); | |
1109 | RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); | |
1110 | RADEON_WRITE(R600_VGT_GS_PER_VS, 2); | |
1111 | RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); | |
1112 | ||
1113 | /* more default values. 2D/3D driver should adjust as needed */ | |
1114 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); | |
1115 | RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); | |
1116 | RADEON_WRITE(R600_SX_MISC, 0); | |
1117 | RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); | |
1118 | RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); | |
1119 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); | |
1120 | RADEON_WRITE(R600_SPI_INPUT_Z, 0); | |
1121 | RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); | |
1122 | RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); | |
1123 | ||
1124 | /* clear render buffer base addresses */ | |
1125 | RADEON_WRITE(R600_CB_COLOR0_BASE, 0); | |
1126 | RADEON_WRITE(R600_CB_COLOR1_BASE, 0); | |
1127 | RADEON_WRITE(R600_CB_COLOR2_BASE, 0); | |
1128 | RADEON_WRITE(R600_CB_COLOR3_BASE, 0); | |
1129 | RADEON_WRITE(R600_CB_COLOR4_BASE, 0); | |
1130 | RADEON_WRITE(R600_CB_COLOR5_BASE, 0); | |
1131 | RADEON_WRITE(R600_CB_COLOR6_BASE, 0); | |
1132 | RADEON_WRITE(R600_CB_COLOR7_BASE, 0); | |
1133 | ||
1134 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1135 | case CHIP_RV610: | |
1136 | case CHIP_RS780: | |
6502fbfa | 1137 | case CHIP_RS880: |
c05ce083 AD |
1138 | case CHIP_RV620: |
1139 | tc_cntl = R600_TC_L2_SIZE(8); | |
1140 | break; | |
1141 | case CHIP_RV630: | |
1142 | case CHIP_RV635: | |
1143 | tc_cntl = R600_TC_L2_SIZE(4); | |
1144 | break; | |
1145 | case CHIP_R600: | |
1146 | tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; | |
1147 | break; | |
1148 | default: | |
1149 | tc_cntl = R600_TC_L2_SIZE(0); | |
1150 | break; | |
1151 | } | |
1152 | ||
1153 | RADEON_WRITE(R600_TC_CNTL, tc_cntl); | |
1154 | ||
1155 | hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); | |
1156 | RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
1157 | ||
1158 | arb_pop = RADEON_READ(R600_ARB_POP); | |
1159 | arb_pop |= R600_ENABLE_TC128; | |
1160 | RADEON_WRITE(R600_ARB_POP, arb_pop); | |
1161 | ||
1162 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
1163 | RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | | |
1164 | R600_NUM_CLIP_SEQ(3))); | |
1165 | RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); | |
1166 | ||
1167 | } | |
1168 | ||
d03f5d59 AD |
1169 | static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, |
1170 | u32 num_tile_pipes, | |
c05ce083 AD |
1171 | u32 num_backends, |
1172 | u32 backend_disable_mask) | |
1173 | { | |
1174 | u32 backend_map = 0; | |
1175 | u32 enabled_backends_mask; | |
1176 | u32 enabled_backends_count; | |
1177 | u32 cur_pipe; | |
1178 | u32 swizzle_pipe[R7XX_MAX_PIPES]; | |
1179 | u32 cur_backend; | |
1180 | u32 i; | |
d03f5d59 | 1181 | bool force_no_swizzle; |
c05ce083 AD |
1182 | |
1183 | if (num_tile_pipes > R7XX_MAX_PIPES) | |
1184 | num_tile_pipes = R7XX_MAX_PIPES; | |
1185 | if (num_tile_pipes < 1) | |
1186 | num_tile_pipes = 1; | |
1187 | if (num_backends > R7XX_MAX_BACKENDS) | |
1188 | num_backends = R7XX_MAX_BACKENDS; | |
1189 | if (num_backends < 1) | |
1190 | num_backends = 1; | |
1191 | ||
1192 | enabled_backends_mask = 0; | |
1193 | enabled_backends_count = 0; | |
1194 | for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { | |
1195 | if (((backend_disable_mask >> i) & 1) == 0) { | |
1196 | enabled_backends_mask |= (1 << i); | |
1197 | ++enabled_backends_count; | |
1198 | } | |
1199 | if (enabled_backends_count == num_backends) | |
1200 | break; | |
1201 | } | |
1202 | ||
1203 | if (enabled_backends_count == 0) { | |
1204 | enabled_backends_mask = 1; | |
1205 | enabled_backends_count = 1; | |
1206 | } | |
1207 | ||
1208 | if (enabled_backends_count != num_backends) | |
1209 | num_backends = enabled_backends_count; | |
1210 | ||
d03f5d59 AD |
1211 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { |
1212 | case CHIP_RV770: | |
1213 | case CHIP_RV730: | |
1214 | force_no_swizzle = false; | |
1215 | break; | |
1216 | case CHIP_RV710: | |
1217 | case CHIP_RV740: | |
1218 | default: | |
1219 | force_no_swizzle = true; | |
1220 | break; | |
1221 | } | |
1222 | ||
c05ce083 AD |
1223 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); |
1224 | switch (num_tile_pipes) { | |
1225 | case 1: | |
1226 | swizzle_pipe[0] = 0; | |
1227 | break; | |
1228 | case 2: | |
1229 | swizzle_pipe[0] = 0; | |
1230 | swizzle_pipe[1] = 1; | |
1231 | break; | |
1232 | case 3: | |
d03f5d59 AD |
1233 | if (force_no_swizzle) { |
1234 | swizzle_pipe[0] = 0; | |
1235 | swizzle_pipe[1] = 1; | |
1236 | swizzle_pipe[2] = 2; | |
1237 | } else { | |
1238 | swizzle_pipe[0] = 0; | |
1239 | swizzle_pipe[1] = 2; | |
1240 | swizzle_pipe[2] = 1; | |
1241 | } | |
c05ce083 AD |
1242 | break; |
1243 | case 4: | |
d03f5d59 AD |
1244 | if (force_no_swizzle) { |
1245 | swizzle_pipe[0] = 0; | |
1246 | swizzle_pipe[1] = 1; | |
1247 | swizzle_pipe[2] = 2; | |
1248 | swizzle_pipe[3] = 3; | |
1249 | } else { | |
1250 | swizzle_pipe[0] = 0; | |
1251 | swizzle_pipe[1] = 2; | |
1252 | swizzle_pipe[2] = 3; | |
1253 | swizzle_pipe[3] = 1; | |
1254 | } | |
c05ce083 AD |
1255 | break; |
1256 | case 5: | |
d03f5d59 AD |
1257 | if (force_no_swizzle) { |
1258 | swizzle_pipe[0] = 0; | |
1259 | swizzle_pipe[1] = 1; | |
1260 | swizzle_pipe[2] = 2; | |
1261 | swizzle_pipe[3] = 3; | |
1262 | swizzle_pipe[4] = 4; | |
1263 | } else { | |
1264 | swizzle_pipe[0] = 0; | |
1265 | swizzle_pipe[1] = 2; | |
1266 | swizzle_pipe[2] = 4; | |
1267 | swizzle_pipe[3] = 1; | |
1268 | swizzle_pipe[4] = 3; | |
1269 | } | |
c05ce083 AD |
1270 | break; |
1271 | case 6: | |
d03f5d59 AD |
1272 | if (force_no_swizzle) { |
1273 | swizzle_pipe[0] = 0; | |
1274 | swizzle_pipe[1] = 1; | |
1275 | swizzle_pipe[2] = 2; | |
1276 | swizzle_pipe[3] = 3; | |
1277 | swizzle_pipe[4] = 4; | |
1278 | swizzle_pipe[5] = 5; | |
1279 | } else { | |
1280 | swizzle_pipe[0] = 0; | |
1281 | swizzle_pipe[1] = 2; | |
1282 | swizzle_pipe[2] = 4; | |
1283 | swizzle_pipe[3] = 5; | |
1284 | swizzle_pipe[4] = 3; | |
1285 | swizzle_pipe[5] = 1; | |
1286 | } | |
c05ce083 AD |
1287 | break; |
1288 | case 7: | |
d03f5d59 AD |
1289 | if (force_no_swizzle) { |
1290 | swizzle_pipe[0] = 0; | |
1291 | swizzle_pipe[1] = 1; | |
1292 | swizzle_pipe[2] = 2; | |
1293 | swizzle_pipe[3] = 3; | |
1294 | swizzle_pipe[4] = 4; | |
1295 | swizzle_pipe[5] = 5; | |
1296 | swizzle_pipe[6] = 6; | |
1297 | } else { | |
1298 | swizzle_pipe[0] = 0; | |
1299 | swizzle_pipe[1] = 2; | |
1300 | swizzle_pipe[2] = 4; | |
1301 | swizzle_pipe[3] = 6; | |
1302 | swizzle_pipe[4] = 3; | |
1303 | swizzle_pipe[5] = 1; | |
1304 | swizzle_pipe[6] = 5; | |
1305 | } | |
c05ce083 AD |
1306 | break; |
1307 | case 8: | |
d03f5d59 AD |
1308 | if (force_no_swizzle) { |
1309 | swizzle_pipe[0] = 0; | |
1310 | swizzle_pipe[1] = 1; | |
1311 | swizzle_pipe[2] = 2; | |
1312 | swizzle_pipe[3] = 3; | |
1313 | swizzle_pipe[4] = 4; | |
1314 | swizzle_pipe[5] = 5; | |
1315 | swizzle_pipe[6] = 6; | |
1316 | swizzle_pipe[7] = 7; | |
1317 | } else { | |
1318 | swizzle_pipe[0] = 0; | |
1319 | swizzle_pipe[1] = 2; | |
1320 | swizzle_pipe[2] = 4; | |
1321 | swizzle_pipe[3] = 6; | |
1322 | swizzle_pipe[4] = 3; | |
1323 | swizzle_pipe[5] = 1; | |
1324 | swizzle_pipe[6] = 7; | |
1325 | swizzle_pipe[7] = 5; | |
1326 | } | |
c05ce083 AD |
1327 | break; |
1328 | } | |
1329 | ||
1330 | cur_backend = 0; | |
1331 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
1332 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
1333 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; | |
1334 | ||
1335 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
1336 | ||
1337 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; | |
1338 | } | |
1339 | ||
1340 | return backend_map; | |
1341 | } | |
1342 | ||
1343 | static void r700_gfx_init(struct drm_device *dev, | |
1344 | drm_radeon_private_t *dev_priv) | |
1345 | { | |
1346 | int i, j, num_qd_pipes; | |
d03f5d59 | 1347 | u32 ta_aux_cntl; |
c05ce083 AD |
1348 | u32 sx_debug_1; |
1349 | u32 smx_dc_ctl0; | |
d03f5d59 | 1350 | u32 db_debug3; |
c05ce083 AD |
1351 | u32 num_gs_verts_per_thread; |
1352 | u32 vgt_gs_per_es; | |
1353 | u32 gs_prim_buffer_depth = 0; | |
1354 | u32 sq_ms_fifo_sizes; | |
1355 | u32 sq_config; | |
1356 | u32 sq_thread_resource_mgmt; | |
1357 | u32 hdp_host_path_cntl; | |
1358 | u32 sq_dyn_gpr_size_simd_ab_0; | |
1359 | u32 backend_map; | |
1360 | u32 gb_tiling_config = 0; | |
d03f5d59 AD |
1361 | u32 cc_rb_backend_disable; |
1362 | u32 cc_gc_shader_pipe_config; | |
c05ce083 AD |
1363 | u32 mc_arb_ramcfg; |
1364 | u32 db_debug4; | |
1365 | ||
1366 | /* setup chip specs */ | |
1367 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1368 | case CHIP_RV770: | |
1369 | dev_priv->r600_max_pipes = 4; | |
1370 | dev_priv->r600_max_tile_pipes = 8; | |
1371 | dev_priv->r600_max_simds = 10; | |
1372 | dev_priv->r600_max_backends = 4; | |
1373 | dev_priv->r600_max_gprs = 256; | |
1374 | dev_priv->r600_max_threads = 248; | |
1375 | dev_priv->r600_max_stack_entries = 512; | |
1376 | dev_priv->r600_max_hw_contexts = 8; | |
1377 | dev_priv->r600_max_gs_threads = 16 * 2; | |
1378 | dev_priv->r600_sx_max_export_size = 128; | |
1379 | dev_priv->r600_sx_max_export_pos_size = 16; | |
1380 | dev_priv->r600_sx_max_export_smx_size = 112; | |
1381 | dev_priv->r600_sq_num_cf_insts = 2; | |
1382 | ||
1383 | dev_priv->r700_sx_num_of_sets = 7; | |
1384 | dev_priv->r700_sc_prim_fifo_size = 0xF9; | |
1385 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1386 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
1387 | break; | |
1388 | case CHIP_RV730: | |
1389 | dev_priv->r600_max_pipes = 2; | |
1390 | dev_priv->r600_max_tile_pipes = 4; | |
1391 | dev_priv->r600_max_simds = 8; | |
1392 | dev_priv->r600_max_backends = 2; | |
1393 | dev_priv->r600_max_gprs = 128; | |
1394 | dev_priv->r600_max_threads = 248; | |
1395 | dev_priv->r600_max_stack_entries = 256; | |
1396 | dev_priv->r600_max_hw_contexts = 8; | |
1397 | dev_priv->r600_max_gs_threads = 16 * 2; | |
1398 | dev_priv->r600_sx_max_export_size = 256; | |
1399 | dev_priv->r600_sx_max_export_pos_size = 32; | |
1400 | dev_priv->r600_sx_max_export_smx_size = 224; | |
1401 | dev_priv->r600_sq_num_cf_insts = 2; | |
1402 | ||
1403 | dev_priv->r700_sx_num_of_sets = 7; | |
1404 | dev_priv->r700_sc_prim_fifo_size = 0xf9; | |
1405 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1406 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
2a71ebcd AD |
1407 | if (dev_priv->r600_sx_max_export_pos_size > 16) { |
1408 | dev_priv->r600_sx_max_export_pos_size -= 16; | |
1409 | dev_priv->r600_sx_max_export_smx_size += 16; | |
1410 | } | |
c05ce083 AD |
1411 | break; |
1412 | case CHIP_RV710: | |
1413 | dev_priv->r600_max_pipes = 2; | |
1414 | dev_priv->r600_max_tile_pipes = 2; | |
1415 | dev_priv->r600_max_simds = 2; | |
1416 | dev_priv->r600_max_backends = 1; | |
1417 | dev_priv->r600_max_gprs = 256; | |
1418 | dev_priv->r600_max_threads = 192; | |
1419 | dev_priv->r600_max_stack_entries = 256; | |
1420 | dev_priv->r600_max_hw_contexts = 4; | |
1421 | dev_priv->r600_max_gs_threads = 8 * 2; | |
1422 | dev_priv->r600_sx_max_export_size = 128; | |
1423 | dev_priv->r600_sx_max_export_pos_size = 16; | |
1424 | dev_priv->r600_sx_max_export_smx_size = 112; | |
1425 | dev_priv->r600_sq_num_cf_insts = 1; | |
1426 | ||
1427 | dev_priv->r700_sx_num_of_sets = 7; | |
1428 | dev_priv->r700_sc_prim_fifo_size = 0x40; | |
1429 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1430 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
1431 | break; | |
2a71ebcd AD |
1432 | case CHIP_RV740: |
1433 | dev_priv->r600_max_pipes = 4; | |
1434 | dev_priv->r600_max_tile_pipes = 4; | |
1435 | dev_priv->r600_max_simds = 8; | |
1436 | dev_priv->r600_max_backends = 4; | |
1437 | dev_priv->r600_max_gprs = 256; | |
1438 | dev_priv->r600_max_threads = 248; | |
1439 | dev_priv->r600_max_stack_entries = 512; | |
1440 | dev_priv->r600_max_hw_contexts = 8; | |
1441 | dev_priv->r600_max_gs_threads = 16 * 2; | |
1442 | dev_priv->r600_sx_max_export_size = 256; | |
1443 | dev_priv->r600_sx_max_export_pos_size = 32; | |
1444 | dev_priv->r600_sx_max_export_smx_size = 224; | |
1445 | dev_priv->r600_sq_num_cf_insts = 2; | |
1446 | ||
1447 | dev_priv->r700_sx_num_of_sets = 7; | |
1448 | dev_priv->r700_sc_prim_fifo_size = 0x100; | |
1449 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1450 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
1451 | ||
1452 | if (dev_priv->r600_sx_max_export_pos_size > 16) { | |
1453 | dev_priv->r600_sx_max_export_pos_size -= 16; | |
1454 | dev_priv->r600_sx_max_export_smx_size += 16; | |
1455 | } | |
1456 | break; | |
c05ce083 AD |
1457 | default: |
1458 | break; | |
1459 | } | |
1460 | ||
1461 | /* Initialize HDP */ | |
1462 | j = 0; | |
1463 | for (i = 0; i < 32; i++) { | |
1464 | RADEON_WRITE((0x2c14 + j), 0x00000000); | |
1465 | RADEON_WRITE((0x2c18 + j), 0x00000000); | |
1466 | RADEON_WRITE((0x2c1c + j), 0x00000000); | |
1467 | RADEON_WRITE((0x2c20 + j), 0x00000000); | |
1468 | RADEON_WRITE((0x2c24 + j), 0x00000000); | |
1469 | j += 0x18; | |
1470 | } | |
1471 | ||
1472 | RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); | |
1473 | ||
1474 | /* setup tiling, simd, pipe config */ | |
1475 | mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); | |
1476 | ||
1477 | switch (dev_priv->r600_max_tile_pipes) { | |
1478 | case 1: | |
1479 | gb_tiling_config |= R600_PIPE_TILING(0); | |
1480 | break; | |
1481 | case 2: | |
1482 | gb_tiling_config |= R600_PIPE_TILING(1); | |
1483 | break; | |
1484 | case 4: | |
1485 | gb_tiling_config |= R600_PIPE_TILING(2); | |
1486 | break; | |
1487 | case 8: | |
1488 | gb_tiling_config |= R600_PIPE_TILING(3); | |
1489 | break; | |
1490 | default: | |
1491 | break; | |
1492 | } | |
1493 | ||
1494 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) | |
1495 | gb_tiling_config |= R600_BANK_TILING(1); | |
1496 | else | |
1497 | gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); | |
1498 | ||
1499 | gb_tiling_config |= R600_GROUP_SIZE(0); | |
1500 | ||
1501 | if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { | |
1502 | gb_tiling_config |= R600_ROW_TILING(3); | |
1503 | gb_tiling_config |= R600_SAMPLE_SPLIT(3); | |
1504 | } else { | |
1505 | gb_tiling_config |= | |
1506 | R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); | |
1507 | gb_tiling_config |= | |
1508 | R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); | |
1509 | } | |
1510 | ||
1511 | gb_tiling_config |= R600_BANK_SWAPS(1); | |
1512 | ||
d03f5d59 AD |
1513 | cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
1514 | cc_rb_backend_disable |= | |
1515 | R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); | |
c05ce083 | 1516 | |
d03f5d59 AD |
1517 | cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
1518 | cc_gc_shader_pipe_config |= | |
c05ce083 AD |
1519 | R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); |
1520 | cc_gc_shader_pipe_config |= | |
1521 | R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); | |
1522 | ||
d03f5d59 AD |
1523 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) |
1524 | backend_map = 0x28; | |
1525 | else | |
1526 | backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, | |
1527 | dev_priv->r600_max_tile_pipes, | |
1528 | (R7XX_MAX_BACKENDS - | |
1529 | r600_count_pipe_bits((cc_rb_backend_disable & | |
1530 | R7XX_MAX_BACKENDS_MASK) >> 16)), | |
1531 | (cc_rb_backend_disable >> 16)); | |
1532 | gb_tiling_config |= R600_BACKEND_MAP(backend_map); | |
c05ce083 AD |
1533 | |
1534 | RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); | |
1535 | RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
1536 | RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
961fb597 JG |
1537 | if (gb_tiling_config & 0xc0) { |
1538 | dev_priv->r600_group_size = 512; | |
1539 | } else { | |
1540 | dev_priv->r600_group_size = 256; | |
1541 | } | |
1542 | dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); | |
1543 | if (gb_tiling_config & 0x30) { | |
1544 | dev_priv->r600_nbanks = 8; | |
1545 | } else { | |
1546 | dev_priv->r600_nbanks = 4; | |
1547 | } | |
c05ce083 AD |
1548 | |
1549 | RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1550 | RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
c05ce083 AD |
1551 | |
1552 | RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1553 | RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); | |
1554 | RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); | |
c05ce083 AD |
1555 | |
1556 | num_qd_pipes = | |
d03f5d59 | 1557 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); |
c05ce083 AD |
1558 | RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); |
1559 | RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); | |
1560 | ||
1561 | /* set HW defaults for 3D engine */ | |
1562 | RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | | |
1563 | R600_ROQ_IB2_START(0x2b))); | |
1564 | ||
1565 | RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); | |
1566 | ||
d03f5d59 AD |
1567 | ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); |
1568 | RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); | |
c05ce083 AD |
1569 | |
1570 | sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); | |
1571 | sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; | |
1572 | RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); | |
1573 | ||
1574 | smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); | |
1575 | smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); | |
1576 | smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); | |
1577 | RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); | |
1578 | ||
d03f5d59 AD |
1579 | if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) |
1580 | RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | | |
1581 | R700_GS_FLUSH_CTL(4) | | |
1582 | R700_ACK_FLUSH_CTL(3) | | |
1583 | R700_SYNC_FLUSH_CTL)); | |
c05ce083 | 1584 | |
d03f5d59 AD |
1585 | db_debug3 = RADEON_READ(R700_DB_DEBUG3); |
1586 | db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); | |
1587 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1588 | case CHIP_RV770: | |
1589 | case CHIP_RV740: | |
1590 | db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); | |
1591 | break; | |
1592 | case CHIP_RV710: | |
1593 | case CHIP_RV730: | |
1594 | default: | |
1595 | db_debug3 |= R700_DB_CLK_OFF_DELAY(2); | |
1596 | break; | |
1597 | } | |
1598 | RADEON_WRITE(R700_DB_DEBUG3, db_debug3); | |
1599 | ||
1600 | if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { | |
c05ce083 AD |
1601 | db_debug4 = RADEON_READ(RV700_DB_DEBUG4); |
1602 | db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; | |
1603 | RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); | |
1604 | } | |
1605 | ||
1606 | RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | | |
1607 | R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | | |
1608 | R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); | |
1609 | ||
1610 | RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | | |
1611 | R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | | |
1612 | R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); | |
1613 | ||
1614 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
1615 | ||
1616 | RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); | |
1617 | ||
1618 | RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); | |
1619 | ||
1620 | RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); | |
1621 | ||
1622 | RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); | |
1623 | ||
1624 | sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | | |
1625 | R600_DONE_FIFO_HIWATER(0xe0) | | |
1626 | R600_ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1627 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1628 | case CHIP_RV770: | |
c05ce083 AD |
1629 | case CHIP_RV730: |
1630 | case CHIP_RV710: | |
d03f5d59 AD |
1631 | sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); |
1632 | break; | |
2a71ebcd | 1633 | case CHIP_RV740: |
c05ce083 AD |
1634 | default: |
1635 | sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); | |
1636 | break; | |
1637 | } | |
1638 | RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); | |
1639 | ||
1640 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1641 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1642 | */ | |
1643 | sq_config = RADEON_READ(R600_SQ_CONFIG); | |
1644 | sq_config &= ~(R600_PS_PRIO(3) | | |
1645 | R600_VS_PRIO(3) | | |
1646 | R600_GS_PRIO(3) | | |
1647 | R600_ES_PRIO(3)); | |
1648 | sq_config |= (R600_DX9_CONSTS | | |
1649 | R600_VC_ENABLE | | |
1650 | R600_EXPORT_SRC_C | | |
1651 | R600_PS_PRIO(0) | | |
1652 | R600_VS_PRIO(1) | | |
1653 | R600_GS_PRIO(2) | | |
1654 | R600_ES_PRIO(3)); | |
1655 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) | |
1656 | /* no vertex cache */ | |
1657 | sq_config &= ~R600_VC_ENABLE; | |
1658 | ||
1659 | RADEON_WRITE(R600_SQ_CONFIG, sq_config); | |
1660 | ||
1661 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | | |
1662 | R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | | |
1663 | R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); | |
1664 | ||
1665 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | | |
1666 | R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); | |
1667 | ||
1668 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | | |
1669 | R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | | |
1670 | R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); | |
1671 | if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) | |
1672 | sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); | |
1673 | else | |
1674 | sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); | |
1675 | RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1676 | ||
1677 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | | |
1678 | R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); | |
1679 | ||
1680 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | | |
1681 | R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); | |
1682 | ||
1683 | sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | | |
1684 | R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | | |
1685 | R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | | |
1686 | R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); | |
1687 | ||
1688 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); | |
1689 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); | |
1690 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); | |
1691 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); | |
1692 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); | |
1693 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); | |
1694 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); | |
1695 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); | |
1696 | ||
1697 | RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | | |
1698 | R700_FORCE_EOV_MAX_REZ_CNT(255))); | |
1699 | ||
1700 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) | |
1701 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | | |
1702 | R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); | |
1703 | else | |
1704 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | | |
1705 | R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); | |
1706 | ||
1707 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1708 | case CHIP_RV770: | |
1709 | case CHIP_RV730: | |
2a71ebcd | 1710 | case CHIP_RV740: |
c05ce083 AD |
1711 | gs_prim_buffer_depth = 384; |
1712 | break; | |
1713 | case CHIP_RV710: | |
1714 | gs_prim_buffer_depth = 128; | |
1715 | break; | |
1716 | default: | |
1717 | break; | |
1718 | } | |
1719 | ||
1720 | num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; | |
1721 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; | |
1722 | /* Max value for this is 256 */ | |
1723 | if (vgt_gs_per_es > 256) | |
1724 | vgt_gs_per_es = 256; | |
1725 | ||
1726 | RADEON_WRITE(R600_VGT_ES_PER_GS, 128); | |
1727 | RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); | |
1728 | RADEON_WRITE(R600_VGT_GS_PER_VS, 2); | |
1729 | ||
1730 | /* more default values. 2D/3D driver should adjust as needed */ | |
1731 | RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); | |
1732 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); | |
1733 | RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); | |
1734 | RADEON_WRITE(R600_SX_MISC, 0); | |
1735 | RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); | |
1736 | RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); | |
1737 | RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); | |
1738 | RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); | |
1739 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); | |
1740 | RADEON_WRITE(R600_SPI_INPUT_Z, 0); | |
1741 | RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); | |
1742 | RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); | |
1743 | ||
1744 | /* clear render buffer base addresses */ | |
1745 | RADEON_WRITE(R600_CB_COLOR0_BASE, 0); | |
1746 | RADEON_WRITE(R600_CB_COLOR1_BASE, 0); | |
1747 | RADEON_WRITE(R600_CB_COLOR2_BASE, 0); | |
1748 | RADEON_WRITE(R600_CB_COLOR3_BASE, 0); | |
1749 | RADEON_WRITE(R600_CB_COLOR4_BASE, 0); | |
1750 | RADEON_WRITE(R600_CB_COLOR5_BASE, 0); | |
1751 | RADEON_WRITE(R600_CB_COLOR6_BASE, 0); | |
1752 | RADEON_WRITE(R600_CB_COLOR7_BASE, 0); | |
1753 | ||
1754 | RADEON_WRITE(R700_TCP_CNTL, 0); | |
1755 | ||
1756 | hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); | |
1757 | RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
1758 | ||
1759 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
1760 | ||
1761 | RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | | |
1762 | R600_NUM_CLIP_SEQ(3))); | |
1763 | ||
1764 | } | |
1765 | ||
1766 | static void r600_cp_init_ring_buffer(struct drm_device *dev, | |
1767 | drm_radeon_private_t *dev_priv, | |
1768 | struct drm_file *file_priv) | |
1769 | { | |
1770 | struct drm_radeon_master_private *master_priv; | |
1771 | u32 ring_start; | |
6546bf6d | 1772 | u64 rptr_addr; |
c05ce083 AD |
1773 | |
1774 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) | |
1775 | r700_gfx_init(dev, dev_priv); | |
1776 | else | |
1777 | r600_gfx_init(dev, dev_priv); | |
1778 | ||
1779 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | |
1780 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
1781 | DRM_UDELAY(15000); | |
1782 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
1783 | ||
1784 | ||
1785 | /* Set ring buffer size */ | |
1786 | #ifdef __BIG_ENDIAN | |
1787 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1788 | RADEON_BUF_SWAP_32BIT | | |
1789 | RADEON_RB_NO_UPDATE | | |
1790 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1791 | dev_priv->ring.size_l2qw); | |
1792 | #else | |
1793 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1794 | RADEON_RB_NO_UPDATE | | |
1795 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1796 | dev_priv->ring.size_l2qw); | |
1797 | #endif | |
1798 | ||
1799 | RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); | |
1800 | ||
1801 | /* Set the write pointer delay */ | |
1802 | RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); | |
1803 | ||
1804 | #ifdef __BIG_ENDIAN | |
1805 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1806 | RADEON_BUF_SWAP_32BIT | | |
1807 | RADEON_RB_NO_UPDATE | | |
1808 | RADEON_RB_RPTR_WR_ENA | | |
1809 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1810 | dev_priv->ring.size_l2qw); | |
1811 | #else | |
1812 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1813 | RADEON_RB_NO_UPDATE | | |
1814 | RADEON_RB_RPTR_WR_ENA | | |
1815 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1816 | dev_priv->ring.size_l2qw); | |
1817 | #endif | |
1818 | ||
1819 | /* Initialize the ring buffer's read and write pointers */ | |
1820 | RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); | |
1821 | RADEON_WRITE(R600_CP_RB_WPTR, 0); | |
1822 | SET_RING_HEAD(dev_priv, 0); | |
1823 | dev_priv->ring.tail = 0; | |
1824 | ||
1825 | #if __OS_HAS_AGP | |
1826 | if (dev_priv->flags & RADEON_IS_AGP) { | |
6546bf6d DA |
1827 | rptr_addr = dev_priv->ring_rptr->offset |
1828 | - dev->agp->base + | |
1829 | dev_priv->gart_vm_start; | |
c05ce083 AD |
1830 | } else |
1831 | #endif | |
1832 | { | |
6546bf6d DA |
1833 | rptr_addr = dev_priv->ring_rptr->offset |
1834 | - ((unsigned long) dev->sg->virtual) | |
1835 | + dev_priv->gart_vm_start; | |
c05ce083 | 1836 | } |
6546bf6d DA |
1837 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR, |
1838 | rptr_addr & 0xffffffff); | |
1839 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, | |
1840 | upper_32_bits(rptr_addr)); | |
c05ce083 AD |
1841 | |
1842 | #ifdef __BIG_ENDIAN | |
1843 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1844 | RADEON_BUF_SWAP_32BIT | | |
1845 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1846 | dev_priv->ring.size_l2qw); | |
1847 | #else | |
1848 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1849 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1850 | dev_priv->ring.size_l2qw); | |
1851 | #endif | |
1852 | ||
1853 | #if __OS_HAS_AGP | |
1854 | if (dev_priv->flags & RADEON_IS_AGP) { | |
1855 | /* XXX */ | |
1856 | radeon_write_agp_base(dev_priv, dev->agp->base); | |
1857 | ||
1858 | /* XXX */ | |
1859 | radeon_write_agp_location(dev_priv, | |
1860 | (((dev_priv->gart_vm_start - 1 + | |
1861 | dev_priv->gart_size) & 0xffff0000) | | |
1862 | (dev_priv->gart_vm_start >> 16))); | |
1863 | ||
1864 | ring_start = (dev_priv->cp_ring->offset | |
1865 | - dev->agp->base | |
1866 | + dev_priv->gart_vm_start); | |
1867 | } else | |
1868 | #endif | |
1869 | ring_start = (dev_priv->cp_ring->offset | |
1870 | - (unsigned long)dev->sg->virtual | |
1871 | + dev_priv->gart_vm_start); | |
1872 | ||
1873 | RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); | |
1874 | ||
1875 | RADEON_WRITE(R600_CP_ME_CNTL, 0xff); | |
1876 | ||
1877 | RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); | |
1878 | ||
c05ce083 AD |
1879 | /* Initialize the scratch register pointer. This will cause |
1880 | * the scratch register values to be written out to memory | |
1881 | * whenever they are updated. | |
1882 | * | |
1883 | * We simply put this behind the ring read pointer, this works | |
1884 | * with PCI GART as well as (whatever kind of) AGP GART | |
1885 | */ | |
6546bf6d DA |
1886 | { |
1887 | u64 scratch_addr; | |
1888 | ||
1889 | scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); | |
1890 | scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; | |
1891 | scratch_addr += R600_SCRATCH_REG_OFFSET; | |
1892 | scratch_addr >>= 8; | |
1893 | scratch_addr &= 0xffffffff; | |
1894 | ||
1895 | RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); | |
1896 | } | |
c05ce083 AD |
1897 | |
1898 | RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); | |
1899 | ||
1900 | /* Turn on bus mastering */ | |
1901 | radeon_enable_bm(dev_priv); | |
1902 | ||
1903 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); | |
1904 | RADEON_WRITE(R600_LAST_FRAME_REG, 0); | |
1905 | ||
1906 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); | |
1907 | RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); | |
1908 | ||
1909 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); | |
1910 | RADEON_WRITE(R600_LAST_CLEAR_REG, 0); | |
1911 | ||
1912 | /* reset sarea copies of these */ | |
1913 | master_priv = file_priv->master->driver_priv; | |
1914 | if (master_priv->sarea_priv) { | |
1915 | master_priv->sarea_priv->last_frame = 0; | |
1916 | master_priv->sarea_priv->last_dispatch = 0; | |
1917 | master_priv->sarea_priv->last_clear = 0; | |
1918 | } | |
1919 | ||
1920 | r600_do_wait_for_idle(dev_priv); | |
1921 | ||
1922 | } | |
1923 | ||
1924 | int r600_do_cleanup_cp(struct drm_device *dev) | |
1925 | { | |
1926 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1927 | DRM_DEBUG("\n"); | |
1928 | ||
1929 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1930 | * may not have been called from userspace and after dev_private | |
1931 | * is freed, it's too late. | |
1932 | */ | |
1933 | if (dev->irq_enabled) | |
1934 | drm_irq_uninstall(dev); | |
1935 | ||
1936 | #if __OS_HAS_AGP | |
1937 | if (dev_priv->flags & RADEON_IS_AGP) { | |
1938 | if (dev_priv->cp_ring != NULL) { | |
1939 | drm_core_ioremapfree(dev_priv->cp_ring, dev); | |
1940 | dev_priv->cp_ring = NULL; | |
1941 | } | |
1942 | if (dev_priv->ring_rptr != NULL) { | |
1943 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); | |
1944 | dev_priv->ring_rptr = NULL; | |
1945 | } | |
1946 | if (dev->agp_buffer_map != NULL) { | |
1947 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1948 | dev->agp_buffer_map = NULL; | |
1949 | } | |
1950 | } else | |
1951 | #endif | |
1952 | { | |
1953 | ||
1954 | if (dev_priv->gart_info.bus_addr) | |
1955 | r600_page_table_cleanup(dev, &dev_priv->gart_info); | |
1956 | ||
1957 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { | |
1958 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); | |
8f497aad | 1959 | dev_priv->gart_info.addr = NULL; |
c05ce083 AD |
1960 | } |
1961 | } | |
1962 | /* only clear to the start of flags */ | |
1963 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, | |
1969 | struct drm_file *file_priv) | |
1970 | { | |
1971 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1972 | struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; | |
1973 | ||
1974 | DRM_DEBUG("\n"); | |
1975 | ||
3ce0a23d JG |
1976 | mutex_init(&dev_priv->cs_mutex); |
1977 | r600_cs_legacy_init(); | |
c05ce083 AD |
1978 | /* if we require new memory map but we don't have it fail */ |
1979 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { | |
1980 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); | |
1981 | r600_do_cleanup_cp(dev); | |
1982 | return -EINVAL; | |
1983 | } | |
1984 | ||
1985 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { | |
1986 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); | |
1987 | dev_priv->flags &= ~RADEON_IS_AGP; | |
1988 | /* The writeback test succeeds, but when writeback is enabled, | |
1989 | * the ring buffer read ptr update fails after first 128 bytes. | |
1990 | */ | |
1991 | radeon_no_wb = 1; | |
1992 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
1993 | && !init->is_pci) { | |
1994 | DRM_DEBUG("Restoring AGP flag\n"); | |
1995 | dev_priv->flags |= RADEON_IS_AGP; | |
1996 | } | |
1997 | ||
1998 | dev_priv->usec_timeout = init->usec_timeout; | |
1999 | if (dev_priv->usec_timeout < 1 || | |
2000 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
2001 | DRM_DEBUG("TIMEOUT problem!\n"); | |
2002 | r600_do_cleanup_cp(dev); | |
2003 | return -EINVAL; | |
2004 | } | |
2005 | ||
2006 | /* Enable vblank on CRTC1 for older X servers | |
2007 | */ | |
2008 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
3ce0a23d | 2009 | dev_priv->do_boxes = 0; |
c05ce083 AD |
2010 | dev_priv->cp_mode = init->cp_mode; |
2011 | ||
2012 | /* We don't support anything other than bus-mastering ring mode, | |
2013 | * but the ring can be in either AGP or PCI space for the ring | |
2014 | * read pointer. | |
2015 | */ | |
2016 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && | |
2017 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
2018 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
2019 | r600_do_cleanup_cp(dev); | |
2020 | return -EINVAL; | |
2021 | } | |
2022 | ||
2023 | switch (init->fb_bpp) { | |
2024 | case 16: | |
2025 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
2026 | break; | |
2027 | case 32: | |
2028 | default: | |
2029 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
2030 | break; | |
2031 | } | |
2032 | dev_priv->front_offset = init->front_offset; | |
2033 | dev_priv->front_pitch = init->front_pitch; | |
2034 | dev_priv->back_offset = init->back_offset; | |
2035 | dev_priv->back_pitch = init->back_pitch; | |
2036 | ||
2037 | dev_priv->ring_offset = init->ring_offset; | |
2038 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
2039 | dev_priv->buffers_offset = init->buffers_offset; | |
2040 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
2041 | ||
2042 | master_priv->sarea = drm_getsarea(dev); | |
2043 | if (!master_priv->sarea) { | |
2044 | DRM_ERROR("could not find sarea!\n"); | |
2045 | r600_do_cleanup_cp(dev); | |
2046 | return -EINVAL; | |
2047 | } | |
2048 | ||
2049 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); | |
2050 | if (!dev_priv->cp_ring) { | |
2051 | DRM_ERROR("could not find cp ring region!\n"); | |
2052 | r600_do_cleanup_cp(dev); | |
2053 | return -EINVAL; | |
2054 | } | |
2055 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
2056 | if (!dev_priv->ring_rptr) { | |
2057 | DRM_ERROR("could not find ring read pointer!\n"); | |
2058 | r600_do_cleanup_cp(dev); | |
2059 | return -EINVAL; | |
2060 | } | |
2061 | dev->agp_buffer_token = init->buffers_offset; | |
2062 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); | |
2063 | if (!dev->agp_buffer_map) { | |
2064 | DRM_ERROR("could not find dma buffer region!\n"); | |
2065 | r600_do_cleanup_cp(dev); | |
2066 | return -EINVAL; | |
2067 | } | |
2068 | ||
2069 | if (init->gart_textures_offset) { | |
2070 | dev_priv->gart_textures = | |
2071 | drm_core_findmap(dev, init->gart_textures_offset); | |
2072 | if (!dev_priv->gart_textures) { | |
2073 | DRM_ERROR("could not find GART texture region!\n"); | |
2074 | r600_do_cleanup_cp(dev); | |
2075 | return -EINVAL; | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | #if __OS_HAS_AGP | |
2080 | /* XXX */ | |
2081 | if (dev_priv->flags & RADEON_IS_AGP) { | |
7659e980 AD |
2082 | drm_core_ioremap_wc(dev_priv->cp_ring, dev); |
2083 | drm_core_ioremap_wc(dev_priv->ring_rptr, dev); | |
2084 | drm_core_ioremap_wc(dev->agp_buffer_map, dev); | |
c05ce083 AD |
2085 | if (!dev_priv->cp_ring->handle || |
2086 | !dev_priv->ring_rptr->handle || | |
2087 | !dev->agp_buffer_map->handle) { | |
2088 | DRM_ERROR("could not find ioremap agp regions!\n"); | |
2089 | r600_do_cleanup_cp(dev); | |
2090 | return -EINVAL; | |
2091 | } | |
2092 | } else | |
2093 | #endif | |
2094 | { | |
3ce0a23d | 2095 | dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; |
c05ce083 | 2096 | dev_priv->ring_rptr->handle = |
3ce0a23d | 2097 | (void *)(unsigned long)dev_priv->ring_rptr->offset; |
c05ce083 | 2098 | dev->agp_buffer_map->handle = |
3ce0a23d | 2099 | (void *)(unsigned long)dev->agp_buffer_map->offset; |
c05ce083 AD |
2100 | |
2101 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
2102 | dev_priv->cp_ring->handle); | |
2103 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
2104 | dev_priv->ring_rptr->handle); | |
2105 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
2106 | dev->agp_buffer_map->handle); | |
2107 | } | |
2108 | ||
2109 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; | |
2110 | dev_priv->fb_size = | |
2111 | (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) | |
2112 | - dev_priv->fb_location; | |
2113 | ||
2114 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | | |
2115 | ((dev_priv->front_offset | |
2116 | + dev_priv->fb_location) >> 10)); | |
2117 | ||
2118 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | | |
2119 | ((dev_priv->back_offset | |
2120 | + dev_priv->fb_location) >> 10)); | |
2121 | ||
2122 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | | |
2123 | ((dev_priv->depth_offset | |
2124 | + dev_priv->fb_location) >> 10)); | |
2125 | ||
2126 | dev_priv->gart_size = init->gart_size; | |
2127 | ||
2128 | /* New let's set the memory map ... */ | |
2129 | if (dev_priv->new_memmap) { | |
2130 | u32 base = 0; | |
2131 | ||
2132 | DRM_INFO("Setting GART location based on new memory map\n"); | |
2133 | ||
2134 | /* If using AGP, try to locate the AGP aperture at the same | |
2135 | * location in the card and on the bus, though we have to | |
2136 | * align it down. | |
2137 | */ | |
2138 | #if __OS_HAS_AGP | |
2139 | /* XXX */ | |
2140 | if (dev_priv->flags & RADEON_IS_AGP) { | |
2141 | base = dev->agp->base; | |
2142 | /* Check if valid */ | |
2143 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && | |
2144 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
2145 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", | |
2146 | dev->agp->base); | |
2147 | base = 0; | |
2148 | } | |
2149 | } | |
2150 | #endif | |
2151 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
2152 | if (base == 0) { | |
2153 | base = dev_priv->fb_location + dev_priv->fb_size; | |
2154 | if (base < dev_priv->fb_location || | |
2155 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
2156 | base = dev_priv->fb_location | |
2157 | - dev_priv->gart_size; | |
2158 | } | |
2159 | dev_priv->gart_vm_start = base & 0xffc00000u; | |
2160 | if (dev_priv->gart_vm_start != base) | |
2161 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
2162 | base, dev_priv->gart_vm_start); | |
2163 | } | |
2164 | ||
2165 | #if __OS_HAS_AGP | |
2166 | /* XXX */ | |
2167 | if (dev_priv->flags & RADEON_IS_AGP) | |
2168 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
2169 | - dev->agp->base | |
2170 | + dev_priv->gart_vm_start); | |
2171 | else | |
2172 | #endif | |
2173 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
2174 | - (unsigned long)dev->sg->virtual | |
2175 | + dev_priv->gart_vm_start); | |
2176 | ||
2177 | DRM_DEBUG("fb 0x%08x size %d\n", | |
2178 | (unsigned int) dev_priv->fb_location, | |
2179 | (unsigned int) dev_priv->fb_size); | |
2180 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); | |
2181 | DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", | |
2182 | (unsigned int) dev_priv->gart_vm_start); | |
2183 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", | |
2184 | dev_priv->gart_buffers_offset); | |
2185 | ||
2186 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; | |
2187 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
2188 | + init->ring_size / sizeof(u32)); | |
2189 | dev_priv->ring.size = init->ring_size; | |
2190 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); | |
2191 | ||
2192 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; | |
2193 | dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); | |
2194 | ||
2195 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
2196 | dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); | |
2197 | ||
2198 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; | |
2199 | ||
2200 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
2201 | ||
2202 | #if __OS_HAS_AGP | |
2203 | if (dev_priv->flags & RADEON_IS_AGP) { | |
2204 | /* XXX turn off pcie gart */ | |
2205 | } else | |
2206 | #endif | |
2207 | { | |
2208 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); | |
2209 | /* if we have an offset set from userspace */ | |
2210 | if (!dev_priv->pcigart_offset_set) { | |
2211 | DRM_ERROR("Need gart offset from userspace\n"); | |
2212 | r600_do_cleanup_cp(dev); | |
2213 | return -EINVAL; | |
2214 | } | |
2215 | ||
2216 | DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); | |
2217 | ||
2218 | dev_priv->gart_info.bus_addr = | |
2219 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
2220 | dev_priv->gart_info.mapping.offset = | |
2221 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; | |
2222 | dev_priv->gart_info.mapping.size = | |
2223 | dev_priv->gart_info.table_size; | |
2224 | ||
2225 | drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); | |
2226 | if (!dev_priv->gart_info.mapping.handle) { | |
2227 | DRM_ERROR("ioremap failed.\n"); | |
2228 | r600_do_cleanup_cp(dev); | |
2229 | return -EINVAL; | |
2230 | } | |
2231 | ||
2232 | dev_priv->gart_info.addr = | |
2233 | dev_priv->gart_info.mapping.handle; | |
2234 | ||
2235 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", | |
2236 | dev_priv->gart_info.addr, | |
2237 | dev_priv->pcigart_offset); | |
2238 | ||
41f13fe8 | 2239 | if (!r600_page_table_init(dev)) { |
c05ce083 AD |
2240 | DRM_ERROR("Failed to init GART table\n"); |
2241 | r600_do_cleanup_cp(dev); | |
2242 | return -EINVAL; | |
2243 | } | |
2244 | ||
2245 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) | |
2246 | r700_vm_init(dev); | |
2247 | else | |
2248 | r600_vm_init(dev); | |
2249 | } | |
2250 | ||
70967ab9 BH |
2251 | if (!dev_priv->me_fw || !dev_priv->pfp_fw) { |
2252 | int err = r600_cp_init_microcode(dev_priv); | |
2253 | if (err) { | |
2254 | DRM_ERROR("Failed to load firmware!\n"); | |
2255 | r600_do_cleanup_cp(dev); | |
2256 | return err; | |
2257 | } | |
2258 | } | |
c05ce083 AD |
2259 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) |
2260 | r700_cp_load_microcode(dev_priv); | |
2261 | else | |
2262 | r600_cp_load_microcode(dev_priv); | |
2263 | ||
2264 | r600_cp_init_ring_buffer(dev, dev_priv, file_priv); | |
2265 | ||
2266 | dev_priv->last_buf = 0; | |
2267 | ||
2268 | r600_do_engine_reset(dev); | |
2269 | r600_test_writeback(dev_priv); | |
2270 | ||
2271 | return 0; | |
2272 | } | |
2273 | ||
2274 | int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) | |
2275 | { | |
2276 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2277 | ||
2278 | DRM_DEBUG("\n"); | |
2279 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { | |
2280 | r700_vm_init(dev); | |
2281 | r700_cp_load_microcode(dev_priv); | |
2282 | } else { | |
2283 | r600_vm_init(dev); | |
2284 | r600_cp_load_microcode(dev_priv); | |
2285 | } | |
2286 | r600_cp_init_ring_buffer(dev, dev_priv, file_priv); | |
2287 | r600_do_engine_reset(dev); | |
2288 | ||
2289 | return 0; | |
2290 | } | |
2291 | ||
2292 | /* Wait for the CP to go idle. | |
2293 | */ | |
2294 | int r600_do_cp_idle(drm_radeon_private_t *dev_priv) | |
2295 | { | |
2296 | RING_LOCALS; | |
2297 | DRM_DEBUG("\n"); | |
2298 | ||
2299 | BEGIN_RING(5); | |
2300 | OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); | |
2301 | OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); | |
2302 | /* wait for 3D idle clean */ | |
2303 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); | |
2304 | OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); | |
2305 | OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); | |
2306 | ||
2307 | ADVANCE_RING(); | |
2308 | COMMIT_RING(); | |
2309 | ||
2310 | return r600_do_wait_for_idle(dev_priv); | |
2311 | } | |
2312 | ||
2313 | /* Start the Command Processor. | |
2314 | */ | |
2315 | void r600_do_cp_start(drm_radeon_private_t *dev_priv) | |
2316 | { | |
2317 | u32 cp_me; | |
2318 | RING_LOCALS; | |
2319 | DRM_DEBUG("\n"); | |
2320 | ||
2321 | BEGIN_RING(7); | |
2322 | OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); | |
2323 | OUT_RING(0x00000001); | |
2324 | if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) | |
2325 | OUT_RING(0x00000003); | |
2326 | else | |
2327 | OUT_RING(0x00000000); | |
2328 | OUT_RING((dev_priv->r600_max_hw_contexts - 1)); | |
2329 | OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); | |
2330 | OUT_RING(0x00000000); | |
2331 | OUT_RING(0x00000000); | |
2332 | ADVANCE_RING(); | |
2333 | COMMIT_RING(); | |
2334 | ||
2335 | /* set the mux and reset the halt bit */ | |
2336 | cp_me = 0xff; | |
2337 | RADEON_WRITE(R600_CP_ME_CNTL, cp_me); | |
2338 | ||
2339 | dev_priv->cp_running = 1; | |
2340 | ||
2341 | } | |
2342 | ||
2343 | void r600_do_cp_reset(drm_radeon_private_t *dev_priv) | |
2344 | { | |
2345 | u32 cur_read_ptr; | |
2346 | DRM_DEBUG("\n"); | |
2347 | ||
2348 | cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); | |
2349 | RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); | |
2350 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
2351 | dev_priv->ring.tail = cur_read_ptr; | |
2352 | } | |
2353 | ||
2354 | void r600_do_cp_stop(drm_radeon_private_t *dev_priv) | |
2355 | { | |
2356 | uint32_t cp_me; | |
2357 | ||
2358 | DRM_DEBUG("\n"); | |
2359 | ||
2360 | cp_me = 0xff | R600_CP_ME_HALT; | |
2361 | ||
2362 | RADEON_WRITE(R600_CP_ME_CNTL, cp_me); | |
2363 | ||
2364 | dev_priv->cp_running = 0; | |
2365 | } | |
2366 | ||
2367 | int r600_cp_dispatch_indirect(struct drm_device *dev, | |
2368 | struct drm_buf *buf, int start, int end) | |
2369 | { | |
2370 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2371 | RING_LOCALS; | |
2372 | ||
2373 | if (start != end) { | |
2374 | unsigned long offset = (dev_priv->gart_buffers_offset | |
2375 | + buf->offset + start); | |
2376 | int dwords = (end - start + 3) / sizeof(u32); | |
2377 | ||
2378 | DRM_DEBUG("dwords:%d\n", dwords); | |
2379 | DRM_DEBUG("offset 0x%lx\n", offset); | |
2380 | ||
2381 | ||
2382 | /* Indirect buffer data must be a multiple of 16 dwords. | |
2383 | * pad the data with a Type-2 CP packet. | |
2384 | */ | |
2385 | while (dwords & 0xf) { | |
2386 | u32 *data = (u32 *) | |
2387 | ((char *)dev->agp_buffer_map->handle | |
2388 | + buf->offset + start); | |
2389 | data[dwords++] = RADEON_CP_PACKET2; | |
2390 | } | |
2391 | ||
2392 | /* Fire off the indirect buffer */ | |
2393 | BEGIN_RING(4); | |
2394 | OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); | |
2395 | OUT_RING((offset & 0xfffffffc)); | |
2396 | OUT_RING((upper_32_bits(offset) & 0xff)); | |
2397 | OUT_RING(dwords); | |
2398 | ADVANCE_RING(); | |
2399 | } | |
2400 | ||
2401 | return 0; | |
2402 | } | |
3ce0a23d JG |
2403 | |
2404 | void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) | |
2405 | { | |
2406 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2407 | struct drm_master *master = file_priv->master; | |
2408 | struct drm_radeon_master_private *master_priv = master->driver_priv; | |
2409 | drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; | |
2410 | int nbox = sarea_priv->nbox; | |
2411 | struct drm_clip_rect *pbox = sarea_priv->boxes; | |
2412 | int i, cpp, src_pitch, dst_pitch; | |
2413 | uint64_t src, dst; | |
2414 | RING_LOCALS; | |
2415 | DRM_DEBUG("\n"); | |
2416 | ||
2417 | if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) | |
2418 | cpp = 4; | |
2419 | else | |
2420 | cpp = 2; | |
2421 | ||
2422 | if (sarea_priv->pfCurrentPage == 0) { | |
2423 | src_pitch = dev_priv->back_pitch; | |
2424 | dst_pitch = dev_priv->front_pitch; | |
2425 | src = dev_priv->back_offset + dev_priv->fb_location; | |
2426 | dst = dev_priv->front_offset + dev_priv->fb_location; | |
2427 | } else { | |
2428 | src_pitch = dev_priv->front_pitch; | |
2429 | dst_pitch = dev_priv->back_pitch; | |
2430 | src = dev_priv->front_offset + dev_priv->fb_location; | |
2431 | dst = dev_priv->back_offset + dev_priv->fb_location; | |
2432 | } | |
2433 | ||
2434 | if (r600_prepare_blit_copy(dev, file_priv)) { | |
2435 | DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); | |
2436 | return; | |
2437 | } | |
2438 | for (i = 0; i < nbox; i++) { | |
2439 | int x = pbox[i].x1; | |
2440 | int y = pbox[i].y1; | |
2441 | int w = pbox[i].x2 - x; | |
2442 | int h = pbox[i].y2 - y; | |
2443 | ||
2444 | DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); | |
2445 | ||
2446 | r600_blit_swap(dev, | |
2447 | src, dst, | |
2448 | x, y, x, y, w, h, | |
2449 | src_pitch, dst_pitch, cpp); | |
2450 | } | |
2451 | r600_done_blit_copy(dev); | |
2452 | ||
2453 | /* Increment the frame counter. The client-side 3D driver must | |
2454 | * throttle the framerate by waiting for this value before | |
2455 | * performing the swapbuffer ioctl. | |
2456 | */ | |
2457 | sarea_priv->last_frame++; | |
2458 | ||
2459 | BEGIN_RING(3); | |
2460 | R600_FRAME_AGE(sarea_priv->last_frame); | |
2461 | ADVANCE_RING(); | |
2462 | } | |
2463 | ||
2464 | int r600_cp_dispatch_texture(struct drm_device *dev, | |
2465 | struct drm_file *file_priv, | |
2466 | drm_radeon_texture_t *tex, | |
2467 | drm_radeon_tex_image_t *image) | |
2468 | { | |
2469 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2470 | struct drm_buf *buf; | |
2471 | u32 *buffer; | |
2472 | const u8 __user *data; | |
2473 | int size, pass_size; | |
2474 | u64 src_offset, dst_offset; | |
2475 | ||
2476 | if (!radeon_check_offset(dev_priv, tex->offset)) { | |
2477 | DRM_ERROR("Invalid destination offset\n"); | |
2478 | return -EINVAL; | |
2479 | } | |
2480 | ||
2481 | /* this might fail for zero-sized uploads - are those illegal? */ | |
2482 | if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { | |
2483 | DRM_ERROR("Invalid final destination offset\n"); | |
2484 | return -EINVAL; | |
2485 | } | |
2486 | ||
2487 | size = tex->height * tex->pitch; | |
2488 | ||
2489 | if (size == 0) | |
2490 | return 0; | |
2491 | ||
2492 | dst_offset = tex->offset; | |
2493 | ||
2494 | if (r600_prepare_blit_copy(dev, file_priv)) { | |
2495 | DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); | |
2496 | return -EAGAIN; | |
2497 | } | |
2498 | do { | |
2499 | data = (const u8 __user *)image->data; | |
2500 | pass_size = size; | |
2501 | ||
2502 | buf = radeon_freelist_get(dev); | |
2503 | if (!buf) { | |
2504 | DRM_DEBUG("EAGAIN\n"); | |
2505 | if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) | |
2506 | return -EFAULT; | |
2507 | return -EAGAIN; | |
2508 | } | |
2509 | ||
2510 | if (pass_size > buf->total) | |
2511 | pass_size = buf->total; | |
2512 | ||
2513 | /* Dispatch the indirect buffer. | |
2514 | */ | |
2515 | buffer = | |
2516 | (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); | |
2517 | ||
2518 | if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { | |
2519 | DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); | |
2520 | return -EFAULT; | |
2521 | } | |
2522 | ||
2523 | buf->file_priv = file_priv; | |
2524 | buf->used = pass_size; | |
2525 | src_offset = dev_priv->gart_buffers_offset + buf->offset; | |
2526 | ||
2527 | r600_blit_copy(dev, src_offset, dst_offset, pass_size); | |
2528 | ||
2529 | radeon_cp_discard_buffer(dev, file_priv->master, buf); | |
2530 | ||
2531 | /* Update the input parameters for next time */ | |
2532 | image->data = (const u8 __user *)image->data + pass_size; | |
2533 | dst_offset += pass_size; | |
2534 | size -= pass_size; | |
2535 | } while (size > 0); | |
2536 | r600_done_blit_copy(dev); | |
2537 | ||
2538 | return 0; | |
2539 | } | |
2540 | ||
2541 | /* | |
2542 | * Legacy cs ioctl | |
2543 | */ | |
2544 | static u32 radeon_cs_id_get(struct drm_radeon_private *radeon) | |
2545 | { | |
2546 | /* FIXME: check if wrap affect last reported wrap & sequence */ | |
2547 | radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; | |
2548 | if (!radeon->cs_id_scnt) { | |
2549 | /* increment wrap counter */ | |
2550 | radeon->cs_id_wcnt += 0x01000000; | |
2551 | /* valid sequence counter start at 1 */ | |
2552 | radeon->cs_id_scnt = 1; | |
2553 | } | |
2554 | return (radeon->cs_id_scnt | radeon->cs_id_wcnt); | |
2555 | } | |
2556 | ||
2557 | static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) | |
2558 | { | |
2559 | RING_LOCALS; | |
2560 | ||
2561 | *id = radeon_cs_id_get(dev_priv); | |
2562 | ||
2563 | /* SCRATCH 2 */ | |
2564 | BEGIN_RING(3); | |
2565 | R600_CLEAR_AGE(*id); | |
2566 | ADVANCE_RING(); | |
2567 | COMMIT_RING(); | |
2568 | } | |
2569 | ||
2570 | static int r600_ib_get(struct drm_device *dev, | |
2571 | struct drm_file *fpriv, | |
2572 | struct drm_buf **buffer) | |
2573 | { | |
2574 | struct drm_buf *buf; | |
2575 | ||
2576 | *buffer = NULL; | |
2577 | buf = radeon_freelist_get(dev); | |
2578 | if (!buf) { | |
2579 | return -EBUSY; | |
2580 | } | |
2581 | buf->file_priv = fpriv; | |
2582 | *buffer = buf; | |
2583 | return 0; | |
2584 | } | |
2585 | ||
2586 | static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, | |
2587 | struct drm_file *fpriv, int l, int r) | |
2588 | { | |
2589 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2590 | ||
2591 | if (buf) { | |
2592 | if (!r) | |
2593 | r600_cp_dispatch_indirect(dev, buf, 0, l * 4); | |
2594 | radeon_cp_discard_buffer(dev, fpriv->master, buf); | |
2595 | COMMIT_RING(); | |
2596 | } | |
2597 | } | |
2598 | ||
2599 | int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) | |
2600 | { | |
2601 | struct drm_radeon_private *dev_priv = dev->dev_private; | |
2602 | struct drm_radeon_cs *cs = data; | |
2603 | struct drm_buf *buf; | |
2604 | unsigned family; | |
2605 | int l, r = 0; | |
2606 | u32 *ib, cs_id = 0; | |
2607 | ||
2608 | if (dev_priv == NULL) { | |
2609 | DRM_ERROR("called with no initialization\n"); | |
2610 | return -EINVAL; | |
2611 | } | |
2612 | family = dev_priv->flags & RADEON_FAMILY_MASK; | |
2613 | if (family < CHIP_R600) { | |
2614 | DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); | |
2615 | return -EINVAL; | |
2616 | } | |
2617 | mutex_lock(&dev_priv->cs_mutex); | |
2618 | /* get ib */ | |
2619 | r = r600_ib_get(dev, fpriv, &buf); | |
2620 | if (r) { | |
2621 | DRM_ERROR("ib_get failed\n"); | |
2622 | goto out; | |
2623 | } | |
2624 | ib = dev->agp_buffer_map->handle + buf->offset; | |
2625 | /* now parse command stream */ | |
2626 | r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); | |
2627 | if (r) { | |
2628 | goto out; | |
2629 | } | |
2630 | ||
2631 | out: | |
2632 | r600_ib_free(dev, buf, fpriv, l, r); | |
2633 | /* emit cs id sequence */ | |
2634 | r600_cs_id_emit(dev_priv, &cs_id); | |
2635 | cs->cs_id = cs_id; | |
2636 | mutex_unlock(&dev_priv->cs_mutex); | |
2637 | return r; | |
2638 | } | |
961fb597 JG |
2639 | |
2640 | void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) | |
2641 | { | |
2642 | struct drm_radeon_private *dev_priv = dev->dev_private; | |
2643 | ||
2644 | *npipes = dev_priv->r600_npipes; | |
2645 | *nbanks = dev_priv->r600_nbanks; | |
2646 | *group_size = dev_priv->r600_group_size; | |
2647 | } |