Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
72 | ||
c2142715 | 73 | #include "radeon_family.h" |
771fe6b9 JG |
74 | #include "radeon_mode.h" |
75 | #include "radeon_reg.h" | |
771fe6b9 JG |
76 | |
77 | /* | |
78 | * Modules parameters. | |
79 | */ | |
80 | extern int radeon_no_wb; | |
81 | extern int radeon_modeset; | |
82 | extern int radeon_dynclks; | |
83 | extern int radeon_r4xx_atom; | |
84 | extern int radeon_agpmode; | |
85 | extern int radeon_vram_limit; | |
86 | extern int radeon_gart_size; | |
87 | extern int radeon_benchmarking; | |
ecc0b326 | 88 | extern int radeon_testing; |
771fe6b9 | 89 | extern int radeon_connector_table; |
4ce001ab | 90 | extern int radeon_tv; |
b27b6375 | 91 | extern int radeon_new_pll; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
771fe6b9 JG |
95 | |
96 | /* | |
97 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
98 | * symbol; | |
99 | */ | |
100 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
225758d8 | 101 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
e821767b | 102 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
771fe6b9 JG |
103 | #define RADEON_IB_POOL_SIZE 16 |
104 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
105 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 106 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 107 | |
771fe6b9 JG |
108 | /* |
109 | * Errata workarounds. | |
110 | */ | |
111 | enum radeon_pll_errata { | |
112 | CHIP_ERRATA_R300_CG = 0x00000001, | |
113 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
114 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
115 | }; | |
116 | ||
117 | ||
118 | struct radeon_device; | |
119 | ||
120 | ||
121 | /* | |
122 | * BIOS. | |
123 | */ | |
6a9ee8af DA |
124 | #define ATRM_BIOS_PAGE 4096 |
125 | ||
8edb381d | 126 | #if defined(CONFIG_VGA_SWITCHEROO) |
6a9ee8af DA |
127 | bool radeon_atrm_supported(struct pci_dev *pdev); |
128 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); | |
8edb381d DA |
129 | #else |
130 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) | |
131 | { | |
132 | return false; | |
133 | } | |
134 | ||
135 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ | |
136 | return -EINVAL; | |
137 | } | |
138 | #endif | |
771fe6b9 JG |
139 | bool radeon_get_bios(struct radeon_device *rdev); |
140 | ||
3ce0a23d | 141 | |
771fe6b9 | 142 | /* |
3ce0a23d | 143 | * Dummy page |
771fe6b9 | 144 | */ |
3ce0a23d JG |
145 | struct radeon_dummy_page { |
146 | struct page *page; | |
147 | dma_addr_t addr; | |
148 | }; | |
149 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
150 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
151 | ||
771fe6b9 | 152 | |
3ce0a23d JG |
153 | /* |
154 | * Clocks | |
155 | */ | |
771fe6b9 JG |
156 | struct radeon_clock { |
157 | struct radeon_pll p1pll; | |
158 | struct radeon_pll p2pll; | |
bcc1c2a1 | 159 | struct radeon_pll dcpll; |
771fe6b9 JG |
160 | struct radeon_pll spll; |
161 | struct radeon_pll mpll; | |
162 | /* 10 Khz units */ | |
163 | uint32_t default_mclk; | |
164 | uint32_t default_sclk; | |
bcc1c2a1 AD |
165 | uint32_t default_dispclk; |
166 | uint32_t dp_extclk; | |
771fe6b9 JG |
167 | }; |
168 | ||
7433874e RM |
169 | /* |
170 | * Power management | |
171 | */ | |
172 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 173 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 174 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
175 | void radeon_pm_suspend(struct radeon_device *rdev); |
176 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
177 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
178 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
3ce0a23d | 179 | |
771fe6b9 JG |
180 | /* |
181 | * Fences. | |
182 | */ | |
183 | struct radeon_fence_driver { | |
184 | uint32_t scratch_reg; | |
185 | atomic_t seq; | |
186 | uint32_t last_seq; | |
225758d8 JG |
187 | unsigned long last_jiffies; |
188 | unsigned long last_timeout; | |
771fe6b9 JG |
189 | wait_queue_head_t queue; |
190 | rwlock_t lock; | |
191 | struct list_head created; | |
192 | struct list_head emited; | |
193 | struct list_head signaled; | |
0a0c7596 | 194 | bool initialized; |
771fe6b9 JG |
195 | }; |
196 | ||
197 | struct radeon_fence { | |
198 | struct radeon_device *rdev; | |
199 | struct kref kref; | |
200 | struct list_head list; | |
201 | /* protected by radeon_fence.lock */ | |
202 | uint32_t seq; | |
771fe6b9 JG |
203 | bool emited; |
204 | bool signaled; | |
205 | }; | |
206 | ||
207 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
208 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
209 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
210 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
211 | void radeon_fence_process(struct radeon_device *rdev); | |
212 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
213 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
214 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
215 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
216 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
217 | void radeon_fence_unref(struct radeon_fence **fence); | |
218 | ||
e024e110 DA |
219 | /* |
220 | * Tiling registers | |
221 | */ | |
222 | struct radeon_surface_reg { | |
4c788679 | 223 | struct radeon_bo *bo; |
e024e110 DA |
224 | }; |
225 | ||
226 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
227 | |
228 | /* | |
4c788679 | 229 | * TTM. |
771fe6b9 | 230 | */ |
4c788679 JG |
231 | struct radeon_mman { |
232 | struct ttm_bo_global_ref bo_global_ref; | |
233 | struct ttm_global_reference mem_global_ref; | |
4c788679 | 234 | struct ttm_bo_device bdev; |
0a0c7596 JG |
235 | bool mem_global_referenced; |
236 | bool initialized; | |
4c788679 JG |
237 | }; |
238 | ||
239 | struct radeon_bo { | |
240 | /* Protected by gem.mutex */ | |
241 | struct list_head list; | |
242 | /* Protected by tbo.reserved */ | |
312ea8da JG |
243 | u32 placements[3]; |
244 | struct ttm_placement placement; | |
4c788679 JG |
245 | struct ttm_buffer_object tbo; |
246 | struct ttm_bo_kmap_obj kmap; | |
247 | unsigned pin_count; | |
248 | void *kptr; | |
249 | u32 tiling_flags; | |
250 | u32 pitch; | |
251 | int surface_reg; | |
252 | /* Constant after initialization */ | |
253 | struct radeon_device *rdev; | |
254 | struct drm_gem_object *gobj; | |
255 | }; | |
771fe6b9 | 256 | |
4c788679 | 257 | struct radeon_bo_list { |
771fe6b9 | 258 | struct list_head list; |
4c788679 | 259 | struct radeon_bo *bo; |
771fe6b9 JG |
260 | uint64_t gpu_offset; |
261 | unsigned rdomain; | |
262 | unsigned wdomain; | |
4c788679 | 263 | u32 tiling_flags; |
e8652753 | 264 | bool reserved; |
771fe6b9 JG |
265 | }; |
266 | ||
771fe6b9 JG |
267 | /* |
268 | * GEM objects. | |
269 | */ | |
270 | struct radeon_gem { | |
4c788679 | 271 | struct mutex mutex; |
771fe6b9 JG |
272 | struct list_head objects; |
273 | }; | |
274 | ||
275 | int radeon_gem_init(struct radeon_device *rdev); | |
276 | void radeon_gem_fini(struct radeon_device *rdev); | |
277 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
278 | int alignment, int initial_domain, |
279 | bool discardable, bool kernel, | |
280 | struct drm_gem_object **obj); | |
771fe6b9 JG |
281 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
282 | uint64_t *gpu_addr); | |
283 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
284 | ||
285 | ||
286 | /* | |
287 | * GART structures, functions & helpers | |
288 | */ | |
289 | struct radeon_mc; | |
290 | ||
291 | struct radeon_gart_table_ram { | |
292 | volatile uint32_t *ptr; | |
293 | }; | |
294 | ||
295 | struct radeon_gart_table_vram { | |
4c788679 | 296 | struct radeon_bo *robj; |
771fe6b9 JG |
297 | volatile uint32_t *ptr; |
298 | }; | |
299 | ||
300 | union radeon_gart_table { | |
301 | struct radeon_gart_table_ram ram; | |
302 | struct radeon_gart_table_vram vram; | |
303 | }; | |
304 | ||
a77f1718 | 305 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 306 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
a77f1718 | 307 | |
771fe6b9 JG |
308 | struct radeon_gart { |
309 | dma_addr_t table_addr; | |
310 | unsigned num_gpu_pages; | |
311 | unsigned num_cpu_pages; | |
312 | unsigned table_size; | |
313 | union radeon_gart_table table; | |
314 | struct page **pages; | |
315 | dma_addr_t *pages_addr; | |
316 | bool ready; | |
317 | }; | |
318 | ||
319 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
320 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
321 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
322 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
323 | int radeon_gart_init(struct radeon_device *rdev); | |
324 | void radeon_gart_fini(struct radeon_device *rdev); | |
325 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
326 | int pages); | |
327 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
328 | int pages, struct page **pagelist); | |
329 | ||
330 | ||
331 | /* | |
332 | * GPU MC structures, functions & helpers | |
333 | */ | |
334 | struct radeon_mc { | |
335 | resource_size_t aper_size; | |
336 | resource_size_t aper_base; | |
337 | resource_size_t agp_base; | |
7a50f01a DA |
338 | /* for some chips with <= 32MB we need to lie |
339 | * about vram size near mc fb location */ | |
3ce0a23d | 340 | u64 mc_vram_size; |
d594e46a | 341 | u64 visible_vram_size; |
3ce0a23d JG |
342 | u64 gtt_size; |
343 | u64 gtt_start; | |
344 | u64 gtt_end; | |
3ce0a23d JG |
345 | u64 vram_start; |
346 | u64 vram_end; | |
771fe6b9 | 347 | unsigned vram_width; |
3ce0a23d | 348 | u64 real_vram_size; |
771fe6b9 JG |
349 | int vram_mtrr; |
350 | bool vram_is_ddr; | |
d594e46a | 351 | bool igp_sideport_enabled; |
771fe6b9 JG |
352 | }; |
353 | ||
06b6476d AD |
354 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
355 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
356 | |
357 | /* | |
358 | * GPU scratch registers structures, functions & helpers | |
359 | */ | |
360 | struct radeon_scratch { | |
361 | unsigned num_reg; | |
362 | bool free[32]; | |
363 | uint32_t reg[32]; | |
364 | }; | |
365 | ||
366 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
367 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
368 | ||
369 | ||
370 | /* | |
371 | * IRQS. | |
372 | */ | |
373 | struct radeon_irq { | |
374 | bool installed; | |
375 | bool sw_int; | |
376 | /* FIXME: use a define max crtc rather than hardcode it */ | |
45f9a39b | 377 | bool crtc_vblank_int[6]; |
73a6d3fc | 378 | wait_queue_head_t vblank_queue; |
b500f680 AD |
379 | /* FIXME: use defines for max hpd/dacs */ |
380 | bool hpd[6]; | |
2031f77c AD |
381 | bool gui_idle; |
382 | bool gui_idle_acked; | |
383 | wait_queue_head_t idle_queue; | |
f2594933 CK |
384 | /* FIXME: use defines for max HDMI blocks */ |
385 | bool hdmi[2]; | |
1614f8b1 DA |
386 | spinlock_t sw_lock; |
387 | int sw_refcount; | |
771fe6b9 JG |
388 | }; |
389 | ||
390 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
391 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
392 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
393 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
771fe6b9 JG |
394 | |
395 | /* | |
396 | * CP & ring. | |
397 | */ | |
398 | struct radeon_ib { | |
399 | struct list_head list; | |
e821767b | 400 | unsigned idx; |
771fe6b9 JG |
401 | uint64_t gpu_addr; |
402 | struct radeon_fence *fence; | |
e821767b | 403 | uint32_t *ptr; |
771fe6b9 | 404 | uint32_t length_dw; |
e821767b | 405 | bool free; |
771fe6b9 JG |
406 | }; |
407 | ||
ecb114a1 DA |
408 | /* |
409 | * locking - | |
410 | * mutex protects scheduled_ibs, ready, alloc_bm | |
411 | */ | |
771fe6b9 JG |
412 | struct radeon_ib_pool { |
413 | struct mutex mutex; | |
4c788679 | 414 | struct radeon_bo *robj; |
9f93ed39 | 415 | struct list_head bogus_ib; |
771fe6b9 JG |
416 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
417 | bool ready; | |
e821767b | 418 | unsigned head_id; |
771fe6b9 JG |
419 | }; |
420 | ||
421 | struct radeon_cp { | |
4c788679 | 422 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
423 | volatile uint32_t *ring; |
424 | unsigned rptr; | |
425 | unsigned wptr; | |
426 | unsigned wptr_old; | |
427 | unsigned ring_size; | |
428 | unsigned ring_free_dw; | |
429 | int count_dw; | |
430 | uint64_t gpu_addr; | |
431 | uint32_t align_mask; | |
432 | uint32_t ptr_mask; | |
433 | struct mutex mutex; | |
434 | bool ready; | |
435 | }; | |
436 | ||
d8f60cfc AD |
437 | /* |
438 | * R6xx+ IH ring | |
439 | */ | |
440 | struct r600_ih { | |
4c788679 | 441 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
442 | volatile uint32_t *ring; |
443 | unsigned rptr; | |
444 | unsigned wptr; | |
445 | unsigned wptr_old; | |
446 | unsigned ring_size; | |
447 | uint64_t gpu_addr; | |
d8f60cfc AD |
448 | uint32_t ptr_mask; |
449 | spinlock_t lock; | |
450 | bool enabled; | |
451 | }; | |
452 | ||
3ce0a23d | 453 | struct r600_blit { |
ff82f052 | 454 | struct mutex mutex; |
4c788679 | 455 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
456 | u64 shader_gpu_addr; |
457 | u32 vs_offset, ps_offset; | |
458 | u32 state_offset; | |
459 | u32 state_len; | |
460 | u32 vb_used, vb_total; | |
461 | struct radeon_ib *vb_ib; | |
462 | }; | |
463 | ||
771fe6b9 JG |
464 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
465 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
466 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
467 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
468 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
469 | int radeon_ib_test(struct radeon_device *rdev); | |
9f93ed39 | 470 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
771fe6b9 JG |
471 | /* Ring access between begin & end cannot sleep */ |
472 | void radeon_ring_free_size(struct radeon_device *rdev); | |
91700f3c | 473 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
771fe6b9 | 474 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
91700f3c | 475 | void radeon_ring_commit(struct radeon_device *rdev); |
771fe6b9 JG |
476 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
477 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
478 | int radeon_ring_test(struct radeon_device *rdev); | |
479 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
480 | void radeon_ring_fini(struct radeon_device *rdev); | |
481 | ||
482 | ||
483 | /* | |
484 | * CS. | |
485 | */ | |
486 | struct radeon_cs_reloc { | |
487 | struct drm_gem_object *gobj; | |
4c788679 JG |
488 | struct radeon_bo *robj; |
489 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
490 | uint32_t handle; |
491 | uint32_t flags; | |
492 | }; | |
493 | ||
494 | struct radeon_cs_chunk { | |
495 | uint32_t chunk_id; | |
496 | uint32_t length_dw; | |
513bcb46 DA |
497 | int kpage_idx[2]; |
498 | uint32_t *kpage[2]; | |
771fe6b9 | 499 | uint32_t *kdata; |
513bcb46 DA |
500 | void __user *user_ptr; |
501 | int last_copied_page; | |
502 | int last_page_index; | |
771fe6b9 JG |
503 | }; |
504 | ||
505 | struct radeon_cs_parser { | |
c8c15ff1 | 506 | struct device *dev; |
771fe6b9 JG |
507 | struct radeon_device *rdev; |
508 | struct drm_file *filp; | |
509 | /* chunks */ | |
510 | unsigned nchunks; | |
511 | struct radeon_cs_chunk *chunks; | |
512 | uint64_t *chunks_array; | |
513 | /* IB */ | |
514 | unsigned idx; | |
515 | /* relocations */ | |
516 | unsigned nrelocs; | |
517 | struct radeon_cs_reloc *relocs; | |
518 | struct radeon_cs_reloc **relocs_ptr; | |
519 | struct list_head validated; | |
520 | /* indices of various chunks */ | |
521 | int chunk_ib_idx; | |
522 | int chunk_relocs_idx; | |
523 | struct radeon_ib *ib; | |
524 | void *track; | |
3ce0a23d | 525 | unsigned family; |
513bcb46 | 526 | int parser_error; |
771fe6b9 JG |
527 | }; |
528 | ||
513bcb46 DA |
529 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
530 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
531 | ||
532 | ||
533 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
534 | { | |
535 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
536 | u32 pg_idx, pg_offset; | |
537 | u32 idx_value = 0; | |
538 | int new_page; | |
539 | ||
540 | pg_idx = (idx * 4) / PAGE_SIZE; | |
541 | pg_offset = (idx * 4) % PAGE_SIZE; | |
542 | ||
543 | if (ibc->kpage_idx[0] == pg_idx) | |
544 | return ibc->kpage[0][pg_offset/4]; | |
545 | if (ibc->kpage_idx[1] == pg_idx) | |
546 | return ibc->kpage[1][pg_offset/4]; | |
547 | ||
548 | new_page = radeon_cs_update_pages(p, pg_idx); | |
549 | if (new_page < 0) { | |
550 | p->parser_error = new_page; | |
551 | return 0; | |
552 | } | |
553 | ||
554 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
555 | return idx_value; | |
556 | } | |
557 | ||
771fe6b9 JG |
558 | struct radeon_cs_packet { |
559 | unsigned idx; | |
560 | unsigned type; | |
561 | unsigned reg; | |
562 | unsigned opcode; | |
563 | int count; | |
564 | unsigned one_reg_wr; | |
565 | }; | |
566 | ||
567 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
568 | struct radeon_cs_packet *pkt, | |
569 | unsigned idx, unsigned reg); | |
570 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
571 | struct radeon_cs_packet *pkt); | |
572 | ||
573 | ||
574 | /* | |
575 | * AGP | |
576 | */ | |
577 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 578 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 579 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
580 | void radeon_agp_fini(struct radeon_device *rdev); |
581 | ||
582 | ||
583 | /* | |
584 | * Writeback | |
585 | */ | |
586 | struct radeon_wb { | |
4c788679 | 587 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
588 | volatile uint32_t *wb; |
589 | uint64_t gpu_addr; | |
590 | }; | |
591 | ||
c93bb85b JG |
592 | /** |
593 | * struct radeon_pm - power management datas | |
594 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
595 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
596 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
597 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
598 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
599 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
600 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
601 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
602 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
603 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
604 | * @needed_bandwidth: current bandwidth needs | |
605 | * | |
606 | * It keeps track of various data needed to take powermanagement decision. | |
607 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
608 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
609 | * (type of memory, bus size, efficiency, ...) | |
610 | */ | |
ce8f5370 AD |
611 | |
612 | enum radeon_pm_method { | |
613 | PM_METHOD_PROFILE, | |
614 | PM_METHOD_DYNPM, | |
615 | }; | |
616 | ||
617 | enum radeon_dynpm_state { | |
618 | DYNPM_STATE_DISABLED, | |
619 | DYNPM_STATE_MINIMUM, | |
620 | DYNPM_STATE_PAUSED, | |
621 | DYNPM_STATE_ACTIVE | |
c913e23a | 622 | }; |
ce8f5370 AD |
623 | enum radeon_dynpm_action { |
624 | DYNPM_ACTION_NONE, | |
625 | DYNPM_ACTION_MINIMUM, | |
626 | DYNPM_ACTION_DOWNCLOCK, | |
627 | DYNPM_ACTION_UPCLOCK, | |
628 | DYNPM_ACTION_DEFAULT | |
c913e23a | 629 | }; |
56278a8e AD |
630 | |
631 | enum radeon_voltage_type { | |
632 | VOLTAGE_NONE = 0, | |
633 | VOLTAGE_GPIO, | |
634 | VOLTAGE_VDDC, | |
635 | VOLTAGE_SW | |
636 | }; | |
637 | ||
0ec0e74f AD |
638 | enum radeon_pm_state_type { |
639 | POWER_STATE_TYPE_DEFAULT, | |
640 | POWER_STATE_TYPE_POWERSAVE, | |
641 | POWER_STATE_TYPE_BATTERY, | |
642 | POWER_STATE_TYPE_BALANCED, | |
643 | POWER_STATE_TYPE_PERFORMANCE, | |
644 | }; | |
645 | ||
ce8f5370 AD |
646 | enum radeon_pm_profile_type { |
647 | PM_PROFILE_DEFAULT, | |
648 | PM_PROFILE_AUTO, | |
649 | PM_PROFILE_LOW, | |
650 | PM_PROFILE_HIGH, | |
651 | }; | |
652 | ||
653 | #define PM_PROFILE_DEFAULT_IDX 0 | |
654 | #define PM_PROFILE_LOW_SH_IDX 1 | |
655 | #define PM_PROFILE_HIGH_SH_IDX 2 | |
656 | #define PM_PROFILE_LOW_MH_IDX 3 | |
657 | #define PM_PROFILE_HIGH_MH_IDX 4 | |
658 | #define PM_PROFILE_MAX 5 | |
659 | ||
660 | struct radeon_pm_profile { | |
661 | int dpms_off_ps_idx; | |
662 | int dpms_on_ps_idx; | |
663 | int dpms_off_cm_idx; | |
664 | int dpms_on_cm_idx; | |
516d0e46 AD |
665 | }; |
666 | ||
56278a8e AD |
667 | struct radeon_voltage { |
668 | enum radeon_voltage_type type; | |
669 | /* gpio voltage */ | |
670 | struct radeon_gpio_rec gpio; | |
671 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
672 | bool active_high; /* voltage drop is active when bit is high */ | |
673 | /* VDDC voltage */ | |
674 | u8 vddc_id; /* index into vddc voltage table */ | |
675 | u8 vddci_id; /* index into vddci voltage table */ | |
676 | bool vddci_enabled; | |
677 | /* r6xx+ sw */ | |
678 | u32 voltage; | |
679 | }; | |
680 | ||
d7311171 AD |
681 | /* clock mode flags */ |
682 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
683 | ||
56278a8e AD |
684 | struct radeon_pm_clock_info { |
685 | /* memory clock */ | |
686 | u32 mclk; | |
687 | /* engine clock */ | |
688 | u32 sclk; | |
689 | /* voltage info */ | |
690 | struct radeon_voltage voltage; | |
d7311171 | 691 | /* standardized clock flags */ |
56278a8e AD |
692 | u32 flags; |
693 | }; | |
694 | ||
a48b9b4e | 695 | /* state flags */ |
d7311171 | 696 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 697 | |
56278a8e | 698 | struct radeon_power_state { |
0ec0e74f | 699 | enum radeon_pm_state_type type; |
56278a8e AD |
700 | /* XXX: use a define for num clock modes */ |
701 | struct radeon_pm_clock_info clock_info[8]; | |
702 | /* number of valid clock modes in this power state */ | |
703 | int num_clock_modes; | |
56278a8e | 704 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
705 | /* standardized state flags */ |
706 | u32 flags; | |
79daedc9 AD |
707 | u32 misc; /* vbios specific flags */ |
708 | u32 misc2; /* vbios specific flags */ | |
709 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
710 | }; |
711 | ||
27459324 RM |
712 | /* |
713 | * Some modes are overclocked by very low value, accept them | |
714 | */ | |
715 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
716 | ||
c93bb85b | 717 | struct radeon_pm { |
c913e23a | 718 | struct mutex mutex; |
a48b9b4e AD |
719 | u32 active_crtcs; |
720 | int active_crtc_count; | |
c913e23a | 721 | int req_vblank; |
839461d3 | 722 | bool vblank_sync; |
2031f77c | 723 | bool gui_idle; |
c93bb85b JG |
724 | fixed20_12 max_bandwidth; |
725 | fixed20_12 igp_sideport_mclk; | |
726 | fixed20_12 igp_system_mclk; | |
727 | fixed20_12 igp_ht_link_clk; | |
728 | fixed20_12 igp_ht_link_width; | |
729 | fixed20_12 k8_bandwidth; | |
730 | fixed20_12 sideport_bandwidth; | |
731 | fixed20_12 ht_bandwidth; | |
732 | fixed20_12 core_bandwidth; | |
733 | fixed20_12 sclk; | |
f47299c5 | 734 | fixed20_12 mclk; |
c93bb85b | 735 | fixed20_12 needed_bandwidth; |
56278a8e AD |
736 | /* XXX: use a define for num power modes */ |
737 | struct radeon_power_state power_state[8]; | |
738 | /* number of valid power states */ | |
739 | int num_power_states; | |
a48b9b4e AD |
740 | int current_power_state_index; |
741 | int current_clock_mode_index; | |
742 | int requested_power_state_index; | |
743 | int requested_clock_mode_index; | |
744 | int default_power_state_index; | |
745 | u32 current_sclk; | |
746 | u32 current_mclk; | |
29fb52ca | 747 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
748 | /* selected pm method */ |
749 | enum radeon_pm_method pm_method; | |
750 | /* dynpm power management */ | |
751 | struct delayed_work dynpm_idle_work; | |
752 | enum radeon_dynpm_state dynpm_state; | |
753 | enum radeon_dynpm_action dynpm_planned_action; | |
754 | unsigned long dynpm_action_timeout; | |
755 | bool dynpm_can_upclock; | |
756 | bool dynpm_can_downclock; | |
757 | /* profile-based power management */ | |
758 | enum radeon_pm_profile_type profile; | |
759 | int profile_index; | |
760 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
c93bb85b JG |
761 | }; |
762 | ||
771fe6b9 JG |
763 | |
764 | /* | |
765 | * Benchmarking | |
766 | */ | |
767 | void radeon_benchmark(struct radeon_device *rdev); | |
768 | ||
769 | ||
ecc0b326 MD |
770 | /* |
771 | * Testing | |
772 | */ | |
773 | void radeon_test_moves(struct radeon_device *rdev); | |
774 | ||
775 | ||
771fe6b9 JG |
776 | /* |
777 | * Debugfs | |
778 | */ | |
779 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
780 | struct drm_info_list *files, | |
781 | unsigned nfiles); | |
782 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
783 | |
784 | ||
785 | /* | |
786 | * ASIC specific functions. | |
787 | */ | |
788 | struct radeon_asic { | |
068a117c | 789 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
790 | void (*fini)(struct radeon_device *rdev); |
791 | int (*resume)(struct radeon_device *rdev); | |
792 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 793 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
225758d8 | 794 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
a2d07b74 | 795 | int (*asic_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
796 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
797 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
798 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
799 | void (*cp_fini)(struct radeon_device *rdev); | |
800 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 801 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 802 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
803 | int (*ring_test)(struct radeon_device *rdev); |
804 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
805 | int (*irq_set)(struct radeon_device *rdev); |
806 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 807 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
808 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
809 | int (*cs_parse)(struct radeon_cs_parser *p); | |
810 | int (*copy_blit)(struct radeon_device *rdev, | |
811 | uint64_t src_offset, | |
812 | uint64_t dst_offset, | |
813 | unsigned num_pages, | |
814 | struct radeon_fence *fence); | |
815 | int (*copy_dma)(struct radeon_device *rdev, | |
816 | uint64_t src_offset, | |
817 | uint64_t dst_offset, | |
818 | unsigned num_pages, | |
819 | struct radeon_fence *fence); | |
820 | int (*copy)(struct radeon_device *rdev, | |
821 | uint64_t src_offset, | |
822 | uint64_t dst_offset, | |
823 | unsigned num_pages, | |
824 | struct radeon_fence *fence); | |
7433874e | 825 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 826 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 827 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 | 828 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
c836a412 | 829 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
771fe6b9 JG |
830 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
831 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
832 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
833 | uint32_t tiling_flags, uint32_t pitch, | |
834 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 835 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
c93bb85b | 836 | void (*bandwidth_update)(struct radeon_device *rdev); |
429770b3 AD |
837 | void (*hpd_init)(struct radeon_device *rdev); |
838 | void (*hpd_fini)(struct radeon_device *rdev); | |
839 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
840 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
062b389c JG |
841 | /* ioctl hw specific callback. Some hw might want to perform special |
842 | * operation on specific ioctl. For instance on wait idle some hw | |
843 | * might want to perform and HDP flush through MMIO as it seems that | |
844 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
845 | * through ring. | |
846 | */ | |
847 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
def9ba9c | 848 | bool (*gui_idle)(struct radeon_device *rdev); |
ce8f5370 | 849 | /* power management */ |
49e02b73 AD |
850 | void (*pm_misc)(struct radeon_device *rdev); |
851 | void (*pm_prepare)(struct radeon_device *rdev); | |
852 | void (*pm_finish)(struct radeon_device *rdev); | |
ce8f5370 AD |
853 | void (*pm_init_profile)(struct radeon_device *rdev); |
854 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); | |
771fe6b9 JG |
855 | }; |
856 | ||
21f9a437 JG |
857 | /* |
858 | * Asic structures | |
859 | */ | |
225758d8 JG |
860 | struct r100_gpu_lockup { |
861 | unsigned long last_jiffies; | |
862 | u32 last_cp_rptr; | |
863 | }; | |
864 | ||
551ebd83 | 865 | struct r100_asic { |
225758d8 JG |
866 | const unsigned *reg_safe_bm; |
867 | unsigned reg_safe_bm_size; | |
868 | u32 hdp_cntl; | |
869 | struct r100_gpu_lockup lockup; | |
551ebd83 DA |
870 | }; |
871 | ||
21f9a437 | 872 | struct r300_asic { |
225758d8 JG |
873 | const unsigned *reg_safe_bm; |
874 | unsigned reg_safe_bm_size; | |
875 | u32 resync_scratch; | |
876 | u32 hdp_cntl; | |
877 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
878 | }; |
879 | ||
880 | struct r600_asic { | |
225758d8 JG |
881 | unsigned max_pipes; |
882 | unsigned max_tile_pipes; | |
883 | unsigned max_simds; | |
884 | unsigned max_backends; | |
885 | unsigned max_gprs; | |
886 | unsigned max_threads; | |
887 | unsigned max_stack_entries; | |
888 | unsigned max_hw_contexts; | |
889 | unsigned max_gs_threads; | |
890 | unsigned sx_max_export_size; | |
891 | unsigned sx_max_export_pos_size; | |
892 | unsigned sx_max_export_smx_size; | |
893 | unsigned sq_num_cf_insts; | |
894 | unsigned tiling_nbanks; | |
895 | unsigned tiling_npipes; | |
896 | unsigned tiling_group_size; | |
897 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
898 | }; |
899 | ||
900 | struct rv770_asic { | |
225758d8 JG |
901 | unsigned max_pipes; |
902 | unsigned max_tile_pipes; | |
903 | unsigned max_simds; | |
904 | unsigned max_backends; | |
905 | unsigned max_gprs; | |
906 | unsigned max_threads; | |
907 | unsigned max_stack_entries; | |
908 | unsigned max_hw_contexts; | |
909 | unsigned max_gs_threads; | |
910 | unsigned sx_max_export_size; | |
911 | unsigned sx_max_export_pos_size; | |
912 | unsigned sx_max_export_smx_size; | |
913 | unsigned sq_num_cf_insts; | |
914 | unsigned sx_num_of_sets; | |
915 | unsigned sc_prim_fifo_size; | |
916 | unsigned sc_hiz_tile_fifo_size; | |
917 | unsigned sc_earlyz_tile_fifo_fize; | |
918 | unsigned tiling_nbanks; | |
919 | unsigned tiling_npipes; | |
920 | unsigned tiling_group_size; | |
921 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
922 | }; |
923 | ||
32fcdbf4 AD |
924 | struct evergreen_asic { |
925 | unsigned num_ses; | |
926 | unsigned max_pipes; | |
927 | unsigned max_tile_pipes; | |
928 | unsigned max_simds; | |
929 | unsigned max_backends; | |
930 | unsigned max_gprs; | |
931 | unsigned max_threads; | |
932 | unsigned max_stack_entries; | |
933 | unsigned max_hw_contexts; | |
934 | unsigned max_gs_threads; | |
935 | unsigned sx_max_export_size; | |
936 | unsigned sx_max_export_pos_size; | |
937 | unsigned sx_max_export_smx_size; | |
938 | unsigned sq_num_cf_insts; | |
939 | unsigned sx_num_of_sets; | |
940 | unsigned sc_prim_fifo_size; | |
941 | unsigned sc_hiz_tile_fifo_size; | |
942 | unsigned sc_earlyz_tile_fifo_size; | |
943 | unsigned tiling_nbanks; | |
944 | unsigned tiling_npipes; | |
945 | unsigned tiling_group_size; | |
946 | }; | |
947 | ||
068a117c JG |
948 | union radeon_asic_config { |
949 | struct r300_asic r300; | |
551ebd83 | 950 | struct r100_asic r100; |
3ce0a23d JG |
951 | struct r600_asic r600; |
952 | struct rv770_asic rv770; | |
32fcdbf4 | 953 | struct evergreen_asic evergreen; |
068a117c JG |
954 | }; |
955 | ||
0a10c851 DV |
956 | /* |
957 | * asic initizalization from radeon_asic.c | |
958 | */ | |
959 | void radeon_agp_disable(struct radeon_device *rdev); | |
960 | int radeon_asic_init(struct radeon_device *rdev); | |
961 | ||
771fe6b9 JG |
962 | |
963 | /* | |
964 | * IOCTL. | |
965 | */ | |
966 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
967 | struct drm_file *filp); | |
968 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
969 | struct drm_file *filp); | |
970 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
971 | struct drm_file *file_priv); | |
972 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
973 | struct drm_file *file_priv); | |
974 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
975 | struct drm_file *file_priv); | |
976 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
977 | struct drm_file *file_priv); | |
978 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
979 | struct drm_file *filp); | |
980 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
981 | struct drm_file *filp); | |
982 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
983 | struct drm_file *filp); | |
984 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
985 | struct drm_file *filp); | |
986 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
987 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
988 | struct drm_file *filp); | |
989 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
990 | struct drm_file *filp); | |
771fe6b9 JG |
991 | |
992 | ||
993 | /* | |
994 | * Core structure, functions and helpers. | |
995 | */ | |
996 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
997 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
998 | ||
999 | struct radeon_device { | |
9f022ddf | 1000 | struct device *dev; |
771fe6b9 JG |
1001 | struct drm_device *ddev; |
1002 | struct pci_dev *pdev; | |
1003 | /* ASIC */ | |
068a117c | 1004 | union radeon_asic_config config; |
771fe6b9 JG |
1005 | enum radeon_family family; |
1006 | unsigned long flags; | |
1007 | int usec_timeout; | |
1008 | enum radeon_pll_errata pll_errata; | |
1009 | int num_gb_pipes; | |
f779b3e5 | 1010 | int num_z_pipes; |
771fe6b9 JG |
1011 | int disp_priority; |
1012 | /* BIOS */ | |
1013 | uint8_t *bios; | |
1014 | bool is_atom_bios; | |
1015 | uint16_t bios_header_start; | |
4c788679 | 1016 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1017 | /* Register mmio */ |
4c9bc75c DA |
1018 | resource_size_t rmmio_base; |
1019 | resource_size_t rmmio_size; | |
771fe6b9 | 1020 | void *rmmio; |
771fe6b9 JG |
1021 | radeon_rreg_t mc_rreg; |
1022 | radeon_wreg_t mc_wreg; | |
1023 | radeon_rreg_t pll_rreg; | |
1024 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1025 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1026 | radeon_rreg_t pciep_rreg; |
1027 | radeon_wreg_t pciep_wreg; | |
1028 | struct radeon_clock clock; | |
1029 | struct radeon_mc mc; | |
1030 | struct radeon_gart gart; | |
1031 | struct radeon_mode_info mode_info; | |
1032 | struct radeon_scratch scratch; | |
1033 | struct radeon_mman mman; | |
1034 | struct radeon_fence_driver fence_drv; | |
1035 | struct radeon_cp cp; | |
1036 | struct radeon_ib_pool ib_pool; | |
1037 | struct radeon_irq irq; | |
1038 | struct radeon_asic *asic; | |
1039 | struct radeon_gem gem; | |
c93bb85b | 1040 | struct radeon_pm pm; |
f657c2a7 | 1041 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
1042 | struct mutex cs_mutex; |
1043 | struct radeon_wb wb; | |
3ce0a23d | 1044 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1045 | bool gpu_lockup; |
1046 | bool shutdown; | |
1047 | bool suspend; | |
ad49f501 | 1048 | bool need_dma32; |
733289c2 | 1049 | bool accel_working; |
e024e110 | 1050 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1051 | const struct firmware *me_fw; /* all family ME firmware */ |
1052 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1053 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
3ce0a23d | 1054 | struct r600_blit r600_blit; |
3e5cb98d | 1055 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1056 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 AD |
1057 | struct workqueue_struct *wq; |
1058 | struct work_struct hotplug_work; | |
18917b60 | 1059 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1060 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
5876dd24 | 1061 | struct mutex vram_mutex; |
dafc3bd5 CK |
1062 | |
1063 | /* audio stuff */ | |
1064 | struct timer_list audio_timer; | |
1065 | int audio_channels; | |
1066 | int audio_rate; | |
1067 | int audio_bits_per_sample; | |
1068 | uint8_t audio_status_bits; | |
1069 | uint8_t audio_category_code; | |
6a9ee8af DA |
1070 | |
1071 | bool powered_down; | |
ce8f5370 | 1072 | struct notifier_block acpi_nb; |
771fe6b9 JG |
1073 | }; |
1074 | ||
1075 | int radeon_device_init(struct radeon_device *rdev, | |
1076 | struct drm_device *ddev, | |
1077 | struct pci_dev *pdev, | |
1078 | uint32_t flags); | |
1079 | void radeon_device_fini(struct radeon_device *rdev); | |
1080 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1081 | ||
3ce0a23d JG |
1082 | /* r600 blit */ |
1083 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
1084 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
1085 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
1086 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
1087 | int size_bytes); | |
1088 | ||
de1b2898 DA |
1089 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1090 | { | |
07bec2df | 1091 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1092 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1093 | else { | |
1094 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1095 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1100 | { | |
07bec2df | 1101 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1102 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1103 | else { | |
1104 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1105 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1106 | } | |
1107 | } | |
1108 | ||
4c788679 JG |
1109 | /* |
1110 | * Cast helper | |
1111 | */ | |
1112 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1113 | |
1114 | /* | |
1115 | * Registers read & write functions. | |
1116 | */ | |
1117 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
1118 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 1119 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1120 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1121 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1122 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1123 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1124 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1125 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1126 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1127 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1128 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1129 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1130 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1131 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1132 | #define WREG32_P(reg, val, mask) \ |
1133 | do { \ | |
1134 | uint32_t tmp_ = RREG32(reg); \ | |
1135 | tmp_ &= (mask); \ | |
1136 | tmp_ |= ((val) & ~(mask)); \ | |
1137 | WREG32(reg, tmp_); \ | |
1138 | } while (0) | |
1139 | #define WREG32_PLL_P(reg, val, mask) \ | |
1140 | do { \ | |
1141 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1142 | tmp_ &= (mask); \ | |
1143 | tmp_ |= ((val) & ~(mask)); \ | |
1144 | WREG32_PLL(reg, tmp_); \ | |
1145 | } while (0) | |
3ce0a23d | 1146 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
771fe6b9 | 1147 | |
de1b2898 DA |
1148 | /* |
1149 | * Indirect registers accessor | |
1150 | */ | |
1151 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1152 | { | |
1153 | uint32_t r; | |
1154 | ||
1155 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1156 | r = RREG32(RADEON_PCIE_DATA); | |
1157 | return r; | |
1158 | } | |
1159 | ||
1160 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1161 | { | |
1162 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1163 | WREG32(RADEON_PCIE_DATA, (v)); | |
1164 | } | |
1165 | ||
771fe6b9 JG |
1166 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1167 | ||
1168 | ||
1169 | /* | |
1170 | * ASICs helpers. | |
1171 | */ | |
b995e433 DA |
1172 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1173 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1174 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1175 | (rdev->family == CHIP_RV200) || \ | |
1176 | (rdev->family == CHIP_RS100) || \ | |
1177 | (rdev->family == CHIP_RS200) || \ | |
1178 | (rdev->family == CHIP_RV250) || \ | |
1179 | (rdev->family == CHIP_RV280) || \ | |
1180 | (rdev->family == CHIP_RS300)) | |
1181 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1182 | (rdev->family == CHIP_RV350) || \ | |
1183 | (rdev->family == CHIP_R350) || \ | |
1184 | (rdev->family == CHIP_RV380) || \ | |
1185 | (rdev->family == CHIP_R420) || \ | |
1186 | (rdev->family == CHIP_R423) || \ | |
1187 | (rdev->family == CHIP_RV410) || \ | |
1188 | (rdev->family == CHIP_RS400) || \ | |
1189 | (rdev->family == CHIP_RS480)) | |
1190 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
1191 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) | |
1192 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1193 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
771fe6b9 JG |
1194 | |
1195 | /* | |
1196 | * BIOS helpers. | |
1197 | */ | |
1198 | #define RBIOS8(i) (rdev->bios[i]) | |
1199 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1200 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1201 | ||
1202 | int radeon_combios_init(struct radeon_device *rdev); | |
1203 | void radeon_combios_fini(struct radeon_device *rdev); | |
1204 | int radeon_atombios_init(struct radeon_device *rdev); | |
1205 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1206 | ||
1207 | ||
1208 | /* | |
1209 | * RING helpers. | |
1210 | */ | |
771fe6b9 JG |
1211 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1212 | { | |
1213 | #if DRM_DEBUG_CODE | |
1214 | if (rdev->cp.count_dw <= 0) { | |
1215 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
1216 | } | |
1217 | #endif | |
1218 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
1219 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
1220 | rdev->cp.count_dw--; | |
1221 | rdev->cp.ring_free_dw--; | |
1222 | } | |
1223 | ||
1224 | ||
1225 | /* | |
1226 | * ASICs macro. | |
1227 | */ | |
068a117c | 1228 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1229 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1230 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1231 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 1232 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 1233 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
225758d8 | 1234 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
a2d07b74 | 1235 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
771fe6b9 JG |
1236 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1237 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 1238 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 1239 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
1240 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1241 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
1242 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1243 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 1244 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
1245 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1246 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
1247 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1248 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1249 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1250 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1251 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1252 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
c836a412 | 1253 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
771fe6b9 JG |
1254 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1255 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1256 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1257 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1258 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
429770b3 AD |
1259 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1260 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1261 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1262 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
def9ba9c | 1263 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a424816f AD |
1264 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
1265 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) | |
1266 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) | |
ce8f5370 AD |
1267 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
1268 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) | |
771fe6b9 | 1269 | |
6cf8a3f5 | 1270 | /* Common functions */ |
700a0cc0 | 1271 | /* AGP */ |
90aca4d2 | 1272 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1273 | extern void radeon_agp_disable(struct radeon_device *rdev); |
4aac0473 | 1274 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
82568565 | 1275 | extern void radeon_gart_restore(struct radeon_device *rdev); |
21f9a437 JG |
1276 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1277 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1278 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1279 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1280 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1281 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 JG |
1282 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1283 | extern void radeon_clocks_fini(struct radeon_device *rdev); | |
1284 | extern void radeon_scratch_init(struct radeon_device *rdev); | |
1285 | extern void radeon_surface_init(struct radeon_device *rdev); | |
1286 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1287 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1288 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1289 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1290 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1291 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1292 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1293 | extern int radeon_resume_kms(struct drm_device *dev); |
1294 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
6cf8a3f5 | 1295 | |
a18d7ea1 | 1296 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
225758d8 JG |
1297 | extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
1298 | extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); | |
9f022ddf | 1299 | |
d4550907 JG |
1300 | /* rv200,rv250,rv280 */ |
1301 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
9f022ddf JG |
1302 | |
1303 | /* r300,r350,rv350,rv370,rv380 */ | |
1304 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1305 | extern void r300_mc_program(struct radeon_device *rdev); | |
d594e46a | 1306 | extern void r300_mc_init(struct radeon_device *rdev); |
ca6ffc64 JG |
1307 | extern void r300_clock_startup(struct radeon_device *rdev); |
1308 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1309 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1310 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1311 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1312 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1313 | |
905b6822 | 1314 | /* r420,r423,rv410 */ |
21f9a437 JG |
1315 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1316 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1317 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1318 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1319 | |
21f9a437 | 1320 | /* rv515 */ |
d39c3b89 JG |
1321 | struct rv515_mc_save { |
1322 | u32 d1vga_control; | |
1323 | u32 d2vga_control; | |
1324 | u32 vga_render_control; | |
1325 | u32 vga_hdp_control; | |
1326 | u32 d1crtc_control; | |
1327 | u32 d2crtc_control; | |
1328 | }; | |
21f9a437 | 1329 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1330 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1331 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1332 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1333 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1334 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1335 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1336 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1337 | |
3bc68535 JG |
1338 | /* rs400 */ |
1339 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1340 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1341 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1342 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1343 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1344 | ||
1345 | /* rs600 */ | |
1346 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1347 | extern int rs600_irq_set(struct radeon_device *rdev); |
1348 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1349 | |
21f9a437 JG |
1350 | /* rs690, rs740 */ |
1351 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1352 | struct drm_display_mode *mode1, | |
1353 | struct drm_display_mode *mode2); | |
1354 | ||
1355 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
d594e46a | 1356 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
21f9a437 JG |
1357 | extern bool r600_card_posted(struct radeon_device *rdev); |
1358 | extern void r600_cp_stop(struct radeon_device *rdev); | |
fe251e2f | 1359 | extern int r600_cp_start(struct radeon_device *rdev); |
21f9a437 JG |
1360 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1361 | extern int r600_cp_resume(struct radeon_device *rdev); | |
655efd3d | 1362 | extern void r600_cp_fini(struct radeon_device *rdev); |
21f9a437 | 1363 | extern int r600_count_pipe_bits(uint32_t val); |
21f9a437 | 1364 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
4aac0473 | 1365 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1366 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1367 | extern int r600_ib_test(struct radeon_device *rdev); | |
1368 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 | 1369 | extern void r600_wb_fini(struct radeon_device *rdev); |
81cc35bf JG |
1370 | extern int r600_wb_enable(struct radeon_device *rdev); |
1371 | extern void r600_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1372 | extern void r600_scratch_init(struct radeon_device *rdev); |
1373 | extern int r600_blit_init(struct radeon_device *rdev); | |
1374 | extern void r600_blit_fini(struct radeon_device *rdev); | |
d8f60cfc | 1375 | extern int r600_init_microcode(struct radeon_device *rdev); |
a2d07b74 | 1376 | extern int r600_asic_reset(struct radeon_device *rdev); |
d8f60cfc AD |
1377 | /* r600 irq */ |
1378 | extern int r600_irq_init(struct radeon_device *rdev); | |
1379 | extern void r600_irq_fini(struct radeon_device *rdev); | |
1380 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1381 | extern int r600_irq_set(struct radeon_device *rdev); | |
0c45249f | 1382 | extern void r600_irq_suspend(struct radeon_device *rdev); |
45f9a39b AD |
1383 | extern void r600_disable_interrupts(struct radeon_device *rdev); |
1384 | extern void r600_rlc_stop(struct radeon_device *rdev); | |
0c45249f | 1385 | /* r600 audio */ |
dafc3bd5 CK |
1386 | extern int r600_audio_init(struct radeon_device *rdev); |
1387 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); | |
1388 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | |
58bd0863 CK |
1389 | extern int r600_audio_channels(struct radeon_device *rdev); |
1390 | extern int r600_audio_bits_per_sample(struct radeon_device *rdev); | |
1391 | extern int r600_audio_rate(struct radeon_device *rdev); | |
1392 | extern uint8_t r600_audio_status_bits(struct radeon_device *rdev); | |
1393 | extern uint8_t r600_audio_category_code(struct radeon_device *rdev); | |
f2594933 | 1394 | extern void r600_audio_schedule_polling(struct radeon_device *rdev); |
58bd0863 CK |
1395 | extern void r600_audio_enable_polling(struct drm_encoder *encoder); |
1396 | extern void r600_audio_disable_polling(struct drm_encoder *encoder); | |
dafc3bd5 CK |
1397 | extern void r600_audio_fini(struct radeon_device *rdev); |
1398 | extern void r600_hdmi_init(struct drm_encoder *encoder); | |
2cd6218c RM |
1399 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1400 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 CK |
1401 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1402 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | |
58bd0863 | 1403 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
dafc3bd5 | 1404 | |
fe251e2f AD |
1405 | extern void r700_cp_stop(struct radeon_device *rdev); |
1406 | extern void r700_cp_fini(struct radeon_device *rdev); | |
0ca2ab52 AD |
1407 | extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
1408 | extern int evergreen_irq_set(struct radeon_device *rdev); | |
fe251e2f | 1409 | |
bcc1c2a1 AD |
1410 | /* evergreen */ |
1411 | struct evergreen_mc_save { | |
1412 | u32 vga_control[6]; | |
1413 | u32 vga_render_control; | |
1414 | u32 vga_hdp_control; | |
1415 | u32 crtc_control[6]; | |
1416 | }; | |
1417 | ||
4c788679 JG |
1418 | #include "radeon_object.h" |
1419 | ||
771fe6b9 | 1420 | #endif |