Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
3368ff0c | 97 | extern int radeon_lockup_timeout; |
771fe6b9 JG |
98 | |
99 | /* | |
100 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
101 | * symbol; | |
102 | */ | |
bb635567 JG |
103 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
104 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 105 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
106 | #define RADEON_IB_POOL_SIZE 16 |
107 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
108 | #define RADEONFB_CONN_LIMIT 4 | |
109 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 110 | |
1b37078b | 111 | /* max number of rings */ |
bb635567 JG |
112 | #define RADEON_NUM_RINGS 3 |
113 | ||
114 | /* fence seq are set to this number when signaled */ | |
115 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | |
1b37078b AD |
116 | |
117 | /* internal ring indices */ | |
118 | /* r1xx+ has gfx CP ring */ | |
bb635567 | 119 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
120 | |
121 | /* cayman has 2 compute CP rings */ | |
bb635567 JG |
122 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
123 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 124 | |
721604a1 | 125 | /* hardcode those limit for now */ |
bb635567 JG |
126 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
127 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 128 | |
771fe6b9 JG |
129 | /* |
130 | * Errata workarounds. | |
131 | */ | |
132 | enum radeon_pll_errata { | |
133 | CHIP_ERRATA_R300_CG = 0x00000001, | |
134 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
135 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
136 | }; | |
137 | ||
138 | ||
139 | struct radeon_device; | |
140 | ||
141 | ||
142 | /* | |
143 | * BIOS. | |
144 | */ | |
145 | bool radeon_get_bios(struct radeon_device *rdev); | |
146 | ||
147 | /* | |
3ce0a23d | 148 | * Dummy page |
771fe6b9 | 149 | */ |
3ce0a23d JG |
150 | struct radeon_dummy_page { |
151 | struct page *page; | |
152 | dma_addr_t addr; | |
153 | }; | |
154 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
155 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
156 | ||
771fe6b9 | 157 | |
3ce0a23d JG |
158 | /* |
159 | * Clocks | |
160 | */ | |
771fe6b9 JG |
161 | struct radeon_clock { |
162 | struct radeon_pll p1pll; | |
163 | struct radeon_pll p2pll; | |
bcc1c2a1 | 164 | struct radeon_pll dcpll; |
771fe6b9 JG |
165 | struct radeon_pll spll; |
166 | struct radeon_pll mpll; | |
167 | /* 10 Khz units */ | |
168 | uint32_t default_mclk; | |
169 | uint32_t default_sclk; | |
bcc1c2a1 AD |
170 | uint32_t default_dispclk; |
171 | uint32_t dp_extclk; | |
b20f9bef | 172 | uint32_t max_pixel_clock; |
771fe6b9 JG |
173 | }; |
174 | ||
7433874e RM |
175 | /* |
176 | * Power management | |
177 | */ | |
178 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 179 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 180 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
181 | void radeon_pm_suspend(struct radeon_device *rdev); |
182 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
183 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
184 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
8a83ec5e | 185 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
f892034a | 186 | void rs690_pm_info(struct radeon_device *rdev); |
20d391d7 AD |
187 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
188 | extern int rv770_get_temp(struct radeon_device *rdev); | |
189 | extern int evergreen_get_temp(struct radeon_device *rdev); | |
190 | extern int sumo_get_temp(struct radeon_device *rdev); | |
1bd47d2e | 191 | extern int si_get_temp(struct radeon_device *rdev); |
285484e2 JG |
192 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
193 | unsigned *bankh, unsigned *mtaspect, | |
194 | unsigned *tile_split); | |
3ce0a23d | 195 | |
771fe6b9 JG |
196 | /* |
197 | * Fences. | |
198 | */ | |
199 | struct radeon_fence_driver { | |
200 | uint32_t scratch_reg; | |
30eb77f4 JG |
201 | uint64_t gpu_addr; |
202 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
203 | /* sync_seq is protected by ring emission lock */ |
204 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 205 | atomic64_t last_seq; |
36abacae | 206 | unsigned long last_activity; |
0a0c7596 | 207 | bool initialized; |
771fe6b9 JG |
208 | }; |
209 | ||
210 | struct radeon_fence { | |
211 | struct radeon_device *rdev; | |
212 | struct kref kref; | |
771fe6b9 | 213 | /* protected by radeon_fence.lock */ |
bb635567 | 214 | uint64_t seq; |
7465280c | 215 | /* RB, DMA, etc. */ |
bb635567 | 216 | unsigned ring; |
771fe6b9 JG |
217 | }; |
218 | ||
30eb77f4 JG |
219 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
220 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 221 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
876dc9f3 | 222 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 223 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
224 | bool radeon_fence_signaled(struct radeon_fence *fence); |
225 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
8a47cc9e | 226 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
7ecc45e3 | 227 | void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
0085c950 JG |
228 | int radeon_fence_wait_any(struct radeon_device *rdev, |
229 | struct radeon_fence **fences, | |
230 | bool intr); | |
771fe6b9 JG |
231 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
232 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 233 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
234 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
235 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
236 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
237 | struct radeon_fence *b) | |
238 | { | |
239 | if (!a) { | |
240 | return b; | |
241 | } | |
242 | ||
243 | if (!b) { | |
244 | return a; | |
245 | } | |
246 | ||
247 | BUG_ON(a->ring != b->ring); | |
248 | ||
249 | if (a->seq > b->seq) { | |
250 | return a; | |
251 | } else { | |
252 | return b; | |
253 | } | |
254 | } | |
771fe6b9 | 255 | |
ee60e29f CK |
256 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
257 | struct radeon_fence *b) | |
258 | { | |
259 | if (!a) { | |
260 | return false; | |
261 | } | |
262 | ||
263 | if (!b) { | |
264 | return true; | |
265 | } | |
266 | ||
267 | BUG_ON(a->ring != b->ring); | |
268 | ||
269 | return a->seq < b->seq; | |
270 | } | |
271 | ||
e024e110 DA |
272 | /* |
273 | * Tiling registers | |
274 | */ | |
275 | struct radeon_surface_reg { | |
4c788679 | 276 | struct radeon_bo *bo; |
e024e110 DA |
277 | }; |
278 | ||
279 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
280 | |
281 | /* | |
4c788679 | 282 | * TTM. |
771fe6b9 | 283 | */ |
4c788679 JG |
284 | struct radeon_mman { |
285 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 286 | struct drm_global_reference mem_global_ref; |
4c788679 | 287 | struct ttm_bo_device bdev; |
0a0c7596 JG |
288 | bool mem_global_referenced; |
289 | bool initialized; | |
4c788679 JG |
290 | }; |
291 | ||
721604a1 JG |
292 | /* bo virtual address in a specific vm */ |
293 | struct radeon_bo_va { | |
294 | /* bo list is protected by bo being reserved */ | |
295 | struct list_head bo_list; | |
296 | /* vm list is protected by vm mutex */ | |
297 | struct list_head vm_list; | |
298 | /* constant after initialization */ | |
299 | struct radeon_vm *vm; | |
300 | struct radeon_bo *bo; | |
301 | uint64_t soffset; | |
302 | uint64_t eoffset; | |
303 | uint32_t flags; | |
304 | bool valid; | |
305 | }; | |
306 | ||
4c788679 JG |
307 | struct radeon_bo { |
308 | /* Protected by gem.mutex */ | |
309 | struct list_head list; | |
310 | /* Protected by tbo.reserved */ | |
312ea8da JG |
311 | u32 placements[3]; |
312 | struct ttm_placement placement; | |
4c788679 JG |
313 | struct ttm_buffer_object tbo; |
314 | struct ttm_bo_kmap_obj kmap; | |
315 | unsigned pin_count; | |
316 | void *kptr; | |
317 | u32 tiling_flags; | |
318 | u32 pitch; | |
319 | int surface_reg; | |
721604a1 JG |
320 | /* list of all virtual address to which this bo |
321 | * is associated to | |
322 | */ | |
323 | struct list_head va; | |
4c788679 JG |
324 | /* Constant after initialization */ |
325 | struct radeon_device *rdev; | |
441921d5 | 326 | struct drm_gem_object gem_base; |
63bc620b DA |
327 | |
328 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
329 | int vmapping_count; | |
4c788679 | 330 | }; |
7e4d15d9 | 331 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 332 | |
4c788679 | 333 | struct radeon_bo_list { |
147666fb | 334 | struct ttm_validate_buffer tv; |
4c788679 | 335 | struct radeon_bo *bo; |
771fe6b9 JG |
336 | uint64_t gpu_offset; |
337 | unsigned rdomain; | |
338 | unsigned wdomain; | |
4c788679 | 339 | u32 tiling_flags; |
771fe6b9 JG |
340 | }; |
341 | ||
b15ba512 JG |
342 | /* sub-allocation manager, it has to be protected by another lock. |
343 | * By conception this is an helper for other part of the driver | |
344 | * like the indirect buffer or semaphore, which both have their | |
345 | * locking. | |
346 | * | |
347 | * Principe is simple, we keep a list of sub allocation in offset | |
348 | * order (first entry has offset == 0, last entry has the highest | |
349 | * offset). | |
350 | * | |
351 | * When allocating new object we first check if there is room at | |
352 | * the end total_size - (last_object_offset + last_object_size) >= | |
353 | * alloc_size. If so we allocate new object there. | |
354 | * | |
355 | * When there is not enough room at the end, we start waiting for | |
356 | * each sub object until we reach object_offset+object_size >= | |
357 | * alloc_size, this object then become the sub object we return. | |
358 | * | |
359 | * Alignment can't be bigger than page size. | |
360 | * | |
361 | * Hole are not considered for allocation to keep things simple. | |
362 | * Assumption is that there won't be hole (all object on same | |
363 | * alignment). | |
364 | */ | |
365 | struct radeon_sa_manager { | |
bfb38d35 | 366 | wait_queue_head_t wq; |
b15ba512 | 367 | struct radeon_bo *bo; |
c3b7fe8b CK |
368 | struct list_head *hole; |
369 | struct list_head flist[RADEON_NUM_RINGS]; | |
370 | struct list_head olist; | |
b15ba512 JG |
371 | unsigned size; |
372 | uint64_t gpu_addr; | |
373 | void *cpu_ptr; | |
374 | uint32_t domain; | |
375 | }; | |
376 | ||
377 | struct radeon_sa_bo; | |
378 | ||
379 | /* sub-allocation buffer */ | |
380 | struct radeon_sa_bo { | |
c3b7fe8b CK |
381 | struct list_head olist; |
382 | struct list_head flist; | |
b15ba512 | 383 | struct radeon_sa_manager *manager; |
e6661a96 CK |
384 | unsigned soffset; |
385 | unsigned eoffset; | |
557017a0 | 386 | struct radeon_fence *fence; |
b15ba512 JG |
387 | }; |
388 | ||
771fe6b9 JG |
389 | /* |
390 | * GEM objects. | |
391 | */ | |
392 | struct radeon_gem { | |
4c788679 | 393 | struct mutex mutex; |
771fe6b9 JG |
394 | struct list_head objects; |
395 | }; | |
396 | ||
397 | int radeon_gem_init(struct radeon_device *rdev); | |
398 | void radeon_gem_fini(struct radeon_device *rdev); | |
399 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
400 | int alignment, int initial_domain, |
401 | bool discardable, bool kernel, | |
402 | struct drm_gem_object **obj); | |
771fe6b9 | 403 | |
ff72145b DA |
404 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
405 | struct drm_device *dev, | |
406 | struct drm_mode_create_dumb *args); | |
407 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
408 | struct drm_device *dev, | |
409 | uint32_t handle, uint64_t *offset_p); | |
410 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
411 | struct drm_device *dev, | |
412 | uint32_t handle); | |
771fe6b9 | 413 | |
c1341e52 JG |
414 | /* |
415 | * Semaphores. | |
416 | */ | |
c1341e52 JG |
417 | /* everything here is constant */ |
418 | struct radeon_semaphore { | |
a8c05940 JG |
419 | struct radeon_sa_bo *sa_bo; |
420 | signed waiters; | |
c1341e52 | 421 | uint64_t gpu_addr; |
c1341e52 JG |
422 | }; |
423 | ||
c1341e52 JG |
424 | int radeon_semaphore_create(struct radeon_device *rdev, |
425 | struct radeon_semaphore **semaphore); | |
426 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, | |
427 | struct radeon_semaphore *semaphore); | |
428 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, | |
429 | struct radeon_semaphore *semaphore); | |
8f676c4c CK |
430 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
431 | struct radeon_semaphore *semaphore, | |
220907d9 | 432 | int signaler, int waiter); |
c1341e52 | 433 | void radeon_semaphore_free(struct radeon_device *rdev, |
220907d9 | 434 | struct radeon_semaphore **semaphore, |
a8c05940 | 435 | struct radeon_fence *fence); |
c1341e52 | 436 | |
771fe6b9 JG |
437 | /* |
438 | * GART structures, functions & helpers | |
439 | */ | |
440 | struct radeon_mc; | |
441 | ||
a77f1718 | 442 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 443 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 444 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 445 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 446 | |
771fe6b9 JG |
447 | struct radeon_gart { |
448 | dma_addr_t table_addr; | |
c9a1be96 JG |
449 | struct radeon_bo *robj; |
450 | void *ptr; | |
771fe6b9 JG |
451 | unsigned num_gpu_pages; |
452 | unsigned num_cpu_pages; | |
453 | unsigned table_size; | |
771fe6b9 JG |
454 | struct page **pages; |
455 | dma_addr_t *pages_addr; | |
456 | bool ready; | |
457 | }; | |
458 | ||
459 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
460 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
461 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
462 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
463 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
464 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
465 | int radeon_gart_init(struct radeon_device *rdev); |
466 | void radeon_gart_fini(struct radeon_device *rdev); | |
467 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
468 | int pages); | |
469 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
470 | int pages, struct page **pagelist, |
471 | dma_addr_t *dma_addr); | |
c9a1be96 | 472 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
473 | |
474 | ||
475 | /* | |
476 | * GPU MC structures, functions & helpers | |
477 | */ | |
478 | struct radeon_mc { | |
479 | resource_size_t aper_size; | |
480 | resource_size_t aper_base; | |
481 | resource_size_t agp_base; | |
7a50f01a DA |
482 | /* for some chips with <= 32MB we need to lie |
483 | * about vram size near mc fb location */ | |
3ce0a23d | 484 | u64 mc_vram_size; |
d594e46a | 485 | u64 visible_vram_size; |
3ce0a23d JG |
486 | u64 gtt_size; |
487 | u64 gtt_start; | |
488 | u64 gtt_end; | |
3ce0a23d JG |
489 | u64 vram_start; |
490 | u64 vram_end; | |
771fe6b9 | 491 | unsigned vram_width; |
3ce0a23d | 492 | u64 real_vram_size; |
771fe6b9 JG |
493 | int vram_mtrr; |
494 | bool vram_is_ddr; | |
d594e46a | 495 | bool igp_sideport_enabled; |
8d369bb1 | 496 | u64 gtt_base_align; |
771fe6b9 JG |
497 | }; |
498 | ||
06b6476d AD |
499 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
500 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
501 | |
502 | /* | |
503 | * GPU scratch registers structures, functions & helpers | |
504 | */ | |
505 | struct radeon_scratch { | |
506 | unsigned num_reg; | |
724c80e1 | 507 | uint32_t reg_base; |
771fe6b9 JG |
508 | bool free[32]; |
509 | uint32_t reg[32]; | |
510 | }; | |
511 | ||
512 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
513 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
514 | ||
515 | ||
516 | /* | |
517 | * IRQS. | |
518 | */ | |
6f34be50 AD |
519 | |
520 | struct radeon_unpin_work { | |
521 | struct work_struct work; | |
522 | struct radeon_device *rdev; | |
523 | int crtc_id; | |
524 | struct radeon_fence *fence; | |
525 | struct drm_pending_vblank_event *event; | |
526 | struct radeon_bo *old_rbo; | |
527 | u64 new_crtc_base; | |
528 | }; | |
529 | ||
530 | struct r500_irq_stat_regs { | |
531 | u32 disp_int; | |
f122c610 | 532 | u32 hdmi0_status; |
6f34be50 AD |
533 | }; |
534 | ||
535 | struct r600_irq_stat_regs { | |
536 | u32 disp_int; | |
537 | u32 disp_int_cont; | |
538 | u32 disp_int_cont2; | |
539 | u32 d1grph_int; | |
540 | u32 d2grph_int; | |
f122c610 AD |
541 | u32 hdmi0_status; |
542 | u32 hdmi1_status; | |
6f34be50 AD |
543 | }; |
544 | ||
545 | struct evergreen_irq_stat_regs { | |
546 | u32 disp_int; | |
547 | u32 disp_int_cont; | |
548 | u32 disp_int_cont2; | |
549 | u32 disp_int_cont3; | |
550 | u32 disp_int_cont4; | |
551 | u32 disp_int_cont5; | |
552 | u32 d1grph_int; | |
553 | u32 d2grph_int; | |
554 | u32 d3grph_int; | |
555 | u32 d4grph_int; | |
556 | u32 d5grph_int; | |
557 | u32 d6grph_int; | |
f122c610 AD |
558 | u32 afmt_status1; |
559 | u32 afmt_status2; | |
560 | u32 afmt_status3; | |
561 | u32 afmt_status4; | |
562 | u32 afmt_status5; | |
563 | u32 afmt_status6; | |
6f34be50 AD |
564 | }; |
565 | ||
566 | union radeon_irq_stat_regs { | |
567 | struct r500_irq_stat_regs r500; | |
568 | struct r600_irq_stat_regs r600; | |
569 | struct evergreen_irq_stat_regs evergreen; | |
570 | }; | |
571 | ||
54bd5206 IH |
572 | #define RADEON_MAX_HPD_PINS 6 |
573 | #define RADEON_MAX_CRTCS 6 | |
f122c610 | 574 | #define RADEON_MAX_AFMT_BLOCKS 6 |
54bd5206 | 575 | |
771fe6b9 | 576 | struct radeon_irq { |
fb98257a CK |
577 | bool installed; |
578 | spinlock_t lock; | |
736fc37f | 579 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 580 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 581 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
582 | wait_queue_head_t vblank_queue; |
583 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
584 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
585 | union radeon_irq_stat_regs stat_regs; | |
771fe6b9 JG |
586 | }; |
587 | ||
588 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
589 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b AD |
590 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
591 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); | |
6f34be50 AD |
592 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
593 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
594 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
595 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
596 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
597 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
598 | |
599 | /* | |
e32eb50d | 600 | * CP & rings. |
771fe6b9 | 601 | */ |
7465280c | 602 | |
771fe6b9 | 603 | struct radeon_ib { |
68470ae7 JG |
604 | struct radeon_sa_bo *sa_bo; |
605 | uint32_t length_dw; | |
606 | uint64_t gpu_addr; | |
607 | uint32_t *ptr; | |
876dc9f3 | 608 | int ring; |
68470ae7 | 609 | struct radeon_fence *fence; |
4bf3dd92 | 610 | struct radeon_vm *vm; |
68470ae7 | 611 | bool is_const_ib; |
220907d9 | 612 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
68470ae7 | 613 | struct radeon_semaphore *semaphore; |
771fe6b9 JG |
614 | }; |
615 | ||
e32eb50d | 616 | struct radeon_ring { |
4c788679 | 617 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
618 | volatile uint32_t *ring; |
619 | unsigned rptr; | |
5596a9db CK |
620 | unsigned rptr_offs; |
621 | unsigned rptr_reg; | |
45df6803 | 622 | unsigned rptr_save_reg; |
89d35807 AD |
623 | u64 next_rptr_gpu_addr; |
624 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
625 | unsigned wptr; |
626 | unsigned wptr_old; | |
5596a9db | 627 | unsigned wptr_reg; |
771fe6b9 JG |
628 | unsigned ring_size; |
629 | unsigned ring_free_dw; | |
630 | int count_dw; | |
069211e5 CK |
631 | unsigned long last_activity; |
632 | unsigned last_rptr; | |
771fe6b9 JG |
633 | uint64_t gpu_addr; |
634 | uint32_t align_mask; | |
635 | uint32_t ptr_mask; | |
771fe6b9 | 636 | bool ready; |
78c5560a AD |
637 | u32 ptr_reg_shift; |
638 | u32 ptr_reg_mask; | |
639 | u32 nop; | |
8b25ed34 | 640 | u32 idx; |
771fe6b9 JG |
641 | }; |
642 | ||
721604a1 JG |
643 | /* |
644 | * VM | |
645 | */ | |
ee60e29f CK |
646 | |
647 | #define RADEON_NUM_VM 16 | |
648 | ||
721604a1 JG |
649 | struct radeon_vm { |
650 | struct list_head list; | |
651 | struct list_head va; | |
ee60e29f | 652 | unsigned id; |
721604a1 JG |
653 | unsigned last_pfn; |
654 | u64 pt_gpu_addr; | |
655 | u64 *pt; | |
2e0d9910 | 656 | struct radeon_sa_bo *sa_bo; |
721604a1 JG |
657 | struct mutex mutex; |
658 | /* last fence for cs using this vm */ | |
659 | struct radeon_fence *fence; | |
9b40e5d8 CK |
660 | /* last flush or NULL if we still need to flush */ |
661 | struct radeon_fence *last_flush; | |
721604a1 JG |
662 | }; |
663 | ||
721604a1 | 664 | struct radeon_vm_manager { |
36ff39c4 | 665 | struct mutex lock; |
721604a1 | 666 | struct list_head lru_vm; |
ee60e29f | 667 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 JG |
668 | struct radeon_sa_manager sa_manager; |
669 | uint32_t max_pfn; | |
721604a1 JG |
670 | /* number of VMIDs */ |
671 | unsigned nvm; | |
672 | /* vram base address for page table entry */ | |
673 | u64 vram_base_offset; | |
67e915e4 AD |
674 | /* is vm enabled? */ |
675 | bool enabled; | |
721604a1 JG |
676 | }; |
677 | ||
678 | /* | |
679 | * file private structure | |
680 | */ | |
681 | struct radeon_fpriv { | |
682 | struct radeon_vm vm; | |
683 | }; | |
684 | ||
d8f60cfc AD |
685 | /* |
686 | * R6xx+ IH ring | |
687 | */ | |
688 | struct r600_ih { | |
4c788679 | 689 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
690 | volatile uint32_t *ring; |
691 | unsigned rptr; | |
d8f60cfc AD |
692 | unsigned ring_size; |
693 | uint64_t gpu_addr; | |
d8f60cfc | 694 | uint32_t ptr_mask; |
c20dc369 | 695 | atomic_t lock; |
d8f60cfc AD |
696 | bool enabled; |
697 | }; | |
698 | ||
8eec9d6f IH |
699 | struct r600_blit_cp_primitives { |
700 | void (*set_render_target)(struct radeon_device *rdev, int format, | |
701 | int w, int h, u64 gpu_addr); | |
702 | void (*cp_set_surface_sync)(struct radeon_device *rdev, | |
703 | u32 sync_type, u32 size, | |
704 | u64 mc_addr); | |
705 | void (*set_shaders)(struct radeon_device *rdev); | |
706 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); | |
707 | void (*set_tex_resource)(struct radeon_device *rdev, | |
708 | int format, int w, int h, int pitch, | |
9bb7703c | 709 | u64 gpu_addr, u32 size); |
8eec9d6f IH |
710 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
711 | int x2, int y2); | |
712 | void (*draw_auto)(struct radeon_device *rdev); | |
713 | void (*set_default_state)(struct radeon_device *rdev); | |
714 | }; | |
715 | ||
3ce0a23d | 716 | struct r600_blit { |
4c788679 | 717 | struct radeon_bo *shader_obj; |
8eec9d6f IH |
718 | struct r600_blit_cp_primitives primitives; |
719 | int max_dim; | |
720 | int ring_size_common; | |
721 | int ring_size_per_loop; | |
3ce0a23d JG |
722 | u64 shader_gpu_addr; |
723 | u32 vs_offset, ps_offset; | |
724 | u32 state_offset; | |
725 | u32 state_len; | |
3ce0a23d JG |
726 | }; |
727 | ||
347e7592 AD |
728 | /* |
729 | * SI RLC stuff | |
730 | */ | |
731 | struct si_rlc { | |
732 | /* for power gating */ | |
733 | struct radeon_bo *save_restore_obj; | |
734 | uint64_t save_restore_gpu_addr; | |
735 | /* for clear state */ | |
736 | struct radeon_bo *clear_state_obj; | |
737 | uint64_t clear_state_gpu_addr; | |
738 | }; | |
739 | ||
69e130a6 | 740 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
741 | struct radeon_ib *ib, struct radeon_vm *vm, |
742 | unsigned size); | |
f2e39221 | 743 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
4ef72566 CK |
744 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
745 | struct radeon_ib *const_ib); | |
771fe6b9 JG |
746 | int radeon_ib_pool_init(struct radeon_device *rdev); |
747 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 748 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 749 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
750 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
751 | struct radeon_ring *ring); | |
e32eb50d CK |
752 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
753 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
754 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
755 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
756 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
d6999bc7 | 757 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
758 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
759 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
7b9ef16b | 760 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
069211e5 CK |
761 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
762 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
55d7c221 CK |
763 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
764 | uint32_t **data); | |
765 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
766 | unsigned size, uint32_t *data); | |
e32eb50d | 767 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
78c5560a AD |
768 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
769 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); | |
e32eb50d | 770 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
771 | |
772 | ||
773 | /* | |
774 | * CS. | |
775 | */ | |
776 | struct radeon_cs_reloc { | |
777 | struct drm_gem_object *gobj; | |
4c788679 JG |
778 | struct radeon_bo *robj; |
779 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
780 | uint32_t handle; |
781 | uint32_t flags; | |
782 | }; | |
783 | ||
784 | struct radeon_cs_chunk { | |
785 | uint32_t chunk_id; | |
786 | uint32_t length_dw; | |
721604a1 JG |
787 | int kpage_idx[2]; |
788 | uint32_t *kpage[2]; | |
771fe6b9 | 789 | uint32_t *kdata; |
721604a1 JG |
790 | void __user *user_ptr; |
791 | int last_copied_page; | |
792 | int last_page_index; | |
771fe6b9 JG |
793 | }; |
794 | ||
795 | struct radeon_cs_parser { | |
c8c15ff1 | 796 | struct device *dev; |
771fe6b9 JG |
797 | struct radeon_device *rdev; |
798 | struct drm_file *filp; | |
799 | /* chunks */ | |
800 | unsigned nchunks; | |
801 | struct radeon_cs_chunk *chunks; | |
802 | uint64_t *chunks_array; | |
803 | /* IB */ | |
804 | unsigned idx; | |
805 | /* relocations */ | |
806 | unsigned nrelocs; | |
807 | struct radeon_cs_reloc *relocs; | |
808 | struct radeon_cs_reloc **relocs_ptr; | |
809 | struct list_head validated; | |
810 | /* indices of various chunks */ | |
811 | int chunk_ib_idx; | |
812 | int chunk_relocs_idx; | |
721604a1 | 813 | int chunk_flags_idx; |
dfcf5f36 | 814 | int chunk_const_ib_idx; |
f2e39221 JG |
815 | struct radeon_ib ib; |
816 | struct radeon_ib const_ib; | |
771fe6b9 | 817 | void *track; |
3ce0a23d | 818 | unsigned family; |
e70f224c | 819 | int parser_error; |
721604a1 JG |
820 | u32 cs_flags; |
821 | u32 ring; | |
822 | s32 priority; | |
771fe6b9 JG |
823 | }; |
824 | ||
513bcb46 | 825 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
ce580fab | 826 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
513bcb46 | 827 | |
771fe6b9 JG |
828 | struct radeon_cs_packet { |
829 | unsigned idx; | |
830 | unsigned type; | |
831 | unsigned reg; | |
832 | unsigned opcode; | |
833 | int count; | |
834 | unsigned one_reg_wr; | |
835 | }; | |
836 | ||
837 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
838 | struct radeon_cs_packet *pkt, | |
839 | unsigned idx, unsigned reg); | |
840 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
841 | struct radeon_cs_packet *pkt); | |
842 | ||
843 | ||
844 | /* | |
845 | * AGP | |
846 | */ | |
847 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 848 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 849 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
850 | void radeon_agp_fini(struct radeon_device *rdev); |
851 | ||
852 | ||
853 | /* | |
854 | * Writeback | |
855 | */ | |
856 | struct radeon_wb { | |
4c788679 | 857 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
858 | volatile uint32_t *wb; |
859 | uint64_t gpu_addr; | |
724c80e1 | 860 | bool enabled; |
d0f8a854 | 861 | bool use_event; |
771fe6b9 JG |
862 | }; |
863 | ||
724c80e1 | 864 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 865 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 866 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
867 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
868 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
724c80e1 | 869 | #define R600_WB_IH_WPTR_OFFSET 2048 |
d0f8a854 | 870 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 871 | |
c93bb85b JG |
872 | /** |
873 | * struct radeon_pm - power management datas | |
874 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
875 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
876 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
877 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
878 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
879 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
880 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
881 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
882 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 883 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
884 | * @needed_bandwidth: current bandwidth needs |
885 | * | |
886 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 887 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
888 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
889 | * (type of memory, bus size, efficiency, ...) | |
890 | */ | |
ce8f5370 AD |
891 | |
892 | enum radeon_pm_method { | |
893 | PM_METHOD_PROFILE, | |
894 | PM_METHOD_DYNPM, | |
895 | }; | |
896 | ||
897 | enum radeon_dynpm_state { | |
898 | DYNPM_STATE_DISABLED, | |
899 | DYNPM_STATE_MINIMUM, | |
900 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
901 | DYNPM_STATE_ACTIVE, |
902 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 903 | }; |
ce8f5370 AD |
904 | enum radeon_dynpm_action { |
905 | DYNPM_ACTION_NONE, | |
906 | DYNPM_ACTION_MINIMUM, | |
907 | DYNPM_ACTION_DOWNCLOCK, | |
908 | DYNPM_ACTION_UPCLOCK, | |
909 | DYNPM_ACTION_DEFAULT | |
c913e23a | 910 | }; |
56278a8e AD |
911 | |
912 | enum radeon_voltage_type { | |
913 | VOLTAGE_NONE = 0, | |
914 | VOLTAGE_GPIO, | |
915 | VOLTAGE_VDDC, | |
916 | VOLTAGE_SW | |
917 | }; | |
918 | ||
0ec0e74f AD |
919 | enum radeon_pm_state_type { |
920 | POWER_STATE_TYPE_DEFAULT, | |
921 | POWER_STATE_TYPE_POWERSAVE, | |
922 | POWER_STATE_TYPE_BATTERY, | |
923 | POWER_STATE_TYPE_BALANCED, | |
924 | POWER_STATE_TYPE_PERFORMANCE, | |
925 | }; | |
926 | ||
ce8f5370 AD |
927 | enum radeon_pm_profile_type { |
928 | PM_PROFILE_DEFAULT, | |
929 | PM_PROFILE_AUTO, | |
930 | PM_PROFILE_LOW, | |
c9e75b21 | 931 | PM_PROFILE_MID, |
ce8f5370 AD |
932 | PM_PROFILE_HIGH, |
933 | }; | |
934 | ||
935 | #define PM_PROFILE_DEFAULT_IDX 0 | |
936 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
937 | #define PM_PROFILE_MID_SH_IDX 2 |
938 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
939 | #define PM_PROFILE_LOW_MH_IDX 4 | |
940 | #define PM_PROFILE_MID_MH_IDX 5 | |
941 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
942 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
943 | |
944 | struct radeon_pm_profile { | |
945 | int dpms_off_ps_idx; | |
946 | int dpms_on_ps_idx; | |
947 | int dpms_off_cm_idx; | |
948 | int dpms_on_cm_idx; | |
516d0e46 AD |
949 | }; |
950 | ||
21a8122a AD |
951 | enum radeon_int_thermal_type { |
952 | THERMAL_TYPE_NONE, | |
953 | THERMAL_TYPE_RV6XX, | |
954 | THERMAL_TYPE_RV770, | |
955 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 956 | THERMAL_TYPE_SUMO, |
4fddba1f | 957 | THERMAL_TYPE_NI, |
14607d08 | 958 | THERMAL_TYPE_SI, |
21a8122a AD |
959 | }; |
960 | ||
56278a8e AD |
961 | struct radeon_voltage { |
962 | enum radeon_voltage_type type; | |
963 | /* gpio voltage */ | |
964 | struct radeon_gpio_rec gpio; | |
965 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
966 | bool active_high; /* voltage drop is active when bit is high */ | |
967 | /* VDDC voltage */ | |
968 | u8 vddc_id; /* index into vddc voltage table */ | |
969 | u8 vddci_id; /* index into vddci voltage table */ | |
970 | bool vddci_enabled; | |
971 | /* r6xx+ sw */ | |
2feea49a AD |
972 | u16 voltage; |
973 | /* evergreen+ vddci */ | |
974 | u16 vddci; | |
56278a8e AD |
975 | }; |
976 | ||
d7311171 AD |
977 | /* clock mode flags */ |
978 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
979 | ||
56278a8e AD |
980 | struct radeon_pm_clock_info { |
981 | /* memory clock */ | |
982 | u32 mclk; | |
983 | /* engine clock */ | |
984 | u32 sclk; | |
985 | /* voltage info */ | |
986 | struct radeon_voltage voltage; | |
d7311171 | 987 | /* standardized clock flags */ |
56278a8e AD |
988 | u32 flags; |
989 | }; | |
990 | ||
a48b9b4e | 991 | /* state flags */ |
d7311171 | 992 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 993 | |
56278a8e | 994 | struct radeon_power_state { |
0ec0e74f | 995 | enum radeon_pm_state_type type; |
8f3f1c9a | 996 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
997 | /* number of valid clock modes in this power state */ |
998 | int num_clock_modes; | |
56278a8e | 999 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1000 | /* standardized state flags */ |
1001 | u32 flags; | |
79daedc9 AD |
1002 | u32 misc; /* vbios specific flags */ |
1003 | u32 misc2; /* vbios specific flags */ | |
1004 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1005 | }; |
1006 | ||
27459324 RM |
1007 | /* |
1008 | * Some modes are overclocked by very low value, accept them | |
1009 | */ | |
1010 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1011 | ||
c93bb85b | 1012 | struct radeon_pm { |
c913e23a | 1013 | struct mutex mutex; |
db7fce39 CK |
1014 | /* write locked while reprogramming mclk */ |
1015 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1016 | u32 active_crtcs; |
1017 | int active_crtc_count; | |
c913e23a | 1018 | int req_vblank; |
839461d3 | 1019 | bool vblank_sync; |
c93bb85b JG |
1020 | fixed20_12 max_bandwidth; |
1021 | fixed20_12 igp_sideport_mclk; | |
1022 | fixed20_12 igp_system_mclk; | |
1023 | fixed20_12 igp_ht_link_clk; | |
1024 | fixed20_12 igp_ht_link_width; | |
1025 | fixed20_12 k8_bandwidth; | |
1026 | fixed20_12 sideport_bandwidth; | |
1027 | fixed20_12 ht_bandwidth; | |
1028 | fixed20_12 core_bandwidth; | |
1029 | fixed20_12 sclk; | |
f47299c5 | 1030 | fixed20_12 mclk; |
c93bb85b | 1031 | fixed20_12 needed_bandwidth; |
0975b162 | 1032 | struct radeon_power_state *power_state; |
56278a8e AD |
1033 | /* number of valid power states */ |
1034 | int num_power_states; | |
a48b9b4e AD |
1035 | int current_power_state_index; |
1036 | int current_clock_mode_index; | |
1037 | int requested_power_state_index; | |
1038 | int requested_clock_mode_index; | |
1039 | int default_power_state_index; | |
1040 | u32 current_sclk; | |
1041 | u32 current_mclk; | |
2feea49a AD |
1042 | u16 current_vddc; |
1043 | u16 current_vddci; | |
9ace9f7b AD |
1044 | u32 default_sclk; |
1045 | u32 default_mclk; | |
2feea49a AD |
1046 | u16 default_vddc; |
1047 | u16 default_vddci; | |
29fb52ca | 1048 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1049 | /* selected pm method */ |
1050 | enum radeon_pm_method pm_method; | |
1051 | /* dynpm power management */ | |
1052 | struct delayed_work dynpm_idle_work; | |
1053 | enum radeon_dynpm_state dynpm_state; | |
1054 | enum radeon_dynpm_action dynpm_planned_action; | |
1055 | unsigned long dynpm_action_timeout; | |
1056 | bool dynpm_can_upclock; | |
1057 | bool dynpm_can_downclock; | |
1058 | /* profile-based power management */ | |
1059 | enum radeon_pm_profile_type profile; | |
1060 | int profile_index; | |
1061 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1062 | /* internal thermal controller on rv6xx+ */ |
1063 | enum radeon_int_thermal_type int_thermal_type; | |
1064 | struct device *int_hwmon_dev; | |
c93bb85b JG |
1065 | }; |
1066 | ||
a4c9e2ee AD |
1067 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1068 | enum radeon_pm_state_type ps_type, | |
1069 | int instance); | |
771fe6b9 | 1070 | |
a92553ab | 1071 | struct r600_audio { |
a92553ab RM |
1072 | int channels; |
1073 | int rate; | |
1074 | int bits_per_sample; | |
1075 | u8 status_bits; | |
1076 | u8 category_code; | |
1077 | }; | |
1078 | ||
771fe6b9 JG |
1079 | /* |
1080 | * Benchmarking | |
1081 | */ | |
638dd7db | 1082 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1083 | |
1084 | ||
ecc0b326 MD |
1085 | /* |
1086 | * Testing | |
1087 | */ | |
1088 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1089 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1090 | struct radeon_ring *cpA, |
1091 | struct radeon_ring *cpB); | |
60a7e396 | 1092 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 MD |
1093 | |
1094 | ||
771fe6b9 JG |
1095 | /* |
1096 | * Debugfs | |
1097 | */ | |
4d8bf9ae CK |
1098 | struct radeon_debugfs { |
1099 | struct drm_info_list *files; | |
1100 | unsigned num_files; | |
1101 | }; | |
1102 | ||
771fe6b9 JG |
1103 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1104 | struct drm_info_list *files, | |
1105 | unsigned nfiles); | |
1106 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
1107 | |
1108 | ||
1109 | /* | |
1110 | * ASIC specific functions. | |
1111 | */ | |
1112 | struct radeon_asic { | |
068a117c | 1113 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1114 | void (*fini)(struct radeon_device *rdev); |
1115 | int (*resume)(struct radeon_device *rdev); | |
1116 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1117 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1118 | int (*asic_reset)(struct radeon_device *rdev); |
54e88e06 AD |
1119 | /* ioctl hw specific callback. Some hw might want to perform special |
1120 | * operation on specific ioctl. For instance on wait idle some hw | |
1121 | * might want to perform and HDP flush through MMIO as it seems that | |
1122 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
1123 | * through ring. | |
1124 | */ | |
1125 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
1126 | /* check if 3D engine is idle */ | |
1127 | bool (*gui_idle)(struct radeon_device *rdev); | |
1128 | /* wait for mc_idle */ | |
1129 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
1130 | /* gart */ | |
c5b3b850 AD |
1131 | struct { |
1132 | void (*tlb_flush)(struct radeon_device *rdev); | |
1133 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
1134 | } gart; | |
05b07147 CK |
1135 | struct { |
1136 | int (*init)(struct radeon_device *rdev); | |
1137 | void (*fini)(struct radeon_device *rdev); | |
2a6f1abb CK |
1138 | |
1139 | u32 pt_ring_index; | |
05b07147 | 1140 | void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, |
089a786e CK |
1141 | unsigned pfn, struct ttm_mem_reg *mem, |
1142 | unsigned npages, uint32_t flags); | |
05b07147 | 1143 | } vm; |
54e88e06 | 1144 | /* ring specific callbacks */ |
4c87bc26 CK |
1145 | struct { |
1146 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
721604a1 | 1147 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1148 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
e32eb50d | 1149 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
4c87bc26 | 1150 | struct radeon_semaphore *semaphore, bool emit_wait); |
eb0c19c5 | 1151 | int (*cs_parse)(struct radeon_cs_parser *p); |
f712812e AD |
1152 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1153 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1154 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
312c4a8c | 1155 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
9b40e5d8 | 1156 | void (*vm_flush)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1157 | } ring[RADEON_NUM_RINGS]; |
54e88e06 | 1158 | /* irqs */ |
b35ea4ab AD |
1159 | struct { |
1160 | int (*set)(struct radeon_device *rdev); | |
1161 | int (*process)(struct radeon_device *rdev); | |
1162 | } irq; | |
54e88e06 | 1163 | /* displays */ |
c79a49ca AD |
1164 | struct { |
1165 | /* display watermarks */ | |
1166 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1167 | /* get frame count */ | |
1168 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1169 | /* wait for vblank */ | |
1170 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1171 | /* set backlight level */ |
1172 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
c79a49ca | 1173 | } display; |
54e88e06 | 1174 | /* copy functions for bo handling */ |
27cd7769 AD |
1175 | struct { |
1176 | int (*blit)(struct radeon_device *rdev, | |
1177 | uint64_t src_offset, | |
1178 | uint64_t dst_offset, | |
1179 | unsigned num_gpu_pages, | |
876dc9f3 | 1180 | struct radeon_fence **fence); |
27cd7769 AD |
1181 | u32 blit_ring_index; |
1182 | int (*dma)(struct radeon_device *rdev, | |
1183 | uint64_t src_offset, | |
1184 | uint64_t dst_offset, | |
1185 | unsigned num_gpu_pages, | |
876dc9f3 | 1186 | struct radeon_fence **fence); |
27cd7769 AD |
1187 | u32 dma_ring_index; |
1188 | /* method used for bo copy */ | |
1189 | int (*copy)(struct radeon_device *rdev, | |
1190 | uint64_t src_offset, | |
1191 | uint64_t dst_offset, | |
1192 | unsigned num_gpu_pages, | |
876dc9f3 | 1193 | struct radeon_fence **fence); |
27cd7769 AD |
1194 | /* ring used for bo copies */ |
1195 | u32 copy_ring_index; | |
1196 | } copy; | |
54e88e06 | 1197 | /* surfaces */ |
9e6f3d02 AD |
1198 | struct { |
1199 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1200 | uint32_t tiling_flags, uint32_t pitch, | |
1201 | uint32_t offset, uint32_t obj_size); | |
1202 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1203 | } surface; | |
54e88e06 | 1204 | /* hotplug detect */ |
901ea57d AD |
1205 | struct { |
1206 | void (*init)(struct radeon_device *rdev); | |
1207 | void (*fini)(struct radeon_device *rdev); | |
1208 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1209 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1210 | } hpd; | |
ce8f5370 | 1211 | /* power management */ |
a02fa397 AD |
1212 | struct { |
1213 | void (*misc)(struct radeon_device *rdev); | |
1214 | void (*prepare)(struct radeon_device *rdev); | |
1215 | void (*finish)(struct radeon_device *rdev); | |
1216 | void (*init_profile)(struct radeon_device *rdev); | |
1217 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1218 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1219 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1220 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1221 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1222 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1223 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1224 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
a02fa397 | 1225 | } pm; |
6f34be50 | 1226 | /* pageflipping */ |
0f9e006c AD |
1227 | struct { |
1228 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
1229 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
1230 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
1231 | } pflip; | |
771fe6b9 JG |
1232 | }; |
1233 | ||
21f9a437 JG |
1234 | /* |
1235 | * Asic structures | |
1236 | */ | |
551ebd83 | 1237 | struct r100_asic { |
225758d8 JG |
1238 | const unsigned *reg_safe_bm; |
1239 | unsigned reg_safe_bm_size; | |
1240 | u32 hdp_cntl; | |
551ebd83 DA |
1241 | }; |
1242 | ||
21f9a437 | 1243 | struct r300_asic { |
225758d8 JG |
1244 | const unsigned *reg_safe_bm; |
1245 | unsigned reg_safe_bm_size; | |
1246 | u32 resync_scratch; | |
1247 | u32 hdp_cntl; | |
21f9a437 JG |
1248 | }; |
1249 | ||
1250 | struct r600_asic { | |
225758d8 JG |
1251 | unsigned max_pipes; |
1252 | unsigned max_tile_pipes; | |
1253 | unsigned max_simds; | |
1254 | unsigned max_backends; | |
1255 | unsigned max_gprs; | |
1256 | unsigned max_threads; | |
1257 | unsigned max_stack_entries; | |
1258 | unsigned max_hw_contexts; | |
1259 | unsigned max_gs_threads; | |
1260 | unsigned sx_max_export_size; | |
1261 | unsigned sx_max_export_pos_size; | |
1262 | unsigned sx_max_export_smx_size; | |
1263 | unsigned sq_num_cf_insts; | |
1264 | unsigned tiling_nbanks; | |
1265 | unsigned tiling_npipes; | |
1266 | unsigned tiling_group_size; | |
e7aeeba6 | 1267 | unsigned tile_config; |
e55b9422 | 1268 | unsigned backend_map; |
21f9a437 JG |
1269 | }; |
1270 | ||
1271 | struct rv770_asic { | |
225758d8 JG |
1272 | unsigned max_pipes; |
1273 | unsigned max_tile_pipes; | |
1274 | unsigned max_simds; | |
1275 | unsigned max_backends; | |
1276 | unsigned max_gprs; | |
1277 | unsigned max_threads; | |
1278 | unsigned max_stack_entries; | |
1279 | unsigned max_hw_contexts; | |
1280 | unsigned max_gs_threads; | |
1281 | unsigned sx_max_export_size; | |
1282 | unsigned sx_max_export_pos_size; | |
1283 | unsigned sx_max_export_smx_size; | |
1284 | unsigned sq_num_cf_insts; | |
1285 | unsigned sx_num_of_sets; | |
1286 | unsigned sc_prim_fifo_size; | |
1287 | unsigned sc_hiz_tile_fifo_size; | |
1288 | unsigned sc_earlyz_tile_fifo_fize; | |
1289 | unsigned tiling_nbanks; | |
1290 | unsigned tiling_npipes; | |
1291 | unsigned tiling_group_size; | |
e7aeeba6 | 1292 | unsigned tile_config; |
e55b9422 | 1293 | unsigned backend_map; |
21f9a437 JG |
1294 | }; |
1295 | ||
32fcdbf4 AD |
1296 | struct evergreen_asic { |
1297 | unsigned num_ses; | |
1298 | unsigned max_pipes; | |
1299 | unsigned max_tile_pipes; | |
1300 | unsigned max_simds; | |
1301 | unsigned max_backends; | |
1302 | unsigned max_gprs; | |
1303 | unsigned max_threads; | |
1304 | unsigned max_stack_entries; | |
1305 | unsigned max_hw_contexts; | |
1306 | unsigned max_gs_threads; | |
1307 | unsigned sx_max_export_size; | |
1308 | unsigned sx_max_export_pos_size; | |
1309 | unsigned sx_max_export_smx_size; | |
1310 | unsigned sq_num_cf_insts; | |
1311 | unsigned sx_num_of_sets; | |
1312 | unsigned sc_prim_fifo_size; | |
1313 | unsigned sc_hiz_tile_fifo_size; | |
1314 | unsigned sc_earlyz_tile_fifo_size; | |
1315 | unsigned tiling_nbanks; | |
1316 | unsigned tiling_npipes; | |
1317 | unsigned tiling_group_size; | |
e7aeeba6 | 1318 | unsigned tile_config; |
e55b9422 | 1319 | unsigned backend_map; |
32fcdbf4 AD |
1320 | }; |
1321 | ||
fecf1d07 AD |
1322 | struct cayman_asic { |
1323 | unsigned max_shader_engines; | |
1324 | unsigned max_pipes_per_simd; | |
1325 | unsigned max_tile_pipes; | |
1326 | unsigned max_simds_per_se; | |
1327 | unsigned max_backends_per_se; | |
1328 | unsigned max_texture_channel_caches; | |
1329 | unsigned max_gprs; | |
1330 | unsigned max_threads; | |
1331 | unsigned max_gs_threads; | |
1332 | unsigned max_stack_entries; | |
1333 | unsigned sx_num_of_sets; | |
1334 | unsigned sx_max_export_size; | |
1335 | unsigned sx_max_export_pos_size; | |
1336 | unsigned sx_max_export_smx_size; | |
1337 | unsigned max_hw_contexts; | |
1338 | unsigned sq_num_cf_insts; | |
1339 | unsigned sc_prim_fifo_size; | |
1340 | unsigned sc_hiz_tile_fifo_size; | |
1341 | unsigned sc_earlyz_tile_fifo_size; | |
1342 | ||
1343 | unsigned num_shader_engines; | |
1344 | unsigned num_shader_pipes_per_simd; | |
1345 | unsigned num_tile_pipes; | |
1346 | unsigned num_simds_per_se; | |
1347 | unsigned num_backends_per_se; | |
1348 | unsigned backend_disable_mask_per_asic; | |
1349 | unsigned backend_map; | |
1350 | unsigned num_texture_channel_caches; | |
1351 | unsigned mem_max_burst_length_bytes; | |
1352 | unsigned mem_row_size_in_kb; | |
1353 | unsigned shader_engine_tile_size; | |
1354 | unsigned num_gpus; | |
1355 | unsigned multi_gpu_tile_size; | |
1356 | ||
1357 | unsigned tile_config; | |
fecf1d07 AD |
1358 | }; |
1359 | ||
0a96d72b AD |
1360 | struct si_asic { |
1361 | unsigned max_shader_engines; | |
0a96d72b | 1362 | unsigned max_tile_pipes; |
1a8ca750 AD |
1363 | unsigned max_cu_per_sh; |
1364 | unsigned max_sh_per_se; | |
0a96d72b AD |
1365 | unsigned max_backends_per_se; |
1366 | unsigned max_texture_channel_caches; | |
1367 | unsigned max_gprs; | |
1368 | unsigned max_gs_threads; | |
1369 | unsigned max_hw_contexts; | |
1370 | unsigned sc_prim_fifo_size_frontend; | |
1371 | unsigned sc_prim_fifo_size_backend; | |
1372 | unsigned sc_hiz_tile_fifo_size; | |
1373 | unsigned sc_earlyz_tile_fifo_size; | |
1374 | ||
0a96d72b AD |
1375 | unsigned num_tile_pipes; |
1376 | unsigned num_backends_per_se; | |
1377 | unsigned backend_disable_mask_per_asic; | |
1378 | unsigned backend_map; | |
1379 | unsigned num_texture_channel_caches; | |
1380 | unsigned mem_max_burst_length_bytes; | |
1381 | unsigned mem_row_size_in_kb; | |
1382 | unsigned shader_engine_tile_size; | |
1383 | unsigned num_gpus; | |
1384 | unsigned multi_gpu_tile_size; | |
1385 | ||
1386 | unsigned tile_config; | |
0a96d72b AD |
1387 | }; |
1388 | ||
068a117c JG |
1389 | union radeon_asic_config { |
1390 | struct r300_asic r300; | |
551ebd83 | 1391 | struct r100_asic r100; |
3ce0a23d JG |
1392 | struct r600_asic r600; |
1393 | struct rv770_asic rv770; | |
32fcdbf4 | 1394 | struct evergreen_asic evergreen; |
fecf1d07 | 1395 | struct cayman_asic cayman; |
0a96d72b | 1396 | struct si_asic si; |
068a117c JG |
1397 | }; |
1398 | ||
0a10c851 DV |
1399 | /* |
1400 | * asic initizalization from radeon_asic.c | |
1401 | */ | |
1402 | void radeon_agp_disable(struct radeon_device *rdev); | |
1403 | int radeon_asic_init(struct radeon_device *rdev); | |
1404 | ||
771fe6b9 JG |
1405 | |
1406 | /* | |
1407 | * IOCTL. | |
1408 | */ | |
1409 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1410 | struct drm_file *filp); | |
1411 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1412 | struct drm_file *filp); | |
1413 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1414 | struct drm_file *file_priv); | |
1415 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1416 | struct drm_file *file_priv); | |
1417 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1418 | struct drm_file *file_priv); | |
1419 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1420 | struct drm_file *file_priv); | |
1421 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1422 | struct drm_file *filp); | |
1423 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1424 | struct drm_file *filp); | |
1425 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1426 | struct drm_file *filp); | |
1427 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1428 | struct drm_file *filp); | |
721604a1 JG |
1429 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
1430 | struct drm_file *filp); | |
771fe6b9 | 1431 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
1432 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1433 | struct drm_file *filp); | |
1434 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1435 | struct drm_file *filp); | |
771fe6b9 | 1436 | |
16cdf04d AD |
1437 | /* VRAM scratch page for HDP bug, default vram page */ |
1438 | struct r600_vram_scratch { | |
87cbf8f2 AD |
1439 | struct radeon_bo *robj; |
1440 | volatile uint32_t *ptr; | |
16cdf04d | 1441 | u64 gpu_addr; |
87cbf8f2 | 1442 | }; |
771fe6b9 | 1443 | |
fd64ca8a LT |
1444 | /* |
1445 | * ACPI | |
1446 | */ | |
1447 | struct radeon_atif_notification_cfg { | |
1448 | bool enabled; | |
1449 | int command_code; | |
1450 | }; | |
1451 | ||
1452 | struct radeon_atif_notifications { | |
1453 | bool display_switch; | |
1454 | bool expansion_mode_change; | |
1455 | bool thermal_state; | |
1456 | bool forced_power_state; | |
1457 | bool system_power_state; | |
1458 | bool display_conf_change; | |
1459 | bool px_gfx_switch; | |
1460 | bool brightness_change; | |
1461 | bool dgpu_display_event; | |
1462 | }; | |
1463 | ||
1464 | struct radeon_atif_functions { | |
1465 | bool system_params; | |
1466 | bool sbios_requests; | |
1467 | bool select_active_disp; | |
1468 | bool lid_state; | |
1469 | bool get_tv_standard; | |
1470 | bool set_tv_standard; | |
1471 | bool get_panel_expansion_mode; | |
1472 | bool set_panel_expansion_mode; | |
1473 | bool temperature_change; | |
1474 | bool graphics_device_types; | |
1475 | }; | |
1476 | ||
1477 | struct radeon_atif { | |
1478 | struct radeon_atif_notifications notifications; | |
1479 | struct radeon_atif_functions functions; | |
1480 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 1481 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 1482 | }; |
7a1619b9 | 1483 | |
e3a15920 AD |
1484 | struct radeon_atcs_functions { |
1485 | bool get_ext_state; | |
1486 | bool pcie_perf_req; | |
1487 | bool pcie_dev_rdy; | |
1488 | bool pcie_bus_width; | |
1489 | }; | |
1490 | ||
1491 | struct radeon_atcs { | |
1492 | struct radeon_atcs_functions functions; | |
1493 | }; | |
1494 | ||
771fe6b9 JG |
1495 | /* |
1496 | * Core structure, functions and helpers. | |
1497 | */ | |
1498 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1499 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1500 | ||
1501 | struct radeon_device { | |
9f022ddf | 1502 | struct device *dev; |
771fe6b9 JG |
1503 | struct drm_device *ddev; |
1504 | struct pci_dev *pdev; | |
dee53e7f | 1505 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 1506 | /* ASIC */ |
068a117c | 1507 | union radeon_asic_config config; |
771fe6b9 JG |
1508 | enum radeon_family family; |
1509 | unsigned long flags; | |
1510 | int usec_timeout; | |
1511 | enum radeon_pll_errata pll_errata; | |
1512 | int num_gb_pipes; | |
f779b3e5 | 1513 | int num_z_pipes; |
771fe6b9 JG |
1514 | int disp_priority; |
1515 | /* BIOS */ | |
1516 | uint8_t *bios; | |
1517 | bool is_atom_bios; | |
1518 | uint16_t bios_header_start; | |
4c788679 | 1519 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1520 | /* Register mmio */ |
4c9bc75c DA |
1521 | resource_size_t rmmio_base; |
1522 | resource_size_t rmmio_size; | |
a0533fbf | 1523 | void __iomem *rmmio; |
771fe6b9 JG |
1524 | radeon_rreg_t mc_rreg; |
1525 | radeon_wreg_t mc_wreg; | |
1526 | radeon_rreg_t pll_rreg; | |
1527 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1528 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1529 | radeon_rreg_t pciep_rreg; |
1530 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1531 | /* io port */ |
1532 | void __iomem *rio_mem; | |
1533 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1534 | struct radeon_clock clock; |
1535 | struct radeon_mc mc; | |
1536 | struct radeon_gart gart; | |
1537 | struct radeon_mode_info mode_info; | |
1538 | struct radeon_scratch scratch; | |
1539 | struct radeon_mman mman; | |
7465280c | 1540 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 1541 | wait_queue_head_t fence_queue; |
d6999bc7 | 1542 | struct mutex ring_lock; |
e32eb50d | 1543 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
1544 | bool ib_pool_ready; |
1545 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
1546 | struct radeon_irq irq; |
1547 | struct radeon_asic *asic; | |
1548 | struct radeon_gem gem; | |
c93bb85b | 1549 | struct radeon_pm pm; |
f657c2a7 | 1550 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 1551 | struct radeon_wb wb; |
3ce0a23d | 1552 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1553 | bool shutdown; |
1554 | bool suspend; | |
ad49f501 | 1555 | bool need_dma32; |
733289c2 | 1556 | bool accel_working; |
e024e110 | 1557 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1558 | const struct firmware *me_fw; /* all family ME firmware */ |
1559 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1560 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1561 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 1562 | const struct firmware *ce_fw; /* SI CE firmware */ |
3ce0a23d | 1563 | struct r600_blit r600_blit; |
16cdf04d | 1564 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 1565 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1566 | struct r600_ih ih; /* r6/700 interrupt ring */ |
347e7592 | 1567 | struct si_rlc rlc; |
d4877cf2 | 1568 | struct work_struct hotplug_work; |
f122c610 | 1569 | struct work_struct audio_work; |
18917b60 | 1570 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1571 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
3299de95 RM |
1572 | bool audio_enabled; |
1573 | struct r600_audio audio_status; /* audio stuff */ | |
ce8f5370 | 1574 | struct notifier_block acpi_nb; |
9eba4a93 | 1575 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1576 | struct drm_file *hyperz_filp; |
9eba4a93 | 1577 | struct drm_file *cmask_filp; |
f376b94f AD |
1578 | /* i2c buses */ |
1579 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
1580 | /* debugfs */ |
1581 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
1582 | unsigned debugfs_count; | |
721604a1 JG |
1583 | /* virtual memory */ |
1584 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 1585 | struct mutex gpu_clock_mutex; |
fd64ca8a LT |
1586 | /* ACPI interface */ |
1587 | struct radeon_atif atif; | |
e3a15920 | 1588 | struct radeon_atcs atcs; |
771fe6b9 JG |
1589 | }; |
1590 | ||
1591 | int radeon_device_init(struct radeon_device *rdev, | |
1592 | struct drm_device *ddev, | |
1593 | struct pci_dev *pdev, | |
1594 | uint32_t flags); | |
1595 | void radeon_device_fini(struct radeon_device *rdev); | |
1596 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1597 | ||
6fcbef7a AK |
1598 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
1599 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
1600 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); | |
1601 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 1602 | |
4c788679 JG |
1603 | /* |
1604 | * Cast helper | |
1605 | */ | |
1606 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1607 | |
1608 | /* | |
1609 | * Registers read & write functions. | |
1610 | */ | |
a0533fbf BH |
1611 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1612 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
1613 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
1614 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
de1b2898 | 1615 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1616 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1617 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1618 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1619 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1620 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1621 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1622 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1623 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1624 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1625 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1626 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1627 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1628 | #define WREG32_P(reg, val, mask) \ |
1629 | do { \ | |
1630 | uint32_t tmp_ = RREG32(reg); \ | |
1631 | tmp_ &= (mask); \ | |
1632 | tmp_ |= ((val) & ~(mask)); \ | |
1633 | WREG32(reg, tmp_); \ | |
1634 | } while (0) | |
1635 | #define WREG32_PLL_P(reg, val, mask) \ | |
1636 | do { \ | |
1637 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1638 | tmp_ &= (mask); \ | |
1639 | tmp_ |= ((val) & ~(mask)); \ | |
1640 | WREG32_PLL(reg, tmp_); \ | |
1641 | } while (0) | |
3ce0a23d | 1642 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
351a52a2 AD |
1643 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1644 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1645 | |
de1b2898 DA |
1646 | /* |
1647 | * Indirect registers accessor | |
1648 | */ | |
1649 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1650 | { | |
1651 | uint32_t r; | |
1652 | ||
1653 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1654 | r = RREG32(RADEON_PCIE_DATA); | |
1655 | return r; | |
1656 | } | |
1657 | ||
1658 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1659 | { | |
1660 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1661 | WREG32(RADEON_PCIE_DATA, (v)); | |
1662 | } | |
1663 | ||
771fe6b9 JG |
1664 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1665 | ||
1666 | ||
1667 | /* | |
1668 | * ASICs helpers. | |
1669 | */ | |
b995e433 DA |
1670 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1671 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1672 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1673 | (rdev->family == CHIP_RV200) || \ | |
1674 | (rdev->family == CHIP_RS100) || \ | |
1675 | (rdev->family == CHIP_RS200) || \ | |
1676 | (rdev->family == CHIP_RV250) || \ | |
1677 | (rdev->family == CHIP_RV280) || \ | |
1678 | (rdev->family == CHIP_RS300)) | |
1679 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1680 | (rdev->family == CHIP_RV350) || \ | |
1681 | (rdev->family == CHIP_R350) || \ | |
1682 | (rdev->family == CHIP_RV380) || \ | |
1683 | (rdev->family == CHIP_R420) || \ | |
1684 | (rdev->family == CHIP_R423) || \ | |
1685 | (rdev->family == CHIP_RV410) || \ | |
1686 | (rdev->family == CHIP_RS400) || \ | |
1687 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
1688 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1689 | (rdev->ddev->pdev->device == 0x9443) || \ | |
1690 | (rdev->ddev->pdev->device == 0x944B) || \ | |
1691 | (rdev->ddev->pdev->device == 0x9506) || \ | |
1692 | (rdev->ddev->pdev->device == 0x9509) || \ | |
1693 | (rdev->ddev->pdev->device == 0x950F) || \ | |
1694 | (rdev->ddev->pdev->device == 0x689C) || \ | |
1695 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 1696 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
1697 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1698 | (rdev->family == CHIP_RS690) || \ | |
1699 | (rdev->family == CHIP_RS740) || \ | |
1700 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1701 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1702 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1703 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
1704 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1705 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 1706 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
1707 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1708 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
1709 | (rdev->flags & RADEON_IS_IGP)) | |
771fe6b9 JG |
1710 | |
1711 | /* | |
1712 | * BIOS helpers. | |
1713 | */ | |
1714 | #define RBIOS8(i) (rdev->bios[i]) | |
1715 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1716 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1717 | ||
1718 | int radeon_combios_init(struct radeon_device *rdev); | |
1719 | void radeon_combios_fini(struct radeon_device *rdev); | |
1720 | int radeon_atombios_init(struct radeon_device *rdev); | |
1721 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1722 | ||
1723 | ||
1724 | /* | |
1725 | * RING helpers. | |
1726 | */ | |
ce580fab | 1727 | #if DRM_DEBUG_CODE == 0 |
e32eb50d | 1728 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 1729 | { |
e32eb50d CK |
1730 | ring->ring[ring->wptr++] = v; |
1731 | ring->wptr &= ring->ptr_mask; | |
1732 | ring->count_dw--; | |
1733 | ring->ring_free_dw--; | |
771fe6b9 | 1734 | } |
ce580fab AK |
1735 | #else |
1736 | /* With debugging this is just too big to inline */ | |
e32eb50d | 1737 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
ce580fab | 1738 | #endif |
771fe6b9 JG |
1739 | |
1740 | /* | |
1741 | * ASICs macro. | |
1742 | */ | |
068a117c | 1743 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1744 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1745 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1746 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
eb0c19c5 | 1747 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
28d52043 | 1748 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 1749 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 AD |
1750 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1751 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) | |
05b07147 CK |
1752 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
1753 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
089a786e | 1754 | #define radeon_asic_vm_set_page(rdev, v, pfn, mem, npages, flags) (rdev)->asic->vm.set_page((rdev), (v), (pfn), (mem), (npages), (flags)) |
f712812e AD |
1755 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
1756 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) | |
1757 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) | |
4c87bc26 | 1758 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
721604a1 | 1759 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
312c4a8c | 1760 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
9b40e5d8 | 1761 | #define radeon_ring_vm_flush(rdev, r, ib) (rdev)->asic->ring[(r)].vm_flush((rdev), (ib)) |
b35ea4ab AD |
1762 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
1763 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 1764 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 1765 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
4c87bc26 CK |
1766 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
1767 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
27cd7769 AD |
1768 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
1769 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) | |
1770 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) | |
1771 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | |
1772 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
1773 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
1774 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
1775 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
1776 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
1777 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
1778 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
1779 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
1780 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
9e6f3d02 AD |
1781 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
1782 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 1783 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
1784 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
1785 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
1786 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
1787 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 1788 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
1789 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1790 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
1791 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
1792 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
1793 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 AD |
1794 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
1795 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) | |
1796 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) | |
1797 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) | |
1798 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
771fe6b9 | 1799 | |
6cf8a3f5 | 1800 | /* Common functions */ |
700a0cc0 | 1801 | /* AGP */ |
90aca4d2 | 1802 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1803 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
1804 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1805 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1806 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1807 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1808 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1809 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1810 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1811 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1812 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1813 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1814 | extern void radeon_surface_init(struct radeon_device *rdev); |
1815 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1816 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1817 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1818 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1819 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1820 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1821 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1822 | extern int radeon_resume_kms(struct drm_device *dev); |
1823 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 1824 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
6cf8a3f5 | 1825 | |
721604a1 JG |
1826 | /* |
1827 | * vm | |
1828 | */ | |
1829 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
1830 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
721604a1 JG |
1831 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
1832 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); | |
ddf03f5c | 1833 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
ee60e29f CK |
1834 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
1835 | struct radeon_vm *vm, int ring); | |
1836 | void radeon_vm_fence(struct radeon_device *rdev, | |
1837 | struct radeon_vm *vm, | |
1838 | struct radeon_fence *fence); | |
089a786e CK |
1839 | u64 radeon_vm_get_addr(struct radeon_device *rdev, |
1840 | struct ttm_mem_reg *mem, | |
1841 | unsigned pfn); | |
721604a1 JG |
1842 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
1843 | struct radeon_vm *vm, | |
1844 | struct radeon_bo *bo, | |
1845 | struct ttm_mem_reg *mem); | |
1846 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, | |
1847 | struct radeon_bo *bo); | |
1848 | int radeon_vm_bo_add(struct radeon_device *rdev, | |
1849 | struct radeon_vm *vm, | |
1850 | struct radeon_bo *bo, | |
1851 | uint64_t offset, | |
1852 | uint32_t flags); | |
1853 | int radeon_vm_bo_rmv(struct radeon_device *rdev, | |
1854 | struct radeon_vm *vm, | |
1855 | struct radeon_bo *bo); | |
1856 | ||
f122c610 AD |
1857 | /* audio */ |
1858 | void r600_audio_update_hdmi(struct work_struct *work); | |
721604a1 | 1859 | |
16cdf04d AD |
1860 | /* |
1861 | * R600 vram scratch functions | |
1862 | */ | |
1863 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
1864 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
1865 | ||
285484e2 JG |
1866 | /* |
1867 | * r600 cs checking helper | |
1868 | */ | |
1869 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
1870 | bool r600_fmt_is_valid_color(u32 format); | |
1871 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
1872 | int r600_fmt_get_blocksize(u32 format); | |
1873 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
1874 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
1875 | ||
3574dda4 DV |
1876 | /* |
1877 | * r600 functions used by radeon_encoder.c | |
1878 | */ | |
1b688d08 RM |
1879 | struct radeon_hdmi_acr { |
1880 | u32 clock; | |
1881 | ||
1882 | int n_32khz; | |
1883 | int cts_32khz; | |
1884 | ||
1885 | int n_44_1khz; | |
1886 | int cts_44_1khz; | |
1887 | ||
1888 | int n_48khz; | |
1889 | int cts_48khz; | |
1890 | ||
1891 | }; | |
1892 | ||
e55d3e6c RM |
1893 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
1894 | ||
2cd6218c RM |
1895 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1896 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 | 1897 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
416a2bd2 AD |
1898 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
1899 | u32 tiling_pipe_num, | |
1900 | u32 max_rb_num, | |
1901 | u32 total_max_rb_num, | |
1902 | u32 enabled_rb_mask); | |
fe251e2f | 1903 | |
e55d3e6c RM |
1904 | /* |
1905 | * evergreen functions used by radeon_encoder.c | |
1906 | */ | |
1907 | ||
1908 | extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
1909 | ||
0af62b01 | 1910 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 1911 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 1912 | |
c4917074 AD |
1913 | /* radeon_acpi.c */ |
1914 | #if defined(CONFIG_ACPI) | |
1915 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
1916 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
1917 | #else | |
1918 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
1919 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
1920 | #endif | |
d7a2952f | 1921 | |
4c788679 JG |
1922 | #include "radeon_object.h" |
1923 | ||
771fe6b9 | 1924 | #endif |