Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
72 | ||
c2142715 | 73 | #include "radeon_family.h" |
771fe6b9 JG |
74 | #include "radeon_mode.h" |
75 | #include "radeon_reg.h" | |
771fe6b9 JG |
76 | |
77 | /* | |
78 | * Modules parameters. | |
79 | */ | |
80 | extern int radeon_no_wb; | |
81 | extern int radeon_modeset; | |
82 | extern int radeon_dynclks; | |
83 | extern int radeon_r4xx_atom; | |
84 | extern int radeon_agpmode; | |
85 | extern int radeon_vram_limit; | |
86 | extern int radeon_gart_size; | |
87 | extern int radeon_benchmarking; | |
ecc0b326 | 88 | extern int radeon_testing; |
771fe6b9 | 89 | extern int radeon_connector_table; |
4ce001ab | 90 | extern int radeon_tv; |
b27b6375 | 91 | extern int radeon_new_pll; |
c913e23a | 92 | extern int radeon_dynpm; |
dafc3bd5 | 93 | extern int radeon_audio; |
f46c0120 | 94 | extern int radeon_disp_priority; |
e2b0a8e1 | 95 | extern int radeon_hw_i2c; |
771fe6b9 JG |
96 | |
97 | /* | |
98 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
99 | * symbol; | |
100 | */ | |
101 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
225758d8 | 102 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
e821767b | 103 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
771fe6b9 JG |
104 | #define RADEON_IB_POOL_SIZE 16 |
105 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
106 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 107 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 108 | |
771fe6b9 JG |
109 | /* |
110 | * Errata workarounds. | |
111 | */ | |
112 | enum radeon_pll_errata { | |
113 | CHIP_ERRATA_R300_CG = 0x00000001, | |
114 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
115 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
116 | }; | |
117 | ||
118 | ||
119 | struct radeon_device; | |
120 | ||
121 | ||
122 | /* | |
123 | * BIOS. | |
124 | */ | |
6a9ee8af DA |
125 | #define ATRM_BIOS_PAGE 4096 |
126 | ||
8edb381d | 127 | #if defined(CONFIG_VGA_SWITCHEROO) |
6a9ee8af DA |
128 | bool radeon_atrm_supported(struct pci_dev *pdev); |
129 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); | |
8edb381d DA |
130 | #else |
131 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) | |
132 | { | |
133 | return false; | |
134 | } | |
135 | ||
136 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ | |
137 | return -EINVAL; | |
138 | } | |
139 | #endif | |
771fe6b9 JG |
140 | bool radeon_get_bios(struct radeon_device *rdev); |
141 | ||
3ce0a23d | 142 | |
771fe6b9 | 143 | /* |
3ce0a23d | 144 | * Dummy page |
771fe6b9 | 145 | */ |
3ce0a23d JG |
146 | struct radeon_dummy_page { |
147 | struct page *page; | |
148 | dma_addr_t addr; | |
149 | }; | |
150 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
151 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
152 | ||
771fe6b9 | 153 | |
3ce0a23d JG |
154 | /* |
155 | * Clocks | |
156 | */ | |
771fe6b9 JG |
157 | struct radeon_clock { |
158 | struct radeon_pll p1pll; | |
159 | struct radeon_pll p2pll; | |
bcc1c2a1 | 160 | struct radeon_pll dcpll; |
771fe6b9 JG |
161 | struct radeon_pll spll; |
162 | struct radeon_pll mpll; | |
163 | /* 10 Khz units */ | |
164 | uint32_t default_mclk; | |
165 | uint32_t default_sclk; | |
bcc1c2a1 AD |
166 | uint32_t default_dispclk; |
167 | uint32_t dp_extclk; | |
771fe6b9 JG |
168 | }; |
169 | ||
7433874e RM |
170 | /* |
171 | * Power management | |
172 | */ | |
173 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 174 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 175 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
56278a8e AD |
176 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
177 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
3ce0a23d | 178 | |
771fe6b9 JG |
179 | /* |
180 | * Fences. | |
181 | */ | |
182 | struct radeon_fence_driver { | |
183 | uint32_t scratch_reg; | |
184 | atomic_t seq; | |
185 | uint32_t last_seq; | |
225758d8 JG |
186 | unsigned long last_jiffies; |
187 | unsigned long last_timeout; | |
771fe6b9 JG |
188 | wait_queue_head_t queue; |
189 | rwlock_t lock; | |
190 | struct list_head created; | |
191 | struct list_head emited; | |
192 | struct list_head signaled; | |
0a0c7596 | 193 | bool initialized; |
771fe6b9 JG |
194 | }; |
195 | ||
196 | struct radeon_fence { | |
197 | struct radeon_device *rdev; | |
198 | struct kref kref; | |
199 | struct list_head list; | |
200 | /* protected by radeon_fence.lock */ | |
201 | uint32_t seq; | |
771fe6b9 JG |
202 | bool emited; |
203 | bool signaled; | |
204 | }; | |
205 | ||
206 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
207 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
208 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
209 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
210 | void radeon_fence_process(struct radeon_device *rdev); | |
211 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
212 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
213 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
214 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
215 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
216 | void radeon_fence_unref(struct radeon_fence **fence); | |
217 | ||
e024e110 DA |
218 | /* |
219 | * Tiling registers | |
220 | */ | |
221 | struct radeon_surface_reg { | |
4c788679 | 222 | struct radeon_bo *bo; |
e024e110 DA |
223 | }; |
224 | ||
225 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
226 | |
227 | /* | |
4c788679 | 228 | * TTM. |
771fe6b9 | 229 | */ |
4c788679 JG |
230 | struct radeon_mman { |
231 | struct ttm_bo_global_ref bo_global_ref; | |
232 | struct ttm_global_reference mem_global_ref; | |
4c788679 | 233 | struct ttm_bo_device bdev; |
0a0c7596 JG |
234 | bool mem_global_referenced; |
235 | bool initialized; | |
4c788679 JG |
236 | }; |
237 | ||
238 | struct radeon_bo { | |
239 | /* Protected by gem.mutex */ | |
240 | struct list_head list; | |
241 | /* Protected by tbo.reserved */ | |
312ea8da JG |
242 | u32 placements[3]; |
243 | struct ttm_placement placement; | |
4c788679 JG |
244 | struct ttm_buffer_object tbo; |
245 | struct ttm_bo_kmap_obj kmap; | |
246 | unsigned pin_count; | |
247 | void *kptr; | |
248 | u32 tiling_flags; | |
249 | u32 pitch; | |
250 | int surface_reg; | |
251 | /* Constant after initialization */ | |
252 | struct radeon_device *rdev; | |
253 | struct drm_gem_object *gobj; | |
254 | }; | |
771fe6b9 | 255 | |
4c788679 | 256 | struct radeon_bo_list { |
771fe6b9 | 257 | struct list_head list; |
4c788679 | 258 | struct radeon_bo *bo; |
771fe6b9 JG |
259 | uint64_t gpu_offset; |
260 | unsigned rdomain; | |
261 | unsigned wdomain; | |
4c788679 | 262 | u32 tiling_flags; |
771fe6b9 JG |
263 | }; |
264 | ||
771fe6b9 JG |
265 | /* |
266 | * GEM objects. | |
267 | */ | |
268 | struct radeon_gem { | |
4c788679 | 269 | struct mutex mutex; |
771fe6b9 JG |
270 | struct list_head objects; |
271 | }; | |
272 | ||
273 | int radeon_gem_init(struct radeon_device *rdev); | |
274 | void radeon_gem_fini(struct radeon_device *rdev); | |
275 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
276 | int alignment, int initial_domain, |
277 | bool discardable, bool kernel, | |
278 | struct drm_gem_object **obj); | |
771fe6b9 JG |
279 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
280 | uint64_t *gpu_addr); | |
281 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
282 | ||
283 | ||
284 | /* | |
285 | * GART structures, functions & helpers | |
286 | */ | |
287 | struct radeon_mc; | |
288 | ||
289 | struct radeon_gart_table_ram { | |
290 | volatile uint32_t *ptr; | |
291 | }; | |
292 | ||
293 | struct radeon_gart_table_vram { | |
4c788679 | 294 | struct radeon_bo *robj; |
771fe6b9 JG |
295 | volatile uint32_t *ptr; |
296 | }; | |
297 | ||
298 | union radeon_gart_table { | |
299 | struct radeon_gart_table_ram ram; | |
300 | struct radeon_gart_table_vram vram; | |
301 | }; | |
302 | ||
a77f1718 | 303 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 304 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
a77f1718 | 305 | |
771fe6b9 JG |
306 | struct radeon_gart { |
307 | dma_addr_t table_addr; | |
308 | unsigned num_gpu_pages; | |
309 | unsigned num_cpu_pages; | |
310 | unsigned table_size; | |
311 | union radeon_gart_table table; | |
312 | struct page **pages; | |
313 | dma_addr_t *pages_addr; | |
314 | bool ready; | |
315 | }; | |
316 | ||
317 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
318 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
319 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
320 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
321 | int radeon_gart_init(struct radeon_device *rdev); | |
322 | void radeon_gart_fini(struct radeon_device *rdev); | |
323 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
324 | int pages); | |
325 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
326 | int pages, struct page **pagelist); | |
327 | ||
328 | ||
329 | /* | |
330 | * GPU MC structures, functions & helpers | |
331 | */ | |
332 | struct radeon_mc { | |
333 | resource_size_t aper_size; | |
334 | resource_size_t aper_base; | |
335 | resource_size_t agp_base; | |
7a50f01a DA |
336 | /* for some chips with <= 32MB we need to lie |
337 | * about vram size near mc fb location */ | |
3ce0a23d | 338 | u64 mc_vram_size; |
d594e46a | 339 | u64 visible_vram_size; |
3ce0a23d JG |
340 | u64 gtt_size; |
341 | u64 gtt_start; | |
342 | u64 gtt_end; | |
3ce0a23d JG |
343 | u64 vram_start; |
344 | u64 vram_end; | |
771fe6b9 | 345 | unsigned vram_width; |
3ce0a23d | 346 | u64 real_vram_size; |
771fe6b9 JG |
347 | int vram_mtrr; |
348 | bool vram_is_ddr; | |
d594e46a | 349 | bool igp_sideport_enabled; |
771fe6b9 JG |
350 | }; |
351 | ||
06b6476d AD |
352 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
353 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
354 | |
355 | /* | |
356 | * GPU scratch registers structures, functions & helpers | |
357 | */ | |
358 | struct radeon_scratch { | |
359 | unsigned num_reg; | |
360 | bool free[32]; | |
361 | uint32_t reg[32]; | |
362 | }; | |
363 | ||
364 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
365 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
366 | ||
367 | ||
368 | /* | |
369 | * IRQS. | |
370 | */ | |
371 | struct radeon_irq { | |
372 | bool installed; | |
373 | bool sw_int; | |
374 | /* FIXME: use a define max crtc rather than hardcode it */ | |
375 | bool crtc_vblank_int[2]; | |
73a6d3fc | 376 | wait_queue_head_t vblank_queue; |
b500f680 AD |
377 | /* FIXME: use defines for max hpd/dacs */ |
378 | bool hpd[6]; | |
1614f8b1 DA |
379 | spinlock_t sw_lock; |
380 | int sw_refcount; | |
771fe6b9 JG |
381 | }; |
382 | ||
383 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
384 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
385 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
386 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
771fe6b9 JG |
387 | |
388 | /* | |
389 | * CP & ring. | |
390 | */ | |
391 | struct radeon_ib { | |
392 | struct list_head list; | |
e821767b | 393 | unsigned idx; |
771fe6b9 JG |
394 | uint64_t gpu_addr; |
395 | struct radeon_fence *fence; | |
e821767b | 396 | uint32_t *ptr; |
771fe6b9 | 397 | uint32_t length_dw; |
e821767b | 398 | bool free; |
771fe6b9 JG |
399 | }; |
400 | ||
ecb114a1 DA |
401 | /* |
402 | * locking - | |
403 | * mutex protects scheduled_ibs, ready, alloc_bm | |
404 | */ | |
771fe6b9 JG |
405 | struct radeon_ib_pool { |
406 | struct mutex mutex; | |
4c788679 | 407 | struct radeon_bo *robj; |
9f93ed39 | 408 | struct list_head bogus_ib; |
771fe6b9 JG |
409 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
410 | bool ready; | |
e821767b | 411 | unsigned head_id; |
771fe6b9 JG |
412 | }; |
413 | ||
414 | struct radeon_cp { | |
4c788679 | 415 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
416 | volatile uint32_t *ring; |
417 | unsigned rptr; | |
418 | unsigned wptr; | |
419 | unsigned wptr_old; | |
420 | unsigned ring_size; | |
421 | unsigned ring_free_dw; | |
422 | int count_dw; | |
423 | uint64_t gpu_addr; | |
424 | uint32_t align_mask; | |
425 | uint32_t ptr_mask; | |
426 | struct mutex mutex; | |
427 | bool ready; | |
428 | }; | |
429 | ||
d8f60cfc AD |
430 | /* |
431 | * R6xx+ IH ring | |
432 | */ | |
433 | struct r600_ih { | |
4c788679 | 434 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
435 | volatile uint32_t *ring; |
436 | unsigned rptr; | |
437 | unsigned wptr; | |
438 | unsigned wptr_old; | |
439 | unsigned ring_size; | |
440 | uint64_t gpu_addr; | |
d8f60cfc AD |
441 | uint32_t ptr_mask; |
442 | spinlock_t lock; | |
443 | bool enabled; | |
444 | }; | |
445 | ||
3ce0a23d | 446 | struct r600_blit { |
ff82f052 | 447 | struct mutex mutex; |
4c788679 | 448 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
449 | u64 shader_gpu_addr; |
450 | u32 vs_offset, ps_offset; | |
451 | u32 state_offset; | |
452 | u32 state_len; | |
453 | u32 vb_used, vb_total; | |
454 | struct radeon_ib *vb_ib; | |
455 | }; | |
456 | ||
771fe6b9 JG |
457 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
458 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
459 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
460 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
461 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
462 | int radeon_ib_test(struct radeon_device *rdev); | |
9f93ed39 | 463 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
771fe6b9 JG |
464 | /* Ring access between begin & end cannot sleep */ |
465 | void radeon_ring_free_size(struct radeon_device *rdev); | |
466 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); | |
467 | void radeon_ring_unlock_commit(struct radeon_device *rdev); | |
468 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
469 | int radeon_ring_test(struct radeon_device *rdev); | |
470 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
471 | void radeon_ring_fini(struct radeon_device *rdev); | |
472 | ||
473 | ||
474 | /* | |
475 | * CS. | |
476 | */ | |
477 | struct radeon_cs_reloc { | |
478 | struct drm_gem_object *gobj; | |
4c788679 JG |
479 | struct radeon_bo *robj; |
480 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
481 | uint32_t handle; |
482 | uint32_t flags; | |
483 | }; | |
484 | ||
485 | struct radeon_cs_chunk { | |
486 | uint32_t chunk_id; | |
487 | uint32_t length_dw; | |
513bcb46 DA |
488 | int kpage_idx[2]; |
489 | uint32_t *kpage[2]; | |
771fe6b9 | 490 | uint32_t *kdata; |
513bcb46 DA |
491 | void __user *user_ptr; |
492 | int last_copied_page; | |
493 | int last_page_index; | |
771fe6b9 JG |
494 | }; |
495 | ||
496 | struct radeon_cs_parser { | |
c8c15ff1 | 497 | struct device *dev; |
771fe6b9 JG |
498 | struct radeon_device *rdev; |
499 | struct drm_file *filp; | |
500 | /* chunks */ | |
501 | unsigned nchunks; | |
502 | struct radeon_cs_chunk *chunks; | |
503 | uint64_t *chunks_array; | |
504 | /* IB */ | |
505 | unsigned idx; | |
506 | /* relocations */ | |
507 | unsigned nrelocs; | |
508 | struct radeon_cs_reloc *relocs; | |
509 | struct radeon_cs_reloc **relocs_ptr; | |
510 | struct list_head validated; | |
511 | /* indices of various chunks */ | |
512 | int chunk_ib_idx; | |
513 | int chunk_relocs_idx; | |
514 | struct radeon_ib *ib; | |
515 | void *track; | |
3ce0a23d | 516 | unsigned family; |
513bcb46 | 517 | int parser_error; |
771fe6b9 JG |
518 | }; |
519 | ||
513bcb46 DA |
520 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
521 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
522 | ||
523 | ||
524 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
525 | { | |
526 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
527 | u32 pg_idx, pg_offset; | |
528 | u32 idx_value = 0; | |
529 | int new_page; | |
530 | ||
531 | pg_idx = (idx * 4) / PAGE_SIZE; | |
532 | pg_offset = (idx * 4) % PAGE_SIZE; | |
533 | ||
534 | if (ibc->kpage_idx[0] == pg_idx) | |
535 | return ibc->kpage[0][pg_offset/4]; | |
536 | if (ibc->kpage_idx[1] == pg_idx) | |
537 | return ibc->kpage[1][pg_offset/4]; | |
538 | ||
539 | new_page = radeon_cs_update_pages(p, pg_idx); | |
540 | if (new_page < 0) { | |
541 | p->parser_error = new_page; | |
542 | return 0; | |
543 | } | |
544 | ||
545 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
546 | return idx_value; | |
547 | } | |
548 | ||
771fe6b9 JG |
549 | struct radeon_cs_packet { |
550 | unsigned idx; | |
551 | unsigned type; | |
552 | unsigned reg; | |
553 | unsigned opcode; | |
554 | int count; | |
555 | unsigned one_reg_wr; | |
556 | }; | |
557 | ||
558 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
559 | struct radeon_cs_packet *pkt, | |
560 | unsigned idx, unsigned reg); | |
561 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
562 | struct radeon_cs_packet *pkt); | |
563 | ||
564 | ||
565 | /* | |
566 | * AGP | |
567 | */ | |
568 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 569 | void radeon_agp_resume(struct radeon_device *rdev); |
771fe6b9 JG |
570 | void radeon_agp_fini(struct radeon_device *rdev); |
571 | ||
572 | ||
573 | /* | |
574 | * Writeback | |
575 | */ | |
576 | struct radeon_wb { | |
4c788679 | 577 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
578 | volatile uint32_t *wb; |
579 | uint64_t gpu_addr; | |
580 | }; | |
581 | ||
c93bb85b JG |
582 | /** |
583 | * struct radeon_pm - power management datas | |
584 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
585 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
586 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
587 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
588 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
589 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
590 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
591 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
592 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
593 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
594 | * @needed_bandwidth: current bandwidth needs | |
595 | * | |
596 | * It keeps track of various data needed to take powermanagement decision. | |
597 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
598 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
599 | * (type of memory, bus size, efficiency, ...) | |
600 | */ | |
c913e23a RM |
601 | enum radeon_pm_state { |
602 | PM_STATE_DISABLED, | |
603 | PM_STATE_MINIMUM, | |
604 | PM_STATE_PAUSED, | |
605 | PM_STATE_ACTIVE | |
606 | }; | |
607 | enum radeon_pm_action { | |
608 | PM_ACTION_NONE, | |
609 | PM_ACTION_MINIMUM, | |
610 | PM_ACTION_DOWNCLOCK, | |
611 | PM_ACTION_UPCLOCK | |
612 | }; | |
56278a8e AD |
613 | |
614 | enum radeon_voltage_type { | |
615 | VOLTAGE_NONE = 0, | |
616 | VOLTAGE_GPIO, | |
617 | VOLTAGE_VDDC, | |
618 | VOLTAGE_SW | |
619 | }; | |
620 | ||
0ec0e74f AD |
621 | enum radeon_pm_state_type { |
622 | POWER_STATE_TYPE_DEFAULT, | |
623 | POWER_STATE_TYPE_POWERSAVE, | |
624 | POWER_STATE_TYPE_BATTERY, | |
625 | POWER_STATE_TYPE_BALANCED, | |
626 | POWER_STATE_TYPE_PERFORMANCE, | |
627 | }; | |
628 | ||
516d0e46 AD |
629 | enum radeon_pm_clock_mode_type { |
630 | POWER_MODE_TYPE_DEFAULT, | |
631 | POWER_MODE_TYPE_LOW, | |
632 | POWER_MODE_TYPE_MID, | |
633 | POWER_MODE_TYPE_HIGH, | |
634 | }; | |
635 | ||
56278a8e AD |
636 | struct radeon_voltage { |
637 | enum radeon_voltage_type type; | |
638 | /* gpio voltage */ | |
639 | struct radeon_gpio_rec gpio; | |
640 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
641 | bool active_high; /* voltage drop is active when bit is high */ | |
642 | /* VDDC voltage */ | |
643 | u8 vddc_id; /* index into vddc voltage table */ | |
644 | u8 vddci_id; /* index into vddci voltage table */ | |
645 | bool vddci_enabled; | |
646 | /* r6xx+ sw */ | |
647 | u32 voltage; | |
648 | }; | |
649 | ||
650 | struct radeon_pm_non_clock_info { | |
651 | /* pcie lanes */ | |
652 | int pcie_lanes; | |
653 | /* standardized non-clock flags */ | |
654 | u32 flags; | |
655 | }; | |
656 | ||
657 | struct radeon_pm_clock_info { | |
658 | /* memory clock */ | |
659 | u32 mclk; | |
660 | /* engine clock */ | |
661 | u32 sclk; | |
662 | /* voltage info */ | |
663 | struct radeon_voltage voltage; | |
664 | /* standardized clock flags - not sure we'll need these */ | |
665 | u32 flags; | |
666 | }; | |
667 | ||
668 | struct radeon_power_state { | |
0ec0e74f | 669 | enum radeon_pm_state_type type; |
56278a8e AD |
670 | /* XXX: use a define for num clock modes */ |
671 | struct radeon_pm_clock_info clock_info[8]; | |
672 | /* number of valid clock modes in this power state */ | |
673 | int num_clock_modes; | |
56278a8e AD |
674 | struct radeon_pm_clock_info *default_clock_mode; |
675 | /* non clock info about this state */ | |
676 | struct radeon_pm_non_clock_info non_clock_info; | |
677 | bool voltage_drop_active; | |
678 | }; | |
679 | ||
27459324 RM |
680 | /* |
681 | * Some modes are overclocked by very low value, accept them | |
682 | */ | |
683 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
684 | ||
c93bb85b | 685 | struct radeon_pm { |
c913e23a | 686 | struct mutex mutex; |
c913e23a RM |
687 | struct delayed_work idle_work; |
688 | enum radeon_pm_state state; | |
689 | enum radeon_pm_action planned_action; | |
690 | unsigned long action_timeout; | |
691 | bool downclocked; | |
c913e23a RM |
692 | int active_crtcs; |
693 | int req_vblank; | |
839461d3 | 694 | bool vblank_sync; |
c93bb85b JG |
695 | fixed20_12 max_bandwidth; |
696 | fixed20_12 igp_sideport_mclk; | |
697 | fixed20_12 igp_system_mclk; | |
698 | fixed20_12 igp_ht_link_clk; | |
699 | fixed20_12 igp_ht_link_width; | |
700 | fixed20_12 k8_bandwidth; | |
701 | fixed20_12 sideport_bandwidth; | |
702 | fixed20_12 ht_bandwidth; | |
703 | fixed20_12 core_bandwidth; | |
704 | fixed20_12 sclk; | |
f47299c5 | 705 | fixed20_12 mclk; |
c93bb85b | 706 | fixed20_12 needed_bandwidth; |
56278a8e AD |
707 | /* XXX: use a define for num power modes */ |
708 | struct radeon_power_state power_state[8]; | |
709 | /* number of valid power states */ | |
710 | int num_power_states; | |
711 | struct radeon_power_state *current_power_state; | |
9038dfdf | 712 | struct radeon_pm_clock_info *current_clock_mode; |
516d0e46 | 713 | struct radeon_power_state *requested_power_state; |
9038dfdf | 714 | struct radeon_pm_clock_info *requested_clock_mode; |
56278a8e | 715 | struct radeon_power_state *default_power_state; |
29fb52ca | 716 | struct radeon_i2c_chan *i2c_bus; |
c93bb85b JG |
717 | }; |
718 | ||
771fe6b9 JG |
719 | |
720 | /* | |
721 | * Benchmarking | |
722 | */ | |
723 | void radeon_benchmark(struct radeon_device *rdev); | |
724 | ||
725 | ||
ecc0b326 MD |
726 | /* |
727 | * Testing | |
728 | */ | |
729 | void radeon_test_moves(struct radeon_device *rdev); | |
730 | ||
731 | ||
771fe6b9 JG |
732 | /* |
733 | * Debugfs | |
734 | */ | |
735 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
736 | struct drm_info_list *files, | |
737 | unsigned nfiles); | |
738 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
739 | |
740 | ||
741 | /* | |
742 | * ASIC specific functions. | |
743 | */ | |
744 | struct radeon_asic { | |
068a117c | 745 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
746 | void (*fini)(struct radeon_device *rdev); |
747 | int (*resume)(struct radeon_device *rdev); | |
748 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 749 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
225758d8 | 750 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
a2d07b74 | 751 | int (*asic_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
752 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
753 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
754 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
755 | void (*cp_fini)(struct radeon_device *rdev); | |
756 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 757 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 758 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
759 | int (*ring_test)(struct radeon_device *rdev); |
760 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
761 | int (*irq_set)(struct radeon_device *rdev); |
762 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 763 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
764 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
765 | int (*cs_parse)(struct radeon_cs_parser *p); | |
766 | int (*copy_blit)(struct radeon_device *rdev, | |
767 | uint64_t src_offset, | |
768 | uint64_t dst_offset, | |
769 | unsigned num_pages, | |
770 | struct radeon_fence *fence); | |
771 | int (*copy_dma)(struct radeon_device *rdev, | |
772 | uint64_t src_offset, | |
773 | uint64_t dst_offset, | |
774 | unsigned num_pages, | |
775 | struct radeon_fence *fence); | |
776 | int (*copy)(struct radeon_device *rdev, | |
777 | uint64_t src_offset, | |
778 | uint64_t dst_offset, | |
779 | unsigned num_pages, | |
780 | struct radeon_fence *fence); | |
7433874e | 781 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 782 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 783 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 | 784 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
c836a412 | 785 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
771fe6b9 JG |
786 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
787 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
788 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
789 | uint32_t tiling_flags, uint32_t pitch, | |
790 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 791 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
c93bb85b | 792 | void (*bandwidth_update)(struct radeon_device *rdev); |
429770b3 AD |
793 | void (*hpd_init)(struct radeon_device *rdev); |
794 | void (*hpd_fini)(struct radeon_device *rdev); | |
795 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
796 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
062b389c JG |
797 | /* ioctl hw specific callback. Some hw might want to perform special |
798 | * operation on specific ioctl. For instance on wait idle some hw | |
799 | * might want to perform and HDP flush through MMIO as it seems that | |
800 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
801 | * through ring. | |
802 | */ | |
803 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
771fe6b9 JG |
804 | }; |
805 | ||
21f9a437 JG |
806 | /* |
807 | * Asic structures | |
808 | */ | |
225758d8 JG |
809 | struct r100_gpu_lockup { |
810 | unsigned long last_jiffies; | |
811 | u32 last_cp_rptr; | |
812 | }; | |
813 | ||
551ebd83 | 814 | struct r100_asic { |
225758d8 JG |
815 | const unsigned *reg_safe_bm; |
816 | unsigned reg_safe_bm_size; | |
817 | u32 hdp_cntl; | |
818 | struct r100_gpu_lockup lockup; | |
551ebd83 DA |
819 | }; |
820 | ||
21f9a437 | 821 | struct r300_asic { |
225758d8 JG |
822 | const unsigned *reg_safe_bm; |
823 | unsigned reg_safe_bm_size; | |
824 | u32 resync_scratch; | |
825 | u32 hdp_cntl; | |
826 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
827 | }; |
828 | ||
829 | struct r600_asic { | |
225758d8 JG |
830 | unsigned max_pipes; |
831 | unsigned max_tile_pipes; | |
832 | unsigned max_simds; | |
833 | unsigned max_backends; | |
834 | unsigned max_gprs; | |
835 | unsigned max_threads; | |
836 | unsigned max_stack_entries; | |
837 | unsigned max_hw_contexts; | |
838 | unsigned max_gs_threads; | |
839 | unsigned sx_max_export_size; | |
840 | unsigned sx_max_export_pos_size; | |
841 | unsigned sx_max_export_smx_size; | |
842 | unsigned sq_num_cf_insts; | |
843 | unsigned tiling_nbanks; | |
844 | unsigned tiling_npipes; | |
845 | unsigned tiling_group_size; | |
846 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
847 | }; |
848 | ||
849 | struct rv770_asic { | |
225758d8 JG |
850 | unsigned max_pipes; |
851 | unsigned max_tile_pipes; | |
852 | unsigned max_simds; | |
853 | unsigned max_backends; | |
854 | unsigned max_gprs; | |
855 | unsigned max_threads; | |
856 | unsigned max_stack_entries; | |
857 | unsigned max_hw_contexts; | |
858 | unsigned max_gs_threads; | |
859 | unsigned sx_max_export_size; | |
860 | unsigned sx_max_export_pos_size; | |
861 | unsigned sx_max_export_smx_size; | |
862 | unsigned sq_num_cf_insts; | |
863 | unsigned sx_num_of_sets; | |
864 | unsigned sc_prim_fifo_size; | |
865 | unsigned sc_hiz_tile_fifo_size; | |
866 | unsigned sc_earlyz_tile_fifo_fize; | |
867 | unsigned tiling_nbanks; | |
868 | unsigned tiling_npipes; | |
869 | unsigned tiling_group_size; | |
870 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
871 | }; |
872 | ||
32fcdbf4 AD |
873 | struct evergreen_asic { |
874 | unsigned num_ses; | |
875 | unsigned max_pipes; | |
876 | unsigned max_tile_pipes; | |
877 | unsigned max_simds; | |
878 | unsigned max_backends; | |
879 | unsigned max_gprs; | |
880 | unsigned max_threads; | |
881 | unsigned max_stack_entries; | |
882 | unsigned max_hw_contexts; | |
883 | unsigned max_gs_threads; | |
884 | unsigned sx_max_export_size; | |
885 | unsigned sx_max_export_pos_size; | |
886 | unsigned sx_max_export_smx_size; | |
887 | unsigned sq_num_cf_insts; | |
888 | unsigned sx_num_of_sets; | |
889 | unsigned sc_prim_fifo_size; | |
890 | unsigned sc_hiz_tile_fifo_size; | |
891 | unsigned sc_earlyz_tile_fifo_size; | |
892 | unsigned tiling_nbanks; | |
893 | unsigned tiling_npipes; | |
894 | unsigned tiling_group_size; | |
895 | }; | |
896 | ||
068a117c JG |
897 | union radeon_asic_config { |
898 | struct r300_asic r300; | |
551ebd83 | 899 | struct r100_asic r100; |
3ce0a23d JG |
900 | struct r600_asic r600; |
901 | struct rv770_asic rv770; | |
32fcdbf4 | 902 | struct evergreen_asic evergreen; |
068a117c JG |
903 | }; |
904 | ||
0a10c851 DV |
905 | /* |
906 | * asic initizalization from radeon_asic.c | |
907 | */ | |
908 | void radeon_agp_disable(struct radeon_device *rdev); | |
909 | int radeon_asic_init(struct radeon_device *rdev); | |
910 | ||
771fe6b9 JG |
911 | |
912 | /* | |
913 | * IOCTL. | |
914 | */ | |
915 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
916 | struct drm_file *filp); | |
917 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
918 | struct drm_file *filp); | |
919 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
920 | struct drm_file *file_priv); | |
921 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
922 | struct drm_file *file_priv); | |
923 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
924 | struct drm_file *file_priv); | |
925 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
926 | struct drm_file *file_priv); | |
927 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
928 | struct drm_file *filp); | |
929 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
930 | struct drm_file *filp); | |
931 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
932 | struct drm_file *filp); | |
933 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
934 | struct drm_file *filp); | |
935 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
936 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
937 | struct drm_file *filp); | |
938 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
939 | struct drm_file *filp); | |
771fe6b9 JG |
940 | |
941 | ||
942 | /* | |
943 | * Core structure, functions and helpers. | |
944 | */ | |
945 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
946 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
947 | ||
948 | struct radeon_device { | |
9f022ddf | 949 | struct device *dev; |
771fe6b9 JG |
950 | struct drm_device *ddev; |
951 | struct pci_dev *pdev; | |
952 | /* ASIC */ | |
068a117c | 953 | union radeon_asic_config config; |
771fe6b9 JG |
954 | enum radeon_family family; |
955 | unsigned long flags; | |
956 | int usec_timeout; | |
957 | enum radeon_pll_errata pll_errata; | |
958 | int num_gb_pipes; | |
f779b3e5 | 959 | int num_z_pipes; |
771fe6b9 JG |
960 | int disp_priority; |
961 | /* BIOS */ | |
962 | uint8_t *bios; | |
963 | bool is_atom_bios; | |
964 | uint16_t bios_header_start; | |
4c788679 | 965 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 966 | struct fb_info *fbdev_info; |
4c788679 | 967 | struct radeon_bo *fbdev_rbo; |
771fe6b9 JG |
968 | struct radeon_framebuffer *fbdev_rfb; |
969 | /* Register mmio */ | |
4c9bc75c DA |
970 | resource_size_t rmmio_base; |
971 | resource_size_t rmmio_size; | |
771fe6b9 | 972 | void *rmmio; |
771fe6b9 JG |
973 | radeon_rreg_t mc_rreg; |
974 | radeon_wreg_t mc_wreg; | |
975 | radeon_rreg_t pll_rreg; | |
976 | radeon_wreg_t pll_wreg; | |
de1b2898 | 977 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
978 | radeon_rreg_t pciep_rreg; |
979 | radeon_wreg_t pciep_wreg; | |
980 | struct radeon_clock clock; | |
981 | struct radeon_mc mc; | |
982 | struct radeon_gart gart; | |
983 | struct radeon_mode_info mode_info; | |
984 | struct radeon_scratch scratch; | |
985 | struct radeon_mman mman; | |
986 | struct radeon_fence_driver fence_drv; | |
987 | struct radeon_cp cp; | |
988 | struct radeon_ib_pool ib_pool; | |
989 | struct radeon_irq irq; | |
990 | struct radeon_asic *asic; | |
991 | struct radeon_gem gem; | |
c93bb85b | 992 | struct radeon_pm pm; |
f657c2a7 | 993 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
994 | struct mutex cs_mutex; |
995 | struct radeon_wb wb; | |
3ce0a23d | 996 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
997 | bool gpu_lockup; |
998 | bool shutdown; | |
999 | bool suspend; | |
ad49f501 | 1000 | bool need_dma32; |
733289c2 | 1001 | bool accel_working; |
e024e110 | 1002 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1003 | const struct firmware *me_fw; /* all family ME firmware */ |
1004 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1005 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
3ce0a23d | 1006 | struct r600_blit r600_blit; |
3e5cb98d | 1007 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1008 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 AD |
1009 | struct workqueue_struct *wq; |
1010 | struct work_struct hotplug_work; | |
18917b60 | 1011 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1012 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
dafc3bd5 CK |
1013 | |
1014 | /* audio stuff */ | |
1015 | struct timer_list audio_timer; | |
1016 | int audio_channels; | |
1017 | int audio_rate; | |
1018 | int audio_bits_per_sample; | |
1019 | uint8_t audio_status_bits; | |
1020 | uint8_t audio_category_code; | |
6a9ee8af DA |
1021 | |
1022 | bool powered_down; | |
771fe6b9 JG |
1023 | }; |
1024 | ||
1025 | int radeon_device_init(struct radeon_device *rdev, | |
1026 | struct drm_device *ddev, | |
1027 | struct pci_dev *pdev, | |
1028 | uint32_t flags); | |
1029 | void radeon_device_fini(struct radeon_device *rdev); | |
1030 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1031 | ||
3ce0a23d JG |
1032 | /* r600 blit */ |
1033 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
1034 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
1035 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
1036 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
1037 | int size_bytes); | |
1038 | ||
de1b2898 DA |
1039 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1040 | { | |
07bec2df | 1041 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1042 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1043 | else { | |
1044 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1045 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1050 | { | |
07bec2df | 1051 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1052 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1053 | else { | |
1054 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1055 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1056 | } | |
1057 | } | |
1058 | ||
4c788679 JG |
1059 | /* |
1060 | * Cast helper | |
1061 | */ | |
1062 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1063 | |
1064 | /* | |
1065 | * Registers read & write functions. | |
1066 | */ | |
1067 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
1068 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 1069 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1070 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1071 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1072 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1073 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1074 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1075 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1076 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1077 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1078 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1079 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1080 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1081 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1082 | #define WREG32_P(reg, val, mask) \ |
1083 | do { \ | |
1084 | uint32_t tmp_ = RREG32(reg); \ | |
1085 | tmp_ &= (mask); \ | |
1086 | tmp_ |= ((val) & ~(mask)); \ | |
1087 | WREG32(reg, tmp_); \ | |
1088 | } while (0) | |
1089 | #define WREG32_PLL_P(reg, val, mask) \ | |
1090 | do { \ | |
1091 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1092 | tmp_ &= (mask); \ | |
1093 | tmp_ |= ((val) & ~(mask)); \ | |
1094 | WREG32_PLL(reg, tmp_); \ | |
1095 | } while (0) | |
3ce0a23d | 1096 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
771fe6b9 | 1097 | |
de1b2898 DA |
1098 | /* |
1099 | * Indirect registers accessor | |
1100 | */ | |
1101 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1102 | { | |
1103 | uint32_t r; | |
1104 | ||
1105 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1106 | r = RREG32(RADEON_PCIE_DATA); | |
1107 | return r; | |
1108 | } | |
1109 | ||
1110 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1111 | { | |
1112 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1113 | WREG32(RADEON_PCIE_DATA, (v)); | |
1114 | } | |
1115 | ||
771fe6b9 JG |
1116 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1117 | ||
1118 | ||
1119 | /* | |
1120 | * ASICs helpers. | |
1121 | */ | |
b995e433 DA |
1122 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1123 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1124 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1125 | (rdev->family == CHIP_RV200) || \ | |
1126 | (rdev->family == CHIP_RS100) || \ | |
1127 | (rdev->family == CHIP_RS200) || \ | |
1128 | (rdev->family == CHIP_RV250) || \ | |
1129 | (rdev->family == CHIP_RV280) || \ | |
1130 | (rdev->family == CHIP_RS300)) | |
1131 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1132 | (rdev->family == CHIP_RV350) || \ | |
1133 | (rdev->family == CHIP_R350) || \ | |
1134 | (rdev->family == CHIP_RV380) || \ | |
1135 | (rdev->family == CHIP_R420) || \ | |
1136 | (rdev->family == CHIP_R423) || \ | |
1137 | (rdev->family == CHIP_RV410) || \ | |
1138 | (rdev->family == CHIP_RS400) || \ | |
1139 | (rdev->family == CHIP_RS480)) | |
1140 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
1141 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) | |
1142 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1143 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
771fe6b9 JG |
1144 | |
1145 | /* | |
1146 | * BIOS helpers. | |
1147 | */ | |
1148 | #define RBIOS8(i) (rdev->bios[i]) | |
1149 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1150 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1151 | ||
1152 | int radeon_combios_init(struct radeon_device *rdev); | |
1153 | void radeon_combios_fini(struct radeon_device *rdev); | |
1154 | int radeon_atombios_init(struct radeon_device *rdev); | |
1155 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1156 | ||
1157 | ||
1158 | /* | |
1159 | * RING helpers. | |
1160 | */ | |
771fe6b9 JG |
1161 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1162 | { | |
1163 | #if DRM_DEBUG_CODE | |
1164 | if (rdev->cp.count_dw <= 0) { | |
1165 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
1166 | } | |
1167 | #endif | |
1168 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
1169 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
1170 | rdev->cp.count_dw--; | |
1171 | rdev->cp.ring_free_dw--; | |
1172 | } | |
1173 | ||
1174 | ||
1175 | /* | |
1176 | * ASICs macro. | |
1177 | */ | |
068a117c | 1178 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1179 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1180 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1181 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 1182 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 1183 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
225758d8 | 1184 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
a2d07b74 | 1185 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
771fe6b9 JG |
1186 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1187 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 1188 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 1189 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
1190 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1191 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
1192 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1193 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 1194 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
1195 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1196 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
1197 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1198 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1199 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1200 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1201 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1202 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
c836a412 | 1203 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
771fe6b9 JG |
1204 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1205 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1206 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1207 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1208 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
429770b3 AD |
1209 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1210 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1211 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1212 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
771fe6b9 | 1213 | |
6cf8a3f5 | 1214 | /* Common functions */ |
700a0cc0 | 1215 | /* AGP */ |
90aca4d2 | 1216 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1217 | extern void radeon_agp_disable(struct radeon_device *rdev); |
4aac0473 | 1218 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
82568565 | 1219 | extern void radeon_gart_restore(struct radeon_device *rdev); |
21f9a437 JG |
1220 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1221 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1222 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1223 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1224 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1225 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 JG |
1226 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1227 | extern void radeon_clocks_fini(struct radeon_device *rdev); | |
1228 | extern void radeon_scratch_init(struct radeon_device *rdev); | |
1229 | extern void radeon_surface_init(struct radeon_device *rdev); | |
1230 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1231 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1232 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1233 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1234 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1235 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1236 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1237 | extern int radeon_resume_kms(struct drm_device *dev); |
1238 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
6cf8a3f5 | 1239 | |
a18d7ea1 | 1240 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
225758d8 JG |
1241 | extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
1242 | extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); | |
9f022ddf | 1243 | |
d4550907 JG |
1244 | /* rv200,rv250,rv280 */ |
1245 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
9f022ddf JG |
1246 | |
1247 | /* r300,r350,rv350,rv370,rv380 */ | |
1248 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1249 | extern void r300_mc_program(struct radeon_device *rdev); | |
d594e46a | 1250 | extern void r300_mc_init(struct radeon_device *rdev); |
ca6ffc64 JG |
1251 | extern void r300_clock_startup(struct radeon_device *rdev); |
1252 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1253 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1254 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1255 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1256 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1257 | |
905b6822 | 1258 | /* r420,r423,rv410 */ |
21f9a437 JG |
1259 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1260 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1261 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1262 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1263 | |
21f9a437 | 1264 | /* rv515 */ |
d39c3b89 JG |
1265 | struct rv515_mc_save { |
1266 | u32 d1vga_control; | |
1267 | u32 d2vga_control; | |
1268 | u32 vga_render_control; | |
1269 | u32 vga_hdp_control; | |
1270 | u32 d1crtc_control; | |
1271 | u32 d2crtc_control; | |
1272 | }; | |
21f9a437 | 1273 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1274 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1275 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1276 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1277 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1278 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1279 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1280 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1281 | |
3bc68535 JG |
1282 | /* rs400 */ |
1283 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1284 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1285 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1286 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1287 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1288 | ||
1289 | /* rs600 */ | |
1290 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1291 | extern int rs600_irq_set(struct radeon_device *rdev); |
1292 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1293 | |
21f9a437 JG |
1294 | /* rs690, rs740 */ |
1295 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1296 | struct drm_display_mode *mode1, | |
1297 | struct drm_display_mode *mode2); | |
1298 | ||
1299 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
d594e46a | 1300 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
21f9a437 JG |
1301 | extern bool r600_card_posted(struct radeon_device *rdev); |
1302 | extern void r600_cp_stop(struct radeon_device *rdev); | |
fe251e2f | 1303 | extern int r600_cp_start(struct radeon_device *rdev); |
21f9a437 JG |
1304 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1305 | extern int r600_cp_resume(struct radeon_device *rdev); | |
655efd3d | 1306 | extern void r600_cp_fini(struct radeon_device *rdev); |
21f9a437 | 1307 | extern int r600_count_pipe_bits(uint32_t val); |
21f9a437 | 1308 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
4aac0473 | 1309 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1310 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1311 | extern int r600_ib_test(struct radeon_device *rdev); | |
1312 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 | 1313 | extern void r600_wb_fini(struct radeon_device *rdev); |
81cc35bf JG |
1314 | extern int r600_wb_enable(struct radeon_device *rdev); |
1315 | extern void r600_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1316 | extern void r600_scratch_init(struct radeon_device *rdev); |
1317 | extern int r600_blit_init(struct radeon_device *rdev); | |
1318 | extern void r600_blit_fini(struct radeon_device *rdev); | |
d8f60cfc | 1319 | extern int r600_init_microcode(struct radeon_device *rdev); |
a2d07b74 | 1320 | extern int r600_asic_reset(struct radeon_device *rdev); |
d8f60cfc AD |
1321 | /* r600 irq */ |
1322 | extern int r600_irq_init(struct radeon_device *rdev); | |
1323 | extern void r600_irq_fini(struct radeon_device *rdev); | |
1324 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1325 | extern int r600_irq_set(struct radeon_device *rdev); | |
0c45249f JG |
1326 | extern void r600_irq_suspend(struct radeon_device *rdev); |
1327 | /* r600 audio */ | |
dafc3bd5 CK |
1328 | extern int r600_audio_init(struct radeon_device *rdev); |
1329 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); | |
1330 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | |
1331 | extern void r600_audio_fini(struct radeon_device *rdev); | |
1332 | extern void r600_hdmi_init(struct drm_encoder *encoder); | |
2cd6218c RM |
1333 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1334 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 CK |
1335 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1336 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | |
1337 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, | |
1338 | int channels, | |
1339 | int rate, | |
1340 | int bps, | |
1341 | uint8_t status_bits, | |
1342 | uint8_t category_code); | |
1343 | ||
fe251e2f AD |
1344 | extern void r700_cp_stop(struct radeon_device *rdev); |
1345 | extern void r700_cp_fini(struct radeon_device *rdev); | |
1346 | ||
bcc1c2a1 AD |
1347 | /* evergreen */ |
1348 | struct evergreen_mc_save { | |
1349 | u32 vga_control[6]; | |
1350 | u32 vga_render_control; | |
1351 | u32 vga_hdp_control; | |
1352 | u32 crtc_control[6]; | |
1353 | }; | |
1354 | ||
4c788679 JG |
1355 | #include "radeon_object.h" |
1356 | ||
771fe6b9 | 1357 | #endif |