Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_ASIC_H__ | |
29 | #define __RADEON_ASIC_H__ | |
30 | ||
31 | /* | |
32 | * common functions | |
33 | */ | |
7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
38 | ||
7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
44 | ||
37e9b6a6 | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
6d92f81d | 46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
37e9b6a6 | 47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
6d92f81d | 48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
37e9b6a6 | 49 | |
771fe6b9 | 50 | /* |
44ca7478 | 51 | * r100,rv100,rs100,rv200,rs200 |
771fe6b9 | 52 | */ |
2b497502 DV |
53 | struct r100_mc_save { |
54 | u32 GENMO_WT; | |
55 | u32 CRTC_EXT_CNTL; | |
56 | u32 CRTC_GEN_CNTL; | |
57 | u32 CRTC2_GEN_CNTL; | |
58 | u32 CUR_OFFSET; | |
59 | u32 CUR2_OFFSET; | |
60 | }; | |
61 | int r100_init(struct radeon_device *rdev); | |
62 | void r100_fini(struct radeon_device *rdev); | |
63 | int r100_suspend(struct radeon_device *rdev); | |
64 | int r100_resume(struct radeon_device *rdev); | |
28d52043 | 65 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
e32eb50d | 66 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
a2d07b74 | 67 | int r100_asic_reset(struct radeon_device *rdev); |
7ed220d7 | 68 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
69 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
70 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
f712812e | 71 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
771fe6b9 JG |
72 | int r100_irq_set(struct radeon_device *rdev); |
73 | int r100_irq_process(struct radeon_device *rdev); | |
74 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
75 | struct radeon_fence *fence); | |
1654b817 | 76 | bool r100_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 77 | struct radeon_ring *cp, |
15d3332f | 78 | struct radeon_semaphore *semaphore, |
7b1f2485 | 79 | bool emit_wait); |
771fe6b9 JG |
80 | int r100_cs_parse(struct radeon_cs_parser *p); |
81 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
82 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
83 | int r100_copy_blit(struct radeon_device *rdev, | |
84 | uint64_t src_offset, | |
85 | uint64_t dst_offset, | |
003cefe0 | 86 | unsigned num_gpu_pages, |
876dc9f3 | 87 | struct radeon_fence **fence); |
e024e110 DA |
88 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
89 | uint32_t tiling_flags, uint32_t pitch, | |
90 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 91 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
c93bb85b | 92 | void r100_bandwidth_update(struct radeon_device *rdev); |
3ce0a23d | 93 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
e32eb50d | 94 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
429770b3 AD |
95 | void r100_hpd_init(struct radeon_device *rdev); |
96 | void r100_hpd_fini(struct radeon_device *rdev); | |
97 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
98 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
99 | enum radeon_hpd_id hpd); | |
2b497502 DV |
100 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
101 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
102 | void r100_cp_disable(struct radeon_device *rdev); | |
103 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
104 | void r100_cp_fini(struct radeon_device *rdev); | |
105 | int r100_pci_gart_init(struct radeon_device *rdev); | |
106 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
107 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
108 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
109 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
110 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
f712812e | 111 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
2b497502 DV |
112 | void r100_irq_disable(struct radeon_device *rdev); |
113 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
114 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
115 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
2b497502 DV |
116 | int r100_cp_reset(struct radeon_device *rdev); |
117 | void r100_vga_render_disable(struct radeon_device *rdev); | |
4c712e6c | 118 | void r100_restore_sanity(struct radeon_device *rdev); |
2b497502 DV |
119 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
120 | struct radeon_cs_packet *pkt, | |
121 | struct radeon_bo *robj); | |
122 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
123 | struct radeon_cs_packet *pkt, | |
124 | const unsigned *auth, unsigned n, | |
125 | radeon_packet0_check_t check); | |
126 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
127 | struct radeon_cs_packet *pkt, | |
128 | unsigned idx); | |
129 | void r100_enable_bm(struct radeon_device *rdev); | |
130 | void r100_set_common_regs(struct radeon_device *rdev); | |
90aca4d2 | 131 | void r100_bm_disable(struct radeon_device *rdev); |
def9ba9c | 132 | extern bool r100_gui_idle(struct radeon_device *rdev); |
49e02b73 AD |
133 | extern void r100_pm_misc(struct radeon_device *rdev); |
134 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
135 | extern void r100_pm_finish(struct radeon_device *rdev); | |
ce8f5370 AD |
136 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
137 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
157fa14d CK |
138 | extern void r100_page_flip(struct radeon_device *rdev, int crtc, |
139 | u64 crtc_base); | |
140 | extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); | |
3ae19b75 | 141 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
89e5181f | 142 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
bae6b562 | 143 | |
ea31bf69 AD |
144 | u32 r100_gfx_get_rptr(struct radeon_device *rdev, |
145 | struct radeon_ring *ring); | |
146 | u32 r100_gfx_get_wptr(struct radeon_device *rdev, | |
147 | struct radeon_ring *ring); | |
148 | void r100_gfx_set_wptr(struct radeon_device *rdev, | |
149 | struct radeon_ring *ring); | |
150 | ||
44ca7478 PN |
151 | /* |
152 | * r200,rv250,rs300,rv280 | |
153 | */ | |
154 | extern int r200_copy_dma(struct radeon_device *rdev, | |
187f3da3 DV |
155 | uint64_t src_offset, |
156 | uint64_t dst_offset, | |
003cefe0 | 157 | unsigned num_gpu_pages, |
876dc9f3 | 158 | struct radeon_fence **fence); |
187f3da3 | 159 | void r200_set_safe_registers(struct radeon_device *rdev); |
771fe6b9 JG |
160 | |
161 | /* | |
162 | * r300,r350,rv350,rv380 | |
163 | */ | |
207bf9e9 JG |
164 | extern int r300_init(struct radeon_device *rdev); |
165 | extern void r300_fini(struct radeon_device *rdev); | |
166 | extern int r300_suspend(struct radeon_device *rdev); | |
167 | extern int r300_resume(struct radeon_device *rdev); | |
a2d07b74 | 168 | extern int r300_asic_reset(struct radeon_device *rdev); |
f712812e | 169 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
207bf9e9 JG |
170 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
171 | struct radeon_fence *fence); | |
172 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
173 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
174 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
207bf9e9 | 175 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
c836a412 | 176 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
187f3da3 DV |
177 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
178 | extern void r300_mc_program(struct radeon_device *rdev); | |
179 | extern void r300_mc_init(struct radeon_device *rdev); | |
180 | extern void r300_clock_startup(struct radeon_device *rdev); | |
181 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
182 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
183 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
184 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
185 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
89e5181f | 186 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
44ca7478 | 187 | |
771fe6b9 JG |
188 | /* |
189 | * r420,r423,rv410 | |
190 | */ | |
9f022ddf JG |
191 | extern int r420_init(struct radeon_device *rdev); |
192 | extern void r420_fini(struct radeon_device *rdev); | |
193 | extern int r420_suspend(struct radeon_device *rdev); | |
194 | extern int r420_resume(struct radeon_device *rdev); | |
ce8f5370 | 195 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
187f3da3 DV |
196 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
197 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
198 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
199 | extern void r420_pipes_init(struct radeon_device *rdev); | |
771fe6b9 JG |
200 | |
201 | /* | |
202 | * rs400,rs480 | |
203 | */ | |
ca6ffc64 JG |
204 | extern int rs400_init(struct radeon_device *rdev); |
205 | extern void rs400_fini(struct radeon_device *rdev); | |
206 | extern int rs400_suspend(struct radeon_device *rdev); | |
207 | extern int rs400_resume(struct radeon_device *rdev); | |
771fe6b9 JG |
208 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
209 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
210 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
211 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
187f3da3 DV |
212 | int rs400_gart_init(struct radeon_device *rdev); |
213 | int rs400_gart_enable(struct radeon_device *rdev); | |
214 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
215 | void rs400_gart_disable(struct radeon_device *rdev); | |
216 | void rs400_gart_fini(struct radeon_device *rdev); | |
89e5181f | 217 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
187f3da3 | 218 | |
771fe6b9 JG |
219 | /* |
220 | * rs600. | |
221 | */ | |
90aca4d2 | 222 | extern int rs600_asic_reset(struct radeon_device *rdev); |
c010f800 JG |
223 | extern int rs600_init(struct radeon_device *rdev); |
224 | extern void rs600_fini(struct radeon_device *rdev); | |
225 | extern int rs600_suspend(struct radeon_device *rdev); | |
226 | extern int rs600_resume(struct radeon_device *rdev); | |
771fe6b9 | 227 | int rs600_irq_set(struct radeon_device *rdev); |
7ed220d7 | 228 | int rs600_irq_process(struct radeon_device *rdev); |
187f3da3 | 229 | void rs600_irq_disable(struct radeon_device *rdev); |
7ed220d7 | 230 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
231 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
232 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
233 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
234 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
c93bb85b | 235 | void rs600_bandwidth_update(struct radeon_device *rdev); |
429770b3 AD |
236 | void rs600_hpd_init(struct radeon_device *rdev); |
237 | void rs600_hpd_fini(struct radeon_device *rdev); | |
238 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
239 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
240 | enum radeon_hpd_id hpd); | |
49e02b73 AD |
241 | extern void rs600_pm_misc(struct radeon_device *rdev); |
242 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
243 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
157fa14d CK |
244 | extern void rs600_page_flip(struct radeon_device *rdev, int crtc, |
245 | u64 crtc_base); | |
246 | extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); | |
187f3da3 | 247 | void rs600_set_safe_registers(struct radeon_device *rdev); |
3ae19b75 | 248 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
89e5181f | 249 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
429770b3 | 250 | |
771fe6b9 JG |
251 | /* |
252 | * rs690,rs740 | |
253 | */ | |
3bc68535 JG |
254 | int rs690_init(struct radeon_device *rdev); |
255 | void rs690_fini(struct radeon_device *rdev); | |
256 | int rs690_resume(struct radeon_device *rdev); | |
257 | int rs690_suspend(struct radeon_device *rdev); | |
771fe6b9 JG |
258 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
259 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
c93bb85b | 260 | void rs690_bandwidth_update(struct radeon_device *rdev); |
187f3da3 DV |
261 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
262 | struct drm_display_mode *mode1, | |
263 | struct drm_display_mode *mode2); | |
89e5181f | 264 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 JG |
265 | |
266 | /* | |
267 | * rv515 | |
268 | */ | |
187f3da3 | 269 | struct rv515_mc_save { |
187f3da3 DV |
270 | u32 vga_render_control; |
271 | u32 vga_hdp_control; | |
6253e4c7 | 272 | bool crtc_enabled[2]; |
187f3da3 | 273 | }; |
81ee8fb6 | 274 | |
068a117c | 275 | int rv515_init(struct radeon_device *rdev); |
d39c3b89 | 276 | void rv515_fini(struct radeon_device *rdev); |
771fe6b9 JG |
277 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
278 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
f712812e | 279 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
c93bb85b | 280 | void rv515_bandwidth_update(struct radeon_device *rdev); |
d39c3b89 JG |
281 | int rv515_resume(struct radeon_device *rdev); |
282 | int rv515_suspend(struct radeon_device *rdev); | |
187f3da3 DV |
283 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
284 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
285 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
286 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
287 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
288 | void rv515_clock_startup(struct radeon_device *rdev); | |
289 | void rv515_debugfs(struct radeon_device *rdev); | |
89e5181f | 290 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 JG |
291 | |
292 | /* | |
293 | * r520,rv530,rv560,rv570,r580 | |
294 | */ | |
d39c3b89 | 295 | int r520_init(struct radeon_device *rdev); |
f0ed1f65 | 296 | int r520_resume(struct radeon_device *rdev); |
89e5181f | 297 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 JG |
298 | |
299 | /* | |
3ce0a23d | 300 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
771fe6b9 | 301 | */ |
3ce0a23d JG |
302 | int r600_init(struct radeon_device *rdev); |
303 | void r600_fini(struct radeon_device *rdev); | |
304 | int r600_suspend(struct radeon_device *rdev); | |
305 | int r600_resume(struct radeon_device *rdev); | |
28d52043 | 306 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
3ce0a23d JG |
307 | int r600_wb_init(struct radeon_device *rdev); |
308 | void r600_wb_fini(struct radeon_device *rdev); | |
3ce0a23d | 309 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
771fe6b9 JG |
310 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
311 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
3ce0a23d | 312 | int r600_cs_parse(struct radeon_cs_parser *p); |
cf4ccd01 | 313 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
3ce0a23d JG |
314 | void r600_fence_ring_emit(struct radeon_device *rdev, |
315 | struct radeon_fence *fence); | |
1654b817 | 316 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 317 | struct radeon_ring *cp, |
15d3332f | 318 | struct radeon_semaphore *semaphore, |
7b1f2485 | 319 | bool emit_wait); |
4d75658b AD |
320 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
321 | struct radeon_fence *fence); | |
1654b817 | 322 | bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
4d75658b AD |
323 | struct radeon_ring *ring, |
324 | struct radeon_semaphore *semaphore, | |
325 | bool emit_wait); | |
326 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
327 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
123bc183 | 328 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
a2d07b74 | 329 | int r600_asic_reset(struct radeon_device *rdev); |
3ce0a23d JG |
330 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
331 | uint32_t tiling_flags, uint32_t pitch, | |
332 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 333 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
f712812e | 334 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
4d75658b | 335 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
3ce0a23d | 336 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
e32eb50d | 337 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
4d75658b | 338 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
072b5acc AD |
339 | int r600_copy_cpdma(struct radeon_device *rdev, |
340 | uint64_t src_offset, uint64_t dst_offset, | |
341 | unsigned num_gpu_pages, struct radeon_fence **fence); | |
4d75658b AD |
342 | int r600_copy_dma(struct radeon_device *rdev, |
343 | uint64_t src_offset, uint64_t dst_offset, | |
344 | unsigned num_gpu_pages, struct radeon_fence **fence); | |
429770b3 AD |
345 | void r600_hpd_init(struct radeon_device *rdev); |
346 | void r600_hpd_fini(struct radeon_device *rdev); | |
347 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
348 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
349 | enum radeon_hpd_id hpd); | |
062b389c | 350 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
def9ba9c | 351 | extern bool r600_gui_idle(struct radeon_device *rdev); |
49e02b73 | 352 | extern void r600_pm_misc(struct radeon_device *rdev); |
ce8f5370 AD |
353 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
354 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
65337e60 SL |
355 | extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
356 | extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
ce8f5370 | 357 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
3313e3d4 AD |
358 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
359 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
3574dda4 DV |
360 | bool r600_card_posted(struct radeon_device *rdev); |
361 | void r600_cp_stop(struct radeon_device *rdev); | |
362 | int r600_cp_start(struct radeon_device *rdev); | |
e32eb50d | 363 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
3574dda4 DV |
364 | int r600_cp_resume(struct radeon_device *rdev); |
365 | void r600_cp_fini(struct radeon_device *rdev); | |
366 | int r600_count_pipe_bits(uint32_t val); | |
367 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
368 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
369 | void r600_scratch_init(struct radeon_device *rdev); | |
3574dda4 | 370 | int r600_init_microcode(struct radeon_device *rdev); |
ea31bf69 AD |
371 | u32 r600_gfx_get_rptr(struct radeon_device *rdev, |
372 | struct radeon_ring *ring); | |
373 | u32 r600_gfx_get_wptr(struct radeon_device *rdev, | |
374 | struct radeon_ring *ring); | |
375 | void r600_gfx_set_wptr(struct radeon_device *rdev, | |
376 | struct radeon_ring *ring); | |
3574dda4 DV |
377 | /* r600 irq */ |
378 | int r600_irq_process(struct radeon_device *rdev); | |
379 | int r600_irq_init(struct radeon_device *rdev); | |
380 | void r600_irq_fini(struct radeon_device *rdev); | |
381 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
382 | int r600_irq_set(struct radeon_device *rdev); | |
383 | void r600_irq_suspend(struct radeon_device *rdev); | |
384 | void r600_disable_interrupts(struct radeon_device *rdev); | |
385 | void r600_rlc_stop(struct radeon_device *rdev); | |
386 | /* r600 audio */ | |
387 | int r600_audio_init(struct radeon_device *rdev); | |
b530602f | 388 | struct r600_audio_pin r600_audio_status(struct radeon_device *rdev); |
3574dda4 | 389 | void r600_audio_fini(struct radeon_device *rdev); |
8f33a156 RM |
390 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); |
391 | void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, | |
392 | size_t size); | |
393 | void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); | |
394 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder); | |
3574dda4 DV |
395 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
396 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
a973bea1 AD |
397 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); |
398 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
89e5181f | 399 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
454d2e2a | 400 | u32 r600_get_xclk(struct radeon_device *rdev); |
d0418894 | 401 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); |
6bd1c385 | 402 | int rv6xx_get_temp(struct radeon_device *rdev); |
1b9ba70a | 403 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
98243917 AD |
404 | int r600_dpm_pre_set_power_state(struct radeon_device *rdev); |
405 | void r600_dpm_post_set_power_state(struct radeon_device *rdev); | |
a4643ba3 | 406 | int r600_dpm_late_enable(struct radeon_device *rdev); |
2e1e6dad CK |
407 | /* r600 dma */ |
408 | uint32_t r600_dma_get_rptr(struct radeon_device *rdev, | |
409 | struct radeon_ring *ring); | |
410 | uint32_t r600_dma_get_wptr(struct radeon_device *rdev, | |
411 | struct radeon_ring *ring); | |
412 | void r600_dma_set_wptr(struct radeon_device *rdev, | |
413 | struct radeon_ring *ring); | |
4a6369e9 AD |
414 | /* rv6xx dpm */ |
415 | int rv6xx_dpm_init(struct radeon_device *rdev); | |
416 | int rv6xx_dpm_enable(struct radeon_device *rdev); | |
417 | void rv6xx_dpm_disable(struct radeon_device *rdev); | |
418 | int rv6xx_dpm_set_power_state(struct radeon_device *rdev); | |
419 | void rv6xx_setup_asic(struct radeon_device *rdev); | |
420 | void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); | |
421 | void rv6xx_dpm_fini(struct radeon_device *rdev); | |
422 | u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
423 | u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
424 | void rv6xx_dpm_print_power_state(struct radeon_device *rdev, | |
425 | struct radeon_ps *ps); | |
242916a5 AD |
426 | void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
427 | struct seq_file *m); | |
f4f85a8c AD |
428 | int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, |
429 | enum radeon_dpm_forced_level level); | |
9d67006e AD |
430 | /* rs780 dpm */ |
431 | int rs780_dpm_init(struct radeon_device *rdev); | |
432 | int rs780_dpm_enable(struct radeon_device *rdev); | |
433 | void rs780_dpm_disable(struct radeon_device *rdev); | |
434 | int rs780_dpm_set_power_state(struct radeon_device *rdev); | |
435 | void rs780_dpm_setup_asic(struct radeon_device *rdev); | |
436 | void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); | |
437 | void rs780_dpm_fini(struct radeon_device *rdev); | |
438 | u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
439 | u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
440 | void rs780_dpm_print_power_state(struct radeon_device *rdev, | |
441 | struct radeon_ps *ps); | |
444bddc4 AD |
442 | void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
443 | struct seq_file *m); | |
63580c3e AB |
444 | int rs780_dpm_force_performance_level(struct radeon_device *rdev, |
445 | enum radeon_dpm_forced_level level); | |
3ce0a23d | 446 | |
3ce0a23d JG |
447 | /* |
448 | * rv770,rv730,rv710,rv740 | |
449 | */ | |
450 | int rv770_init(struct radeon_device *rdev); | |
451 | void rv770_fini(struct radeon_device *rdev); | |
452 | int rv770_suspend(struct radeon_device *rdev); | |
453 | int rv770_resume(struct radeon_device *rdev); | |
3574dda4 | 454 | void rv770_pm_misc(struct radeon_device *rdev); |
157fa14d CK |
455 | void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
456 | bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); | |
3574dda4 DV |
457 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
458 | void r700_cp_stop(struct radeon_device *rdev); | |
459 | void r700_cp_fini(struct radeon_device *rdev); | |
43fb7787 AD |
460 | int rv770_copy_dma(struct radeon_device *rdev, |
461 | uint64_t src_offset, uint64_t dst_offset, | |
462 | unsigned num_gpu_pages, | |
463 | struct radeon_fence **fence); | |
454d2e2a | 464 | u32 rv770_get_xclk(struct radeon_device *rdev); |
ef0e6e65 | 465 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
6bd1c385 | 466 | int rv770_get_temp(struct radeon_device *rdev); |
8f33a156 RM |
467 | /* hdmi */ |
468 | void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
66229b20 AD |
469 | /* rv7xx pm */ |
470 | int rv770_dpm_init(struct radeon_device *rdev); | |
471 | int rv770_dpm_enable(struct radeon_device *rdev); | |
a3f11245 | 472 | int rv770_dpm_late_enable(struct radeon_device *rdev); |
66229b20 AD |
473 | void rv770_dpm_disable(struct radeon_device *rdev); |
474 | int rv770_dpm_set_power_state(struct radeon_device *rdev); | |
475 | void rv770_dpm_setup_asic(struct radeon_device *rdev); | |
476 | void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); | |
477 | void rv770_dpm_fini(struct radeon_device *rdev); | |
478 | u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
479 | u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
480 | void rv770_dpm_print_power_state(struct radeon_device *rdev, | |
481 | struct radeon_ps *ps); | |
bd210d11 AD |
482 | void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
483 | struct seq_file *m); | |
8b5e6b7f AD |
484 | int rv770_dpm_force_performance_level(struct radeon_device *rdev, |
485 | enum radeon_dpm_forced_level level); | |
b06195d9 | 486 | bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); |
3ce0a23d | 487 | |
bcc1c2a1 AD |
488 | /* |
489 | * evergreen | |
490 | */ | |
3574dda4 | 491 | struct evergreen_mc_save { |
3574dda4 DV |
492 | u32 vga_render_control; |
493 | u32 vga_hdp_control; | |
62444b74 | 494 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
3574dda4 | 495 | }; |
81ee8fb6 | 496 | |
0fcdb61e | 497 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
bcc1c2a1 AD |
498 | int evergreen_init(struct radeon_device *rdev); |
499 | void evergreen_fini(struct radeon_device *rdev); | |
500 | int evergreen_suspend(struct radeon_device *rdev); | |
501 | int evergreen_resume(struct radeon_device *rdev); | |
123bc183 AD |
502 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
503 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
a2d07b74 | 504 | int evergreen_asic_reset(struct radeon_device *rdev); |
bcc1c2a1 | 505 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
12920591 | 506 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
bcc1c2a1 AD |
507 | void evergreen_hpd_init(struct radeon_device *rdev); |
508 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
509 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
510 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
511 | enum radeon_hpd_id hpd); | |
45f9a39b AD |
512 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
513 | int evergreen_irq_set(struct radeon_device *rdev); | |
514 | int evergreen_irq_process(struct radeon_device *rdev); | |
cb5fcbd5 | 515 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
d2ead3ea | 516 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
49e02b73 AD |
517 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
518 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
519 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
a4c9e2ee | 520 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
27810fb2 | 521 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
23d33ba3 | 522 | int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
a8b4925c | 523 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
157fa14d CK |
524 | extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, |
525 | u64 crtc_base); | |
526 | extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); | |
3ae19b75 | 527 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
3574dda4 | 528 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
89e5181f | 529 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
233d1ad5 AD |
530 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
531 | struct radeon_fence *fence); | |
532 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, | |
533 | struct radeon_ib *ib); | |
534 | int evergreen_copy_dma(struct radeon_device *rdev, | |
535 | uint64_t src_offset, uint64_t dst_offset, | |
536 | unsigned num_gpu_pages, | |
537 | struct radeon_fence **fence); | |
a973bea1 AD |
538 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); |
539 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
6bd1c385 AD |
540 | int evergreen_get_temp(struct radeon_device *rdev); |
541 | int sumo_get_temp(struct radeon_device *rdev); | |
29a15221 | 542 | int tn_get_temp(struct radeon_device *rdev); |
dc50ba7f AD |
543 | int cypress_dpm_init(struct radeon_device *rdev); |
544 | void cypress_dpm_setup_asic(struct radeon_device *rdev); | |
545 | int cypress_dpm_enable(struct radeon_device *rdev); | |
546 | void cypress_dpm_disable(struct radeon_device *rdev); | |
547 | int cypress_dpm_set_power_state(struct radeon_device *rdev); | |
548 | void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); | |
549 | void cypress_dpm_fini(struct radeon_device *rdev); | |
d0b54bdc | 550 | bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); |
6596afd4 AD |
551 | int btc_dpm_init(struct radeon_device *rdev); |
552 | void btc_dpm_setup_asic(struct radeon_device *rdev); | |
553 | int btc_dpm_enable(struct radeon_device *rdev); | |
554 | void btc_dpm_disable(struct radeon_device *rdev); | |
e8a9539f | 555 | int btc_dpm_pre_set_power_state(struct radeon_device *rdev); |
6596afd4 | 556 | int btc_dpm_set_power_state(struct radeon_device *rdev); |
e8a9539f | 557 | void btc_dpm_post_set_power_state(struct radeon_device *rdev); |
6596afd4 | 558 | void btc_dpm_fini(struct radeon_device *rdev); |
e8a9539f AD |
559 | u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); |
560 | u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
a84301c6 | 561 | bool btc_dpm_vblank_too_short(struct radeon_device *rdev); |
9f3f63f2 AD |
562 | void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
563 | struct seq_file *m); | |
80ea2c12 AD |
564 | int sumo_dpm_init(struct radeon_device *rdev); |
565 | int sumo_dpm_enable(struct radeon_device *rdev); | |
14ec9fab | 566 | int sumo_dpm_late_enable(struct radeon_device *rdev); |
80ea2c12 | 567 | void sumo_dpm_disable(struct radeon_device *rdev); |
422a56bc | 568 | int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); |
80ea2c12 | 569 | int sumo_dpm_set_power_state(struct radeon_device *rdev); |
422a56bc | 570 | void sumo_dpm_post_set_power_state(struct radeon_device *rdev); |
80ea2c12 AD |
571 | void sumo_dpm_setup_asic(struct radeon_device *rdev); |
572 | void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); | |
573 | void sumo_dpm_fini(struct radeon_device *rdev); | |
574 | u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
575 | u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
576 | void sumo_dpm_print_power_state(struct radeon_device *rdev, | |
577 | struct radeon_ps *ps); | |
fb70160c AD |
578 | void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
579 | struct seq_file *m); | |
5d5e5591 AD |
580 | int sumo_dpm_force_performance_level(struct radeon_device *rdev, |
581 | enum radeon_dpm_forced_level level); | |
4546b2c1 | 582 | |
e3487629 AD |
583 | /* |
584 | * cayman | |
585 | */ | |
b40e7e16 AD |
586 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
587 | struct radeon_fence *fence); | |
e3487629 AD |
588 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
589 | int cayman_init(struct radeon_device *rdev); | |
590 | void cayman_fini(struct radeon_device *rdev); | |
591 | int cayman_suspend(struct radeon_device *rdev); | |
592 | int cayman_resume(struct radeon_device *rdev); | |
e3487629 | 593 | int cayman_asic_reset(struct radeon_device *rdev); |
721604a1 JG |
594 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
595 | int cayman_vm_init(struct radeon_device *rdev); | |
596 | void cayman_vm_fini(struct radeon_device *rdev); | |
498522b4 | 597 | void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
089a786e | 598 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
721604a1 | 599 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
cd459e52 | 600 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
f60cbd11 AD |
601 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
602 | struct radeon_ib *ib); | |
123bc183 | 603 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
f60cbd11 | 604 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
24c16439 CK |
605 | void cayman_dma_vm_set_page(struct radeon_device *rdev, |
606 | struct radeon_ib *ib, | |
607 | uint64_t pe, | |
608 | uint64_t addr, unsigned count, | |
609 | uint32_t incr, uint32_t flags); | |
610 | ||
f60cbd11 | 611 | void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
45f9a39b | 612 | |
ea31bf69 AD |
613 | u32 cayman_gfx_get_rptr(struct radeon_device *rdev, |
614 | struct radeon_ring *ring); | |
615 | u32 cayman_gfx_get_wptr(struct radeon_device *rdev, | |
616 | struct radeon_ring *ring); | |
617 | void cayman_gfx_set_wptr(struct radeon_device *rdev, | |
618 | struct radeon_ring *ring); | |
619 | uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, | |
620 | struct radeon_ring *ring); | |
621 | uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, | |
622 | struct radeon_ring *ring); | |
623 | void cayman_dma_set_wptr(struct radeon_device *rdev, | |
624 | struct radeon_ring *ring); | |
625 | ||
69e0b57a AD |
626 | int ni_dpm_init(struct radeon_device *rdev); |
627 | void ni_dpm_setup_asic(struct radeon_device *rdev); | |
628 | int ni_dpm_enable(struct radeon_device *rdev); | |
629 | void ni_dpm_disable(struct radeon_device *rdev); | |
fee3d744 | 630 | int ni_dpm_pre_set_power_state(struct radeon_device *rdev); |
69e0b57a | 631 | int ni_dpm_set_power_state(struct radeon_device *rdev); |
fee3d744 | 632 | void ni_dpm_post_set_power_state(struct radeon_device *rdev); |
69e0b57a AD |
633 | void ni_dpm_fini(struct radeon_device *rdev); |
634 | u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
635 | u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
636 | void ni_dpm_print_power_state(struct radeon_device *rdev, | |
637 | struct radeon_ps *ps); | |
bdf0c4f0 AD |
638 | void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
639 | struct seq_file *m); | |
170a47f0 AD |
640 | int ni_dpm_force_performance_level(struct radeon_device *rdev, |
641 | enum radeon_dpm_forced_level level); | |
76ad73e5 | 642 | bool ni_dpm_vblank_too_short(struct radeon_device *rdev); |
d70229f7 AD |
643 | int trinity_dpm_init(struct radeon_device *rdev); |
644 | int trinity_dpm_enable(struct radeon_device *rdev); | |
bda44c1a | 645 | int trinity_dpm_late_enable(struct radeon_device *rdev); |
d70229f7 | 646 | void trinity_dpm_disable(struct radeon_device *rdev); |
a284c48a | 647 | int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); |
d70229f7 | 648 | int trinity_dpm_set_power_state(struct radeon_device *rdev); |
a284c48a | 649 | void trinity_dpm_post_set_power_state(struct radeon_device *rdev); |
d70229f7 AD |
650 | void trinity_dpm_setup_asic(struct radeon_device *rdev); |
651 | void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); | |
652 | void trinity_dpm_fini(struct radeon_device *rdev); | |
653 | u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
654 | u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
655 | void trinity_dpm_print_power_state(struct radeon_device *rdev, | |
656 | struct radeon_ps *ps); | |
490ab931 AD |
657 | void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
658 | struct seq_file *m); | |
9b5de596 AD |
659 | int trinity_dpm_force_performance_level(struct radeon_device *rdev, |
660 | enum radeon_dpm_forced_level level); | |
11877060 | 661 | void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
d70229f7 | 662 | |
43b3cd99 AD |
663 | /* DCE6 - SI */ |
664 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
b530602f AD |
665 | int dce6_audio_init(struct radeon_device *rdev); |
666 | void dce6_audio_fini(struct radeon_device *rdev); | |
43b3cd99 | 667 | |
02779c08 AD |
668 | /* |
669 | * si | |
670 | */ | |
671 | void si_fence_ring_emit(struct radeon_device *rdev, | |
672 | struct radeon_fence *fence); | |
673 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
674 | int si_init(struct radeon_device *rdev); | |
675 | void si_fini(struct radeon_device *rdev); | |
676 | int si_suspend(struct radeon_device *rdev); | |
677 | int si_resume(struct radeon_device *rdev); | |
123bc183 AD |
678 | bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
679 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
02779c08 AD |
680 | int si_asic_reset(struct radeon_device *rdev); |
681 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
682 | int si_irq_set(struct radeon_device *rdev); | |
683 | int si_irq_process(struct radeon_device *rdev); | |
684 | int si_vm_init(struct radeon_device *rdev); | |
685 | void si_vm_fini(struct radeon_device *rdev); | |
498522b4 | 686 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
02779c08 | 687 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
8c5fd7ef AD |
688 | int si_copy_dma(struct radeon_device *rdev, |
689 | uint64_t src_offset, uint64_t dst_offset, | |
690 | unsigned num_gpu_pages, | |
691 | struct radeon_fence **fence); | |
24c16439 CK |
692 | void si_dma_vm_set_page(struct radeon_device *rdev, |
693 | struct radeon_ib *ib, | |
694 | uint64_t pe, | |
695 | uint64_t addr, unsigned count, | |
696 | uint32_t incr, uint32_t flags); | |
8c5fd7ef | 697 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
454d2e2a | 698 | u32 si_get_xclk(struct radeon_device *rdev); |
d0418894 | 699 | uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); |
2539eb02 | 700 | int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
6bd1c385 | 701 | int si_get_temp(struct radeon_device *rdev); |
a9e61410 AD |
702 | int si_dpm_init(struct radeon_device *rdev); |
703 | void si_dpm_setup_asic(struct radeon_device *rdev); | |
704 | int si_dpm_enable(struct radeon_device *rdev); | |
963c115d | 705 | int si_dpm_late_enable(struct radeon_device *rdev); |
a9e61410 AD |
706 | void si_dpm_disable(struct radeon_device *rdev); |
707 | int si_dpm_pre_set_power_state(struct radeon_device *rdev); | |
708 | int si_dpm_set_power_state(struct radeon_device *rdev); | |
709 | void si_dpm_post_set_power_state(struct radeon_device *rdev); | |
710 | void si_dpm_fini(struct radeon_device *rdev); | |
711 | void si_dpm_display_configuration_changed(struct radeon_device *rdev); | |
7982128c AD |
712 | void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
713 | struct seq_file *m); | |
a160a6a3 AD |
714 | int si_dpm_force_performance_level(struct radeon_device *rdev, |
715 | enum radeon_dpm_forced_level level); | |
02779c08 | 716 | |
0672e27b AD |
717 | /* DCE8 - CIK */ |
718 | void dce8_bandwidth_update(struct radeon_device *rdev); | |
719 | ||
44fa346f AD |
720 | /* |
721 | * cik | |
722 | */ | |
723 | uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); | |
2c67912c | 724 | u32 cik_get_xclk(struct radeon_device *rdev); |
6e2c3c0a AD |
725 | uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
726 | void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
87167bb1 | 727 | int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
5ad6bf91 | 728 | int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
0672e27b AD |
729 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
730 | struct radeon_fence *fence); | |
1654b817 | 731 | bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, |
0672e27b AD |
732 | struct radeon_ring *ring, |
733 | struct radeon_semaphore *semaphore, | |
734 | bool emit_wait); | |
735 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
736 | int cik_copy_dma(struct radeon_device *rdev, | |
737 | uint64_t src_offset, uint64_t dst_offset, | |
738 | unsigned num_gpu_pages, | |
739 | struct radeon_fence **fence); | |
c9dbd705 AD |
740 | int cik_copy_cpdma(struct radeon_device *rdev, |
741 | uint64_t src_offset, uint64_t dst_offset, | |
742 | unsigned num_gpu_pages, | |
743 | struct radeon_fence **fence); | |
0672e27b AD |
744 | int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
745 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
746 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
747 | void cik_fence_gfx_ring_emit(struct radeon_device *rdev, | |
748 | struct radeon_fence *fence); | |
749 | void cik_fence_compute_ring_emit(struct radeon_device *rdev, | |
750 | struct radeon_fence *fence); | |
1654b817 | 751 | bool cik_semaphore_ring_emit(struct radeon_device *rdev, |
0672e27b AD |
752 | struct radeon_ring *cp, |
753 | struct radeon_semaphore *semaphore, | |
754 | bool emit_wait); | |
755 | void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
756 | int cik_init(struct radeon_device *rdev); | |
757 | void cik_fini(struct radeon_device *rdev); | |
758 | int cik_suspend(struct radeon_device *rdev); | |
759 | int cik_resume(struct radeon_device *rdev); | |
760 | bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
761 | int cik_asic_reset(struct radeon_device *rdev); | |
762 | void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
763 | int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
764 | int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
765 | int cik_irq_set(struct radeon_device *rdev); | |
766 | int cik_irq_process(struct radeon_device *rdev); | |
767 | int cik_vm_init(struct radeon_device *rdev); | |
768 | void cik_vm_fini(struct radeon_device *rdev); | |
769 | void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
24c16439 CK |
770 | void cik_sdma_vm_set_page(struct radeon_device *rdev, |
771 | struct radeon_ib *ib, | |
772 | uint64_t pe, | |
773 | uint64_t addr, unsigned count, | |
774 | uint32_t incr, uint32_t flags); | |
0672e27b AD |
775 | void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
776 | int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); | |
ea31bf69 AD |
777 | u32 cik_gfx_get_rptr(struct radeon_device *rdev, |
778 | struct radeon_ring *ring); | |
779 | u32 cik_gfx_get_wptr(struct radeon_device *rdev, | |
780 | struct radeon_ring *ring); | |
781 | void cik_gfx_set_wptr(struct radeon_device *rdev, | |
782 | struct radeon_ring *ring); | |
783 | u32 cik_compute_get_rptr(struct radeon_device *rdev, | |
784 | struct radeon_ring *ring); | |
785 | u32 cik_compute_get_wptr(struct radeon_device *rdev, | |
786 | struct radeon_ring *ring); | |
787 | void cik_compute_set_wptr(struct radeon_device *rdev, | |
788 | struct radeon_ring *ring); | |
789 | u32 cik_sdma_get_rptr(struct radeon_device *rdev, | |
790 | struct radeon_ring *ring); | |
791 | u32 cik_sdma_get_wptr(struct radeon_device *rdev, | |
792 | struct radeon_ring *ring); | |
793 | void cik_sdma_set_wptr(struct radeon_device *rdev, | |
794 | struct radeon_ring *ring); | |
286d9cc6 AD |
795 | int ci_get_temp(struct radeon_device *rdev); |
796 | int kv_get_temp(struct radeon_device *rdev); | |
44fa346f | 797 | |
cc8dbbb4 AD |
798 | int ci_dpm_init(struct radeon_device *rdev); |
799 | int ci_dpm_enable(struct radeon_device *rdev); | |
90208427 | 800 | int ci_dpm_late_enable(struct radeon_device *rdev); |
cc8dbbb4 AD |
801 | void ci_dpm_disable(struct radeon_device *rdev); |
802 | int ci_dpm_pre_set_power_state(struct radeon_device *rdev); | |
803 | int ci_dpm_set_power_state(struct radeon_device *rdev); | |
804 | void ci_dpm_post_set_power_state(struct radeon_device *rdev); | |
805 | void ci_dpm_setup_asic(struct radeon_device *rdev); | |
806 | void ci_dpm_display_configuration_changed(struct radeon_device *rdev); | |
807 | void ci_dpm_fini(struct radeon_device *rdev); | |
808 | u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
809 | u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
810 | void ci_dpm_print_power_state(struct radeon_device *rdev, | |
811 | struct radeon_ps *ps); | |
94b4adc5 AD |
812 | void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
813 | struct seq_file *m); | |
89536fd6 AD |
814 | int ci_dpm_force_performance_level(struct radeon_device *rdev, |
815 | enum radeon_dpm_forced_level level); | |
5496131e | 816 | bool ci_dpm_vblank_too_short(struct radeon_device *rdev); |
942bdf7f | 817 | void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
cc8dbbb4 | 818 | |
41a524ab AD |
819 | int kv_dpm_init(struct radeon_device *rdev); |
820 | int kv_dpm_enable(struct radeon_device *rdev); | |
d8852c34 | 821 | int kv_dpm_late_enable(struct radeon_device *rdev); |
41a524ab AD |
822 | void kv_dpm_disable(struct radeon_device *rdev); |
823 | int kv_dpm_pre_set_power_state(struct radeon_device *rdev); | |
824 | int kv_dpm_set_power_state(struct radeon_device *rdev); | |
825 | void kv_dpm_post_set_power_state(struct radeon_device *rdev); | |
826 | void kv_dpm_setup_asic(struct radeon_device *rdev); | |
827 | void kv_dpm_display_configuration_changed(struct radeon_device *rdev); | |
828 | void kv_dpm_fini(struct radeon_device *rdev); | |
829 | u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); | |
830 | u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); | |
831 | void kv_dpm_print_power_state(struct radeon_device *rdev, | |
832 | struct radeon_ps *ps); | |
ae3e40e8 AD |
833 | void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
834 | struct seq_file *m); | |
2b4c8022 AD |
835 | int kv_dpm_force_performance_level(struct radeon_device *rdev, |
836 | enum radeon_dpm_forced_level level); | |
77df508a | 837 | void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
b7a5ae97 | 838 | void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); |
41a524ab | 839 | |
e409b128 CK |
840 | /* uvd v1.0 */ |
841 | uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, | |
842 | struct radeon_ring *ring); | |
843 | uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, | |
844 | struct radeon_ring *ring); | |
845 | void uvd_v1_0_set_wptr(struct radeon_device *rdev, | |
846 | struct radeon_ring *ring); | |
847 | ||
848 | int uvd_v1_0_init(struct radeon_device *rdev); | |
849 | void uvd_v1_0_fini(struct radeon_device *rdev); | |
850 | int uvd_v1_0_start(struct radeon_device *rdev); | |
851 | void uvd_v1_0_stop(struct radeon_device *rdev); | |
852 | ||
853 | int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
854 | int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
1654b817 | 855 | bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, |
e409b128 CK |
856 | struct radeon_ring *ring, |
857 | struct radeon_semaphore *semaphore, | |
858 | bool emit_wait); | |
859 | void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
860 | ||
861 | /* uvd v2.2 */ | |
862 | int uvd_v2_2_resume(struct radeon_device *rdev); | |
863 | void uvd_v2_2_fence_emit(struct radeon_device *rdev, | |
864 | struct radeon_fence *fence); | |
865 | ||
866 | /* uvd v3.1 */ | |
1654b817 | 867 | bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, |
e409b128 CK |
868 | struct radeon_ring *ring, |
869 | struct radeon_semaphore *semaphore, | |
870 | bool emit_wait); | |
871 | ||
872 | /* uvd v4.2 */ | |
873 | int uvd_v4_2_resume(struct radeon_device *rdev); | |
874 | ||
d93f7937 CK |
875 | /* vce v1.0 */ |
876 | uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, | |
877 | struct radeon_ring *ring); | |
878 | uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, | |
879 | struct radeon_ring *ring); | |
880 | void vce_v1_0_set_wptr(struct radeon_device *rdev, | |
881 | struct radeon_ring *ring); | |
882 | int vce_v1_0_init(struct radeon_device *rdev); | |
883 | int vce_v1_0_start(struct radeon_device *rdev); | |
884 | ||
885 | /* vce v2.0 */ | |
886 | int vce_v2_0_resume(struct radeon_device *rdev); | |
887 | ||
771fe6b9 | 888 | #endif |