projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 771fe6b9 JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __RADEON_ASIC_H__ | |
| 29 | #define __RADEON_ASIC_H__ | |
| 30 | ||
| 31 | /* | |
| 32 | * common functions | |
| 33 | */ | |
| 7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | ||
| 7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
| 44 | ||
| 37e9b6a6 | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 6d92f81d | 48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
| 37e9b6a6 | 49 | |
| f93bdefe AD |
50 | u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, |
| 51 | struct radeon_ring *ring); | |
| 52 | u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, | |
| 53 | struct radeon_ring *ring); | |
| 54 | void radeon_ring_generic_set_wptr(struct radeon_device *rdev, | |
| 55 | struct radeon_ring *ring); | |
| 37e9b6a6 | 56 | |
| 771fe6b9 | 57 | /* |
| 44ca7478 | 58 | * r100,rv100,rs100,rv200,rs200 |
| 771fe6b9 | 59 | */ |
| 2b497502 DV |
60 | struct r100_mc_save { |
| 61 | u32 GENMO_WT; | |
| 62 | u32 CRTC_EXT_CNTL; | |
| 63 | u32 CRTC_GEN_CNTL; | |
| 64 | u32 CRTC2_GEN_CNTL; | |
| 65 | u32 CUR_OFFSET; | |
| 66 | u32 CUR2_OFFSET; | |
| 67 | }; | |
| 68 | int r100_init(struct radeon_device *rdev); | |
| 69 | void r100_fini(struct radeon_device *rdev); | |
| 70 | int r100_suspend(struct radeon_device *rdev); | |
| 71 | int r100_resume(struct radeon_device *rdev); | |
| 28d52043 | 72 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| e32eb50d | 73 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 74 | int r100_asic_reset(struct radeon_device *rdev); |
| 7ed220d7 | 75 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
76 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 77 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| f712812e | 78 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 771fe6b9 JG |
79 | int r100_irq_set(struct radeon_device *rdev); |
| 80 | int r100_irq_process(struct radeon_device *rdev); | |
| 81 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
| 82 | struct radeon_fence *fence); | |
| 15d3332f | 83 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 84 | struct radeon_ring *cp, |
| 15d3332f | 85 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 86 | bool emit_wait); |
| 771fe6b9 JG |
87 | int r100_cs_parse(struct radeon_cs_parser *p); |
| 88 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 89 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 90 | int r100_copy_blit(struct radeon_device *rdev, | |
| 91 | uint64_t src_offset, | |
| 92 | uint64_t dst_offset, | |
| 003cefe0 | 93 | unsigned num_gpu_pages, |
| 876dc9f3 | 94 | struct radeon_fence **fence); |
| e024e110 DA |
95 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 96 | uint32_t tiling_flags, uint32_t pitch, | |
| 97 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 98 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| c93bb85b | 99 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 3ce0a23d | 100 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 101 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 429770b3 AD |
102 | void r100_hpd_init(struct radeon_device *rdev); |
| 103 | void r100_hpd_fini(struct radeon_device *rdev); | |
| 104 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 105 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
| 106 | enum radeon_hpd_id hpd); | |
| 2b497502 DV |
107 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 108 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
| 109 | void r100_cp_disable(struct radeon_device *rdev); | |
| 110 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
| 111 | void r100_cp_fini(struct radeon_device *rdev); | |
| 112 | int r100_pci_gart_init(struct radeon_device *rdev); | |
| 113 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
| 114 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
| 115 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
| 116 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
| 117 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
| f712812e | 118 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 2b497502 DV |
119 | void r100_irq_disable(struct radeon_device *rdev); |
| 120 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 121 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 122 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
| 2b497502 DV |
123 | int r100_cp_reset(struct radeon_device *rdev); |
| 124 | void r100_vga_render_disable(struct radeon_device *rdev); | |
| 4c712e6c | 125 | void r100_restore_sanity(struct radeon_device *rdev); |
| 2b497502 DV |
126 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 127 | struct radeon_cs_packet *pkt, | |
| 128 | struct radeon_bo *robj); | |
| 129 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
| 130 | struct radeon_cs_packet *pkt, | |
| 131 | const unsigned *auth, unsigned n, | |
| 132 | radeon_packet0_check_t check); | |
| 133 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
| 134 | struct radeon_cs_packet *pkt, | |
| 135 | unsigned idx); | |
| 136 | void r100_enable_bm(struct radeon_device *rdev); | |
| 137 | void r100_set_common_regs(struct radeon_device *rdev); | |
| 90aca4d2 | 138 | void r100_bm_disable(struct radeon_device *rdev); |
| def9ba9c | 139 | extern bool r100_gui_idle(struct radeon_device *rdev); |
| 49e02b73 AD |
140 | extern void r100_pm_misc(struct radeon_device *rdev); |
| 141 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
| 142 | extern void r100_pm_finish(struct radeon_device *rdev); | |
| ce8f5370 AD |
143 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
| 144 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 6f34be50 AD |
145 | extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 146 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 147 | extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3ae19b75 | 148 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 149 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| bae6b562 | 150 | |
| 44ca7478 PN |
151 | /* |
| 152 | * r200,rv250,rs300,rv280 | |
| 153 | */ | |
| 154 | extern int r200_copy_dma(struct radeon_device *rdev, | |
| 187f3da3 DV |
155 | uint64_t src_offset, |
| 156 | uint64_t dst_offset, | |
| 003cefe0 | 157 | unsigned num_gpu_pages, |
| 876dc9f3 | 158 | struct radeon_fence **fence); |
| 187f3da3 | 159 | void r200_set_safe_registers(struct radeon_device *rdev); |
| 771fe6b9 JG |
160 | |
| 161 | /* | |
| 162 | * r300,r350,rv350,rv380 | |
| 163 | */ | |
| 207bf9e9 JG |
164 | extern int r300_init(struct radeon_device *rdev); |
| 165 | extern void r300_fini(struct radeon_device *rdev); | |
| 166 | extern int r300_suspend(struct radeon_device *rdev); | |
| 167 | extern int r300_resume(struct radeon_device *rdev); | |
| a2d07b74 | 168 | extern int r300_asic_reset(struct radeon_device *rdev); |
| f712812e | 169 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 207bf9e9 JG |
170 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 171 | struct radeon_fence *fence); | |
| 172 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
| 173 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 174 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 207bf9e9 | 175 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| c836a412 | 176 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 187f3da3 DV |
177 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 178 | extern void r300_mc_program(struct radeon_device *rdev); | |
| 179 | extern void r300_mc_init(struct radeon_device *rdev); | |
| 180 | extern void r300_clock_startup(struct radeon_device *rdev); | |
| 181 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
| 182 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
| 183 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
| 184 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
| 185 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
| 89e5181f | 186 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| 44ca7478 | 187 | |
| 771fe6b9 JG |
188 | /* |
| 189 | * r420,r423,rv410 | |
| 190 | */ | |
| 9f022ddf JG |
191 | extern int r420_init(struct radeon_device *rdev); |
| 192 | extern void r420_fini(struct radeon_device *rdev); | |
| 193 | extern int r420_suspend(struct radeon_device *rdev); | |
| 194 | extern int r420_resume(struct radeon_device *rdev); | |
| ce8f5370 | 195 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
| 187f3da3 DV |
196 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 197 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
| 198 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
| 199 | extern void r420_pipes_init(struct radeon_device *rdev); | |
| 771fe6b9 JG |
200 | |
| 201 | /* | |
| 202 | * rs400,rs480 | |
| 203 | */ | |
| ca6ffc64 JG |
204 | extern int rs400_init(struct radeon_device *rdev); |
| 205 | extern void rs400_fini(struct radeon_device *rdev); | |
| 206 | extern int rs400_suspend(struct radeon_device *rdev); | |
| 207 | extern int rs400_resume(struct radeon_device *rdev); | |
| 771fe6b9 JG |
208 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 209 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 210 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 211 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 187f3da3 DV |
212 | int rs400_gart_init(struct radeon_device *rdev); |
| 213 | int rs400_gart_enable(struct radeon_device *rdev); | |
| 214 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
| 215 | void rs400_gart_disable(struct radeon_device *rdev); | |
| 216 | void rs400_gart_fini(struct radeon_device *rdev); | |
| 89e5181f | 217 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
| 187f3da3 | 218 | |
| 771fe6b9 JG |
219 | /* |
| 220 | * rs600. | |
| 221 | */ | |
| 90aca4d2 | 222 | extern int rs600_asic_reset(struct radeon_device *rdev); |
| c010f800 JG |
223 | extern int rs600_init(struct radeon_device *rdev); |
| 224 | extern void rs600_fini(struct radeon_device *rdev); | |
| 225 | extern int rs600_suspend(struct radeon_device *rdev); | |
| 226 | extern int rs600_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 227 | int rs600_irq_set(struct radeon_device *rdev); |
| 7ed220d7 | 228 | int rs600_irq_process(struct radeon_device *rdev); |
| 187f3da3 | 229 | void rs600_irq_disable(struct radeon_device *rdev); |
| 7ed220d7 | 230 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
231 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 232 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 233 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 234 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 235 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| 429770b3 AD |
236 | void rs600_hpd_init(struct radeon_device *rdev); |
| 237 | void rs600_hpd_fini(struct radeon_device *rdev); | |
| 238 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 239 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
| 240 | enum radeon_hpd_id hpd); | |
| 49e02b73 AD |
241 | extern void rs600_pm_misc(struct radeon_device *rdev); |
| 242 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
| 243 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
| 6f34be50 AD |
244 | extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 245 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 246 | extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 187f3da3 | 247 | void rs600_set_safe_registers(struct radeon_device *rdev); |
| 3ae19b75 | 248 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 249 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
| 429770b3 | 250 | |
| 771fe6b9 JG |
251 | /* |
| 252 | * rs690,rs740 | |
| 253 | */ | |
| 3bc68535 JG |
254 | int rs690_init(struct radeon_device *rdev); |
| 255 | void rs690_fini(struct radeon_device *rdev); | |
| 256 | int rs690_resume(struct radeon_device *rdev); | |
| 257 | int rs690_suspend(struct radeon_device *rdev); | |
| 771fe6b9 JG |
258 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 259 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 260 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 187f3da3 DV |
261 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 262 | struct drm_display_mode *mode1, | |
| 263 | struct drm_display_mode *mode2); | |
| 89e5181f | 264 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
265 | |
| 266 | /* | |
| 267 | * rv515 | |
| 268 | */ | |
| 187f3da3 | 269 | struct rv515_mc_save { |
| 187f3da3 DV |
270 | u32 vga_render_control; |
| 271 | u32 vga_hdp_control; | |
| 6253e4c7 | 272 | bool crtc_enabled[2]; |
| 187f3da3 | 273 | }; |
| 81ee8fb6 | 274 | |
| 068a117c | 275 | int rv515_init(struct radeon_device *rdev); |
| d39c3b89 | 276 | void rv515_fini(struct radeon_device *rdev); |
| 771fe6b9 JG |
277 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 278 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| f712812e | 279 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| c93bb85b | 280 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| d39c3b89 JG |
281 | int rv515_resume(struct radeon_device *rdev); |
| 282 | int rv515_suspend(struct radeon_device *rdev); | |
| 187f3da3 DV |
283 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| 284 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
| 285 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
| 286 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 287 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 288 | void rv515_clock_startup(struct radeon_device *rdev); | |
| 289 | void rv515_debugfs(struct radeon_device *rdev); | |
| 89e5181f | 290 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
291 | |
| 292 | /* | |
| 293 | * r520,rv530,rv560,rv570,r580 | |
| 294 | */ | |
| d39c3b89 | 295 | int r520_init(struct radeon_device *rdev); |
| f0ed1f65 | 296 | int r520_resume(struct radeon_device *rdev); |
| 89e5181f | 297 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
298 | |
| 299 | /* | |
| 3ce0a23d | 300 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 771fe6b9 | 301 | */ |
| 3ce0a23d JG |
302 | int r600_init(struct radeon_device *rdev); |
| 303 | void r600_fini(struct radeon_device *rdev); | |
| 304 | int r600_suspend(struct radeon_device *rdev); | |
| 305 | int r600_resume(struct radeon_device *rdev); | |
| 28d52043 | 306 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
| 3ce0a23d JG |
307 | int r600_wb_init(struct radeon_device *rdev); |
| 308 | void r600_wb_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 309 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 771fe6b9 JG |
310 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 311 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 3ce0a23d | 312 | int r600_cs_parse(struct radeon_cs_parser *p); |
| cf4ccd01 | 313 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
| 3ce0a23d JG |
314 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 315 | struct radeon_fence *fence); | |
| 15d3332f | 316 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 317 | struct radeon_ring *cp, |
| 15d3332f | 318 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 319 | bool emit_wait); |
| 4d75658b AD |
320 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
| 321 | struct radeon_fence *fence); | |
| 322 | void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, | |
| 323 | struct radeon_ring *ring, | |
| 324 | struct radeon_semaphore *semaphore, | |
| 325 | bool emit_wait); | |
| 326 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 327 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 123bc183 | 328 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 329 | int r600_asic_reset(struct radeon_device *rdev); |
| 3ce0a23d JG |
330 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 331 | uint32_t tiling_flags, uint32_t pitch, | |
| 332 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 333 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| f712812e | 334 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 4d75658b | 335 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 3ce0a23d | 336 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 337 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 4d75658b | 338 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| f2ba57b5 | 339 | int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 3ce0a23d JG |
340 | int r600_copy_blit(struct radeon_device *rdev, |
| 341 | uint64_t src_offset, uint64_t dst_offset, | |
| 876dc9f3 | 342 | unsigned num_gpu_pages, struct radeon_fence **fence); |
| 4d75658b AD |
343 | int r600_copy_dma(struct radeon_device *rdev, |
| 344 | uint64_t src_offset, uint64_t dst_offset, | |
| 345 | unsigned num_gpu_pages, struct radeon_fence **fence); | |
| 429770b3 AD |
346 | void r600_hpd_init(struct radeon_device *rdev); |
| 347 | void r600_hpd_fini(struct radeon_device *rdev); | |
| 348 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 349 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
| 350 | enum radeon_hpd_id hpd); | |
| 062b389c | 351 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
| def9ba9c | 352 | extern bool r600_gui_idle(struct radeon_device *rdev); |
| 49e02b73 | 353 | extern void r600_pm_misc(struct radeon_device *rdev); |
| ce8f5370 AD |
354 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
| 355 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
| 65337e60 SL |
356 | extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 357 | extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| ce8f5370 | 358 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
| 3313e3d4 AD |
359 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 360 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
| 3574dda4 DV |
361 | bool r600_card_posted(struct radeon_device *rdev); |
| 362 | void r600_cp_stop(struct radeon_device *rdev); | |
| 363 | int r600_cp_start(struct radeon_device *rdev); | |
| e32eb50d | 364 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
| 3574dda4 DV |
365 | int r600_cp_resume(struct radeon_device *rdev); |
| 366 | void r600_cp_fini(struct radeon_device *rdev); | |
| 367 | int r600_count_pipe_bits(uint32_t val); | |
| 368 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
| 369 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
| 370 | void r600_scratch_init(struct radeon_device *rdev); | |
| 371 | int r600_blit_init(struct radeon_device *rdev); | |
| 372 | void r600_blit_fini(struct radeon_device *rdev); | |
| 373 | int r600_init_microcode(struct radeon_device *rdev); | |
| 374 | /* r600 irq */ | |
| 375 | int r600_irq_process(struct radeon_device *rdev); | |
| 376 | int r600_irq_init(struct radeon_device *rdev); | |
| 377 | void r600_irq_fini(struct radeon_device *rdev); | |
| 378 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 379 | int r600_irq_set(struct radeon_device *rdev); | |
| 380 | void r600_irq_suspend(struct radeon_device *rdev); | |
| 381 | void r600_disable_interrupts(struct radeon_device *rdev); | |
| 382 | void r600_rlc_stop(struct radeon_device *rdev); | |
| 383 | /* r600 audio */ | |
| 384 | int r600_audio_init(struct radeon_device *rdev); | |
| 3299de95 | 385 | struct r600_audio r600_audio_status(struct radeon_device *rdev); |
| 3574dda4 | 386 | void r600_audio_fini(struct radeon_device *rdev); |
| 3574dda4 DV |
387 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
| 388 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
| a973bea1 AD |
389 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); |
| 390 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
| 4546b2c1 | 391 | /* r600 blit */ |
| f237750f | 392 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
| 220907d9 CK |
393 | struct radeon_fence **fence, struct radeon_sa_bo **vb, |
| 394 | struct radeon_semaphore **sem); | |
| 876dc9f3 | 395 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
| 220907d9 | 396 | struct radeon_sa_bo *vb, struct radeon_semaphore *sem); |
| 4546b2c1 DV |
397 | void r600_kms_blit_copy(struct radeon_device *rdev, |
| 398 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
| f237750f CK |
399 | unsigned num_gpu_pages, |
| 400 | struct radeon_sa_bo *vb); | |
| 89e5181f | 401 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 454d2e2a | 402 | u32 r600_get_xclk(struct radeon_device *rdev); |
| d0418894 | 403 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); |
| 6bd1c385 | 404 | int rv6xx_get_temp(struct radeon_device *rdev); |
| 3ce0a23d | 405 | |
| f2ba57b5 CK |
406 | /* uvd */ |
| 407 | int r600_uvd_init(struct radeon_device *rdev); | |
| 408 | int r600_uvd_rbc_start(struct radeon_device *rdev); | |
| 409 | void r600_uvd_rbc_stop(struct radeon_device *rdev); | |
| 410 | int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 411 | void r600_uvd_fence_emit(struct radeon_device *rdev, | |
| 412 | struct radeon_fence *fence); | |
| 413 | void r600_uvd_semaphore_emit(struct radeon_device *rdev, | |
| 414 | struct radeon_ring *ring, | |
| 415 | struct radeon_semaphore *semaphore, | |
| 416 | bool emit_wait); | |
| 417 | void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 418 | ||
| 3ce0a23d JG |
419 | /* |
| 420 | * rv770,rv730,rv710,rv740 | |
| 421 | */ | |
| 422 | int rv770_init(struct radeon_device *rdev); | |
| 423 | void rv770_fini(struct radeon_device *rdev); | |
| 424 | int rv770_suspend(struct radeon_device *rdev); | |
| 425 | int rv770_resume(struct radeon_device *rdev); | |
| 3574dda4 DV |
426 | void rv770_pm_misc(struct radeon_device *rdev); |
| 427 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 428 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
| 429 | void r700_cp_stop(struct radeon_device *rdev); | |
| 430 | void r700_cp_fini(struct radeon_device *rdev); | |
| 43fb7787 AD |
431 | int rv770_copy_dma(struct radeon_device *rdev, |
| 432 | uint64_t src_offset, uint64_t dst_offset, | |
| 433 | unsigned num_gpu_pages, | |
| 434 | struct radeon_fence **fence); | |
| 454d2e2a | 435 | u32 rv770_get_xclk(struct radeon_device *rdev); |
| f2ba57b5 | 436 | int rv770_uvd_resume(struct radeon_device *rdev); |
| ef0e6e65 | 437 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6bd1c385 | 438 | int rv770_get_temp(struct radeon_device *rdev); |
| 3ce0a23d | 439 | |
| bcc1c2a1 AD |
440 | /* |
| 441 | * evergreen | |
| 442 | */ | |
| 3574dda4 | 443 | struct evergreen_mc_save { |
| 3574dda4 DV |
444 | u32 vga_render_control; |
| 445 | u32 vga_hdp_control; | |
| 62444b74 | 446 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
| 3574dda4 | 447 | }; |
| 81ee8fb6 | 448 | |
| 0fcdb61e | 449 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| bcc1c2a1 AD |
450 | int evergreen_init(struct radeon_device *rdev); |
| 451 | void evergreen_fini(struct radeon_device *rdev); | |
| 452 | int evergreen_suspend(struct radeon_device *rdev); | |
| 453 | int evergreen_resume(struct radeon_device *rdev); | |
| 123bc183 AD |
454 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 455 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| a2d07b74 | 456 | int evergreen_asic_reset(struct radeon_device *rdev); |
| bcc1c2a1 | 457 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
| 12920591 | 458 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| bcc1c2a1 AD |
459 | void evergreen_hpd_init(struct radeon_device *rdev); |
| 460 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
| 461 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 462 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
| 463 | enum radeon_hpd_id hpd); | |
| 45f9a39b AD |
464 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 465 | int evergreen_irq_set(struct radeon_device *rdev); | |
| 466 | int evergreen_irq_process(struct radeon_device *rdev); | |
| cb5fcbd5 | 467 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| d2ead3ea | 468 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
| 49e02b73 AD |
469 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 470 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
| 471 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
| a4c9e2ee | 472 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 27810fb2 | 473 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
| 23d33ba3 | 474 | int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| a8b4925c | 475 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6f34be50 AD |
476 | extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 477 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 478 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3ae19b75 | 479 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 3574dda4 DV |
480 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 481 | int evergreen_blit_init(struct radeon_device *rdev); | |
| 89e5181f | 482 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| 233d1ad5 AD |
483 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
| 484 | struct radeon_fence *fence); | |
| 485 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, | |
| 486 | struct radeon_ib *ib); | |
| 487 | int evergreen_copy_dma(struct radeon_device *rdev, | |
| 488 | uint64_t src_offset, uint64_t dst_offset, | |
| 489 | unsigned num_gpu_pages, | |
| 490 | struct radeon_fence **fence); | |
| a973bea1 AD |
491 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); |
| 492 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
| 6bd1c385 AD |
493 | int evergreen_get_temp(struct radeon_device *rdev); |
| 494 | int sumo_get_temp(struct radeon_device *rdev); | |
| 4546b2c1 | 495 | |
| e3487629 AD |
496 | /* |
| 497 | * cayman | |
| 498 | */ | |
| b40e7e16 AD |
499 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
| 500 | struct radeon_fence *fence); | |
| f2ba57b5 CK |
501 | void cayman_uvd_semaphore_emit(struct radeon_device *rdev, |
| 502 | struct radeon_ring *ring, | |
| 503 | struct radeon_semaphore *semaphore, | |
| 504 | bool emit_wait); | |
| e3487629 AD |
505 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 506 | int cayman_init(struct radeon_device *rdev); | |
| 507 | void cayman_fini(struct radeon_device *rdev); | |
| 508 | int cayman_suspend(struct radeon_device *rdev); | |
| 509 | int cayman_resume(struct radeon_device *rdev); | |
| e3487629 | 510 | int cayman_asic_reset(struct radeon_device *rdev); |
| 721604a1 JG |
511 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 512 | int cayman_vm_init(struct radeon_device *rdev); | |
| 513 | void cayman_vm_fini(struct radeon_device *rdev); | |
| 498522b4 | 514 | void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 089a786e | 515 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
| 43f1214a AD |
516 | void cayman_vm_set_page(struct radeon_device *rdev, |
| 517 | struct radeon_ib *ib, | |
| 518 | uint64_t pe, | |
| dce34bfd CK |
519 | uint64_t addr, unsigned count, |
| 520 | uint32_t incr, uint32_t flags); | |
| 721604a1 | 521 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| cd459e52 | 522 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| f60cbd11 AD |
523 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
| 524 | struct radeon_ib *ib); | |
| 123bc183 | 525 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
| f60cbd11 AD |
526 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
| 527 | void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
| 45f9a39b | 528 | |
| 43b3cd99 AD |
529 | /* DCE6 - SI */ |
| 530 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
| 531 | ||
| 02779c08 AD |
532 | /* |
| 533 | * si | |
| 534 | */ | |
| 535 | void si_fence_ring_emit(struct radeon_device *rdev, | |
| 536 | struct radeon_fence *fence); | |
| 537 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 538 | int si_init(struct radeon_device *rdev); | |
| 539 | void si_fini(struct radeon_device *rdev); | |
| 540 | int si_suspend(struct radeon_device *rdev); | |
| 541 | int si_resume(struct radeon_device *rdev); | |
| 123bc183 AD |
542 | bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 543 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 02779c08 AD |
544 | int si_asic_reset(struct radeon_device *rdev); |
| 545 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 546 | int si_irq_set(struct radeon_device *rdev); | |
| 547 | int si_irq_process(struct radeon_device *rdev); | |
| 548 | int si_vm_init(struct radeon_device *rdev); | |
| 549 | void si_vm_fini(struct radeon_device *rdev); | |
| 43f1214a AD |
550 | void si_vm_set_page(struct radeon_device *rdev, |
| 551 | struct radeon_ib *ib, | |
| 552 | uint64_t pe, | |
| 82ffd92b AD |
553 | uint64_t addr, unsigned count, |
| 554 | uint32_t incr, uint32_t flags); | |
| 498522b4 | 555 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 02779c08 | 556 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 8c5fd7ef AD |
557 | int si_copy_dma(struct radeon_device *rdev, |
| 558 | uint64_t src_offset, uint64_t dst_offset, | |
| 559 | unsigned num_gpu_pages, | |
| 560 | struct radeon_fence **fence); | |
| 561 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
| 454d2e2a | 562 | u32 si_get_xclk(struct radeon_device *rdev); |
| d0418894 | 563 | uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); |
| 2539eb02 | 564 | int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 6bd1c385 | 565 | int si_get_temp(struct radeon_device *rdev); |
| 02779c08 | 566 | |
| 0672e27b AD |
567 | /* DCE8 - CIK */ |
| 568 | void dce8_bandwidth_update(struct radeon_device *rdev); | |
| 569 | ||
| 44fa346f AD |
570 | /* |
| 571 | * cik | |
| 572 | */ | |
| 573 | uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); | |
| 2c67912c | 574 | u32 cik_get_xclk(struct radeon_device *rdev); |
| 6e2c3c0a AD |
575 | uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 576 | void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 87167bb1 CK |
577 | int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 578 | int cik_uvd_resume(struct radeon_device *rdev); | |
| 0672e27b AD |
579 | void cik_sdma_fence_ring_emit(struct radeon_device *rdev, |
| 580 | struct radeon_fence *fence); | |
| 581 | void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, | |
| 582 | struct radeon_ring *ring, | |
| 583 | struct radeon_semaphore *semaphore, | |
| 584 | bool emit_wait); | |
| 585 | void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 586 | int cik_copy_dma(struct radeon_device *rdev, | |
| 587 | uint64_t src_offset, uint64_t dst_offset, | |
| 588 | unsigned num_gpu_pages, | |
| 589 | struct radeon_fence **fence); | |
| 590 | int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 591 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 592 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 593 | void cik_fence_gfx_ring_emit(struct radeon_device *rdev, | |
| 594 | struct radeon_fence *fence); | |
| 595 | void cik_fence_compute_ring_emit(struct radeon_device *rdev, | |
| 596 | struct radeon_fence *fence); | |
| 597 | void cik_semaphore_ring_emit(struct radeon_device *rdev, | |
| 598 | struct radeon_ring *cp, | |
| 599 | struct radeon_semaphore *semaphore, | |
| 600 | bool emit_wait); | |
| 601 | void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 602 | int cik_init(struct radeon_device *rdev); | |
| 603 | void cik_fini(struct radeon_device *rdev); | |
| 604 | int cik_suspend(struct radeon_device *rdev); | |
| 605 | int cik_resume(struct radeon_device *rdev); | |
| 606 | bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 607 | int cik_asic_reset(struct radeon_device *rdev); | |
| 608 | void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 609 | int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 610 | int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
| 611 | int cik_irq_set(struct radeon_device *rdev); | |
| 612 | int cik_irq_process(struct radeon_device *rdev); | |
| 613 | int cik_vm_init(struct radeon_device *rdev); | |
| 614 | void cik_vm_fini(struct radeon_device *rdev); | |
| 615 | void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
| 616 | void cik_vm_set_page(struct radeon_device *rdev, | |
| 617 | struct radeon_ib *ib, | |
| 618 | uint64_t pe, | |
| 619 | uint64_t addr, unsigned count, | |
| 620 | uint32_t incr, uint32_t flags); | |
| 621 | void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
| 622 | int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 623 | u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, | |
| 624 | struct radeon_ring *ring); | |
| 625 | u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, | |
| 626 | struct radeon_ring *ring); | |
| 627 | void cik_compute_ring_set_wptr(struct radeon_device *rdev, | |
| 628 | struct radeon_ring *ring); | |
| 44fa346f | 629 | |
| 771fe6b9 | 630 | #endif |